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HANOI UNIVERSITY OF SCIENCE AND TECHNOLOGY

SCHOOL OF ELECTRONICS AND TELECOMMUNICATIONS

A GRADUATION THESIS FOR

BACHELOR OF ENGINEERING
Topic:

DESIGN OF LOW POWER HIGH LINEARITY SAR
ADC WITH REDUNDANCY AND DIGITAL
BACKGROUND CALIBRATION
Student:

NGUYEN VIET TAN – 20092354

Class:

Microelectronics – Advance Program – K54

Supervisor:

Dr. NGUYEN VU THANG

Committee member:

Hanoi, 6-2014

MINISTRY OF EDUCATION AND TRAINING

SOCIALIST REPUBLIC OF VIETNAM

HANOI UNIVERSITY OF SCIENCE AND TECHNOLOGY

Independence-Freedom-Happiness

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HANOI UNIVERISITY OF SCIENCE AND TECHNOLOGY

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Abstract
Smart devices such as smart phone, smart watch, tablet… are booming over
the last few years. One of the most important things that make these devices become
so popular is that they use different way from traditional ones to interface with user:
the touchscreen. With the touchscreen, the user can interact directly with what is
displayed, rather than using a mouse, touchpad, or any other intermediate device.
Every time, to know command from user, the analog signal from the touch panel (a
part of touch screen) will always be converted to digital signal by Analog to Digital
Converters (ADCs) and then sent to the CPU. Therefore, the ADC here plays a key
role in the sensitivity and energy-saving of the touch panel.
All smart devices are handheld device so the problem of saving power is one
of the most important one. So, up to now, Successive Approximation Register
(SAR) ADC is always chosen in the touch panel because of its low power
consumption. However, the resolution of SAR ADC is medium compare to other
kinds of ADC, this makes it become not suitable for the demand of high sensitivity
and accuracy touch panel. In order to solve the problem, this thesis describes the
design of a high linearity low power 12-bit synchronous successive approximation
register (SAR) ADC for touch panel.
The prototype has been implemented in TSMC 0.18µm Mixed-Signal CMOS
technology, the simulated effective number of bits (ENOB) at near Nyquist
frequency is 12.3-bit. The total power consumption of 15.7µW is achieved at
100ksps results in figure of merit (FoM) of only 30.9fJ/conversion-step.

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enthusiasm. Last but not least. Nguyen Vu Thang for the continuous support of my Bachelor study and research. Taiwan for his valuable advises. Do Minh Phu. Teaching Assistant and Research Assistant at IC Design Lab. friends. for the sleepless nights we were working together before deadlines. Without their constant and unconditional support. There are a lot of thing that I have learned from him: how to do research. for their tremendous encouragement and unconditional support throughout my life. motivation. this would have never been accomplished. I have been so happy and lucky to be surrounded by family.Acknowledgment Five years studying in Hanoi University of Science and Technology is a wonderful time in my life that I will never forget. Dao Ba Anh. . to write a paper. Hsinchu. professors and classmates who have provided cheers and support. I would like to thank my labmates in IC Design Lab: Nguyen Minh Duc. work in a group… He gave me smart and valuable advises for problems in my research as well as in my life whenever I needed. National Tsing Hua University. Mai Tuan Anh. Nguyen Tien Dat and my friends in Hanoi University of Science and Technology for the stimulating discussions. I would like to thank Duong Viet Duc. Throughout this time. I would like to express my sincere gratitude to my advisor Dr. It is not a long time. support and experiment sharing through my Bachelor. I would to thank my family who always has faith in me. for his patience. give a coherent talk. but not a short time either. I am indebted to all of them. and immense knowledge. and for all the fun we have had in the last five years.

.........................................................3...................................3.1...........................................3............2........3.... Dynamic Error Sources in SAR ADCs ............ 17 2................... 5 1.....................................4................................................... Amount of redundancy....6.....3........................... Quantization Noise ....................................... Resolution ............. 25 3...3................1................3.... Capacitor Mismatches ......................... 15 2................................................ 26 3...................5...................... Error tolerance windows for redundancy .......... 29 Chapter 4 Digital Background Calibration of SAR ADCs ....................... 4 1.............................3............ Thesis contributions ........................................ Radix and number of steps ................3........... 28 3..1................................................... 27 3...........1.. Architecture Selection ....................... 1 1..............................................................................2.......................... Digital calibratability ..3.. 2 1...1............1.............. Performance Metrics of SAR ADCs .....2............ 21 3.................. Offset Errors ............................... 15 2......... 4 1............................2....................................................................2.. The SAR Architecture .......2...................................... 4 1.. Structure of Projected Capacitive Touch technology with mutual capacitive approach .................................................................................3......1........................................ Figure of Merit (FoM) .. 6 Chapter 2 Overview of Traditional SAR ADCs ....2............................ Overview of digital calibration in SAR ADC ........................... 18 Chapter 3 Redundancy SAR ADCs ...... 9 2.............................. Dynamic Threshold Comparison........... Binary Successive Approximation Algorithm................................................2..............4... Motivation ....2.............. Condition of digital calibratability ...... 1 1..5....... 27 3.......... 32 4... 3 1..1........... 11 2........................................................2...............................................2...................................................6.................................................... Superposition Principle.............................................1............................... Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) ................1............................................................................................ Effective Resolution .................................................. Signal-to-Noise Ratio (SNR).............................4. 32 4.........1.................... Static Error Sources in SAR ADCs ............3............. 4 1.................................... 5 1..................................................... Redundancy Overview ...................................... 34 ............................................. Target Specifications .... 6 1...................................... 9 2.................................1......................Contents Chapter 1 Introduction ........... 5 1.............................................................. 21 3.............

4.2. Perturbation-Based Calibration Algorithm....................................................... 35
Chapter 5 Design and Implementation of a Redundancy SAR ADCs with
Digital Background Calibration ................................................................................. 40
5.1. Architecture ...................................................................................................... 40
5.1.1.

SAR ADC architecture ........................................................................... 41

5.1.2.

Calibration architecture .......................................................................... 42

5.2. Key circuit building block ................................................................................ 43
5.2.1.

Capacitive DAC Design ......................................................................... 43

5.2.1.1.

Monotonic Capacitor DAC Switching Operation ............................... 43

5.2.1.2.

Main DAC design ............................................................................... 47

5.2.2.

Sampling Network Design ..................................................................... 49

5.2.3.

Dynamic comparator design ................................................................... 50

5.2.4.

Preamplifier design ................................................................................. 51

5.2.5.

Control logic design ............................................................................... 52

5.2.5.1.

Flip flop design ................................................................................... 52

5.2.5.2.

Clock generator ................................................................................... 53

5.2.5.3.

Comparator control logic .................................................................... 53

5.2.5.4.

Switch control logic ............................................................................ 55

5.2.5.5.

Dynamic threshold comparison .......................................................... 56

5.2.5.6.

Digital calibration circuits ................................................................... 57

Chapter 6

Simulation results ................................................................................... 60

6.1. Prototype Performance ..................................................................................... 60
6.1.1.

Dynamic performance ............................................................................ 60

6.1.2.

Static performance .................................................................................. 61

6.1.3.

Performance summary and comparison ................................................. 61

Chapter 7

Conclusion and future work .................................................................. 64

7.1. Conclusion ........................................................................................................ 64
7.2. Future work....................................................................................................... 65
Bibliography ................................................................................................................. 66

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List of figure
Figure 1-1. Basic construction of a projected capacitive touch panel [1] ........................ 2
Figure 1-2. Block diagram of touch panel ....................................................................... 2
Figure 1-3. FoM versus sampling frequency of state-of-the-art ADCs published at
ISSCC and VLSI Symposium [3] .................................................................................... 3
Figure 1-4. A plot of the resolution versus the input sampling frequency for recent
published analog-to-digital converters in ISSCC and VLSI [3] ...................................... 3
Figure 2-1. An example of 5-bit quantization using a binary search algorithm [3]....... 10
Figure 2-2. Basic block diagram of a SAR ADC [3] ..................................................... 12
Figure 2-3. Schematics of the charge redistribution SAR implementation [3].............. 12
Figure 2-4. Switching scheme of a conventional SAR ADC [3] ................................... 13
Figure 2-5. An example ADC transfer function for SAR ADCs with/without
capacitor mismatches [3]................................................................................................ 16
Figure 2-6. Effective number of bits (ENOB) versus normalized capacitor mismatch
in a 12-bit binary weighted SAR ADC [3]...................................................... 17
Figure 2-7. Schematic of a SAR ADC with offset errors [3] ......................................... 18
Figure 3-1: Binary search algorithm without redundancy. The search step sizes in
this example are binary weighted with values equal to 8, 4, 2 and 1 [3] ....................... 22
Figure 3-2: Comparison of using a traditional binary search algorithm (4-bit 4-step)
and a sub-binary search algorithm (4-bit 6-step) [3]...................................................... 24
Figure 3-3: Digital error correction using redundancy in SAR ADCs [3] ..................... 24
Figure 3-4: Highlighted error tolerance windows (

) for a sub-binary search SAR

ADC [3] .......................................................................................................................... 26
Figure 3-5: Transfer functions for SAR designs with step sizes that are binary,
subradix-2 and super-radix-2 weighted [3] .................................................................... 25
Figure 3-6: Illustration of Dynamic Threshold Comparison technique ......................... 26
Figure 3-7: Effective number of bits (N) versus number of steps (M) for different
radices (α) [3] ................................................................................................................. 28

Figure 3-8: The maximum radix α and the minimum number of conversion steps [3] . 30
Figure 4-1. The superposition property of linear system [27] ....................................... 34
Figure 4-2: The perturbation of a linear SAR ADC (with optimal bit weights). [27] ... 36
Figure 4-3: The perturbation of a nonlinear ADC (with error in the MSB bit weight
only). [27] ....................................................................................................................... 36
Figure 5-1: The architecture of overall ADC ................................................................. 41
Figure 5-2: SAR ADC architecture ................................................................................ 42
Figure 5-3: The block diagram of the perturbation-based background digital
calibration. ...................................................................................................................... 42
Figure 5-4: Conventional SAR switching algorithm, showing energy consumption
related to capacitor switching transitions [3] ................................................................. 44
Figure 5-5: The top-plate waveform when using the conventional switching
algorithm [3]................................................................................................................... 44
Figure 5-6: The top-plate waveform when using the monotonic switching algorithm
[3] ................................................................................................................................... 46
Figure 5-7: Monotonic switching algorithm [3] ............................................................ 47
Figure 5-8: Comparing energy consumption of different switching algorithms [3] ...... 48
Figure 5-9: Bootstrap switch in [38] .............................................................................. 50
Figure 5-10: Dynamic comparator with a current source. ............................................. 51
Figure 5-11: The schematic of the preamplifier............................................................. 52
Figure 5-12: Split-output True Single Phase Clock (TSPC) Flip Flop .......................... 53
Figure 5-13: Clock generator a) Schematic. b) Timing diagram ................................... 54
Figure 5-14: Comparator control circuit a) Schematic. b) Timing diagram .................. 55
Figure 5-15: DAC Control Logic ................................................................................... 56
Figure 5-16: Dynamic threshold comparison circuit ..................................................... 57
Figure 5-17: Block diagram of the inner product block................................................. 58
Figure 5-18: Block diagram of LMS bloc ...................................................................... 58
Figure 6-1: The measured output spectra of the SAR ADC .......................................... 61
Figure 6-2: The measured DNL and INL of the SAR ADC .......................................... 62

..... 49 Table 6-1: Comparison of the state-of-the-art works ....................................................................................................... Current state-of-the-art SAR ADCs .............................. 62 .................List of table Table 1-1.................. 7 Table 5-1: Comparison of different switching schemes in terms of various figures of merit [3] ........................................................................... 48 Table 5-2: DAC capacitors value ...........................................................................

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Section 1.3 describes the fundamentals and performance metrics. All PCT touch screens are made up of a matrix of rows and columns of conductive material as in Figure 1-1. The capacitance change at every individual point on the grid can be measured by measuring the voltage in the other axis. The motivation of the proposed ADC will be explained in section 1.5. Bringing a finger or conductive stylus close to the surface of the touch panel changes the local electrostatic field which reduces the mutual capacitance. After studying carefully about these things.4. Mutual capacitance allows multi-touch operation where multiple fingers. 1. the structure and operation of a most common capacitive touchscreen will be described. This will result in the decrease of the voltage of the column. There is a capacitor at every intersection of each row and each column.1. palms or styli can be accurately tracked at the same time.1. also PCAP) technology is a variant of capacitive touch technology.2 will discuss the reason why the SAR architecture is selected.1 Introduction Chapter 1 Introduction In this chapter. The chapter is organized as follow. In section 1. This voltage will be digitalized by an ADC and the output code will be sent to processor to accurately determine the touch location. the structure of touch panel and all the metrics of an ADC will be discussed. Section 1. and finally. the target specifications will be described in section 1. Structure of Projected Capacitive Touch technology with mutual capacitive approach Projected Capacitive Touch (PCT. [2] 1 . the design target will be created. A voltage is applied to the rows (or columns) periodically.

2 Introduction Figure 1-1. a survey on performance of various types of ADC is necessary for determining the most suitable type of ADC for the target application. medium to high resolution and low to medium sampling frequency. A widely survey of recent published analog-to-digital converters in ISSCC and VLSI [3] is used to compare the resolution. Basic construction of a projected capacitive touch panel [1] Grid TX Drive Processor ADC RX Sense Figure 1-2. 2 . speed and power consumptions are 10-12 bits. few hundred kS/s and few microwatts. successive approximation register (SAR) ADC is the best candidate for the target application.2. energy efficiency and sampling frequency range among various types of ADC. Architecture Selection At very first step of the design process. From Figure 1-3 and Figure 1-4. with high energy efficiency. respectively. The typical requirements of an ADC in touch panel applications in resolution. Block diagram of touch panel 1.

it is important to understand the fundamentals of the technical terms that define the performance of a SAR ADC. to determine the target specification.3. FoM versus sampling frequency of state-of-the-art ADCs published at ISSCC and VLSI Symposium [3] Figure 1-4.3 Introduction Figure 1-3. A plot of the resolution versus the input sampling frequency for recent published analog-to-digital converters in ISSCC and VLSI [3] 1. 3 . Performance Metrics of SAR ADCs After ADC architecture is selected.

1. Resolution determines the step size of the least significant bit as in Equation 1.3. N. the full scaled analog input is quantized by a total of steps.3 is the deviation of each analog step away from one LSB. the difference between the actual analog input and the quantized digital output is defined as the quantization noise (error) which is derived as Equation 1. where N is the resolution of the ADC.4.1) 1. Due to rounding error. and represents reference voltage. 4 .5. as shown in Equation 1. Integral nonlinearity (INL) represents the linearity of the ADC by measuring the distance of the code centers in the A/D converter characteristic from the ideal line (drawn from zero point to full scale point of the transfer function). Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) In SAR ADC. code ( (( ) ) ( )) (∑ (1. It is calculated by Equation 1.4) 1.3. Quantization Noise In a SAR ADC.2) 1. the maximum SNR is 74dB.4 Introduction 1. ( ) (1. (1.3. the magnitude of each analog output step of the DAC is equal to one LSB.1. of the ADC.4. The differential nonlinearity (DNL) expressed in Equation 1. Signal-to-Noise Ratio (SNR) Signal-to-noise ratio (SNR) is the ratio of rms value of the full scaled sinusoid input signal to the rms value of quantization noise. INL can be calculated as the cumulative sum of DNL from code ( ) to ( ) ).3. For an ideal 12-bit ADC.2. Resolution The resolution represents the number of digital output code.3. where N is the resolution.3) (1.2. each step is equal to 1 LSB.

The biggest challenge in designing a high linearity is the DAC capacitors mismatch error.5 Introduction ( ) (1. the voltage change that we need can be reduced and the applied voltage will be not so high as a result.3. other non-idealities and practical errors also degrade the SNR which is represented by the term of effective number of bits (ENOB). Motivation As describe in section 1. It does not only guarantee digitally correctable static nonlinearities of the converter but also 5 . the change in mutual capacitance at every individual point can be measured by determining the voltage change at the other axis. ( ) (1. the voltage that is apply in one axis must be quite large.6) 1.1. To make this voltage change large enough about several millivolts.6. (1. To overcome this problem..6.5) 1. This make the power consumption of the touch panel become very large.5. about 18 volts. there is one way that if the resolution of the ADC becomes large enough. as defined in Equation 1. Figure of Merit (FoM) The Figure of Merit (FoM) defined as Equation 1. which is the typical dominant factor that limits static linearity in a switched-capacitor SAR ADC.7 is the widely adopted term to evaluate the overall performance of different types of ADC by normalizing power consumption ( ) with input frequency ( ) and ENOB. To deal with this problem. the implementation utilizes sub-radix-2 redundant architecture combined with digital background calibration engine.3. Effective Resolution Not only quantization noise.7) 1. The redundancy gives chances to reduce area of the DAC circuit as well as improve the performance of switched-capacitor SAR ADC.4.

which have quite the same typical specification requirements of an ADC in touch panel applications (operate with sampling frequency range of several hundred kS/s.6. Chapter 3 and chapter 4 will introduce about redundancy SAR ADC and perturbation based calibration algorithm respectively. 1. 1. and future work will be drawn in Chapter 7. The materials in chapter 2. the conclusion. This thesis is organized as follows. chapter 3 and chapter 4 are mainly taken form [3] and [4]. 6 . the reuse of main DAC to implement Dynamic Threshold Comparison (DTC) to save the area and increase the error tolerance of the circuit.5. Target Specifications Before defining the target specifications. In chapter 2. it is worthwhile to visit some of other state-of-the-art SAR ADCs (shown in Table 1. enabling the downsizing of all sampling capacitors to save power and silicon area. The main contributions are the proposed calibration circuit to save hardware resource and power.1). This leads to a FoM of 293fJ/Conversion step. resolution around 10 bits or larger and power consumption in the range of few microwatts to few tens of microwatts). the overview of traditional SAR ADC will be presented. Finally. The target specifications for the SAR ADC are to operate with a voltage supply of 1.6 Introduction offer means to combat dynamic errors in the conversion process. the ENOB needs to be greater than 11 bit while total power consumption less than 60 W. Chapter 6 will demonstrate the simulation results. The design implementation will be discussed in details in Chapter 5.8V at sampling rate of 100kS/s. Thesis contributions This work focuses on design of high precision and power efficient SAR ADC. A perturbationbased digital calibration technique is also applied to accomplish simultaneous identification of multiple capacitor mismatch errors of the ADC.

13µm 0.1 0.3 11 10.3 209 165 164.9 11 Total Power (mW) 3 0.5 0.06 FOM (fJ/C-S) 51.2V 1.1 ENOB (bit) 11.18µm 65nm 0.8V Resolution (bit) 12 12 12 14 12 Fs (MS/s) 22.5 11. Current state-of-the-art SAR ADCs 7 .18µm Supply (V) 1.7 Introduction Ref [4] [5] [6] [7] This work Year 2011 2013 2007 2013 -- Source JSSC TCAS2 JSSC JSSC -- Technology 0.025 31.1 80 0.2V 2.107 0.25 0.35µm 0.3V 1V 1.7 293 Table 1-1.

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Due to the non-idealities of the circuit components. The final part of this chapter focuses on analyzing these errors. errors will occur during the conversion process. 9 . The first bit is generated by comparing the input to the mid-full-scale-level of the current search range. the SAR architecture was selected among various types of ADC due to its energy-efficient switching and digital scalability with technology. the target specification was determined. After presenting about performance metrics of SAR ADC. they are broken down into static and dynamic parts. Depend on the comparison result. N comparisons to complete a conversion. 2. the structure of projected capacitive touch technology was introduced. half of the search range is eliminated and the same process continues until the entire conversion is completed.9 Overview of Traditional SAR ADCs Chapter 2 Overview of Traditional SAR ADCs In previous chapter. these errors limit the achievable speed and accuracy of a SAR ADC. Binary Successive Approximation Algorithm In binary successive approximation algorithm. Based on the sources of these errors.1. the operation of a traditional SAR ADC will be analyzed. Instead of using one clock cycle per conversion. the Binary Successive Approximation Algorithm search algorithm for Nyquist-rate ADCs is introduced. The implementation and operation of a SAR ADC will be discussed in the second part of this chapter. Depend on the requirement (high resolution but low power consumption) of the ADC for touch panel. the motivation of this work and studying some of other state-of-the-art SAR ADCs performance. this algorithm requires N clock cycles and thus. In this chapter. one bit is resolved at a time. First.

this is so difficult to accomplish in practice. Traditional SAR ADCs use the binary search 10 .2 using binary successive approximation search is shown in Figure 2-1. During the first comparison. Therefore. once a search range is eliminated from the search process. In the last search. (equal to 6. so if an error is made. it can never be reentered. the correct search range cannot be recovered or returned and thus the digital output can never be corrected.2 is less than 16. Figure 2-1. the search range is full scale from 0 to 31. none of the search ranges overlap. As a result. each conversion step need to be accurate and correct. resulting in quantization error within . the first output bit of ADC is '0' and the upper half of previous search range is eliminated. The mid decision level of the current search range is represented by the solid black lines while the solid red line indicates the location of the input level. The searching process continues until the final binary output 00110 is produced after five clock cycles. to produce correct digital outputs. At the beginning of the process. In an ideal binary implementation. Since 6.10 Overview of Traditional SAR ADCs An example of a 5-bit quantization of input 6. An example of 5-bit quantization using a binary search algorithm [3] Binary conversion is quite sensitive to errors made during the conversion process. the range of uncertainty is reduced to one LSB.2) is compared with the mid-full-scale level of the initial search range.

2. DAC. At the end of the conversion process.1) ∑ During the sample and hold phase.11 Overview of Traditional SAR ADCs algorithm. The total charge stored in the array is ( ) (2. Each capacitor within the DAC can be re-configured by connecting it to either the input or the plus/minus reference voltages. In this implementation. The total capacitance sums up to . the input signal is sampled at the bottom plates of the DAC array by connecting them to the input and the top plate of the array to ground (Figure 2-4(a)). In the conversion process. the SAR control reconfigures and updates the DAC. the capacitive DAC performs both sample/hold function and subtractions in the charge domain using capacitors. the charge is properly re-distributed such that the top plate voltage on the DAC is approximately the same as the voltage on the other input of the comparator .which is zero in case depicted in Figure 2-3. the comparator generates each bit by comparing with and depend on the output bits of the comparator. The SAR Architecture The SAR architecture performs the A-to-D conversions over multiple clock cycles by using the value of the previous determined bit to assist in finding the next significant bit.2) 11 . where (2. The SAR consists of an N-bit binary-weighted capacitive DAC. SAR control and comparator. 9]. A typical block diagram of a SAR ADC is shown in Figure 2-2. it will be shown that digital error correction (or redundancy) can be used to greatly alleviate this problem. a SAR control logic block and a comparator. however. in a later chapter. each block plays a different role: the S&H samples one instance of the continuous analog input signal during the first clock period and holds this value for the remaining conversion process. It involves four basic building blocks: sample and hold (S&H). 2. An effective implementation of the DAC is the so-called charge redistribution or capacitor array scheme [8.

respectively. The top plate voltages of the two configurations can be 12 . Basic block diagram of a SAR ADC [3] Figure 2-3. For simplicity. Using the charge conservation principle. Schematics of the charge redistribution SAR implementation [3] The conversion phase is begun after the sampling phase. only if and it .12 Overview of Traditional SAR ADCs Figure 2-2. By comparing the first output bit next bit calculation. the voltage on the top plate of the array. becomes (2. After that. the most-significant-bit (MSB) capacitor is connected to remaining capacitors are connected to while the (Figure 2-4(b)). can be determined and the configuration is set for the stays connected with will be switched to ground for the remaining cycles if is switched to directly to ground.3) In Equation 2.3. Figure 2-4(c) and Figure 2-4(d) show two different configurations. it is assumed that and . in this example. During the first step. the first input sampling contributes to the first term and the the MSB capacitor contributes to the second term. . .

4 and 2. The process of comparing and reconfiguring continues until the last bit is obtained. ( ) (2.4) 13 .5.13 Overview of Traditional SAR ADCs Figure 2-4. Switching scheme of a conventional SAR ADC [3] calculated by Equations 2.

The ADC is robust against circuit non-idealities.7) where is the total parasitic capacitance on the top plate. the total charge on at the beginning and at the end of the process is the same and therefore. The bottom-plate sampling essentially enables this feature. Thus. The architecture is less limited by technology and supply voltage scaling compared to other 14 . such as parasitic capacitances. As a result. but does not change the polarity of the comparison result. these will not affect the conversion process if the reference voltages are completely settled. [ ]. gate capacitance of comparators. Therefore.. the voltage on the top plate changes but returns to a voltage that is near zero at the end of the process. and . from the perspective of charge. the input is converted into binary-weighted bit sequences.14 Overview of Traditional SAR ADCs (2. On the other hand. The attenuation factor can be calculated as (2.. it will not affect the overall accuracy of the conversion process. if no pre-amplifier is used in the comparator design. the parasitic capacitance on the top plate decreases the amplitude of sampled input. and the final voltage on is (2. using a charge redistribution scheme in a SAR ADC has a lot of advantages. Note that both the top and bottom plates of the DAC can have parasitic capacitances contributed from non-ideal layout/wiring. This attenuation reduces the effective signal power. In summary. It is energy efficient and only has dynamic but no DC power consumption. The parasitic capacitances on the bottom plate are driven by low impedance reference voltage supplies.6) ∑ This voltage represents the quantization error of the entire conversion process.5) At the end of the conversion. In the sampling phase. capacitor does not cause any charge error. During the conversion. the top plate is connected to ground before the node becomes floating until the end of the conversion phase. thus will not affect the correct output bits.

diffusion interactions. Even though some of these mismatches sources can be combated by using careful design and layout.15 Overview of Traditional SAR ADCs architectures since most parts of the ADC are digital. this 12-bit example is free of any DNL and INL errors.. Systematic mismatches results from temperature gradients. It also has the potential to take full advantage of improved energy efficiency and speed in deeplyscaled CMOS.1. Lastly. Typically. 15 . mismatches in the capacitive DAC can lead to incorrect charge distribution during the conversion phase.3. oxide thickness . Capacitor Mismatches Good capacitor matching is the key for high accuracy ADCs. doping. it is still difficult to attain more than 10 bits of resolution. wire sizing.3. integral nonlinearity (INL). This implies linear mapping between the inputs and the outputs. Static Error Sources in SAR ADCs Even with all the architectural benefits discussed in the previous section. A correctly implemented SAR ADC typically supports full rail-torail input range. the input/output transfer function resembles a straight dotted line in Figure 2-5. When capacitors within the DAC are perfectly matched in a SAR ADC. mismatches in transistors can lead to offset errors in the comparator… 2. the solution for this is to increase the overall dimension or to use special layout technique to improve matching. 2. These types of mismatches cannot be completely eliminated. of practical value from desired value. biases in the processing steps. Random mismatches include the difference in device dimensions.. since the sampling capacitors are shared with the configurable DAC. which can be advantageous for high-resolution designs. not analog.. the static performance of converter (measured by metrics: differential nonlinearity (DNL). Since all the steps have equal size and they are evenly spaced over the full range. mechanical stresses. SAR ADCs can save significant areas and result in small chip area. offset error and gain error) is still limited by the matching of analog components by many ways. The variation sources can be divided into random statistical fluctuation and systematic mismatches. for example.. It is controlled and influenced by manufacturing processes and physical design.

which makes the DNL exceeds -1. Typically. Figure 2-6 shows the plot of ENOB versus the standard deviation of the unit capacitor [3]. the transfer function deviates from the straight line as shown by the solid blue curve in Figure 2-5. As a result.16 Overview of Traditional SAR ADCs Figure 2-5. Misalignment in the horizontal direction creates missing levels. An example ADC transfer function for SAR ADCs with/without capacitor mismatches [3] On the other hand. It can be seen that even at 1% standard deviation in . control and calibration for the mismatches in capacitors play a key role in high-resolution design. missing codes are digitally correctable while missing levels are not. Therefore. one effective way to deal with capacitor mismatches. the ENOB can be degraded by more than 1 bit without taking into consideration other non-idealities in the design. Misalignment in the vertical direction creates missing codes. Misalignments occur in both the vertical and horizontal directions. 16 . will be discussed in Chapter 3 and 4. which implies that some part of the original analog information is lost. when mismatch errors are present. ADCs should be designed to avoid missing levels. More details on digital calibration.

The first offset comes from charge injection of the sampling switches. First.2. which is also signal-independent for two reasons. independent of input voltages. 17 . Second. and thus. Hence. only the offset of that comparator affects the operation. Offset Errors The offset error in a SAR ADC only causes a linear shift in the transfer function. the top plate always returns to zero at the end of the conversion phase. the amount of charge injected onto the plate is mostly constant and independent of the input signal.3. only one comparator is used repeatedly during the conversion phase. at least to the first-order estimation. Effective number of bits (ENOB) versus normalized capacitor mismatch in a 12-bit binary weighted SAR ADC [3] 2. The second source of offset errors in a SAR ADC is the offset of the comparator. different from some other architectures (the flash ADC…). the switch turns off and the charge stored in the gate-to-channel capacitors is injected onto the top plate of the DAC. Therefore. but does not cause linearity problems since the error is signal-independent. There are two sources of offset. By employing bottom-plate sampling. At the sampling instance. the offset voltage is always the same.17 Overview of Traditional SAR ADCs Figure 2-6. the input common mode voltage of the comparator at the end of the conversion phase is the same regardless of the input signal.

18 .4. The RC settling of the DAC determines the minimal time that needs to be allocated for each conversion step and therefore also determines the maximum operation speed of the ADC. each conversion is given enough time for to completely settle within the necessary resolution.8 shows that the additional terms introduced by offset voltages do not depend on the input voltage. Since traditional SAR ADCs uses binary search in which each analog input always maps to one distinct digital output code.12. where is given in is the total resistance of the switches and is the total capacitance of the DAC. The required time for an N -bit ADC to settle within Equation 2. small and should be used in the design. As a result. (2.8) ∑ Figure 2-7. Schematic of a SAR ADC with offset errors [3] 2. conversion errors can occur because the comparator makes its decision before settles adequately. To improve speed of SAR ADCs. errors made during the conversion process cannot be recovered at the end of the search process.18 Overview of Traditional SAR ADCs The residue at the end of the conversion given by Equation 2. it is essential that each comparison is made correctly during the conversion process to ensure correct operation. it is assumed that during the SAR operations. . In reality. Dynamic Error Sources in SAR ADCs When analyzing the static error sources.

19 .9) ( ) (2.19 Overview of Traditional SAR ADCs (2. the sampling rate of SAR ADC in this work is very low. therefore the dynamic error will not affect the performance of target SAR ADC.10) As in defined specification in chapter 1. only 200ks/s.

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in a binary search process. amenability to digital scaling. It will be shown that having redundant bits provides the extra leverage during the search process so that conversion errors in the earlier steps can be corrected later and redundancy can provide the necessary digital calibratability to calibrate out the mismatches in the capacitor array. its resolution and speed are still limited by a few key design challenges that need to be resolved. no conversion errors can be tolerated because for every analog input value. small chip size. The chapter is begin by giving a conceptual overview of SAR redundancy and discussed its benefits in terms of achievable resolution over the traditional binary search algorithm. Once a decision error is made. 3. energy efficiency. such as its efficiency in terms of conversion steps. Since the target designed SAR ADC has the sampling frequency very low. The relationship between the two parameters is analyzed.21 Redundancy SAR ADCs Chapter 3 Redundancy SAR ADCs In chapter 2. we introduce and analyze the redundancy algorithm in SAR ADCs and background digital calibration to see how it can help mitigate the limitation discussed previously.1. In this chapter. there is a unique corresponding digital output code. only 100ksps. only capacitor mismatches but not the incomplete reference voltage settling due to high switching activities is the main linearity and performance limiting factors. and ease of implementation. Even though it has many architectural advantages. Redundancy Overview As described in Chapter 2. due to its one-to21 . The expected random mismatches within the capacitors determine the amount of redundancy that is necessary to cover this variation. the operation as well as the structure of a traditional binary weighted SAR ADC is discussed.

search range. Essentially. the decision levels. Even though this search 22 . 2 and 1 [3] Although the binary search presented in Figure 3-1 has no error tolerance capability. In the plot. once a range is eliminated during the searching process. it suggests that if the search ranges within the same cycle do overlap. Figure 3-1: Binary search algorithm without redundancy. In the plot. the ADC cannot recover and produce the correct output codes. This is shown clearer in Figure 3-1. since none of the ranges within the same search cycle overlaps. This confirms the previous conclusion that errors made during the conversion process cannot be corrected in a binary search. and search sequence for a 4-bit binary-weighted SAR ADC are highlighted. a sub-radix-2 search needs more than N steps to convert an analog input into a N-bit digital output. the range is dropped from the search procedure and it will never be reconsidered again. a less than radix-2 (sub-radix-2) search is needed. 4. The search step sizes in this example are binary weighted with values equal to 8.22 Redundancy SAR ADCs one mapping property. the already dropped search range can potentially be recovered to produce the correct digital output. The x-axis indicates the sequences of binary search and the y -axis shows the full search range. To create overlapped search ranges.

the right-most plot shows an example in which a decision error is made in the second step. ( ) where ∑.() . 1. respectively. On the other hand. 1]. 2. The total steps s is 15 in both cases. the middle plot shows an example where a decision error is made in the rst step and finally.23 Redundancy SAR ADCs algorithm is less efficient in terms of the number of steps required to reach a certain resolution. 1] to achieve the same resolution. where M > N.2. The left-most plot shows an ideal example where all decisions are made correctly. For example.2) . a redundancy SAR ADC requires M steps to realize N-bit digital output. s(i)'s represent the step sizes during the search process. This demonstrates that redundancy has the capability to digitally realize correct oputput code for at least some bit decision errors. N is the effective resolution and M is the total number of steps.1. Here. The final digital output for an N -bit M -step ADC can be calculated using Equation 3. 2. In an N-bit binary weighted algorithm.3 and 3. it provides room for the necessary error tolerances to boost the robustness of the overall operation. the extra two steps is added to the original binary search to provide error tolerance.1 and they all result in the same Dout (= 6) as shown in Equation 3. An example demonstrating this error resilience is given in Figure 3-3.4. () . ( ) (3. the binary case only requires four steps with binary weighted s = [8. The two search algorithms is compared in Figure 3-2. Their digital outputs is calculated by using Equation 3.2. 3. 1. there are N steps s(i)'s with binary weighted values . In this example. - ( ) ( ( ) ) ( 23 ( ) ) ( ) (3. 2.1) - is the final digital output expressed in decimals. implying that the two algorithms have identical search range. while the sub-binary case requires six steps with s = [8. b[n] is the digital output bit. 4. in Figure 3-2. For = 6. . each of these above cases gives different digital output bit sequences: [010010]. [100010] and [100010]. where i is between 0 and .

4) Figure 3-2: Comparison of using a traditional binary search algorithm (4-bit 4step) and a sub-binary search algorithm (4-bit 6-step) [3] Figure 3-3: Digital error correction using redundancy in SAR ADCs [3] 24 .24 Redundancy SAR ADCs .3) ) ) ( ) (3. - ( ( ) ) ( ) ( ( ) ( ) ) ( ) ( ( ) (3. - ( ) ( .

then the sum of the follow-on step sizes.1.25 Redundancy SAR ADCs 3. s(n-3):….5 can be intuitively understood as follows. s(n-2). the error tolerance window is given by Equation 3. s(1). if an analog voltage falls within this range and error is made. Figure 3-4: Transfer functions for SAR designs with step sizes that are binary. 2. That exceeded amount is the tolerance window for that decision level. the ADC can recover from the errors if there are no mistakes in the rest of the conversion process. 2. must be large enough and exceed the value of the current step size to correct this mistake. subradix-2 and super-radix-2 weighted [3] 25 . For the 5th output bit. 1]. ( ) ∑ () ( ) (3. ( ) ( ) ( ) ( ) ( ) The formula 3. Error tolerance windows for redundancy The redundancy only provide limited amount of error tolerance for SAR algorithm. if the decision errors are too large.6) output bit. For the output bit. This error tolerance window is denoted as .5. Figure 3-4 shows a redundant SAR ADC with s = [8. This implies that during the transition.6. 2. For the (3. During the conversion process. If erroneous occurs. For each conversion step. a range of recoverable analog voltage can be highlighted around the decision level. the next decision level will either move up or down by the step size of s(n-1) once a decision is made. (n) can be calculated according to Equation 3.5) As an example.1. the errors still cannot be recovered and the digital outputs will be incorrect. even with redundancy.

Therefore. Dynamic Threshold Comparison Error-tolerance window Error-tolerance window Middle range Middle range Input voltage temporary shift Input voltage Figure 3-6: Illustration of Dynamic Threshold Comparison technique From previous section. The main idea of this technique is if the input voltage sits outside the error-tolerance window.2. To further improve the error resilience of SAR ADC. the decision error can be corrected in later steps.1.26 Redundancy SAR ADCs Figure 3-5: Highlighted error tolerance windows ( ) for a sub-binary search SAR ADC [3] 3. it should be temporary shift into this window to exploit the error resilience of the redundancy. it can be seen that if an input voltage falls inside error-tolerance window. Dynamic Threshold Comparison technique [4] will be utilized. this technique 26 .

Condition of digital calibratability Figure 3-5 shown three transfer functions which represent 3 different cases.27 Redundancy SAR ADCs provides extra error tolerance capability for the ADC with the input voltage outside error window. 3. the range of window is enlarged when DTC technique is applied. Figure 3-5 (a) shows the ideal case of transfer function in which the analog input is linearly mapped to digital output code. Digital calibratability The previous section discussed about how dynamic conversion error can be resolved by using redundancy. redundancy can be built into all decision levels 27 . the condition of digital calibratability in the presence of static mismatches in capacitors will be explored. In this case. In contrast. vertical misalignments (missing codes) appear in the transfer function. In the section. which is referred as the sub-radix-2 search and Figure 3-5 (c) has the MSB step size larger than its nominal value.2. it can be seen that the dominant error source of the target ADC is capacitors mismatches. Figure 3-5 (b) shows the case that the MSB step size smaller than its nominal value. a horizontal misalignment (missing level) appears in the transfer function. the error-tolerance window does not increase unlimited. In other words. which lead to mismatches in the searching steps. 3. digitally correctable codes can be created. In contrast to previous case. s(n). In this case. which is referred as the super-radix-2 search. In a super-radix-2 search. in a subradix-2 search.2. the analog information is lost since multiple analog inputs are mapped to the same digital output code and the errors cannot be corrected digitally. By designing step size s(N) intentionally smaller than the sum of the remaining s(n). The large vertical jump is embodied in the redundant search algorithm.1. the error is digitally correctable in this case. Note that by utilized DTC technique. In chapter 2. the amount of range extension will depend on the way of implementation of this technique in SAR ADC. more than one digital output codes could potentially be mapped to one analog input while some of the digital output codes never show up during normal operations. By extending this idea into every search step in the sub-binary search. since the analog information is not lost.

Amount of redundancy As discussed in the previous discussion. redundancy is built into the search algorithm. 3.7 with respect to different amounts of DAC capacitance variation will be established.7. There will be no missing levels and all static errors are digitally correctable as long as all decision levels satisfy Inequality 3. a relationship that determines the amount of redundancy needed to guarantee Inequality 3.1. To achieve this inequality. whenever Inequality 3.2. 2. N .7 is satisfied.28 Redundancy SAR ADCs ∑ () ( ) (3. one simple way is choosing a fixed radix that is less than 2.7.…. Figure 3-7: Effective number of bits (N) versus number of steps (M) for different radices (α) [3] 28 . In this section. Even though the design is originally built to satisfy Equation 3. the added variation in the search steps resulted from random manufacturing variation of capacitors can break this relationship and create missing levels that are not digitally correctable.7) where i = 1.2.

even in the face of variation will be found.9) ( ) where is the sum of all the step sizes. can be calculated using Equation 3.9 (3. N is the effective number of bits and M is the total number of conversion steps. they are more resilient against both dynamic and static conversion errors. Due to manufacturing variation. ). In this section. . s(M-1). α. 3. 1.8) ) where i = M-1.2. require more steps to achieve the same resolution as the converters with larger radix. A plot of maximum radix and the minimum number of conversion steps needed for a given amount of capacitor mismatches in a 12-bit ADC is shown in Figure 3-8 [3].7 can be re-written as follows (3.3. α. Radix and number of steps In order to incorporate redundancy to provide the capability to digitally calibrate for static random mismatches.1.7 must be satisfied at all times even with the presence of variation. From this figure.…. Inequality 3. the following relationship is obtained () ( (3. Equation 3. N. Figure 3-7 shows that although converters with smaller radix.10) ∑ where is the desired (or designed) relationship between the capacitances in the DAC. it can be seen that when the variance of capacitor 29 . M-2. the appropriate radix number and the number of steps such that Inequality 3. The effective number of bits.….29 Redundancy SAR ADCs When the ADC is designed with a fixed radix. Manufacturing variation in 's can break this relationship. s(0)) are proportional to the capacitor sizes ( . Since the step sizes (s(M ).…. random variation in capacitor size is unavoidable.10 is satisfied with high probability.

in this implementation. in order to achieve digital calibratability in a 12-bit ADC [3] 30 . this corresponds to the classic non-redundant binary search ADC case.30 Redundancy SAR ADCs is 0%. α = 2. On the other hand.0 and M = 12. Figure 3-8: The maximum radix α and the minimum number of conversion steps M versus the standard deviation of the unit capacitor. it is estimated that is about 7%. then α = 1.86 and M = 14 are obtained.

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a digital background calibration schemes that can utilize the redundant information to digitally remove the nonlinearity is provided. Although they are quite effective in removing static 32 . to take another step towards designing higher resolution SAR converters. To alleviate effect of nonlinearities on SAR performance. in [12] proposed a capacitor error averaging technique to achieve exact multiplication by a factor of two regardless of capacitor mismatch error in a pipelined ADC. and Song et al. In this chapter. the total number of steps and the radix number for the target ADC were chosen. The requirements can be expressed in a simple relationship between the maximum radix number.2. a lot of new calibration techniques to achieve designs with higher accuracy have developed. static nonlinearities usually limit the resolution of SAR ADC from going above 8-10 bits [10]. 4. To ensure digital calibratability in the presence of capacitors mismatches. redundancy can provide error tolerance for the ADC during the conversion process. the minimum total number of conversion steps and the expected manufacturing random variance of capacitors. The most common of these techniques [11-16] is that they use analog components in the signal path to remove static nonlinearity. some requirements on redundancy are needed. Overview of digital calibration in SAR ADC Without trimming or calibration. If implemented correctly.32 Digital Background Calibration of SAR ADCs Chapter 4 Digital Background Calibration of SAR ADCs In Chapter 3. the redundancy algorithm in SAR ADC was introduced. From this relationship. Li et al. For example. in [11] came up with a ratio-independent algorithmic technique.

In foreground calibration. They can be divided into two groups: foreground calibration and background calibration. have also been developed. [20- 23]. an injected calibration signal cause a constant shift of (the corresponding digitized output of independent of the input signals at the output. Other calibration schemes extract nonlinearities by using statistically-based methods [18. respectively. the calibration is done during a calibration phase at startup and nonlinearity is measured by driving the inputs with specific calibration signals to extract the mismatch information. which can realize the benefit of technology scaling. The mismatch data stored in a RAM is used to correct matching errors of the capacitor array during the normal operation. these techniques typically degrade conversion speed and add circuit noise. Therefore. when will ) which is is subtracted from the final digitized output. Besides. The ratio errors of the capacitors will be extracted sequentially from the MSB capacitor to the LSB capacitor during calibration.33 Digital Background Calibration of SAR ADCs nonlinearities in the design. These calibration schemes interrupt the normal operation of the ADC since they require collection of measurement data at the beginning of the operation. The circuit noise based FoM degradation is roughly 12X and 9X in [11] and [12]. Using this approach. For example. 19]. another approaches estimate the static errors by using the input signal itself instead of a calibration 33 . The calibration engine is designed to null this correlation by adjusting the calibration parameters. so they cannot track parameter drifts. the injected signal should have no correlation with the output signal. Rather than tampering with the input signal path. digital calibration techniques. In contrast. these calibration schemes are typical to run during manufacturing or at startup. onto the signal path [4]. in [17] developed a self-calibrated capacitor array in a SAR ADC. With an ideal linear transfer function. . the signal range and the over-range protection is reduced since the signal path must accommodate the addition of the calibration signal. To minimize the effect. digital background calibration does not interrupt the normal conversion process since it runs transparently in the background. Lee et al. A common approach is to inject a known calibration signal.

25] and [26]. Even though the reference ADC may run at a slower speed compared with the core ADCs. while subtracting the output codes by and 34 in Figure 4-2(b) vertically .2) Equation (4. the SAR ADC is represented by an operation Q(X).2) implies that the correct quantization value of input voltage can be obtained by subtracting the perturbation signal in digital domain in a linear A/D conversion. the Q(X) is a linear operation. In Figure 4-1. Equation (4. The superposition property of linear system [27] Denote ( ) as .2) can also be intuitively explained as follow: adding and horizontally shifts the original transfer curve as in Figure 4-2(a).34 Digital Background Calibration of SAR ADCs signal [24-26]. which maps analog samples to output digital codes.1. Therefore. these techniques will increase power consumption or reduce in conversion speed. Assuming ideal quantization. The ADC respectively maps its input and Q( and (the perturbation signal) to the output Q( ) ).1) Figure 4-1. In this work. 4. using the superposition principle ( ) ( ) ( ) (4. the perturbation based digital background calibration [4] and [27] is used because of its simplicity and effectiveness as demonstrated in [4]. respectively. Adaptive equalization techniques are used to resolve nonlinearity problems for pipelined and SAR ADCs in [24. Superposition Principle The superposition principle of a linear system is the soul of the perturbationbased digital calibration. an accurate reference ADC is typically used to estimate and correct the errors. Then the Equation (4. This calibration algorithm will be discussed carefully in the next parts. In these techniques.1) is rewritten as ( ) ( ) (4.

which provides a better opportunity to observe the error. and . The difference between them gives a chance to observe the bit weight error. However. is given at the output. the error (window) diminishes and the transfer curve is linearized. By adjusting the bit weights to obtain optimal ones.2. In Figure 4-3(a) and (b). the same horizontal and vertical perturbations respectively as Figure 4-2(a) and (b) is shown. Perturbation-Based Calibration Algorithm The perturbation-based digital calibration for a SAR ADC with N conversion steps can be described as follow: A single SAR ADC digitizes each analog sample twice. The two perturbed transfer curves in Figure 4-3(b) form a window with a horizontal size of 2 instead of aligning with the original one in this case. If transfer curve is linear and all bit weights are optimal. W={ and and respectively. two different digital codes are obtained. Each analog input can be digitized twice using both of the dashed and dash dotted curves in Figure 4-3(a) and (b) respectively. same bit weights.35 Digital Background Calibration of SAR ADCs shifts the transfer curve accordingly. With the }. A large results in a wide window. In general. the two quantizations are perturbed by analog offsets of then two N-bit raw codes. but the perturbation detects all of them in the same mechanism as the MSB example above. [27] 4. For example. considering the MSB bit weight error where the transfer curve distorts at the transition from the digital code 011∙∙∙1 to the digital code 100∙∙∙0 and assuming the other bit weights are optimal. the two perturbed transfer curves line up with the original one. assuming . N-1. i=0. (these bit weights represent conversion step in chapter 3) the weighted sums and 35 are obtained by . The superposition property of the linear transfer curve holds again. every bit weight derails from its nominal bit weight so the transfer curve is distorted at various locations. in a nonlinear case the superposition property does not hold. Therefore. In reality. ∙∙∙. However. accordingly. when an analog sample falls in the window. is adapted so the injected can be precisely removed in digital domain.

[27] ∑( ) .3) ∑( ) .4) 36 .36 Digital Background Calibration of SAR ADCs Figure 4-2: The perturbation of a linear SAR ADC (with optimal bit weights). - (4. [27] Figure 4-3: The perturbation of a nonlinear ADC (with error in the MSB bit weight only). - (4.

Equation (4. Plugging Equations (4. the mean of averaging) yields the correct digital output of and cancelled in .7) is in the form of a generalized code-domain linear equalizer. to drive that ⃛ to 0. - .37 Digital Background Calibration of SAR ADCs where is the quantized input-referred offset. ⃛ where and (4.5) are quantized versions of ⃛ desired value of and . In steady state.5).8) (4. a zero error is obtained. Eventually.7) - Equation (4. (4. -( - . - . all optimal bit weights are learnt. . and the ratio between the capacitor ( ) and the total capacitance ( ) defines the bit weight. -) . where and . In the double conversion both the quantization noise and the comparator noise are reduced by 3 dB. - . 37 ( .6). as depicted in Figure 3-10. Otherwise.3) and (4. an LMS algorithm is applied by adjusting the N individual bit weights and the simultaneously using Equation (4. Equation (4. Assuming optimal bit weights are learnt.4) calculate the weighted sums of all bits of and .9): .4) into Equation (4. ∑[ ( ⃛ )] .8) and Equation (4. - (4. The superposition property of the linear transfer curve shown in Figure 39 holds in this case.5) gives. the error between the two conversions is obtained by Equation (4. With digitally subtracted. Then.9) are the step sizes of the update equations.1) holds. the non-zero error indicates the nonlinearity in the transfer curve. the calibration engine forces the error to zero in a least-mean-square sense. Similarly the is ( ) ( ) (4. Putting Equation (4.3) and (4.1) and into Equation (4. - .6) where Q(•) is ideal quantization.

by adding only a pair of injection capacitors. Compare to a highly linear reference ADC required by the equalization-based digital calibration [17. so this does not affect much to the ADC performance. 32]. The deterministic character and the zero-error-forcing nature of this calibration result in a much shorter convergence time than the correlation-based ones [22. the hardware overhead is negligible. 24. Although the dynamic range of the ADC is reduced by analog offset injection. this calibration requires significantly lower circuitry complexity and less design effort. it is typically tiny compared to the full-scale range. [28-30]. 25]. Unlike the splitting-based calibration where the generation of multiple decision paths and double routing are involved [31]. the sampling rate of target ADC is quite low.38 Digital Background Calibration of SAR ADCs The perturbation based calibration only requires an analog offset injection. Although the calibration reduces the conversion speed by half. 38 .

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with 40 . the real implementation of a redundant SAR ADC is described. 5. The superposition principle in which the calibration is based on was explained first. Its operation can be described as follow. the implementation at the architectural level will be focused on. Secondly. an enhanced digital calibration circuit which require less hardware resource compare to [4] is introduced. A single SAR ADC digitizes each analog sample twice.1. preamplifier… will be described. In this chapter. the perturbation based calibration algorithm that is able to utilize the redundancy information to digitally correct output code was introduced.40 Design and Implementation of Redundancy SAR ADC with Digital Background Calibration Chapter 5 Design and Implementation of Redundancy SAR ADC with Digital Background Calibration In Chapter 4. All the circuit blocks are combined and how all these blocks work together is analyzed carefully. Then the calibration algorithm was described in details. From that. some circuit blocks such as bootstrapped switch. In the first part. And the last once. DAC switching scheme that is able to achieve higher energy efficiency than conventional switching schemes will be presented. Architecture The architecture of overall ADC is shown in Figure 5-1. A new way to implement the dynamic threshold comparison which requires less area is proposed in this part. The next part of the chapter describes the design at the circuit level with discussion of several new contributions. its advantages and disadvantages compare to other algorithms also was discussed. comparator. Firstly.

Then. After that. and . The process to generate all procedure above is repeated except the perturbation connecting capacitor to the ground. the largest capacitor on the higher voltage potential side is switched to ground while the other one (on the lower side) remains unchanged. the bottom plates of the capacitors are reset to . the ADC samples the input signal on the top plates via bootstrapped switches. Its operation can be described as follow. respectively. a perturbation signal is added to the input by connecting capacitor to the ground.1. At the same time. after the ADC turns off the bootstrapped switches. .1. D - Calibration Engine d +∆a. all capacitors are reset to . the comparator continues comparing and the switch or will be closed. At first. the comparator performs the first comparison without switching any capacitor. which increases the settling speed and input bandwidth. The procedure is repeated until the LSB is decided and the raw 14 bit of After that. is begun. D +. 41 is obtained. Next. resulting in two 14-bit raw codes. The is added to the input by . the calibration engine will calculate * output d and update the new value of bit weights SAR ADC Vin and +.41 Design and Implementation of Redundancy SAR ADC with Digital Background Calibration two analog offsets. -∆a Figure 5-1: The architecture of overall ADC 5. Depend on the comparator output. SAR ADC architecture Figure 5-2 shows the architecture of SAR ADC. Depend on values of and .

24). 1 subtractor …).42 Design and Implementation of Redundancy SAR ADC with Digital Background Calibration Vref S12p S 11p S 10p C 12 C 11 C 10 S 7p C7 S 2p S 1p S 0p C2 C1 C0 C0 C tp V+ V i+ V iBootstrapped switch SAR Control Logic V- preamplifier C 12 C 11 C 10 S12n S 11n S 10n C7 S 7n C tn C2 C1 C0 C0 S 2n S 1n S 0n clk Vref Dynamic threshold comparison Signal injection Figure 5-2: SAR ADC architecture 5.d 2 - 2∆d LMS error Figure 5-3: The block diagram of the perturbation-based background digital calibration.23) and (3. The inner product block is used to calculate the weighted sum from 14-bit raw code . From this difference and value of and (from 14-bit . This way of implementation will save a lot of hardware resource as well as power compare to the implementation in [4] (1 inner product block.1. -∆a d+ . 42 . we can obtain all other important parameter such as output code d.2.d w +∆a. Calibration architecture The block diagram of the calibration engine is shown in Figure 5-3. bit weights W… as in Equation (3. It is also utilized to calculate the difference between raw code and ). d+ d + + SAR ADC Vin d+ .

After that. respectively. we will introduce this algorithm with binary weighted capacitor for easy to understand and compare to other switching algorithms. 43 . Then the switching scheme either takes the “up” or “down” transitions depending on whether the bit is “0” or “1”. The procedure is repeated until the LSB is decided.43 Design and Implementation of Redundancy SAR ADC with Digital Background Calibration 5. wasting energy during operation. Conventional switching algorithm In a SAR ADC. it does not move the charges among capacitors efficiently. Capacitive DAC Design 5. they are disconnected from the DAC at the end of sampling phase. Key circuit building block 5.2.2. Even though this switching algorithm is able to produce the correct logic operations.1. The first output bit is produced by comparing the voltage on the plus and minus nodes of the comparator. the top-plate waveform for a 6bit ADC using the conventional switching algorithm is shown in Figure 5-5.1. The conventional SAR switching algorithm for a 3-bit ADC in a fully differential implementation is shown in Figure 5-4. The DAC is configured by charging the MSB capacitor to and the remaining capacitors to ground for the top array and. the differential inputs are sampled onto the upper and lower arrays of the DAC.1. During the first phase.2. The energy consumption of each transition in conventional switching algorithm is shown in Figure 5-4. Although the implemented Capacitive DAC uses sub-radix-2 monotonic switching algorithm. Monotonic Capacitor DAC Switching Operation In this part. the DAC is used for 2 two purposes: sampling the input voltage and generating error residues between the input and the current digital estimate. the opposite is done for the bottom array. Monotonic Capacitor DAC Switching algorithm will be described. The total energy consumption for this operation is .

the sign bit of the input signal is generated by comparing the magnitude of and in the first transition. As shown in 44 . In the above example. showing energy consumption related to capacitor switching transitions [3] Figure 5-5: The top-plate waveform when using the conventional switching algorithm [3] Observing the first two transitions. it can be seen that energy efficiency can be improved.44 Design and Implementation of Redundancy SAR ADC with Digital Background Calibration Figure 5-4: Conventional SAR switching algorithm.

which reduces both charge transfer in the capacitive DAC network and the transitions of the control circuit. The major differences between this algorithm and the conventional one is that the common-mode voltage of the reference DAC gradually decreases from half to ground but never increases. For each bit generation cycle. It implies that simpler algorithm can be developed to avoid this energy loss. there are a total of four potential transition paths that the SAR algorithm can take. without consuming any energy. the comparator directly compares and . the sum of all capacitors in a DAC is . Assume that the upper most path is taken. In contrast. This switching algorithm consumes no energy before the first comparison since the comparator directly performs the first comparison without switching any capacitor. At the end of sapling phase. Figure 5-6 shows the top-plate waveform for a 6-bit ADC using the monotonic switching algorithm. Intuitively. the conventional one consumes 45 before the first comparison. The average switching energy of an n-bit conventional switching algorithm can be derived as follows: ∑ ( ) (5. the input is disconnected from the DAC. The . the MSB capacitor on the higher voltage potential side is charged to ground while the other one (on the lower side) remains connected to . resulting in smaller power dissipation. Depending on the comparator output. only half that of the conventional one. The ADC samples the input signal on the top plates while the bottom plates of the capacitors are reset to . depending on the values of the input signal.45 Design and Implementation of Redundancy SAR ADC with Digital Background Calibration Figure 5-4. Figure 5-7 shows 3-bit examples of the monotonic switching algorithm. For an n-bit ADC. the first step makes up more than 75% of the total energy consumption to just generate the sign bit. The procedure is repeated until the LSB is decided. Without switching any capacitor. in [33] proposed a monotonic switching algorithm. the sign bit can be generated by directly comparing and after sampling.1) Monotonic Switching Algorithm Liu et al. only one capacitor is switched.

total capacitance. common mode remaining fixed during the conversion process. However. in terms of some figures of merit such as the total number of switches. Therefore.2) Figure 5-6: The top-plate waveform when using the monotonic switching algorithm [3] Summary and Comparison of the Monotonic Switching Algorithm with conventional and other algorithms The average energy consumption of the five switching schemes versus different number of bits is shown in Figure 5-8 [3]. which results in the necessary of another circuit (which will consume quite a lot power) to generate this voltage. The average switching energy of an n-bit monotonic switching algorithm can be derived as follows: ∑ (5. The common figures of merit that are used to evaluate switching algorithms are shown in Table 5-1 [3]. in this work. From this table. the monotonic switching algorithm will be chosen because of its efficient and non-requirement of additional voltage source. whether the switching scheme allowing rail-to-rail input swing. they require additional voltage source to provide common mode voltage. and energy consumption.46 Design and Implementation of Redundancy SAR ADC with Digital Background Calibration subsequent switching transition of the monotonic switching procedure is also more efficient than that of the conventional one. 46 . the IMCS and MCS algorithm are the best.

The first approach utilizing unit-element DACs implements the subbinary redundancy in digital control logic [34].2. 2 approaches have been proposed. a unit-element DAC increases the logic complexity of the ADC. successive 47 . i. [35]..1. [36] and [37]. by using sub-radix-2 approach [29]. In a more simple way.47 Design and Implementation of Redundancy SAR ADC with Digital Background Calibration Figure 5-7: Monotonic switching algorithm [3] 5. it requires a binary-to-thermometer decoder. due to the weighting of the DAC capacitors. Main DAC design To achieve 12-bit accuracy. The advantage of the technique is digital programmability/flexibility. a fully differential architecture is used to suppress the substrate and supply noise and has good common-mode noise rejection.2. However. which will increase the power of the circuit. redundancy can be built directly into the DAC.e. In a sub-radix-2 SAR ADC. To implement redundancy in SAR ADC.

a radix of 1. eliminating the extra decoding effort and circuit complexity. As described in chapter 4. to achieve an effective number of bit (ENOB) greater than 12 bits. By utilizing digital background calibration. The value of capacitors is shown in table 5-2. it enables an aggressive downsizing of the sampling capacitors in the 12-bit prototype to minimizing the power consumption and area.86 with 14 conversion steps was chosen. 48 . Figure 5-8: Comparing energy consumption of different switching algorithms [3] Table 5-1: Comparison of different switching schemes in terms of various figures of merit [3] In this work a sub-radix-2 architecture is utilized.48 Design and Implementation of Redundancy SAR ADC with Digital Background Calibration search ranges are sub-binary.

is here to help to keep is on is also boosted.2. ) is sampled by which boots node C to during sampling. It is a simple solution to eliminate the signal-dependency of the channel charge injection problem.2. The charge boosting path node C to node A which is turned on and off by . Because the gate of . and .49 Design and Implementation of Redundancy SAR ADC with Digital Background Calibration Capacitor Value (fF) 1715 922 496 266 143 77 41 22 12 6 3 2 1 Table 5-2: DAC capacitors value 5. Through . At the same time. the bottom plate (node ) are discharged to ground through (node C) is charged to is cut off by . and and . Sampling Network Design Figure 5-9 shows the bootstrap switch [38] implemented in this work. input signal ( turns on and charges node A to is higher than and . and top plate . it can handle voltage that . The gate-to-source voltage ( 49 ) of is now a constant . When sampling clock (clks) is low the gate of discharged to ground through B) boosting capacitor ( through When clks turns high. node B is charged to (node A) are . Meanwhile.

for proper function within the input common-mode voltage range from half to ground. Dynamic comparator design As shown in Figure 5-10. As Clkc goes to low (assume that and the current in ). both comparator outputs are reset to high. ( ) ( ) ( (5.3.Design and Implementation of Redundancy SAR ADC with Digital Background Calibration 50 which is ( ( . During the conversion phase. In addition. The operation of the comparator can be described as follow. . the sampling switch can also handle rail to rail input. with the boosted .4) VDD Clk_d+ M7 M3 C M 10 M4 M6 Clk_d+ M9 A M1 M5 CS MS V+ ( V-) B Clk_d+ V i+ ( V i-) M8 C DAC Figure 5-9: Bootstrap switch in [38] 5.3) ) ( ) (5. At the rising edge of the control signal sent by SAR control (Clkc). is turn on. the channel charge ( ) of the bootstrap switch are isolated from ) and on-resistance . a p-type dynamic latched comparator is implemented in this work. Thus. Because a dynamic comparator does not consume static current. it is suitable for energy efficient design. There are current that go through will increase more rapidly than the current in 50 and . and is less sensitive to substrate noise.).2. the comparator uses a p-type input pair. the input voltages of the comparator approach ground.

and sensitivity requirement of the dynamic latch. Preamplifier design Figure 5-11 shows the preamplifier schematic of the prototype ADC. This up. the differential outputs are then gated to trigger internal control signal which is feedback to turn off the comparator for additional power saving.2. It consists of 2 stages: The first stage is a Song’s preamplifier and the second stage is a resistively loaded pseudo-differential amplifier. In order to minimize the flicker noise.51 Design and Implementation of Redundancy SAR ADC with Digital Background Calibration Therefore the current in drives will cause the gate-source voltage of low and ultimately increase. Once the comparison is done. 5.4. As the comparator is idle in the sampling phase. VDD VBIAS Mb M7 M14 M8 Vp M1 M2 Vn M10 M12 Out_p Out_n M15 M9 M5 M3 M4 M6 M11 M13 gnd on Figure 5-10: Dynamic comparator with a current source. the signal “on” (Figure 5-12) is pulled high to shut off the bias current to save power. The total preamplifier DC gain is given by (5.5) The active-load NMOS transistors M3 and M4 in the first stage also act as the current mirror for the second stage to define its bias current. The preamplifier provides around 30-dB gain to relax the noise. 51 . the input pair of the first stage is PMOS. offset.

2. This flip flop uses only single clock and 2 clock transistors. The parasitic capacitor at gate of and is turn on while will be charged to is turn or discharged to ground depend on value of D. is off and is on. The operation of split-output TSPC flip flop can be described as follow. split-output True single Phase Clock (TSPC) flip flop as in Figure 5-12 is used because of its low power consumption compare to other types of flip flop. Voltage value of parasitic capacitor at gate decide voltage at gate of capacitor at gate of and and and and will . the flip flop is reset by pulling the gate of and ground. Flip flop design In this design.5. At this time up to and become 0. 52 .52 Design and Implementation of Redundancy SAR ADC with Digital Background Calibration VBIAS M11 on M7 M10 M9 V+ M8 M1 V- M2 R1 R2 R2 Vp Out_p Vn Out_n R1 M3 M4 M5 on M6 Figure 5-11: The schematic of the preamplifier 5. The value of input D will be stored in parasitic and can be taken out through 2 inverters made by . the flip flop operates as normal.5.2. which will result in small dynamic power consumption. The role of and the gate of and down to act as 2 inverters to make the output Q is stop the current go from through and to the ground (in case D=1. off. rst=1 and clk=0) to save power. When clk changes from low to high.1. When rst signal is low. When rst signal becomes high. When the clk is low. Control logic design 5.

Its operation can be described as follow.53 Design and Implementation of Redundancy SAR ADC with Digital Background Calibration rst M r1 M4 M1 Clk M2 M7 rst M5 M9 M r3 Q D rst rst M r5 M r2 M6 M3 rst M r4 M8 M10 Figure 5-12: Split-output True Single Phase Clock (TSPC) Flip Flop 5.2. 5.3. This makes the on signal become high and both comparator and preamplifier are turn off. The aclk signal is pulled low also and then the series of negative edge flip flop will generate the desire clock signal These clock signals will be used to control the switches of capacitor array.5. Clock generator The role of clock generator block shown in Figure 5-13 is generating the signals that allow the switches in the DAC work. This makes the signal Ready becomes low to indicate that comparator finish its work.2.2.5. signal ready change from low to high. When the comparator finishes comparing and . Comparator control logic The schematic of comparator control circuit is shown in Figure 5. 53 . The main function of this circuit is to turn off the comparator and preamplifier whenever the comparison is completed to save power. but 1 output is high and the other is low. When the comparator finishes the comparison. both output signals Out_p and Out_n are not low anymore.14 a).

b) Timing diagram 54 Q DFF D clk 13 Q clk 14 .54 Design and Implementation of Redundancy SAR ADC with Digital Background Calibration Rst_local aclk DFF VDD D Q DFF D clk 1 Q DFF D clk 2 Q DFF D Q clk 3 DFF D clk 4 Q DFF D clk 5 Q DFF D clk 6 Q DFF D clk 7 DFF Q D Q clk 8 DFF D clk 9 Q DFF D clk 10 Q DFF D clk 11 DFF Q D clk 12 comparator Out_p ready Out_n clk aclk a) Clk_d+ Clk_main clk ready aclk Rst_local clk 1 clk 2 clk 3 clk 4 clk11 clk 12 clk13 clk14 b) Figure 5-13: Clock generator a) Schematic.

If the output is high. If the output is low. b) Timing diagram 5. all . a static flip-flop samples the comparator output. At the falling edge of capacitors are reconnected to . To prevent unnecessary energy consumption and to keep the RC value the same.55 Design and Implementation of Redundancy SAR ADC with Digital Background Calibration preamplifier comparator Vcm+ Out_p Vcm- Out_n ready on Clk_main clks a) Clk_main clk ready on b) Figure 5-14: Comparator control circuit a) Schematic.5. the relevant capacitor is kept connected to . the sizes of the first six switch buffers are scaled down according to the driven capacitances and the buffers of the last three capacitors are unit size ones.15 At the rising edge of . Switch control logic The schematic of switch control logic is shown in Figure 5. This work uses an inverter as a switch buffer.2.4. the relevant capacitor is switched from to ground. 55 .

5. 2 LSBs for the first seven conversion steps.2.5. In this work. . This ideally results in dynamic error tolerances of 82. Figure 5-16 shows the implementation of DTC. 56 . Therefore. to exploit the error tolerance of the sub-radix-2 architecture.56 Design and Implementation of Redundancy SAR ADC with Digital Background Calibration Vref Clki Vpi Q buffer Out_p (Out_n) D Vcm+ (Vcm-) Case 1 Case 2 Clki Clki Out_p Out_p Vpi Vpi Figure 5-15: DAC Control Logic 5. the comparison threshold is pulled close to the midpoint of the redundancy range. the DTC effect is transient and (1) remains valid. The technique is only applied to the first seven bits in this design. the reuse of capacitor in DAC to implement DTC is proposed. However. the bottom plate of an capacitor in when the decision is in progress and is switched to branch will be tied to ground after the bit is resolved. Dynamic threshold comparison As mentioned in chapter 3. 44. An additional capacitor is needed to temporarily shift the threshold as in [4]. this will require additional capacitor and the area will increase as a result. To temporary shift the threshold.

57 Design and Implementation of Redundancy SAR ADC with Digital Background Calibration Vref Clk i Out_p (Out_n) Q D Vcm+ (Vcm-) Clk i-6 Clk i-7 Figure 5-16: Dynamic threshold comparison circuit 5. The block diagram of LMS block is shown in Figure 5-18. Digital calibration circuits In the block diagram of the calibration engine shown in Figure 5-3. It can be seen that the value of and will be update simultaneously at the rising edge of signal Update_w.9). These block diagram is used to implement the Equation (4. 57 . A folding structure is utilized to exploit natural serial output to implement the inner product block in digital calibration logic. the inner product blocks operate at the rate of the conversion steps.6. shown in Figure 5-17. The adder and the register accumulate either ( ) and this is or or depending on the polarity of .2.8) and (4. which is much higher than operation rate of the two adders and the LMS block.5. the power consumption of the inner product blocks dominates the power of the calibration circuits. Therefore.

error b i+ b i- D Q Wi D Q 2∆ d Wi Update_w Update_w Figure 5-18: Block diagram of LMS block 58 2∆ d .error µ∆.58 Design and Implementation of Redundancy SAR ADC with Digital Background Calibration D D Q d+ Q Clk_d + w13 ready w12 w11 d+ .d - MUX w2 w1 w0 bi Figure 5-17: Block diagram of the inner product block b i+ b iµw.

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6. other works fabricate the ADC first and then the calibration engine is implemented in software or FPGA. the simulation time need to obtain this amount of samples is too large. the simulated results of prototype chip will be presented.1. TSMC 0. large amount of samples are obtained at only about millisecond. By using hardware simulation. The circuit is present from architecture level to circuit block level. With the sine wave input signal.18µm Mixedsignal CMOS technology.1. The prototype 12-bit SAR ADC was implemented in a 1. The full results of SAR ADC with capacitor mismatches will be added later on. In this design. All the improvements such as the novel method to implement dynamic threshold comparison and calibration engine are discussed. Prototype Performance 6. Since the nature of least mean square algorithm in calibration engine require a lot of samples to obtain the optimal bit weights (about 22000 samples in [4]).1.60 Simulation Results Chapter 6 Simulation Results In Chapter 4.8V. 60 . Dynamic performance Analog to Digital Converter dynamic performance requires FFT (Fast Fourier Transform) test method to measure ENOB (effective number of bit) and SNDR (signal-to-noise plus distortion ratio). the output digital code will be transfer to spectrum through FFT transformation method. in this chapter. the implementation of SAR ADC is introduced. In this chapter. Thus. Normally. only simulation results of SAR ADC without calibration and capacitors mismatches are described. Matlab computing is used to simulate spectrum of output code with FFT transformation 4096 points.

61 .1. the maximum DNL and INL errors are +0. Static performance To simulate the static performance of ADC. Performance summary and comparison The overall performance of the prototype from simulation is summary and compare with others work in Table 6-1.78V is driven at the input while the sampling rate is still 100ksps.72LSB. From Figure 6-2.1.3.49/ − 2.8/−1LSB and +2. respectively. respectively. 6.2.61 Simulation Results With the sampling rate of 100ksps. This result is not so good but acceptable for the target SAR ADC.3 bit. Figure 6-1: The measured output spectra of the SAR ADC 6. the ramp input signal from 1. results in a SNDR and ENOB of 75.8 dB and 12.78V to 1. the measured output power spectral densities (PSDs) of the SAR ADC at Nyquist frequency input is shown in Figure 61. The dynamic performance of this ADC is quite good even at Nyquist frequency input.

2V 2.3V 1V 1.1 ENOB (bit) 11.9 Table 6-1: Comparison of the state-of-the-art works .025 31.016 FOM (fJ/C-S) 51.3 DNL (LSB) N/A 0.2V 1.5 11.62 Simulation Results Figure 6-2: The measured DNL and INL of the SAR ADC Ref [4] [5] [6] [7] This work Year 2011 2013 2007 2013 -- Source JSSC TCAS2 JSSC JSSC -- Technology 0.13µm 0.8/-1 INL (LSB) N/A 0.9 12.18µm 65nm 0.14 0.35µm 0.72 Total Power (mW) 3 0.7 30.49/-2.5 0.66 N/A 0.107 0.3 11 10.8V Resolution (bit) 12 12 12 14 12 Fs (MS/s) 22. 62 .1 0.3 209 165 164.38 0.1 80 0.18µm Supply (V) 1.25 0.68 N/A 2.

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high-resolution ADCs with low-power operation. SAR ADCs are favored due to their high energy efficiency. However. sub-radix 2 SAR ADC architecture combined with calibration engine is utilized. 64 . respectively. Since the require time for the hold ADC simulation is quite large. the resolution of SAR ADC is only medium compare to others. Among prevalent ADC architectures. only the prototype 12 bit redundant SAR ADC without capacitor mismatches and calibration engine has been simulated.7-µW power from a 1.1. To deal with this problem. archives 75. This combination provides a lot of advantages such as aggressive unit capacitor downsizing. Improvements to the calibration engine and dynamic threshold comparison implementation have been proposed to further improve the linearity as well as power consumption.8-dB signal-to-noise-plus-distortion ratio (SNDR) and maximum DNL and INL errors are +0.72LSB. With low sampling speed. error tolerant capability… and all the capacitors mismatch coefficients are identified with negligible hardware overhead and minimal modification of the original ADC circuits to calculate correctly the output code. while dissipating only 15. The ADC has been implemented in TSMC 0.8-V supply.8/−1LSB and +2. which is dominant by the capacitors mismatch.18µm Mixed-Signal CMOS technology.64 Conclusion and Future Works Chapter 7 Conclusion and Future Work 7. at 100ks/s.49/ − 2. Conclusion Touch panel for handheld device requires low-speed. the nonlinearity of the SAR ADC is static nonlinearity.

[32]. there are still many opportunities for improvement. Future work The overall performance of ADC has not been finished yet. Although this SAR ADC is able to archive better linearity compare to other works. Although the deterministic and zero-forcing nature of perturbation based calibration algorithm results in a much shorter convergence time compared to the correlation-based background calibration techniques [22]. Therefore. 65 .65 Conclusion and Future Works 7. the Inverted Merged Capacitor Switching Algorithm [3] can be utilized. Moreover. and the signal to noise ratio cannot be maximized. The main goal is to push the SAR architecture to achieve higher resolution while still being able to achieve lower power consumption. To deal with this problem. To solve these problems. this algorithm is sensitive to parasitic capacitances. the analog offset injection will reduce the dynamic range of SAR ADC.2. Though the monotonic switching algorithm has some advantages such as high power efficiency and non-requirement of addition power source. another way to add injection signal will be researched. it should be completed as soon as possible to evaluate the effect of digital background calibration and redundancy on linearity of SAR ADC. it is still not the most energy efficiency algorithm.

pp. Department of Electrical Engineering and Computer Science.P. “A 14b 80 MS/s SAR ADC With 73. Seung-TakRyu. 2013 [6] Verma. 2014. Decker. E. Hodges.com/patents/WO2014055807A1?cl=en [3] Albert Hsu Ting Chang. 10. Issue: 6. S. JunhuaShen . N.com/Sensors_and_Transducers/Image_Sensors_an d Optical_Detectors/Designing_touch_sensors_in_3D. 2661 – 2672.42.60. vol. 10. “All-MOS Charge-Redistribution Analog-to-Digital Conversion Techniques. “Low-Power High-Performance SAR ADC with Redundancy and Digital Background Calibration. Nov. vol. [4] Wenbo Liu. A. Massachusetts Institute of Technology. 1196 – 1205.Bibliography [1] http://www. 2011 [5] Seung-YeobBaek.” Circuits and Systems II: Express Briefs.google.350. pp.” Solid-State Circuits. Pingli Huang. pp. Dec. King. June 2007 [7] Kapusta. Baharav. no. D. Jae-Kyum Lee. [Online]. and D.. “A 12-bit. Suarez. Hongxing Li et al. 3-mW Redundant Successive Approximation-Register Analog-to-Digital Converter With Digital Calibration.” IEEE Journal of Solid-State Circuits. Issue: 9.” Doctor of Philosophy Thesis.” Solid-State Circuits. 45-MS/s. P. IEEE Journal of. R. Issue: 11. vol. “Pressure sensing touch system utilizing optical and capacitive systems” Apr. pp. . IEEE Journal of.48.electronicproducts. “An Ultra Low Energy 12-bit RateResolution Scalable SAR ADC for Wireless Sensor Nodes. 1975. Sept. J. Issue: 12. 46. 562 – 566. Available: http://www. 2013 [8] R. 3059 – 3066. Gray.aspx . S.” Solid-State Circuits. pp. II. “An 88-dB Max-SFDR 12bit SAR ADC With Speed Enhanced ADEC and Dual Registers.. June 2013. last access on31/3/2014 [2] I. Pikula. PCT/US2013/063. vol. Yun Chiu. vol. WO Patent App. . 66 .6 dB SNDR in 65 nm CMOS. Chandrakasan. 6. 379–385. IEEE Transactions on. IEEE Journal of.

vol. Aug. Li. “A Pipelined 13-Bit 250-KS/s 5-V Analog-to-Digital Converter. Dec. vol. “All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques. 1378–1381. pp. 2005. 67 .” in IEEE International Symposium on Circuits and Systems.[9] J.-Y. Gray.-S. vol. vol. 1988. Mar. Jin. I. 828–836. pp. 19.” IEEE Journal of Solid-State Circuits. 47. 2008. Gray. 1316–1323. Tompsett. pp. Gray. Hodges. 371–379. 6. M. 31. [17] H. [16] Y. Gray. vol. 10. and R. May 2005. 1984. vol. “A Self-Calibrating 15 Bit CMOS A/D Converter. Gray. pp. Brooks and H. [12] B. and K. and P. “Inherently Linear Capacitor Error-Averaging Techniques for Pipelined A/D Conversion. Nov. D. 2969–2979. Castello.-S. 23. pp. “A Ratio-Independent Algorithmic Analog-to-Digital Conversion Technique.” IEEE Transactions on Circuits and Systems I: Regular Papers. “A CMOS Ratio-Independent and Gain-Insensitive Algorithmic Analog-to-Digital Converter. Dec. 229–232. and R.” IEEE Journal of Solid-State Circuits. 55. Lee. 1324–1333. “Reference Refreshing Cyclic Analog-to-Digital and Digital-to-Analog Converters. M. Chin and C. [15] S.” IEEE Journal of Solid-State Circuits.-S. [10] L. pp. Lakshmikumar. pp. Dec. 1201–1207. Song. vol. [11] P.” IEEE Journal of SolidState Circuits. 19. McCreary and P. 1996. 1975. 2000.-Y. [18] L. 21. 1984. “A Digital Self-Calibration Algorithm for ADCs Based on Histogram Test Using Low-Linearity Input Signals. ISCAS 2005. Lee. “Background Calibration of Pipelined ADCs Via Decision Boundary Gap Estimation. 544–554. [14] S.” IEEE Journal of Solid-State Circuits.” IEEE Journal of Solid-State Circuits. pp. Chiu. vol. no. Dec.-C. [13] C.” IEEE Journal of Solid-State Circuits. P. Aug. 23. vol. Chen. pp. 1988. 813–819. Sutarja and P. Wu.” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. D. 1986. Geiger. Chin. pp. “A 12-Bit 1-MSample/s Capacitor Error-Averaging Pipelined A/D Converter. Shih and P.

2009 [27] W. “A 220mW 14b 40MSPS Gain Calibrated Pipelined ADC. pp. Liu. ESSCIRC 2001. 50. Ma.-K.” in Proceedings of the 27th European Solid-State Circuits Conference.-Y. O. Chiu. vol. [26] W.-T. Electrical and Computer Engineering in the Graduate College of the University of Illinois at UrbanaChampaign. 51.2003. Siragusa and I. “Background Calibration Techniques for Multistage Pipelined ADCs with Digital Redundancy. pp. Mar. Hsien. 2001. Chen. Moldsvor. 2005. pp. G. and Y. ESSCIRC 2005. 165– 168. “Gain Error Correction Technique for Pipelined Analogue-to-Digital Converters.” IEEE Transactions on Circuits and Systems I: Regular Papers. Chang. J. vol. 2010. Li and U. Apr. Galton. Boser.” Electronics Letters. Y. “A 600MS/s 30mW 0. Bjornsen. [20] E.[19] J.13µm CMOS ADC Array Achieving over 60dB SFDR with Adaptive Digital Equalization. [22] B. [25] Y. pp. 2005. Sept. Nikolic. “Low-power high-performance SAR ADC design with digital calibration technique” Doctor of Philosophy Thesis. and K. Dec. 2001. Eklund. B. [23] J. Sonkusale. Chen. pp.-W.” in Proceedings of the 31st European Solid-State Circuits Conference. Yang.-K. Lee. and P.-P. Liu. Saether. Nagaraj. 2040–2050. “Least Mean Square Adaptive Digital Background Calibration of Pipelined Analog-to-Digital Converters. E. pp. 38. 531–538. pp. 36. “Histogram Based Correction of Matching Errors in Subranged ADC. 68 . “True Background Calibration Technique for Pipelined ADC. Sept. Elbornsson and J.-K. and T. [21] J. Chiu. [24] S. T. Y. vol. Sept. W. 36. 555–558. S. Jan. Tsang. Van der Spiegel. 82–83.2000. C. Gray. 2003.” IEEE Journal of Solid-State Circuits.” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. pp. Moon. 786–788.2004. Murmann and B.” Electronics Letters. vol. Ytterdal.” in IEEE International Conference on Solid-State Circuits (ISSCC). 2000. 617–618. B. 38– 46. T. vol. “A 12-bit 75-MS/s Pipelined ADC using OpenLoopResidue Amplification.

10-bit. “A 12-bit 20-MS/s pipelined ADC with nested digital background calibration. D. “A 1. pp. Feb.13-µm CMOS. 176–177.455-461..” in IEEE Int. “A low-power 12-b analog-to digital converter with on-chip precision trimming.. Chang. 9. “A self-calibration technique for redundant A/D converters providing 16b accuracy. Liu. pp. M. 1981.” in Symposium on VLSI Circuits. “Digital cancelation of D/A converter noise in pipelined A/D converters.059 CMOS SAR ADC achieving over 90 dB SFDR. pp. Bradshaw. 301-304. and Y. G.” in IEEE ISSCC Dig.”IEEE J.2-V 10-b 20-Msample/s nonbinary successive approximation ADC in 0.” IEEE J. and R.13-µm CMOS process. 2008. no. Tech. 2003. 2002.35 GS/s. Tech.” in IEEE Journal of Solid-State Circuits. 10 b. pp. 175 mW time-interleaved AD converter in 0. Feb. [35] S. 409-412. 778–786.5/45 MS/s 3. Solid-State Circuits. 43.” in Custom Integr. 236–237. [34] F. “An error-correcting 14 b/20 s CMOS A/D converter. B. Apr. no. Papers. 14. Cicuits Conf. “A 12 b 22.3-MS/s CMOS pipeline analog-to-digital converter. no. pp. and P. Lewis.. Kuttner. II. 5. K. Lin. “A 1. pp. 34.” IEEE Trans. 2008. Feb. vol. [32] I.-S Tan. Huang. Hurst. M. Papers. 47.5-V. Abo and P. May 1999 69 .” in IEEE ISSCC Dig.”inIEEE ISSCC Dig. Galton. Tech. [31] C. 1993. Circuits Syst. [36] W.” in Custom Integr. 380–381 [37] Z. 4. De Wit. and Y. P. Wang. Sep.-Y.-J. ”A 1. R. vol.599-606. Louwsam et al. [33] C. “Background ADC calibration in digital domain. 28. “A 0. vol. Gray. Liu. Huang. Sep.0 mW 0. Boyacigiller. pp. no. K Hester. Solid-State Circuits. June 2009. and S..[28] M. Mar. 1988. [29] D. 4. 204-205.-H. Weir. Draxelmayr. [30] X. pp. G. Solid-State Circuits Conf. 2000.-Z. S. vol. 62–63 [38] A. 2010. Papers. P. Circuits Conf..-C. Apr. pp. Tsang et al. Chiu.13-µmCMOS. Feb. 185-196.-J. pp. pp.92mW 10-bit 50MS/s SAR ADC in 0.