12IS44

R. V. COLLEGE OF ENGINEERING
(Autonomous Institution under VTU)
VI Semester B. E. Examinations, May/Jun 14

Computer Organization and Architecture
(Model question paper )
Time: 03 Hours

Maximum Marks: 100

Instructions to candidates:
1. Answer all questions from Part A. Part A questions should be answered in first 3 pages of
the answer book only
2. Answer FIVE full questions from Part B.
Part – A
1.1
1.2
1.3

The ____________ are used to designate the source or destination of the data on the data bus.
What is thrashing?

1.4
1.5
1.6
1.7
1.8
1.9
1.10
1.11

The performance of cache memory is frequently measured in terms of a quantity called
Draw the typical DRAM cell
What is soft error with respect to memory?
Expand RAID
What is the international reference alphabet ?
Express -1/32 in IEEE 32-bit floating point format
What is the sign-extension rule for twos complement numbers?
Consider the following operation on a binary word. Start with the least significant bit. Copy all bits
that are 0 until the first bit is reached and copy that bit, too. Then take the complement of each bit
there after. What is the result?
What is a delayed branch?
What is the relationship between instructions and micro-instructions?
What is the purpose of control memory?
What is the difference between a hardwired implementation and a microprogrammed implementation
of a control unit?
What is the function of HOLDA ?
Expand MISD
What is interleaved multithreading ?
Give one benefit of clustering
What is passive standby ?

1.12
1.13
1.14
1.15
1.16
1.17
1.18
1.19
1.20

If the main memory is of 8K bytes and the cache memory is of 2K words. It uses associative
mapping. Then each word of cache memory shall be ______ bits

Briefly describe the three possible approaches to cache coherency.777 * 102 OR List four alternative methods of rounding the result of a floating-point operation. biased. Briefly explain the following representations: sign magnitude. OR Describe the implementation of the multiply instruction in the hypothetical machine designed by Wilkes. 4 8 4 How does SDRAM differ from ordinary DRAM ? Write characteristics of Winchester Disk Format.12IS44 Part . Your ALU can add its two input registers. 5. Assume a microinstruction set that includes a microinstruction with the following symbolic form: where is the sign bit of the accumulator and are the first seven bits of the microinstruction.566 * 102 + 7. Numbers are to be stored in two’s complement representation. which branches if the AC 0 is negative. Provide a typical list of the inputs and outputs of a control unit. Use narrative and a flowchart. write a microprogram that implements a Branch Register Minus (BRM) machine instruction.B 2 a b c 3 a b 4 a b c 5 a b c 6 a b c 7 a b c 8 a b c 9 a b List andexplain the classes of interrupt Elicit with timing diagram data transfer on the PCI Draw the bus configuration in high-performance architecture OR Discuss set associative Mapping Cache Organization with a neat diagram. 04 06 06 Describe the geometric depection of twos complement integers Draw the Hardware Implementation of Unsigned Binary Multiplication Show how the following floating-point additions are performed (where significands are truncated to 4 decimal digits). but it cannot subtract. The interface of the device includes two ports: one for status and one fo r data output. twos complement. Show the results in normalized form. How long does it take to scan and service the device given a clocking rate of 8 MHz? Assume for simplicitythat all pertinent instruction cycles take 12 clock cycles. Explain how redundancy achieved in RAID system? OR Draw the flow chart of simple interrupt processing Describe with neat diagram the characteristics of I/O channels A microprocessor scans the status of an output I/O device e very 20 ms. List the micro-operations your control unit must perform to cause a subtraction. Assume that bits C1 through Cn of the microinstruction specify a parallel set 04 10 06 06 06 04 04 06 06 08 04 08 04 . Write the six stage CPU Instruction pipeline 07 04 05 Explain the distinction between the written sequence and the time sequence of an instruction. This is accomplished by means of a timer alerting the processor every 20 ms. and it can logically complement the bits of either input register. Using this microinstruction.

execute. Why are they not needed in a microprogrammed control unit? c 10 a b 11 a b c Give the A Taxonomy of Parallel Processor Architectures Explain the different approaches to executing Multiple Threads OR Let α be the percentage of program code that can be executed simultaneously by n processors in a computer system. Assume that the remaining code must be executed sequentially by a single processor.12IS44 of micro-operations.Two 1-bit flags designate the current phase in a hardwired implementation. NUMA. indirect. Each processor has an execution rate of x MIPS. and CC-NUMA? *************** 04 06 10 08 04 04 . (i). in terms of n. a. Express the program symbolically A simple processor has four major phases to its instruction cycle: fetch. (ii) If n = 16 and x=14 MIPS. α and x. determine the value α of that will yield a system performance of 40 MIPS. Derive an expression for the effective MIPS rate when using the system for exclusive execution of this program. and interrupt. What are some of the potential advantages of an SMP compared with a uniprocessor? What are the differences among UMA. Why are these flags needed? b.