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Mitigation of Capacitor Banks Switching Transients considering

Injected Harmonics
Meisam Sadeghi*, Ebrahim Babaei **, Mehrdad Rabetian* and Habiballah Nahalparvari*
*Tabriz Power Electrical Distribution Company, Hakim Nezami St. Valiasr, Tabriz, Iran.

Maisam_Sadeghi@ieee.org, Rabetian.m@gmail.com
**Faculty of Electrical and Computer Engineering, University of Tabriz, 29Bahman Boulevard, Tabriz, Iran.

e-babaei@tabrizu.ac.ir

Abstract: Installing capacitor banks in electric power systems


provide well known benefits, including reactive power
compensation, voltage support and power factor correction.
However, the capacitor banks modify the harmonic voltages
and currents in the network and give rise to current and voltage
transients. These transients, reach in harmonics, may be
harmful for the capacitor and become an increasing concern for
both electric utilities and customers since its switching usually
occurs quite frequently. In this paper, firstly, transients caused
by capacitor bank switching for a specific part of Uraemia
(IRAN) Power Network which has recently been installed in
132kV level, especially from the view point of harmonic
spectrum and THD (Total Harmonic Distortion) are analyzed
and contemplated. After that, the role and effect of some
common methods in harmonic spectrum and THD mitigation
are contemplated and compared.

Keywords: Capacitor
harmonics, THD.
1.

bank

switching,

Also it can cause increase in the duty on switching


devices, which may be stressed beyond the specified
ratings in American National Standards Institute
(ANSI)/IEEE standards [4].
Observations show that if voltage magnification
happens in the network, the over voltage can increase
even to 2pu-4pu to the various range of low voltage
capacitor banks.
As mentioned above, not only switching of capacitor
banks effects on over voltages and inrush currents are to
be considered, but also injected switching harmonics
especially in the case of series resonance of capacitor
banks must be paid attention to.

transients,

Introduction

Shunt capacitors supply reactive power and boost local


voltages. They are used throughout the system and are
applied in a wide range of sizes. The main advantages of
shunt capacitors are their low cost and their flexibility of
installation and operation [1, 2].
Shunt capacitors are used extensively in distribution
systems for power-factor correction and feeder voltage
control [1]. Shunt capacitors are also used to compensate
the inductive losses in transmission systems and to ensure
satisfactory voltage levels during heavy loading
conditions.
The application of shunt capacitors can lead to the
effects like: Bring about severe harmonic distortion and
resonance with load-generated harmonics [3]; Increase
the transient inrush current of power transformers in the
system [1], create over voltages, and prolong its decay
rate ; put stress on capacitor themselves due to switching
transients [1]; Discharge into an external fault, and
produce damaging over voltages across currenttransformer (CT) secondary terminals; and Impact
sensitive loads, i.e., drive systems, and bring about a
shutdown [2].

Adding capacitors will cause the power system to be


tuned to a specific harmonic. This is known as parallel
resonance between the capacitors and the source
inductance (including the transformer). A parallel
resonance presents high impedance to injected harmonics
near the resonance frequency.
The resonance frequency of a capacitor can be
estimated by [5-7]:

f r = f system

short

circuit

(1)

rated

S short circut = 3V LL I sc
Where:
fr:

is the resonance frequency.

fsystem:

is the power system frequency.

(2)

Sshort-circuit: is the short-circuit power (MVA) at the point


where the capacitor is to be connected.
Qrated:

is the rated reactive power.

VLL :

is the line voltage (kV).

I sc :

is the short circuit current at the point where

the capacitor bank is to be connected (kA).


The methods used for decreasing the effects of
capacitor banks switching can be classified into two main
groups. The first group includes methods that are used to
mitigate the effects of capacitor banks switching, and the
second group includes methods that are used to prevent
parameters that intensify and worsen these effects. Some
of the common methods can be summarized as follows
[3, 5, 6, and 8]:
1. Inductances or resistances in series with power
breakers,
2. Pre-insertion resistances,
3. Pre-insertion inductances,
4. Applying synchronous switching control in order
to prevent transients,
5. Applying MOVS (metal oxide varistors),
6. Using power switches like SF6 breakers.
In [9] a new and cost-effective method using
sequential switching scheme for mitigating the transient
over-voltages occurring due to capacitor switching is
presented.
The method utilizes neutral grounding
impedance connected at the neutral point of the switched
capacitor bank together with sequential pole switching.
In [1] a resistance is used to decrease the harmonics at the
cost of loss, also this method cant decrease the initial
voltage peak suitably. In [5], the reasons of generation
and increase of capacitor banks switching transients are
carefully analyzed through mathematic equations and the
results of applying series resistance and inductor have
been presented, but voltage peak and amplitude analysis
is only included. In [10] the principle of controlled
switching for three-phase shunt capacitor banks with
ungrounded neutral and using Vacuum Circuit Breaker is
introduced.
The methods presented in these papers that are mainly
discussing about reduction of capacitor bank switching
transients are just focusing on transient voltage peaks and
its reduction. They dont take injected harmonics and
THD into consideration and if they include any harmonic
analysis, the methods that are suitable for transient
voltage peak reduction are used for harmonic and THD
mitigation so the necessity of an economical method that
can deal properly both with transient over voltages and
injected harmonics, is undeniable.
The role and importance of transient analysis and
especially harmonics and distortions on voltage and
current waveforms generated by capacitor bank switching
which can effect the power quality particularly on
distribution section, (that is full of sensitive electrical
appliances which are being increasingly used in power
networks) reveals the necessity of analyzing these
switching transients which wildly occur in power
systems.

Therefore, in this paper, these transients will be


analyzed in a sample system and some methods for
switching transients mitigation with their advantages and
disadvantages especially on harmonic and THD
reduction, will be presented.
2.

Analysing Capacitor Banks Switching


Transients in a Sample System

In this section, a part of Uremia power system (Iran)


that has recently been equipped with capacitor banks in
132kV voltage level will be contemplated for its
switching transient. The single line diagram of this
network is given in Fig. 1.
Bus 42
(20 kV )

Bus 72
(132 kV )

Load Bus
(20 kV )

12 MVAr
30 MW

0.5MW
Line 15.3km

38.8MVA

/Y
20 / 132 kV
30 MVA

0.196 0.02154 H

BRK 1
Main CB
18MVAr
4 F

Y /Y
132 / 20 kV

BRK 2
PF CB

0.5MVAr

Fig 1: Simplified single line diagram of the sample power system

The length of the line, where the capacitor banks have


been installed, is 15.3km and the generator works at
maximum power of 38.8MVA at bus bar 42 which is 20
kV and is connected to bus bar 72 through a 20/132kV,
30MVA transformer. In bus bar 72, two 18MVAr
capacitor banks are installed at the beginning of the three
phase-one circuit 132kV transmission line. The line is
15.3km long.
As it is seen in Fig. 1, transmission lines, capacitor
banks and other components are replaced with equivalent
RLC circuits and the line parameters have been
calculated per km as follows:
R = 0 .132 ,
L = 14.08 104 H , and C = 8.118 109 F . The load of line
for 20kV voltage level is 30MW and 12MVAr on average
according to network load reports. A 0.5MVAr capacitor
bank on 20kV voltage level is also assumed to be used
for power factor correction.
In order to simulate the effects of capacitor banks
switching on voltage and current of network using EMTP
PSCAD4.2.1 software, the low voltage capacitor bank
has been energized at 30ms and the high voltage
18MVAr capacitor bank is switched at 70ms.
As it is seen in Fig. 2, when the high voltage capacitor
is switched at 70ms while the low voltage capacitor bank
is in the circuit, a distortion takes place in voltage and
current waveforms which lasts for about 4 cycles. This
distortion generates a transient over voltage with the peak
amplitude of 30.096kV which is equal to 1.88pu in load
bus voltage and consequently results in an inrush current
with the peak amplitude of 0.3kA which is equal to
2.18pu in load bus current.

30
20
10
0
-10
-20
-30

According to above-mentioned calculations, the


harmonics which will have maximum amplitude at
switching moment is near the forth harmonic.
Injected harmonics in first cycle after switching and
THD are given in Fig. 3.

V load bus[kV]

Load voltage harmonics


14.0

0.000

0.025

0.050

0.075

0.100

0.125

0.150

a)

0.40
0.30
0.20
0.10
0.00
-0.10
-0.20
-0.30
-0.40

I load bus[kA]
-0.0

[4] 8.70911

a)

100

0.000

0.050

0.100

0.150

0.20

b)

It is necessary to mention that apart from over voltages


and inrush currents, the harmonics that are injected to the
network caused by capacitor bank switching can
generally excess IEEE 519-1992 AND ENRE 184/00
standards for THD and harmonics. Thus harmonic
analysis of the capacitor bank switching will be taken
into consideration. Therefore, equivalent harmonics of
resonance frequencies are calculated as follows:
Resonance frequencies are calculated from equations
(1) and (2) in this way as follows:
So the resonance frequency of 18MVAr capacitor
bank is:
3 132 10 3 1 . 5 10 3
= 218 . 24 Hz
18 10 6

In order to calculate the main switching injected


harmonic to the transmission line, the resonance
frequency should be divided to main system frequency as
shown in (3) [10]:
H =

fr
fs

80
60
40

Fig. 2: a) Voltage and b) current of load bus when 18MVAr capacitor


bank is switching

f r = 50

THD of load voltage

(3)

So the main switching harmonic will be calculated in


this way:
218 . 24
H =
= 4 .3 4
50

20
0
0.060 0.080 0.100 0.120 0.140 0.160 0.180 0.200
b)
Fig 3: a) Harmonics and b) THD of load bus voltage when 18MVAr
capacitor bank is switching

As it is seen in Fig. 3, with the switching of capacitor


bank, the main generated harmonics are the 3rd, 4th and 5th
ones. These generated harmonics are dependent on the
maximum power that each line can transmit and also the
capacity of the banks [4]. The generated THD also
increased after switching by 78% and fades after 130ms
(about 5 cycles).
As the use of electrical appliances and loads which are
sensitive to distortions caused by harmonics, is
increasing, analysis of these distortions and ways of their
prevention becomes more important. Paying attention to
the popularity of capacitor banks in whether distribution
or transmission lines. It can be said that the switching of
these banks can play a very important role in harmonic
and distortion occurrence.
3.

Analysing the Common Methods of Reducing


Capacitor Bank Switching Effects on Harmonic
Distortion and Generated THD

In this section, the role and importance of methods like


series inductance and resistance, pre-insertion impedance
and also synchronous switching control in harmonics and
THD mitigation are contemplated.
It is notable that permanent series impedance increases
losses, while applying pre-insertion method can minimize
losses. Synchronous switching needs an accurate control
circuit to be designed in order to recognize the

R optimum

1
2

(4)

LS
C

In Fig. 4, four methods of series resistor, series


inductance, pre-insertion R&L and synchronous
switching control are compared from the view point of
their effectiveness on reduction of 3 main generated
harmonics (3rd, 4th and 5th) when capacitor bank is
switched.
a)s eries R , b)s eries L, c )pre-ins ertion R & L, d)s y nc horonous s w ithc ing
generated harm onic s in firs t c y c le after s witc hing
14

b c

a)
b)
c)
d)

12

Voltage [kV]

10

s e rie s R
s e rie s L
pre -in s e rtion R & L
s yn ch oron ou s s with cin g

4
H arm onic s

Fig. 4: Harmonics of load bus voltage when 18MVAr capacitor bank is


switching and equipped with (from left to right): a) series R b)
series L c) pre-insertion R&L d) synchronous switching

As it is seen in Fig. 4, applying a series resistance


( 10 ) decrease the amplitude of the harmonics (3rd, 4th
and 5th) by 18%. The resistance must be less than 15 in
order to keep losses in an acceptable range. Applying a
series inductor decreases the amplitude of the harmonics
by 50%, but it is necessary to mention that applying this
element shifts the generated harmonics toward first
harmonic which results in a bigger filter size. Applying
pre-insertion method with 80 resistance according to
equation (4), causes the same problem, but mitigates the
amplitude of the harmonics by 80%. Synchronous
switching decreases the amplitude of harmonics by 75%
and also doesnt have the problem of generated
harmonics movement toward fundamental harmonic.
In Fig. 5 the effect of the above-mentioned methods on
THD is given while the capacitor bank is switched on the
system.
Fig 5 shows that series resistant have the least effect
on THD peak mitigation. Using series inductor mitigates
THD peak by 40% but it damps less slowly. Applying
both pre-insertion R&L and synchronous switching

decreases THD peak by 70% and the damping is


appropriate as well.

THD (%)

appropriate time of switching and will increase the


expenditure consequently.
The appropriate values of R and L can be calculated
practically. The optimum amount of resistance for preinsertion impedances can also be deriven from this
equation [5, 6]:

Fig 5. THD of load bus voltage when 18MVAr capacitor bank is


switched and equipped with: a) series R, b) series L, c) pre-insertion
R&L, d) synchronous switching

4. Conclusions
In this paper, capacitor bank switching transients,
especially when voltage magnification occurs, were
analyzed. The results show that generated harmonics and
THD can have adverse effects on network and loads,
unless switching transients are anticipated and controlled.
Applying common switching transients mitigation
methods such as series resistor, series inductor, preinsertion R&L and synchronous switching reveals that
simultaneous use of series resistor and inductor in the
form of pre-insertion with proper values is an effective
and economical approach.
And in the case of choosing each method these
statements can be taken into consideration:
As the amount of resistance increases, THD and
amplitude of generated harmonics mitigate but
losses increase.
As inductance increases, the amplitude of
generated harmonics decreases even more, but the
harmonics come nearer to the fundamental
harmonic and also THD damps more slowly and
remains more in the system.
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