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NES Cart Types

--- ---- ----By:


Kevin Horton

I have devised a few naming conventions to make describing how the NES
'ticks' easier. I'll try to use conventional names where applicable,
but I had to create some new ones. If possible, I use Nintendo's own
naming conventions; i.e. MMC, CHR ROM, etc.
CIRAM: This is the internal 2K of video RAM located at 0000-1FFF in the
PPU's address space. It stands for 'Character Internal RAM'
P-ROM: Same as PRG ROM, or VROM.
C-ROM: Same as CHR ROM.
C-RAM: Same as CHR RAM.

PPU access: You have A0-A13, /A13, D0-D7, /WR and /RD. A13 is usually
connected to /CE of the CIRAM to enable it for addresses 0000-1FFF.
Likewise, /A13 is usually used to enable the C-ROM or C-RAM on the cart
(which is then mapped into 2000-3FFF).
Related to the PPU is the CIRAM. You have two lines of it to use as you
see fit. There are many ways they can be put to use...
1) You can disable the CIRAM all together by pulling pin 57 high. You can
then place 4K of RAM onto the bus with it's /CE tied to pin 58. This
will place that 4K of RAM at 0000-1FFF. Gauntlet is an example of a cart
that does this. (The carts I've seen use a 6264 8K RAM with A12 tied
low so it's effectively 4K).
2) Horizontal / Vertical mirroring. A10 of the CIRAM was brought out to
the cart edge for just this reason. If you tie it to A10, you'll get
vertical mirroring; since the first two banks will be in sequence.
However, if you tie it to A11, you'll get horizontal mirroring; adjacent
twin banks will be the same.
3) The MMCs can control the A10 line of the CIRAM to change either the
screen or mirroring type on the fly.
4) The LS161 mappers can change the state of the A10 line; however why
this would be desireable is anyone's guess. :-)
Cart Pinout:
-----------Top
Bottom
----------------------------

+-------+
|01 37| CLK 21.47727Mhz (NTSC)
|02 38| M2
|03 39| PRG A12
|04 40| PRG A13
|05 41| PRG A14
|06 42| PRG D7
|07 43| PRG D6
|08 44| PRG D5
|09 45| PRG D4
|10 46| PRG D3
|11 47| PRG D2
|12 48| PRG D1
|13 49| PRG D0
|14 50| PRG /CE (/A15 & /M2)
|15 51| EXP 9
|16 52| EXP 8
|17 53| EXP 7
|18 54| EXP 6
|19 55| EXP 5
|20 56| CHR /WR
|21 57| CIRAM /CE
|22 58| CHR A13
|23 59| CHR A7
|24 60| CHR A8
|25 61| CHR A9
|26 62| CHR A11
|27 63| CHR A10
|28 64| CHR A12
|29 65| CHR /A13
|30 66| CHR D7
|31 67| CHR D6
|32 68| CHR D5
|33 69| CHR D4
|34 70| SECURITY
|35 71| SECURITY
|36 72| GND
+-------+
Cartridge Connector

GND
PRG A11
PRG A10
PRG A9
PRG A8
PRG A7
PRG A6
PRG A5
PRG A4
PRG A3
PRG A2
PRG A1
PRG A0
PRG R/W
/IRQ
EXP 0
EXP 1
EXP 2
EXP 3
EXP 4
CHR /RD
CIRAM A10
CHR A6
CHR A5
CHR A4
CHR A3
CHR A2
CHR A1
CHR A0
CHR D0
CHR D1
CHR D2
CHR D3
SECURITY
SECURITY
+5V

Expansion Connector: (found on the underside of the NES unit)


-------------------------------------------------------------

+5V
GND
Audio In
R/W
A15
cart con. pin #51
Cart con. pin #52
Cart con. pin #53
Cart con. pin #54
Cart con. pin #55
/OE for stick 2

+-------\
|01 48|
|02 47|
|03 46|
|04 45|
|05 44|
|06 43|
|07 42|
|08 41|
|09 40|
|10 39|
|11 38|

+5V
GND
NC
Out2
Out1
Out0
Cart
Cart
Cart
Cart
Cart

(from CPU)
(from CPU)
(from CPU- strobe on sticks)
con. pin #16
con. pin #17
con. pin #18
con. pin #19
con. pin #20

Player #1 D1
Player #1 D3
/IRQ
Player #2 D2
Player #2 D3
/OE for stick 2
Player #2,D4
Player #2,D0
Player #2,D1
Audio out
Video out
+9V
4.00MHz CLK

|12 37| /OE for stick 1


|13 36| Player #1 D4
|14 35| Player #1 D0
|15 34| /OE for stick 1
|16 33| Player #1 D2
|17 32| D0
|18 31| D1
|19 30| D2
|20 29| D3
|21 28| D4
|22 27| D5
|23 26| D6
|24 25| D7
+-------/
Expansion Connector

Joypad Connector (player 1 and player 2 have identical pinouts)


--------------------------------------------------------------GND
CLK
Strobe
D0

+|O\
|OO\ - +5V
|OO| - D3
|OO| - D4
+--+

Joypad connector (front view)


D0, D3 and D4 connect to the data bus via a 74368 hex inverting tristate
buffer. The strobe line of both pads connect to pin 39 of the CPU.
CLK is connected to the /OE line of it's respective 74368, which also
connects to either pin 36 or 35 of the CPU depending if it's player
#1 or #2 (respectively).
Each pad contains a 4021 8-bit shift register. To read the button
states, you first pull pin 39 high then low:
LDX #$01
STX $4016
DEX
STX $4016
You then read $4016 (or $4017 for player 2) to get the button status
one button at a time (Each read clocks the shift register, getting the
next data bit ready to be read). Some games require exactly $40 or
$41 to be returned from an LDA $4016 (or $4017). This is bad coding
style, since only D0-D4 are connected. So, the upper three bits
are supposidly 'undefined'. However, if you examine exactly what's going
on, you can see why it returns $40 or $41.
Since the inputs to the tristate buffer are all pulled high via resistors,
and that the buffer is inverting, you will see the lower 5 bits as 0 when
they are read. Since D4-D1 are usually not used (only the light gun and
expansion connector connect to them) and D0 is the data input from the

joypad, the lower 5 bits will be either 00000b or 00001b depending on if


a button is down (1) or up (0). So, that takes care of D0-D4. D5-D7 are
not connected to anything related to joypad reading, so they will pick up
'garbage' off the data bus during a joypad read. But, they always seem to
pick up 010xxxxxb (where xxxxx is from the joypads). If we examine the
opcodes that the processor executes, it will be clear:
8100: $A9 ;opcode for LDA
8101: $16 ;lower byte of address
8102: $40 ;upper byte of address
As you can see, the last byte that happens to hit the data bus *right*
before the read is $40 - the same value we see when we do a joypad read!
This is because the capacitance of the data line 'stores' the value that
was last on it in the stray capacitance of the drivers, circuit traces,
cart connector, etc.
To test the theory is pretty simple. Instead of doing an LDA $4016,
do an indirect LDA instead:
8100:
8102:
8104:
8106:
8108:

LDA
STA
LDA
STA
LDA

#$16
$80
#$40
$81
($80)

Because this takes more space and more cycles than a simple LDA $4016,
this method is of course never used. It can be used to detect if you're
running on an emulator or not though. ;-) The 'correct' way to read the
joypad is:
8100: LDA $4016
8103: AND #$01
This will strip the invalid bits and avoid any chance for error. The
way *I* would read the pads is like so:
8100:
8102:
8104:
8107:
8108:
810B:
810E:
810F:
8110:
8111:
8112:
8113:
8115:

LDY
LDX
STX
DEX
STX
LDA
ROR
TXA
ROL
TAX
DEY
BNE
RTS

#$08 ;Number of iterations


#$01
$4016 ;store 1 out the strobe
$4016 ;store 0 out the strobe
$4016 ;read the button
;transfer it to the carry flag
;rotate X left, storing the bit into the lowest pos.
810B

;loop 8 times for all 8 buttons


;return acc with status of all 8 buttons

This piece of code first strobes the sticks to 'lock' the button values
in, then it grabs the first button status and rotates it into the carry
flag. The X register is then transferred to the Acc. so the button
value can be shifted into it. It's moved back to X, and the Y register
is decremented once. The whole cycle repeats 8 times, whereby a complete
byte is formed containing the status of all 8 buttons.

Chip pinouts
------------

Signal types are listed in parenthesis:


(r)
(s)
(n)
(w)

this
this
this
this

line
line
line
line

goes to the ROM only.


is Shared between the ROM, MMC/chip, and Nintendo
connects to the NES cart edge only, and not the ROM
connects to the WRAM only and nowhere else

MMC1 Chip:
(24 pin shrink-DIP)
---------Comes in several varieties: 'MMC1', 'MMC1A', and 'MMC1B2'

PRG A14
PRG A15
PRG A16
PRG A17
PRG /CE
WRAM CE
CHR A12
CHR A13
CHR A14
CHR A15
CHR A16 (r) or WRAM /CE

(r)
(r)
(r)
(r)
(r)
(w)
(r)
(r)
(r)
(r)
(w)
GND

.---\/---.
|01
24|
|02
23|
|03
22|
|04
21|
|05
20|
|06
19|
|07
18|
|08
17|
|09
16|
|10
15|
|11
14|
|12
13|
`--------'

+5V
M2
PRG A13 (s)
PRG A14 (n)
PRG /CE (n)
PRG D7 (s)
PRG D0 (s)
PRG R/W
CIRAM A10 (n)
CHR A12 (n)
CHR A11 (s)
CHR A10 (s)

MMC1
MMC2 Chip:
(40/42 pin shrink-DIP)
---------Comes in one flavour: 'MMC2 RD387-001'

PRG A14
PRG A13
PRG A15
PRG A14
PRG A12
PRG A13
PRG A16
PRG /CE
PRG D4
PRG D3
PRG D0
PRG D1
PRG D2
PRG R/W
PRG /CE

GND
M2
(n)
(n)
(r)
(r)
(s)
(r)
(r)
(r)
(s)
(s)
(s)
(s)
(s)
(n)
(n)

.----\/----.
|
|
|XX
XX|
|01
40|
|02
39|
|03
38|
|04
37|
|05
36|
|06
35|
|07
34|
|08
33|
|09
32|
|10
31|
|11
30|
|12
29|
|13
28|
|14
27|
|15
26|
|16
25|

+5V
+5V
GND
CIRAM A10 (n)
CHR A15 (r)
CHR A12 (r)
CHR A14 (r)
CHR A12 (n)
CHR A13 (r)
CHR A16 (r)
CHR A8 (s)
CHR A5 (s)
CHR A9 (s)
CHR A4 (s)
CHR A11 (s)
CHR A3 (s)
CHR A7 (s)

CHR /RD (s) - |17


24|
CHR A0 (s) - |18
23|
CHR A6 (s) - |19
22|
GND - |20
21|
|
|
`----------'

CHR
CHR
CHR
CHR

A2 (s)
A10 (s)
A1 (s)
/CE (s)

MMC2
(note: the pins marked with 'X's are optional; they are only used if
the MMC2 were to be 42 pins instead of 40.)
MMC3 Chip:
(44 pin QFP)
---------Comes in three types: 'MMC3A', 'MMC3B', and 'MMC3C'
33
23
|
|
.-------.
34-|
|-22
| MMC3B |
44-|
|-12
\-------'
|
|
1
11
Pin# Function
---- -------1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

Pin# Function
---- --------

??? *1
23
CHR A10 (r) 24
CHR A12 (n) 25
CHR A11 (n) 26
CHR A10 (n) 27
GND
28
CHR A13 (r) 29
CHR A14 (r) 30
CHR A12 (r) 31
CIRAM A10 (n)*32
CHR A15 (r) 33
CHR A17 (r) 34
/IRQ
35
PRG /CE (n) 36
GND
37
??? *2
38
PRG R/W (n) 39
PRG A15 (r) 40
PRG A13 (r) 41
PRG A14 (n) 42
PRG A16 (r) 43
PRG A14 (r) 44

PRG A17 (r)


PRG A13 (n)
PRG A18 (r)
PRG /CE (r)
+5V
GND
M2
WRAM /CE (w)
PRG D7 (s)
PRG A0 (s)
PRG D6 (s)
PRG D0 (s)
PRG D5 (s)
PRG D1 (s)
PRG D4 (s)
PRG D2 (s)
PRG D3 (s)
GND
WRAM CE (w)
WRAM /WE (w)
CHR A11 (r)
CHR A16 (r)

*: On Gauntlet, this is unused.


*1: PINS 1 & 2. Sometimes these are connected together. If they are not,

pin 1 is left floating.


*2: PIN 16. Sometimes this is connected to ground. Other times it is left
floating.
It seems that pins 1,2 & 16 are related; pins 1 & 2 are shorted as are pins
15 and 16. Or else pisn 1 & 2 are left open as well as 15 & 16. I've never
seen say, pins 1 & 2 shorted while pin 16 was open or vice-versa. I suspect
they relate to extra RAM in the CHR section.
MMC4 Chip:
---------No info as of yet- tell me which carts have MMC4's in 'em!
MMC5 Chip:
(100 pin QFP)
---------Only comes in one type: 'MMC5'

80
51
|
|
.----------------.
81-|
|-50
|
MMC5
|
100-|
|-31
\----------------'
|
|
1
30
Pin# Function
---- --------

Pin# Function
---- --------

Pin# Function
---- --------

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48

51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73

RC0
RC1
RC2
+5V
CHR
CHR
CHR
CHR
CHR
CHR
CHR
CHR
CHR
CHR
CHR
CHR
CHR
CHR
CHR
CHR
CHR
CHR
CHR

*1
*1
*1
A0 (s)
A1 (s)
A2 (s)
A3 (s)
A4 (s)
A5 (s)
A6 (s)
A7 (s)
A8 (s)
A9 (s)
A10 (r)
A11 (r)
A12 (r)
A13 (r)
A14 (r)
A15 (r)
A16 (r)
A17 (r)
A18 (r)

CHR A11 (n)


CHR A12 (n)
CHR A13 (n)
NC
NC
CIRAM /CE (n)
CIRAM A10 (n)
CHR /WR (n)
CHR /RD (s?)
/IRQ (n)
PRG D0 (s)
PRG D1 (s)
PRG D2 (s)
PRG D3 (s)
PRG D4 (s)
PRG D5 (s)
PRG D6 (s)
PRG D7 (s)
+5V
PRG A0 (s)
PRG A1 (s)
PRG A2 (s)
PRG A3 (s)

Pin# Function
---- --------

PRG A6 (s)
76
PRG A7 (s)
77
PRG A8 (s)
78
PRG A9 (s)
79
PRG A10 (s) 80
VCC of RAM (w)81
+Vbatt
82
PRG A11 (s) 83
PRG A12 (s) 84
PRG A13 (r) 85
PRG A14 (r) 86
PRG A15 (r) 87
PRG A16 (r) 88
PRG A17 (r) 89
PRG A18 (r) 90
PRG A19 (r) 91
PRG A13 (n) 92
PRG A14 (n) 93
A13 (w)-all# 94
A14 (w)-all 95
/CE (w)-0
96
/CE (w)-1
97
NC
98

/WE (w)-all
NC
NC
M2 (n)
GND
NC
NC
CE (w)-all
CHR D0 (s)
CHR D1 (s)
CHR D2 (s)
CHR D3 (s)
CHR D4 (s)
CHR D5 (s)
CHR D6 (s)
CHR D7 (s)
NC
NC
CHR A0 (r) *2
CHR A1 (r) *2
CHR A2 (r) *2
CL3 *2
SL3 *2

24 - CHR A19 (r)


25 - CHR A10 (n)

49 - PRG A4 (s)
50 - PRG A5 (s)

74 - PRG /CE (r) 99 - GND


75 - NC
100 - RC3 *1

#: This pins have not been confirmed, and their use has been extrapolated
by the use of adjacent pins.
*1: PINS 1,2,3 & 100. These appear to be some form of data input. They are
un-used on this particular board (Castlevania 3), and their exact
purpose is unknown; however pin #54 of the cart connects to this extra
circuitry. this pin only connects to the access port underneath the
NES unit, so I doubt if this was ever used in any cart.
*2: PINS 94 thru 98. These set the cart in either SL or CL mode. I have no
clue what the diffrence between the two modes are; the cart I checked
(Castlevania 3) was set to CL mode.
To set to CL mode:
Connect CHR A0 from the NES to A0
Connect CHR A1 from the NES to A1
Connect CHR A2 from the NES to A2
Connect pins 97 and 98 together.
Leave pins 94,95 & 96 floating on

on the CHR ROM.


on the CHR ROM.
on the CHR ROM.
the MMC5

To set to SL mode:
Connect pin 94 of the MMC5 to A0 of the CHR ROM.
Connect pin 95 of the MMC5 to A1 of the CHR ROM.
Connect pin 96 of the MMC5 to A2 of the CHR ROM.
Connect pin 98 to ground.
Leave pin 97 floating.
The difference between the two modes is unknown.

MMC6 Chip:
(64 pin QFP)
---------There is one known flavour: 'MMC6B' I suspect there may be an 'A' rev. also.
48
33
|
|
.---------.
49-|
|-32
|
|
| MMC6B |
|
|
64-|
|-17
\---------'
|
|
1
16
Pin# Function
---- --------

Pin# Function
---- --------

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

PRG A13 (n)


M2
GND
GND
GND
NC
GND
+5V
+5V
+batt
GND
+5V
threshold
CHR A10 (n)
CHR A11 (n)
NC
CHR A10 (r)
CHR A16 (r)
CHR A11 (r)
CHR A12 (n)
CHR A13 (r)
CHR A12 (r)
CHR A14 (r)
GND
+batt
CHR A18?(r)
CIRAM A10 (n)
CHR /RD (s)
CHR /CE (s)
CHR A17 (r)
/IRQ
PRG /CE (n)

33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

R/W
PRG D2 (s)
PRG D3 (s)
PRG D1 (s)
GND
+batt
PRG D4 (s)
PRG D0 (s)
PRG D5 (s)
PRG A0 (s)
PRG D6 (s)
PRG A1 (s)
PRG D7 (s)
PRG A2 (s)
PRG /CE (r)
PRG A3 (s)
PRG A4 (s)
PRG A16 (r)
PRG A5 (s)
PRG A6 (s)
PRG A9 (s)
PRG A7 (s)
PRG A8 (s)
+batt
GND
PRG A12 (s)
PRG A13 (r)
PRG A15 (r)
PRG A14 (r)
PRG A18?(r)
PRG A14 (n)
PRG A17 (r)

Notes: A10 & A11 do not go to this chip.


Threshold: Tied to a resistor divider between +5V and GND;
resistor to +5V is 180 ohms, resistor to ground is 470 ohms.

LS161 bankswitching
------------------Quite a few carts seem to use either a single 74LS161, or a combination
of an LS161 and LS32, or an LS161 and LS02.
There are two main styles of LS161-only carts:
NES-CN-ROM-256-[02,05]
---------------------You can select either H or V mirroring; PRG ROM is *not* bankswitched
and is either 16K or 32K. CHR ROM, however is bankswitched. It's set
up as up to 4 8K pages. CHR ROM is either 16K or 32K.
.---\/---.

+5V
PRG /CE
PRG D0
PRG D1
PRG D4
PRG D5
GND
GND

|01
16|
|02
15|
|03
14|
|04
13|
|05
12|
|06
11|
|07
10|
|08
09|
`--------'

+5V
NC
CHR
CHR
CHR
CHR
GND
R/W

A14
A13
A12
A11

(r)
(r)
control
control

'161
NES-AOROM-03
-----------Very similar to above; however cart does not bankswitch CHR area; instead
just has an 8K RAM chip. P-ROM is 256K in both carts I have.

+5V
PRG /CE
PRG D0
PRG D1
PRG D2
PRG D4
GND
GND

.---\/---.
|01
16|
|02
15|
|03
14|
|04
13|
|05
12|
|06
11|
|07
10|
|08
09|
`--------'

+5V
NC
PRG A15
PRG A16
PRG A17
CIRAM A10
GND
R/W

'161
NES-BN-ROM-01
------------Identical to above, except has a 28-pin 128K ROM instead.
NES-UN-ROM-05 & Konami #531320
-----------------------------This uses both an LS161 and an LS32. The ROM is set up like on a nonbankswitched cart except this time only A0-A13 go to the ROM's A0-A13.
A14 is used to control the LS32 and hence which bank the processor 'sees'.
When A14 is high, it forces all the bankswitch address lines high; so the
processor sees the last bank no matter what. When A14 is low, the OR gates
will pass whatever is on the other input (which happens to be connected
to the outputs of the '161). There is an 8K RAM for the CHR area.
The Konami board is functionally the same; however the routing is slightly
different.

+5V
PRG /CE
PRG D0
PRG D1
PRG D2

.---\/---.
|01
16|
|02
15|
|03
14|
|04
13|
|05
12|

+5V
NC
Pin 13 of '32
Pin 2 of '32
Pin 9 of '32

GND - |06
11| - NC
GND - |07
10| - GND
GND - |08
09| - R/W
`--------'
'161

A14
Pin 13 of '161
ROM A15
GND
GND
NC
GND

.---\/---.
|01
14|
|02
13|
|03
12|
|04
11|
|05
10|
|06
09|
|07
08|
`--------'

+5V
Pin
A14
ROM
A14
Pin
ROM

14 of '161
A14
12 of '161
A16

'32

NES-ANROM-03
-----------This cart has an 8K RAM chip for the CHR area. It contains an LS161
for the selecting the current bank, and an LS02 to disable to PRG ROM
during any write to the bankswitch circuit. Marat was saying he didn't
know why the programs would write to an address associated with a bank;
i.e. To switch to bank #05:
LDA #$05
STA $FFF5
The reason is to avoid a bus conflict with the ROM; The ROM has the
value 0$5 stored in address $FFF5. This is required, because the ROM is
*not* disabled during a data write to the ROM's area!!! However, the
LS02 added to this cart allieviates those problems. It disables the
ROM during any data write to the cart area.
+5V
PRG /CE
PRG D0
PRG D1
+5V
PRG D4
GND
GND

.---\/---.
|01
16|
|02
15|
|03
14|
|04
13|
|05
12|
|06
11|
|07
10|
|08
09|
`--------'
'161

.---\/---.

+5V
NC
PRG A15
PRG A16
NC
CIRAM A10
GND
R/W

To pin 12
R/W
R/W
NC
GND
GND
GND

|01
14|
|02
13|
|03
12|
|04
11|
|05
10|
|06
09|
|07
08|
`--------'

+5V
To pins 8 & 9
To pin 1
PRG /CE
To /CE of ROM
To pin 13
To pin 13

'02

CPU (p/n: RP2A03G)


------------------Pins 39,38, and 37 correspond to STA $4016 bits D0,D1, and D2 resp.
Pin 36 goes low during an LDA $4016, and pin 35 goes low during an
LDA $4017.
Audio 1 is the output for the two squarewave channels, and
Audio 2 is the output for triangle, noise, and PCM.

Audio 1
Audio 2
/RST
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
GND

.----\/----.
|
|
|01
40|
|02
39|
|03
38|
|04
37|
|05
36|
|06
35|
|07
34|
|08
33|
|09
32|
|10
31|
|11
30|
|12
29|
|13
28|
|14
27|
|15
26|
|16
25|
|17
24|
|18
23|
|19
22|
|20
21|
|
|
`----------'
CPU

PPU (p/n: RP2C02G)


-------------------

.----\/----.

+5V
Strobe on sticks
Exp. conn pin #44
Exp. conn pin #45
/OE for stick #1
/OE for stick #2
/NMI
R/W
/IRQ
M2
GND (Abort?)
21.47727Mhz CLK
D0
D1
D2
D3
D4
D5
D6
D7

/ VBL
|
D0
FROM / TO CPU |
D1
|
D2
Section |
D3
|
D4
|
D5
|
D6
|
D7
|
A2
|
A1
|
A0
| /CE
| GND
| GND
| GND
| GND
|CLK In
\ R/W
GND

|
|
|01
40|
|02
39|
|03
38|
|04
37|
|05
36|
|06
35|
|07
34|
|08
33|
|09
32|
|10
31|
|11
30|
|12
29|
|13
28|
|14
27|
|15
26|
|16
25|
|17
24|
|18
23|
|19
22|
|20
21|
|
|
`----------'
PPU

+5V
ALE
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A8
A9
A10
A11
A12
A13
/RD
/WR
/RST
Video Out

Maximum ROM capacities for the various bankswitch methods:


+---------+-------+-------+---------------------------------------+
| Type | P-ROM | C-ROM |
Notes
|
+---------+-------+-------+---------------------------------------+
| -none- | 32K |
8K |
No bankswitching
|
+---------+-------+-------+---------------------------------------+
| MMC1 | 256K | 128K |
Without extra RAM
|
+---------+-------+-------+---------------------------------------+
| MMC1 | 128K | 128K |
With extra RAM
|
+---------+-------+-------+---------------------------------------+
| MMC2 | 128K | 128K |
|
+---------+-------+-------+---------------------------------------+
| MMC3 | 512K | 256K |
|
+---------+-------+-------+---------------------------------------+
| MMC5 | 1024K | 1024K |
|
+---------+-------+-------+---------------------------------------+
| MMC6 | 512K | 512K | Appears to be extention of the MMC3 |
+---------+-------+-------+---------------------------------------+
|CNROM-256| 32K | 32K |
LS161
|
+---------+-------+-------+---------------------------------------+
| ANROM | 128K |
0K |
LS161 & LS02
|
+---------+-------+-------+---------------------------------------+
| UNROM | 128K |
0K | Same as Konami #351320 - LS161 & LS32 |
+---------+-------+-------+---------------------------------------+
| BNROM | 128K |
0K |
LS161
|
+---------+-------+-------+---------------------------------------+
| AOROM | 256K |
0K |
LS161
|
+---------+-------+-------+---------------------------------------+
| ??? | 64K | 64K |
Colour Dreams cart
|
+---------+-------+-------+---------------------------------------+
| ??? | 64K | 64K |Same as above; with imp. lockout-defeat|
+---------+-------+-------+---------------------------------------+
| BC6 | 128K | 128K |
Wisdom Tree / Colour Dreams
|

+---------+-------+-------+---------------------------------------+
| 47516 | 64K | 64K |
AGCI's copy of the C.D. cart
|
+---------+-------+-------+---------------------------------------+
|Nina-001 | 64K | 64K |AVE/SEI cart (ex: Impossible Mission 2)|
+---------+-------+-------+---------------------------------------+
|Nina-003 | 32K | 32K |
AVE cart (ex: Tiles of Fate)
|
+---------+-------+-------+---------------------------------------+

Boards:
------*****************************************
*
Non-bankswitched carts
*
*****************************************
NES-NROM-[01,03,05]
------------------8K of C-ROM, 32K of P-ROM

*****************************************
*
LS161 bankswitching cart boards
*
*****************************************
NES-CN-ROM-256-02
----------------Contains either 16K or 32K of P-ROM, as well as 16K or 32K of C-ROM.
NES-ANROM-03
-----------Uses an LS161 and an LS02. Contains 8K of C-RAM, and 128K of P-ROM.
The LS02 prevents bus conflicts between the CPU and the ROM.
NES-UNROM-[05,09] & 351320
-------------------------Uses an LS161 and LS32. This is a fairly intresting method. It breaks
the P-ROM up into two 16K banks... the last 16K always points to the last
16K of the ROM. The first is under software control; however. Contains
8K of C-RAM and 128K of P-ROM
NES-BN-ROM-01
------------Has 128K of P-ROM which can be switched in 32K blocks. Also contains
8K of C-RAM.
NES-AOROM-03
-----------Has 256K of P-ROM which can be switched in 32K blocks. Also contains
8K of C-RAM.

*****************************************
*
MMC1 containing boards
*
*****************************************
NES-SNROM-[01,03,05,06]
----------------------8K of WRAM at 6000-7FFF (with the capibility to be battery-backed) of the
CPU's address space. Up to 512K of P-ROM, and 8K of C-RAM.
NES-SEROM-04
-----------16K or 32K of C-ROM, and 32K of P-ROM. (the latter is not bankswitched)
NES-SGROM-04
-----------8K of C-RAM, and up to 512K of P-ROM.
NES-SLROM-04
-----------Up to 256K of C-ROM and 512K of P-ROM.
351908 (Konami)
--------------Uses 128K of C-ROM and 128K of P-ROM.

*****************************************
*
MMC2 containing boards
*
*****************************************
NES-PNROM-05
-----------Used on only one cart (unconfirmed)
Has 128K of C-ROM and 128K of P-ROM as well as an MMC2
*****************************************
*
MMC3 containing boards
*
*****************************************
NES-TKROM-10
-----------8K battery-backed SRAM, 256K of C-ROM, and 512K of P-ROM.
NES-TR1ROM-01
-------------

Intresting cart. Has 4K of RAM mapped into 0000-1FFF of the PPU's


address space (it disables the CIRAM), and 64K of C-ROM at 2000-3FFF.
There is space for up to 512K of P-ROM.
NES-TLROM-03
-----------Up to 256K of C-ROM and 512K of P-ROM.
NES-TSROM-[04,06,07]
-------------------8K of WRAM mapped in at 6000-7FFF in the CPU's address space. Up to
256K of C-ROM and 512K of P-ROM.
NES-TGROM-01
-----------8K of C-RAM, with up to 512K of P-ROM.
352026 (Konami)
--------------128K of C-ROM and 128K of P-ROM.
*****************************************
*
MMC5 containing boards
*
*****************************************
Used on only one more than one cart!
NES-ELROM-01
-----------Has 256K of C-ROM and 256K of P-ROM as well as an MMC5
NES-ETROM-01
-----------One word: Wow! two 8K RAM chips, battery backed, MMC5, ???K P-ROM and
???K C-ROM. The board takes up *all* the space in the cart shell!
*****************************************
*
MMC6 containing boards
*
*****************************************
NES-HKROM-01
-----------Has 256K of C-ROM and up to 512K
to the MMC6 chip itsself; and is
internal RAM appears to be 1K in
MMC acts in a similar way to the

of P-ROM. There's some RAM internal


battery-backed on this board. The
size. From what I can tell, this
MMC3 in all other respects.

*****************************************

*
Misc. boards by 3rd-parties
*
*****************************************
[No part #, says '(c) 1990 Color Dreams Inc.' on the bottom side]
Made by Colour dreams; Uses a 74LS377 which has had the part # scratched
off. :-) Good thing I have my handy-dandy chip ID'er. Also contains
32K of C-ROM and 32K of P-ROM.
[No part #, says '(c) 1991 Color Dreams, Inc.' on the bottom side]
Very similar to the above, except this time there's 64K of P-ROM and
64K of C-ROM.
BC6 (MFG. by Colour Dreams)
--------------------------Same as above two, except this time there's 128K of C-ROM and 128K of P-ROM.
47516 (MFG. by AGCI)
-------------------Intresting. It's almost identical to the above; except the bankswitch
chip is house numbered (It's got the same pinout as a 74LS377 ;-) I've
got to finish my reader so I can confirm that it is a 74377.
Nina-001 (MFG. by SEI)
---------------------Odd board. Has 6 74-series chips to do bankswitching; 8K of WRAM,
a Faux lockout-chip (called 'Nina' intrestingly enough), 64K of C-ROM,
and 64K of P-ROM.
Nina-003 (MFG. by AVE)
---------------------This appears to be made by the same co. as above. 32K of P-ROM, and
32K of C-ROM. Three TTL chips do the bankswitching.
A800XXX (Tengen)
---------------Very strange. Has a 'Mimic 1' chip on it to do bankswitching, and of
course the Tengen version of the lockout chip! :-) The ROM sizes are
unknown at the moment.
BIC-48 & BIC-43 (Camerica)
-------------------------Uses a 20-pin bankswitch chip labeled 'BF9093'. Has 8K of C-RAM and
256K of P-ROM.
BIC-62 (Camerica)
----------------Uses a 20-pin bankswitch chip labeled 'BF9097'. Has 8K of C-RAM and
256K of P-ROM.

*****************************************
*
LS377 containing boards
*
*****************************************
These include carts by Colour Dreams, AGCI, Wisdom Tree, Bunch Games, etc.
[no part #; Colour Dreams]
-------------------------You can tell this board apart from it's characteristic 'L' shape.
Maximum of 64K of both P-ROM and C-ROM. P-ROM is switched in 32K banks,
while C-ROM is switched in 8K banks. There is a one byte register you
write to anywhere from $8000-$FFFF to change banks. It's laid out like so:
D0-D3 holds the desired P-ROM bank (each bank is 32K)
D4-D7 holds the desired C-ROM bank (each bank is 8K)
Mirroring is perminantly set to Horizontal.
[no part #; Colour Dreams]
-------------------------This board has 5 transistors, two resistor networks, three electrolytic
caps, and a MAX7660CPA inverting charge-pump chip.
Identical to above, except has improved lockout-defeating circuitry.
BC6 (Colour Dreams)
------------------This was used on Wisdom Tree carts only, as far as I know.
It has 128K of both P-ROM and C-ROM.
Mirroring set perminantly to Horizontal.
47516 (AGCI)
-----------This is an exact copy of the Colour Dreams cart! There are three
transistors, and the LS377, however each part is labeled:
AGCI#1, AGCI#2, AGCI#3 (the three transistors) and AGCI#4 (the LS377 chip).
Pretty funny that they would copy the Colour Dreams cart exactly- right
down to the exact part values! It does have one slight variation, though.
You can set the mirroring to either H or V... it's 'factory set' to
Horizontal.
The maximum amount of both C-ROM and P-ROM is 64K.

*****************************************
*
American Video Entertainment
*
*****************************************
Note: the same company that designed the AVE cart board also designed
the ones for SEI.
NINA-03
------Uses a Faux-lockout chip in a 14-pin package. Allows 32K of both
P-ROM and C-ROM. The P-ROM area is not bankswitched. Uses two
TTL chips to perform the bankswitch on the C-ROM- an LS175 and an
LS138.
You change banks by writing to anything with A14 and A8 high, and A15
and A13 low. This would be 6100-61FF, 6300-63FF ... 7F00-7FFF. Only D0
and D1 are used. D0 and D1 determine which 8K bank to use for the C-ROM.
NINA-001
-------Uses six TTL chips- LS173 * 2, LS139, LS133, LS74, and LS00. There is
8K of WRAM, 64K of both P-ROM and C-ROM, and a faux-lockout chip labelled
'NINA'.
Mirroring is perminantly set to Horizontal. It has 8K of WRAM mapped in
at $6000-$7FFF. You select the P-ROM bank by writing to $7FFD. The C-ROM
area is broken into two parts- $0000-$0FFF and $1000-$1FFF. You can
select the desired bank for *each* section individually.
You select the 4K bank via writing to $7FFE, and the upper bank via $7FFF.
Note that you *must* use these addresses since no others are decoded.
There is only one bit implemented for the P-ROM bank and only 4 bits
implemented for the C-ROM banks.

*****************************************
*
Cart list
*
*****************************************
*Nintendo*
Cart Name
---------

PN P-ROM W-RAM C-ROM C-RAM Board #


-- ----- ----- ----- ----- -------

Mega Man 2
Solar Jetman
Ironsword
Tetris
Boulder Dash
Super Mario 2
Super Mario 3
Zelda

XR
LJ
IR
EI
XB
MW
UM
ZL

256K
256K
256K
32K
32K
128K
256K
128K 8K

8K
8K
8K
32K
32K
128K
128K
8K

SGROM-0
AOROM-03
AOROM-03
SEROM-04
SEROM-04
TSROM-04
TSROM-06
SNROM-01

batt-backed

Metroid
A Boy and his Blob
Streetfighter 2010
Deadly Towers
Super Pitfall
Gauntlet
Snake's Revenge
Star Tropics
Kirby's Adventure
Castlevania 3
Punch Out
Mega Man 4
Dig Dug ][
Bomberman ][
Super Mario Bros.
Gyromite
Joust
Solstice
Quantum Fighter
Top Gun Second Miss.
Alpha Mission
Silver Surfer
Ultima Exodus
Goonies ][
Uncharted Waters
Commando

MT
B5
YA
DE
PI
GL
E2
OC
KR
VN
QP
4V
I2
BW
SM
GY
JU
LX
3K
??
AM
VQ
UL
??
QK
CO

128K
128K
128K
128K
128K
128K
128K
256K
512K
256K
128K
512K
32K
128K
32K
32K
16K
128K
128K
128K
32K
128K
256K
128K
512K
128K

8K

8K

SNROM-03
SLROM-06
TLROM-03
8K
BNROM-01
8K
UNROM-05
64K 4KVRAM TRIROM-01
128K
351908
128K
HKROM-01 batt-backed
256K
TKROM-10 batt-backed
256K
ELROM-01
128K
PNROM-05
8K
TGROM-01
8K
NROM-256-05
8K
SNROM-06
8K
NROM-256-03
8K
NROM-256-01
16K
CNROM-256-05
8K
ANROM-03
128K
TLROM-03
128K
352026
32K
CNROM-256-02
256K
TSROM-07
8K
SNROM-05 batt-backed
8K
351320
128K
ETROM-01
8K
UNROM-09
128K
128K

8K

8K

8K
16K

*Colour Dreams* (note: they also made Wisdom Tree carts)


Cart name
---------

Program
-------

Character Chips/Board
--------- -----------

Joshua (WT)
128K ROM 128K ROM
Sunday Funday (WT)
128K ROM 128K ROM
Bible Buffet (WT)
128K ROM 128K ROM
Raid 2000
64K ROM 32K ROM
Silent Assault
64K ROM 64K ROM
Taggin' Dragon
32K ROM 32K ROM
Master Chu & Drunkard Hu 32K ROM 32K ROM
The Pradikus Conflict
64K ROM 64K ROM
Secret Storm
64K ROM 64K ROM

BC6
BC6
BC6
???
???
???
???
???
???

##
-SPCN 9901630053
SPCN ???
SPCN ???

*AGCI*
Cart name
---------

Program
-------

Character Chips/Board
--------- -----------

Shock Wave

64K ROM

64K ROM

47516

64K ROM
32K ROM

64K ROM
32K ROM

NINA-001
NINA-03

*SEI / AVE*
----------Impossible Mission ][
Tiles of Fate

##
--

Cart name
---------

Program
-------

Character Chips/Board
--------- -----------

##
--

Cart name
---------

Program
-------

Character Chips/Board
--------- -----------

##
--

The Ultimate Stuntman


Firehawk

??K ROM

*Camerica / Code Masters*

8K RAM

KT-B-5024

???

Universal CHR area should consist of:


8K of RAM at 0000-1FFF; switchable to 2K or 4K. Must allow A10/A11/A12 and
/CE access
8K of RAM at 2000-3FFF; must allow A10/A11/A12/CE/WE/OE access
1024K of C-ROM at 2000-3FFF bankswitched. Must allow to be able to be
switched from 2K, 4K, 8K, 16K, 32K, 64K, 128K, 256K, 512K, and 1024K.
Universal PRG area should consist of:
12K of RAM switchable at 5000-7FFF; should be able to turn off individual
256-byte segments.
1024K of ROM switchable from 2K to 1024K.
Universal Bankswitch controller should have:
MMC1B
MMC2
MMC3C
MMC5
MMC6
Camerica (two types so far)
LS377
LS161 (all iterations)