Lab Workbook

HW/SW System Debug

HW/SW System Debug

Introduction
This lab guides you through the process of performing on-chip hardware/software verification using
Chipscope-Pro and the software debugger.

Objectives
After completing this lab, you will be able to:

Add ChipScope Analyzer cores into a system

Cross debug with Chipscope Analayzer and the SDK debugger

Procedure
This lab is separated into steps that consist of general overview statements that provide information on
the detailed instructions that follow. Follow these detailed instructions to progress through the lab.
This lab comprises 4 primary steps: You will open the lab 6 project, instantiate Chipscope cores, setup
SDK and Chipscope, and, finally, perform hardware/software verification.

Design Description
You will extend the system created in the previous lab by adding Chipscope ICON and IBA cores. The
IBA core will be added to the AXI bus. You will set trigger conditions in the Chipscope Analyzer software
(running on PC) to capture bus transactions when the value of the count variable is written to the LEDs.
When the hardware trigger condition is met, you will see that the software debugger stops at the line of
code that was last executed. This lab comprises the following steps:

Figure 1. Complete MicroBlaze System

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General Flow for this Lab

Step 1:
Open the lab
6 project

Step 2:
Instantiate
Chipscope
cores

Step 3:
Setup SDK
and
Chipscope

Step 4:
Perform
hardware/sof
tware
verification

Open the Project

1-1.

Step 1

Create a lab6 folder under c:\xup\embedded\labs. If you wish to continue

with your completed design from lab5 then copy the contents of the lab5
folder into the lab6 folder or copy the content of labsolution\lab5 folder into
the lab6. Launch Xilinx Platform Studio (XPS) and open the project file
located in c:\xup\embedded\ labs\lab6.

1-1-1. Create a lab6 folder in the c:\xup\embedded\labs directory. If you wish to continue with your
completed design from lab5 then copy the contents of the lab5 folder into the lab6 folder,
otherwise copy the content of labsolution\lab5 folder into the lab6 folder.
1-1-2. Open XPS by clicking Start > All Programs > Xilinx Design Tools > ISE Design Suite 14.2 >
EDK > Xilinx Platform Studio
1-1-3. Browse to the lab6 directory and open the project system.xmp

Instantiate ChipScope Cores

2-1.

Step 2

Add the ChipScope cores using the Debug Configuration wizard.

Configure the device and the design to the following ports, as shown in the
Figure 2. Setup the trigger to trigger when a certain values are on the
led_ip AXI bus

Figure 2. ChipScope Core Connections

2-1-1. Select Debug > Debug Configuration.
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Figure 3. Debug Configuration

2-1-2. Click the Add Chipscope Peripheral... button and select the first option, To monitor AXI
Interconnect signals (adding AXI Monitor). Click OK.

Figure 4. Add the AXI Monitor

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2-1-3. Select led_ip_0.s_AXI from dropdown window as the Monitor Bus Signal and set the Select
the Number of signal samples you want to collect option to 1024.

Figure 5. Setting Basic Debug Configuration Options

2-1-4. Click the Advanced tab. Under the User tab, in the ILA setting panel, check the Enable
Trigger Input port.

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Figure 6. Setting ILA setting options

2-1-5. Select Extended as the port match type for the Write Data Port Settings and Write Address
Port Settings.

Figure 7. Setting write address and data options

2-1-6. Click OK, and view the Bus Interface noting the newly added Chipscope Cores in the System
Assembly View.

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Figure 8. Chipscope cores added to the MicroBlaze system

2-1-7. Select Hardware > Generate Bitstream.

Setup SDK and ChipScope

3-1.

Step 3

Export the project to SDK and establish a connection to the target using
XMD. Having successfully generated your design it is possible to begin
viewing it in operation using the SDK debugger and ChipScope Pro tools.
Starting the SDK debugger (Software Debug)

3-1-1. Open SDK by selecting Project > Export Hardware Design to SDK
3-1-2. Check Include Bitstream and BMM File option and click on Export & Launch SDK button.
3-1-3. Browse to c:\xup\embedded\labs\lab6\SDK\SDK_Export as the workspace, and click OK.
A debug perspective will open as that was the last view we had used in Lab5.
3-1-4. In Debug perspective, disable a breakpoint placed in the interrupt handler by right-clicking on the
line where breakpoint is present and select Disable Breakpoint.
3-1-5. With the board connected and powered, select Xilinx Tools > Program FPGA to update the
bitstream with the bootloop executable.

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3-1-6. Click on Browse buttons and select system.bit and system_bd.bmm files from
c:\xup\embedded\labs\lab6\SDK\SDK_Export\lab1_hw_platform directory. Select bootloop
as the application.
3-1-7. Click on Program.
3-1-8. Start the debugger by selecting Run > Debug.
The SDK Debugger should now be connected to the target and operation should be suspended.
Code operation will be halted at the first line following the main( ) routine

Figure 9. SDK Debugger Connected to Target via XMD

3-2.

Start ChipScope Pro (Hardware Debug)

NOTE: There is a bug in the tools with Digilent programming cable. If you
are using the Digilent Programming cable (instead of Xilinx Programming
cable), the xmd crashes when you open ChipScope Analyzer and connect
to the device. The workaround is to replace the xmd.exe file located in
either <EDK_Install>\bin\nt\unwrapped (for 32-bit machine) or
<EDK_Install>\bin\nt64\unwrapped (for 64-bit) with the extracted xmd.exe
from xmd_32.zip or xmd_64.zip file included with the labsource.zip file.

3-2-1. Launch the ChipScope Pro Analyzer tool by selecting Start > All Programs > Xilinx Design
Tools > ISE Design Suite 14.2 > ChipScope Pro > ChipScope 64-bit (or 32-bit) > Analyzer.

3-2-2. Click

to connect the board.

3-2-3. Click OK to open ChipScope Pro Analyzer with default Trigger Setup and Waveform signal
windows.
3-2-4. Select File > Import. In the Signal Import dialogue click on the Select New File button.
3-2-5. Browse to the implementation directory and select the following chipscope definition and
connection file (CDC) C:\xup\embedded\labs\lab6\implementation
\ chipscope_axi_monitor_0_wrapper\chipscope_axi_monitor_0.cdc and click OK
The CDC file contains signals associated with the LED core which should now be listed in the
Trigger Setup and Waveform signal windows.

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3-2-6. Click on the check-box of Auto-Create Buses (if not checked) and click OK.
3-2-7. In waveform window, select all signals except MON_AXI_AWADDR and MON_AXI_WDATA
buses In the Waveform window, right-click, and select Remove from Viewer.

Figure 10. Chipscope Waveform View setup

Perform HW/SW Verification

4-1.

Step 4

Setup the trigger to capture 32 data samples when count values greater
than 5 are written to the LEDs.

4-1-1. Change the Radix of M2 and M8 from binary (Bin) to Hexadecimal (Hex) by clicking on the
respective boxes and selecting Hex.
4-1-2. Set M2: MON_AXI_AWADDR == 7F40_0000 (or base address of led_ip peripheral) and M8:
MON_AXI_WDATA > 0000_0005 by selecting and adjusting the value box.
4-1-3. Click the field under Trigger Condition Equation, which opens the Trigger Condition:
TriggerCondition0 dialog box. Select M2 and Select M8, and then click OK to close.
The Trigger Condition Equation field should now display M2 && M8. Click OK.
4-1-4. Set the trigger window depth to 32 and position to 0
4-1-5. Set the Storage Qualification (M2&&M8) so that you capture count values greater than 5 when
written to the led_ip peripheral.
Your settings should be similar to what is shown next.

Figure 11. Chipscope Trigger settings

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4-1-6. Start the run to capture data by selecting Trigger Setup > Run.
The ChipScope should be waiting for the trigger condition to meet since the program is not
running and the LEDs are 0x00.

4-2.

Run Software debugger and wait for the condition to trigger

4-2-1. In SDK, type con in the XMD window to run the program.
4-2-2. After Sample buffer is full, select Mon_AXI_AWADDR in the waveform window, right-click and
select Reverse Bus Order. Similarly, reverse the MON_AXI_WDATA bus order.
4-2-3. The ILA core will trigger when a value greater than 5 is written to the LEDs. The buffer will be
filled with 32 data samples, which will be displayed in Chipscope-Pro Analyzer.

Base address of
Figure Peripheral
15. Chipscope-Pro Debug Results
LEDs_8Bit

Interrupt count values

Notes:
1) You may have to zoom in to see the results.
2) You can set the radix for each signal accordingly by right-clicking and specifying the radix
value
4-2-4. Stop the debugger in SDK by typing stop in the XMD Console window.
4-2-5. Close SDK, XPS, and ChipScope programs.

Conclusion
Chipscope HW debug modules can be added as IP modules in EDK, and the ChipScope analyzer can be
used in conjunction with SDK debugger, to provide a debug environment that allows cross triggering and
debug between hardware and software using a shared JTAG connection.

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Completed MHS File

# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 14.2 Build EDK_P.28xd
# Wed Sep 19 09:57:18 2012
# Target Board: digilent nexys3 Rev B
# Family: spartan6
# Device: xc6slx16
# Package: csg324
# Speed Grade: -3
# ##############################################################################
PARAMETER VERSION = 2.1.0
PORT RS232_Uart_1_sout = RS232_Uart_1_sout, DIR = O
PORT RS232_Uart_1_sin = RS232_Uart_1_sin, DIR = I
PORT RESET = RESET, DIR = I, SIGIS = RST, RST_POLARITY = 1
PORT GCLK = GCLK, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
PORT dip_GPIO_IO_I_pin = dip_GPIO_IO_I, DIR = I, VEC = [7:0]
PORT push_GPIO_IO_I_pin = push_GPIO_IO_I, DIR = I, VEC = [3:0]
PORT led_ip_0_LED_pin = led_ip_0_LED, DIR = O, VEC = [7:0]
BEGIN proc_sys_reset
PARAMETER INSTANCE = proc_sys_reset_0
PARAMETER HW_VER = 3.00.a
PARAMETER C_EXT_RESET_HIGH = 1
PORT MB_Debug_Sys_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst
PORT Dcm_locked = proc_sys_reset_0_Dcm_locked
PORT MB_Reset = proc_sys_reset_0_MB_Reset
PORT Slowest_sync_clk = clk_100_0000MHz
PORT Interconnect_aresetn = proc_sys_reset_0_Interconnect_aresetn
PORT Ext_Reset_In = RESET
PORT BUS_STRUCT_RESET = proc_sys_reset_0_BUS_STRUCT_RESET
END
BEGIN lmb_v10
PARAMETER INSTANCE = microblaze_0_ilmb
PARAMETER HW_VER = 2.00.b
PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
PORT LMB_CLK = clk_100_0000MHz
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = microblaze_0_i_bram_ctrl
PARAMETER HW_VER = 3.10.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00003fff
BUS_INTERFACE SLMB = microblaze_0_ilmb
BUS_INTERFACE BRAM_PORT = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block
END
BEGIN lmb_v10
PARAMETER INSTANCE = microblaze_0_dlmb
PARAMETER HW_VER = 2.00.b
PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
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PORT LMB_CLK = clk_100_0000MHz

END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = microblaze_0_d_bram_ctrl
PARAMETER HW_VER = 3.10.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00003fff
BUS_INTERFACE SLMB = microblaze_0_dlmb
BUS_INTERFACE BRAM_PORT = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block
END
BEGIN bram_block
PARAMETER INSTANCE = microblaze_0_bram_block
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block
BUS_INTERFACE PORTB = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block
END
BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER HW_VER = 8.40.a
PARAMETER C_INTERCONNECT = 2
PARAMETER C_USE_BARREL = 1
PARAMETER C_USE_FPU = 0
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_ICACHE_BASEADDR = 0X00000000
PARAMETER C_ICACHE_HIGHADDR = 0X3FFFFFFF
PARAMETER C_USE_ICACHE = 0
PARAMETER C_ICACHE_ALWAYS_USED = 0
PARAMETER C_DCACHE_BASEADDR = 0X00000000
PARAMETER C_DCACHE_HIGHADDR = 0X3FFFFFFF
PARAMETER C_USE_DCACHE = 0
PARAMETER C_DCACHE_ALWAYS_USED = 0
BUS_INTERFACE ILMB = microblaze_0_ilmb
BUS_INTERFACE DLMB = microblaze_0_dlmb
BUS_INTERFACE M_AXI_DP = axi4lite_0
BUS_INTERFACE DEBUG = microblaze_0_debug
BUS_INTERFACE INTERRUPT = axi_intc_0_INTERRUPT
PORT MB_RESET = proc_sys_reset_0_MB_Reset
PORT CLK = clk_100_0000MHz
END
BEGIN mdm
PARAMETER INSTANCE = debug_module
PARAMETER HW_VER = 2.10.a
PARAMETER C_INTERCONNECT = 2
PARAMETER C_USE_UART = 1
PARAMETER C_BASEADDR = 0x41400000
PARAMETER C_HIGHADDR = 0x4140ffff
BUS_INTERFACE S_AXI = axi4lite_0
BUS_INTERFACE MBDEBUG_0 = microblaze_0_debug
PORT Debug_SYS_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst
PORT S_AXI_ACLK = clk_100_0000MHz
END
BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
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PARAMETER HW_VER = 4.03.a

PARAMETER C_CLKIN_FREQ = 100000000
PARAMETER C_CLKOUT0_FREQ = 100000000
PARAMETER C_CLKOUT0_GROUP = NONE
PORT LOCKED = proc_sys_reset_0_Dcm_locked
PORT CLKOUT0 = clk_100_0000MHz
PORT RST = RESET
PORT CLKIN = GCLK
END
BEGIN axi_interconnect
PARAMETER INSTANCE = axi4lite_0
PARAMETER HW_VER = 1.06.a
PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
PORT interconnect_aclk = clk_100_0000MHz
PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn
END
BEGIN axi_uartlite
PARAMETER INSTANCE = RS232_Uart_1
PARAMETER HW_VER = 1.02.a
PARAMETER C_BAUDRATE = 115200
PARAMETER C_DATA_BITS = 8
PARAMETER C_USE_PARITY = 0
PARAMETER C_ODD_PARITY = 1
PARAMETER C_BASEADDR = 0x40600000
PARAMETER C_HIGHADDR = 0x4060ffff
BUS_INTERFACE S_AXI = axi4lite_0
PORT S_AXI_ACLK = clk_100_0000MHz
PORT TX = RS232_Uart_1_sout
PORT RX = RS232_Uart_1_sin
END
BEGIN axi_gpio
PARAMETER INSTANCE = dip
PARAMETER HW_VER = 1.01.b
PARAMETER C_GPIO_WIDTH = 8
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_BASEADDR = 0x40000000
PARAMETER C_HIGHADDR = 0x4000ffff
BUS_INTERFACE S_AXI = axi4lite_0
PORT S_AXI_ACLK = clk_100_0000MHz
PORT GPIO_IO_I = dip_GPIO_IO_I
END
BEGIN axi_gpio
PARAMETER INSTANCE = push
PARAMETER HW_VER = 1.01.b
PARAMETER C_GPIO_WIDTH = 4
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_BASEADDR = 0x40040000
PARAMETER C_HIGHADDR = 0x4004ffff
BUS_INTERFACE S_AXI = axi4lite_0
PORT S_AXI_ACLK = clk_100_0000MHz
PORT GPIO_IO_I = push_GPIO_IO_I
END
BEGIN led_ip
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HW/SW System Debug

PARAMETER INSTANCE = led_ip_0

PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x7f400000
PARAMETER C_HIGHADDR = 0x7f40ffff
BUS_INTERFACE S_AXI = axi4lite_0
PORT S_AXI_ACLK = clk_100_0000MHz
PORT LED = led_ip_0_LED
END
BEGIN axi_bram_ctrl
PARAMETER INSTANCE = axi_bram_ctrl_0
PARAMETER HW_VER = 1.03.a
PARAMETER C_S_AXI_PROTOCOL = AXI4LITE
PARAMETER C_S_AXI_BASEADDR = 0x40050000
PARAMETER C_S_AXI_HIGHADDR = 0x40051fff
BUS_INTERFACE S_AXI = axi4lite_0
BUS_INTERFACE BRAM_PORTA = axi_bram_ctrl_0_BRAM_PORTA
BUS_INTERFACE BRAM_PORTB = axi_bram_ctrl_0_BRAM_PORTB
PORT S_AXI_ACLK = clk_100_0000MHz
END
BEGIN bram_block
PARAMETER INSTANCE = axi_bram_ctrl_0_bram_block_1
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = axi_bram_ctrl_0_BRAM_PORTA
BUS_INTERFACE PORTB = axi_bram_ctrl_0_BRAM_PORTB
END
BEGIN axi_timer
PARAMETER INSTANCE = delay
PARAMETER HW_VER = 1.03.a
PARAMETER C_ONE_TIMER_ONLY = 1
PARAMETER C_BASEADDR = 0x41c00000
PARAMETER C_HIGHADDR = 0x41c0ffff
BUS_INTERFACE S_AXI = axi4lite_0
PORT S_AXI_ACLK = clk_100_0000MHz
PORT Interrupt = delay_Interrupt
PORT CaptureTrig0 = net_gnd
END
BEGIN axi_intc
PARAMETER INSTANCE = axi_intc_0
PARAMETER HW_VER = 1.02.a
PARAMETER C_BASEADDR = 0x41200000
PARAMETER C_HIGHADDR = 0x4120ffff
BUS_INTERFACE S_AXI = axi4lite_0
BUS_INTERFACE INTERRUPT = axi_intc_0_INTERRUPT
PORT S_AXI_ACLK = clk_100_0000MHz
PORT Intr = delay_Interrupt
END
BEGIN chipscope_axi_monitor
PARAMETER INSTANCE = chipscope_axi_monitor_0
PARAMETER HW_VER = 3.05.a
PARAMETER C_MAX_SEQUENCER_LEVELS = 2
PARAMETER C_USE_INTERFACE = 0
PARAMETER C_NUM_DATA_SAMPLES = 1024
PARAMETER C_USE_TRIG_IN = 1
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PARAMETER C_MON_AXI_WDATA_MATCH_TYPE = extended

PARAMETER C_MON_AXI_AWADDR_MATCH_TYPE = extended
BUS_INTERFACE MON_AXI = led_ip_0.S_AXI
PORT chipscope_icon_control = chipscope_axi_monitor_0_icon_ctrl
PORT MON_AXI_ACLK = clk_100_0000MHz
END
BEGIN chipscope_icon
PARAMETER INSTANCE = chipscope_icon_0
PARAMETER HW_VER = 1.06.a
PARAMETER C_NUM_CONTROL_PORTS = 1
PORT control0 = chipscope_axi_monitor_0_icon_ctrl
END

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