Write test benches for 8 bit ALU and up down counter using for, while, repeat and file

I/O.
8 bit ALU code
module alu8bit #(parameter n=7)(
output reg [n+n:0]z,
output reg carry,
input [n:0]b,
input [n:0]a,
input [2:0]sel
);
always@(a,b,sel)
begin
casex(sel)
3'b000:
{z,carry}=a+b;
3'b001:
{z,carry}=a-b;
3'b010:
z=a-1;
3'b011 :
z=a+1;
3'b100:
z=a&b;
3'b101:
z=a|b;
3'b110:
z=a^b;
3'b111:
z=~a;
endcase
end
endmodule

Test benches
1.Linear
module tb_ALU8();
parameter n=7;
wire [n+n:0]z;
wire carry;
reg [n:0]b;
reg [n:0]a;
reg [2:0]sel;
alu8bit a1();
initial
begin
a=8'b00000101; b=8'b01111010 ;sel=3'b000;
#20 a=8'b00100101; b=8'b10111010 ;sel=3'b001;
#20 a=8'b00011101; b=8'b10101010 ;sel=3'b010;
#20 a=8'b00000101; b=8'b11111010 ;sel=3'b011;
#20 a=8'b01100101; b=8'b00111010 ;sel=3'b100;
#20 a=8'b11000101; b=8'b11001010 ;sel=3'b001;
#20 a=8'b01100101; b=8'b01111010 ;sel=3'b010;

$monitor ("a = %b, b = %b, sel = %b, z = %b , carry = %b", a, b, sel, z, carry) ;
end
endmodule

2. For loop
module alu8bit_tb;
integer f1;
int i;
alu8bit a1();
initial
f1=$fopen("./Results_comb/alu_8bit1.txt");

initial
begin
{a,b}=16'b0;
sel=3'b000;
for(i=0;i<=25;i=i+1)

#10
{a,b}={a,b}+16'b0000001000000001;
#10 sel=sel+3'b001;
#20
$fmonitor("a=%b,b=%b,z=%b,carry=%b",a,b,z,carry);
end
always@ (*)
$fmonitor (f1, "\a = %b, b = %b, carry = %b, z = %b,sel = %b", a, b, carry,z,sel);
endmodule
3. Repeat
module alu8bit_tb;
integer f1;
alu8bit a1();
initial
f1=$fopen("./Results_comb/alu_8bit.txt");

initial
begin
{a,b}=16'b0;
sel=3'b000;
repeat(10)
#10
{a,b}={a,b}+16'b0000001000000001;
repeat(10)
#10 sel=sel+3'b001;
#20

$fmonitor("a=%b,b=%b,z=%b,carry=%b",a,b,z,carry);
#200 $finish;

end
always@ (*)
$fmonitor (f1, "\a = %b, b = %b, carry = %b, z = %b,sel = %b", a, b, carry,z,sel);
Endmodule

4.While
module tb_while();
integer f1;
integer I;
alu8bit a1();
initial
f1=$fopen("./Results_comb/alu_8bit2.txt");
initial
begin
{a,b}=16'b0;
sel=3'b000;
i=0;
while(i<25)
begin
#10
{a,b}={a,b}+16'b0000000000000001;
#10 sel=sel+3'b001;
#20
$fmonitor("a=%b,b=%b,z=%b,carry=%b",a,b,z,carry);
i=i+1;
end
end
always@ (*)
$fmonitor (f1, "\a = %b, b = %b, carry = %b, z = %b,sel = %b", a, b, carry,z,sel);

endmodule

Code for 4 bit up down counter

module counter_up_down #(parameter width = 7)(
output reg [width:0] count,
input [width:0] data,
input load, Up, clear, clock);
always@(posedge clock, negedge clear)

else
else
else

if(!clear)
count <= {(width+1){1'b0}};
if (load) count <= data;
if (Up) count <= count + 1'b1;
count <= count - 1'b1;

endmodule

Test benches
1. Linear
module counter_up_down_tb();
counter_up_down c1();
always
#5 clock=~clock;
initial
begin
clock=0; clear=0;load=0;
#50 clear=0;
#50 clear=1;
#5 data=8'b11111111;
#5 load=1;
#5 Up=0;
#5 load=0;
#100 Up=1;

$monitor("%b,%b,%b,%b,%b,%b",data,load,Up,clock,clear,count);
end
endmodule
2. For loop
module counter_up_down_tb();
integer f1;
integer i;
counter_up_down c1();
always
#5 clock=~clock;
initial
f1=$fopen("./Results_comb/counter.txt");

initial
begin
clock=0; clear=0;load=0;data=8'b11111111;Up=0;
for(i=0;i<200;i=i+1)
#5 clear=1;
#5 data=data+i;
#5 load=load+1'b 1;
#5 Up=Up+1'b 1;
end
always@ (*)

$fmonitor (f1, "\data = %b, load = %b, Up = %b, clear = %b,clock = %b,count = %b", data,
load,Up,clear,clock,count);

Endmodule
3. Repeat
module counter_up_down_tb();
integer f1;
counter_up_down c1();
always
#5 clock=~clock;
initial
f1=$fopen("./Results_comb/counter.txt");

initial
begin
clock=0; clear=0;load=0;data=8'b11111111;
repeat(10)
#50 clear=1;
#5 data=data+8'b00000001;
#5 load=1;
#5 Up=0;
#5 load=0;
#100 Up=1;
#200 $finish;
end
always@ (*)
$fmonitor (f1, "\data = %b, load = %b, Up = %b, clear = %b,clock = %b,count = %b", data,
load,Up,clear,clock,count);

endmodule

4. While
module counter_up_down_tb();
integer f1;
integer i;
counter_up_down c1();
always
#5 clock=~clock;
initial
f1=$fopen("./Results_comb/counter.txt");

initial
begin
clock=0; clear=0;load=0;data=8'b11111111;Up=0;i=0;
while(i<25)
begin
#5 clear=1;
#5 data=data+i;
#5 load=load+1'b 1;
#5 Up=Up+1'b 1;
i=i+1;
end
end
always@ (*)
$fmonitor (f1, "\data = %b, load = %b, Up = %b, clear = %b,clock = %b,count = %b", data,
load,Up,clear,clock,count);

Endmodule