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PLC

Chapter 1:
Introduction to Programmable Controllers
1.1 Definitions of PLC
The programmable (logic) controller (PLC) is an electronic device for
machine or process control. The PLC receives signals via inputs, processes them
according to the instructions of a program, and transfers signals to the outputs. The
program is created using programming software which is able to link inputs and
outputs in any required sequence, to measure time, or even carry out arithmetic
operations.

1.2 PLC Components and Principles of Operation


A typical PLC can be divided into five components. These components consist
of the processor unit, memory, power supply, input/output section (interface) and the
programming device. Some manufacturers refer to the processor as a C.P.U. or central
processing unit. The components are shown in Figure 1-1.

Figure 1-1. Programmable controller block diagram.

The input/ output (I/O) system is physically connected to the field devices that
are encountered in the machine or that are used in the control of a process (Figure 1-2).
These field devices may be discrete or analog input/output devices, such as limit
switches, pressure transducers, push buttons, motor starters, solenoids, etc. The
discrete input modules are available in wide range of voltages for various
applications. Some more common voltage modules are 120V AC, 240V AC, 24VDC.
The I/O interfaces provide the connection between the CPU and the information
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providers (inputs) and controllable devices (outputs). Optically coupled input and
output modules are used as they provide isolation of processor circuit from the real
word input and output devices which may be energized on higher level voltages
(Figure 1-3 and Figure 1-4).

Figure 1-2. Typical input / output modules

(a) input module (b) output module

(a) Simplified DC discrete input module circuit with indication light

(b) Simplified AC discrete input module circuit with indication light


Figure 1-3. Optically coupled discrete input modules

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(a) Simplified DC discrete output module circuit

(a) Simplified AC discrete output module circuit


Figure 1-4. Optically coupled discrete output modules

Although not generally considered a part of the controller, the programming


device, usually a personal computer or a manufacturers miniprogrammer unit, is
required to enter the control program into memory. The programming device must be
connected to the controller when entering or monitoring the control program.
The operation of a programmable controller is relatively simple. During its
operation, the CPU completes three processes: (1) it reads, or accepts, the input data
from the field devices via the input interfaces, (2) it executes, or performs, the control
program stored in the memory system, and (3) it writes, or updates, the output
devices via the output interfaces. This process of sequentially reading the inputs,
executing the program in memory, and updating the outputs is known as scanning.
Figure 1-5. illustrates a graphic representation of a scan.

Figure 1-5. Illustration of a scan.

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The total time for one complete program scan is a function of processor speed,
I/O modules used, and length of user program. Typically,
hundreds of complete scans can take place in 1 second.
Horizontal Scanning Order (rung scanning,)
The processor examines input and output
instructions from the first command, top left in the
program, horizontally, rung by rung.

Vertical Scanning Order (column scanning)


The processor examines input and output
instructions from the first command, vertically, column
by column and page by page. Pages are executed in
sequence.

1.3 PLC Size


There are five classes of PLC according to number of inputs , number of
outputs, cost, and physical size:
1. Nano:
2. Micro
3. Small
4. Medium
5. large
Some PLCs are integrated into a single unit (Picocontroller, Micrologix),
whereas others are modular (PLC5, SLC500). Integrated PLCs are sometimes called
brick PLCs because of their small size. These PLCs have embedded I/O (i.e. the I/O
is a part of the same unit as the controller itself). Modular PLCs have extended I/O.
Figure 1-6. show a PLC size examples

Figure 1-6. Allen-Bradley PLCs examples

1.4 Advantages and disadvantages of PLCs


In general, PLC architecture is modular and flexible, allowing hardware and
software elements to expand as the application requirements change. In the event that
an application outgrows the limitations of the programmable controller, the unit can
be easily replaced with a unit having greater memory and I/O capacity, and the old
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hardware can be reused for a smaller application. A PLC system provides many
benefits to control solutions, from reliability and repeatability to programmability.
Table 1-1 lists some of the many features and benefits obtained with a
programmable controller.
Table 1.1

PLC Disadvantages
Fixed Program Applications.
Some applications are single-function applications. It does not pay to use a
PLC that includes multiple programming capabilities if they are not needed.
Their operational sequence is seldom or never changed, so the
reprogramming available with the PLC would not be necessary.
Fail-Safe Operation.
In relay systems, the stop button electrically disconnects the circuit; if the
power fails, the system stops. This, of course, can be programmed into the
PLC; however, in some PLC programs, you may have to apply an input
voltage to cause a device to stop. These systems may not be fail-safe.

1.5 Typical area of PLC applications


Since its inception, the PLC has been successfully applied in virtually every
segment of industry, including steel mills, paper plants, food-processing plants,
chemical plants, and power plants. PLCs perform a great variety of control tasks, from
repetitive ON/OFF control of simple machines to sophisticated manufacturing and
process control.
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Chapter 2:
Logic Concepts
Operations performed by digital equipment, such as programmable controllers,
are based on three fundamental logic functionsAND, OR, and NOT. These
functions combine binary variables to form statements. Each function has a rule that
determines the statement outcome (TRUE or FALSE) and a symbol that represents it.
For the purpose of this discussion, the result of a statement is called an output (Y), and
the conditions of the statement are called inputs (A and B).

2.1 Logic Functions


THE AND FUNCTION
An AND function can have an unlimited number of inputs, but it can have only
one output. Figure 2-1 shows a two-input AND gate and its electrical circuit
representation, based on all possible input combinations. The letters A and B represent
inputs to the controller. This mapping of outputs according to predefined inputs is
called a truth table.

Figure 2-1. Two-input AND gate.

The boolean expression of AND gate is:

Y = AB
We can representation AND gate by a ladder logic as:

AND Ladder logic representation

THE OR FUNCTION
As with the AND function, an OR gate function can have an unlimited number
of inputs but only one output. Figure 2-2 shows an OR function and its electrical circuit
representation the resulting output Y, based on all possible input combinations.

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Figure 2-2. Two-input OR gate.

The boolean expression of OR gate is:

Y=A+B
We can representation OR gate by a ladder logic as:

OR Ladder logic representation

THE NOT FUNCTION


The NOT function, unlike the AND and OR functions, can have only one input.
It is seldom used alone, but rather in conjunction with an AND or an OR gate. Figure
2-3 shows the NOT operation and its electrical-circuit representation. Note that an A
with a bar on top represents NOT A.

Figure 2-3. NOT gate.

The boolean expression of NOT gate is:

Y=
We can representation OR gate by a ladder logic as:

NOT Ladder logic representation


At first glance, it is not as easy to visualize the application of the NOT function
as it is the AND and OR functions. However, a closer examination of the NOT
function shows it to be simple and quite useful. At this point, it is helpful to recall
three points that we have discussed:
1. Assigning a 1 or 0 to a condition is arbitrary.
2. A 1 is normally associated with TRUE, HIGH, ON, etc.
3. A 0 is normally associated with FALSE, LOW, OFF, etc.

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Examining statements 2 and 3 shows that logic 1 is normally expected to


activate some device (e.g., if Y = 1, then motor runs), and logic 0 is normally expected
to deactivate some device (e.g., if Y = 0, then motor stops). If these conventions were
reversed, such that logic 0 was expected to activate some device (e.g., if Y = 0, then
motor runs) and logic 1 was expected to deactivate some device (e.g., Y = 1, then
motor stops), the NOT function would then have a useful application.

THE EXCLUSIVE OR FUNCTION (XOR)


The EXCLUSIVE OR function, can have only two input and one output.

Figure 2-4. XOR gate and its truth table.

XOR Electrical-circuit and ladder logic representation.

The boolean expression of XOR gate is:

THE EXCLUSIVE NOR FUNCTION (XNOR)


The EXCLUSIVE NOR function, can have only two input and one output.

Figure 2-5. XNOR gate and its truth table.

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XNOR Electrical-circuit and

ladder logic representation

The boolean expression of XOR gate is:

EXAMPLE 2-1
Show the logic gate, truth table, and circuit representation for a solenoid valve (V1)
that will be open (Energized) if selector switch S1 is ON (closed) and if level switch
L1 is NOT ON (Not closed, liquid has not reached level).

SOLUTION

Note: In this example, the level switch L1 is normally open, but it closes when the liquid level
reaches L1. The ladder circuit requires an auxiliary control relay (CR1) to implement the not
normally open L1 signal. When L1 closes (ON), CR1 is energized, thus opening the normally
closed CR1-1 contacts and deactivating V1. S1 is ON when the system operation is enabled.

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2.2 Principles of Boolean Algebra and Logic


An understanding of the Boolean techniques for writing shorthand expressions
for complex logical statements can be useful when creating a control program of
Boolean statements or conventional ladder diagrams.
Figure 2-4 summarizes the basic Boolean operators as they relate to the basic
digital logic functions AND, OR, and NOT. These operators use capital letters to
represent the wire label of an input signal, a multiplication sign () to represent the
AND operation, and an addition sign (+) to represent the OR operation. A bar over a
letter represents the NOT operation.

Figure 2-4. Boolean algebra as related to the AND, OR, and NOT functions.

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Table 2-1. Logic operations using Boolean algebra.

EXAMPLES
1-Boolean Equation:

Ladder Logic for Equation

2- Boolean Equation:

Ladder Logic for Equation

3- Boolean Equation:

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The circuit and equivalent ladder logic.

4- Given the controller equation;

The circuit is given below, and equivalent ladder logic is shown

The PLC does not allow for programming vertical contacts Figure 2-6.. In the real
world, one could wire the circuit as shown in the figure, but programming restrictions
would not allow the PLC to be programmed in this manner, the user must reprogram
the rung with forward power flow to all contact elements. The next example illustrates
the solution to the vertical contact rung in Figure 2-6.
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Figure 2-6. Reverse power flow at contact D.

EXAMPLE 2-2
Solve the logic rung shown in Figure 2-6. so that no reverse power flow condition
exists. The reverse condition is not part of the required logic for the output to be
energized.
SOLUTION
The forward power flow of the logic determines output Y. Lets implement it
using logic concepts. The output Y is defined, using forward paths only, as:

which can be minimized, using Boolean algebras distributed rule.

shows the implementation of this logic gate, while


ladder-equivalent solution.
Figure 2-7

Figure 2-8

gives the

Figure 2-7. Logic solution for Example 2-3.

Figure 2-8. Ladder diagram implementation for Example 2-3.

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Chapter 3:
PLC Programming
3.1 Programming Devices
Although the way to enter the control program into the PLC has changed since
the first PLCs came onto the market, PLC manufacturers have always maintained an
easy human interface for program entry. This means that users do not have to spend
much time learning how to enter a program, but rather they can spend their time
programming and solving the control problem. Most PLCs are programmed using
very similar instructions. The only difference may be the mechanics associated with
entering the program into the PLC, which may vary from manufacturer to
manufacturer. This involves both the type of instruction used by each particular PLC
and the methodology for entering the instruction using a programming device. The
two basic types of programming devices are:
Miniprogrammers
Personal Computers
Miniprogrammers, also known as handheld or manual programmers, are an
inexpensive and portable way to program small PLCs (up to 128 I/O). Physically,
these devices resemble handheld calculators, but they have a larger display and a
somewhat different keyboard. The type of display is usually LED (light-emitting
diode) or dot matrix LCD (liquid crystal display), and the keyboard consists of
numeric keys, programming instruction keys, and special function keys. Instead of
handheld units, some controllers have built-in miniprogrammers. In some instances,
these built-in programmers are detachable from the PLC. Even though they are used
mainly for editing and inputting control programs, miniprogrammers can also be
useful tools for starting up, changing, and monitoring the control logic. Figure 3-1
shows a typical miniprogrammer along with a small PLC, in which miniprogrammers
are generally used.
Most miniprogrammers are designed so that they are compatible with two or
more controllers in a product family. The miniprogrammer is most often used with the
smallest member of the PLC family or, in some cases, with the next larger member,
which is normally programmed using a personal computer with special PLC
programming software. With this programming option, small changes or monitoring
required by the larger controller can be accomplished without carrying a personal
computer to the PLC location.
Some miniprogrammers offer removable memory cards or modules, which store
a complete program that can be reloaded at any time into any member of the PLC
family. This type of storage is useful in applications where the control program of one
machine needs to be duplicated and easily transferred to other machines.

Figure 3-1. A typical miniprogrammer and a small PLC.

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Personal computers
Common usage of the personal computer (PC) in our daily lives has led to the
practical elimination of dedicated PLC programming devices. Due to the personal
computers general-purpose architecture and standard operating system, most PLC
manufacturers and other independent suppliers provide the necessary PC software to
implement ladder program entry, editing, documentation, and real-time monitoring of
the PLCs control program. The large screens of PCs can show one or more ladder
rungs of the control program during programming or monitoring operation.
Personal computers are the programming devices of choice not so much because
of their PLC programming capabilities, but because PCs are usually already present at
the location where the user is performing the programming.
The different types of desktop, laptop, and portable PCs give the programmer
flexibility they can be used as programming devices, but they can also be used in
applications other than PLC programming. For instance, a personal computer can be
used to program a PLC, but it may also be connected to the PLCs local area network
to gather and store, on a hard disk, process information that could be vital for future
product enhancements.

3.2

Types of PLC Languages

The five types of programming languages used in PLCs are:


1- Ladder (Logic) Diagram (LAD or LD)- Relay logic diagram based programming
2- Function Block Diagrams (FBD)- A graphical dataflow programming method
3- Instruction List (Statement List )(IL) -This is effectively mnemonic programming
4- Structured Text (ST)- A BASIC like programming language
5- Sequential Function Charts (SFC)- A graphical method for structuring programs
1- Ladder Diagram (LAD)
A very commonly used method of programming PLCs is based on the use of
ladder diagrams. Writing a program is then equivalent to drawing a switching circuit.
The ladder diagram consists of two vertical lines representing the power rails. Circuits
are connected as horizontal lines, i.e. the rungs of the ladder, between these two
verticals.

Figure 3-2. Ladder Diagram.

In drawing a ladder diagram Figure 3-2., certain conventions are adopted:


1- The vertical lines of the diagram represent the power rails between which circuits
are connected. The power flow is taken to be from the left-hand vertical across a
rung.
2- Each rung on the ladder defines one operation in the control process.
3- A ladder diagram is read from left to right and from top to bottom.
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4- Each rung must start with an input or inputs and must end with at least one output.
The term input is used for a control action, such as closing the contacts of a
switch, used as an input to the PLC. The term output is used for a device
connected to the output of a PLC, e.g. a contactor.
5- A particular device can appear in more than one rung of a ladder. For example, we
might have a relay which switches-on one or more devices. The same letters
and/or numbers are used to label the device in each situation.
6- The inputs and outputs are all identified by their addresses or notation used
depending on the PLC manufacturer. This is the address of the input or output in
the memory of the PLC.
2- Function Block Diagram (FBD)
The term function block diagram (FBD) is used for PLC programs described in
terms of graphical blocks. It is described as being a graphical language for depicting
signal and data flows through blocks, these being reusable software elements. A
function block is a program instruction unit which, when executed, yields one or more
output values. Thus a block is represented in the manner shown in the figure below
with the function name written in the box.

Figure 3-2. function block diagram.

3- Instruction Lists ( IL)


Instruction lists (IL) is a programming method, which can be considered to be
the entering of a ladder program using text. Instruction list gives programs which
consist of a series of instructions, each instruction being on a new line. An instruction
consists of an operator followed by one of more operands, i.e. the subjects of the
operator. In terms of ladder diagrams an operator may be regarded as a ladder
element. Each instruction may either use or change the value stored in a memory
register. For this, mnemonic codes are used, each code corresponding to an
operator/ladder element. The codes used differ to some extent from manufacturer to
manufacturer, though a standard IEC 61131 has been proposed and is being widely
adopted. Table 3.1 shows some of the codes used by manufacturers, and the proposed
standard.
4- Structured Text (ST)
If you know how to program in any high level language, such as Basic or C, you
will be comfortable with Structured Text (ST) programming. The language is
composed of written statements separated by semicolons. The statements use
predefined statements and program subroutines to change variables. The variables can
be explicitly defined values, internally stored variables, or inputs and outputs. An
example program is shown in Figure 3-3.

Figure 3-3. ST program example.

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Table 3.1 Instruction code mnemonics

5- Sequential Function Charts (SFC)


Sequential Function Charts (SFCs) are a graphical technique for writing
concurrent control programs. For the application shown in Figure 3-4, the PLC will
execute action 2 only after step 1 receives a valid input and transition 1 occurs (i.e.,
the limit switch LS_Reach triggers). After the PLC finishes action 2, it will wait for
transition 2 (IF Temp_1100) to occur and then move to step 3.

Figure 3-4. SFC program example.

3.3

Examples
AND Gate

FBD

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Standard IL
(*Load I0.0*)
(*AND I0.1*)
(* Store result in Q0.0, i.e. output to Q0.0*)

LD I0.0
AND I0.1
ST
Q0.0

Siemens

OR Gate
LAD

FBD

Siemens
IL

NOT Gate
LAD

FBD

Siemens
IL

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Siemens (Simatic Step7-300)

I0.0

&

I0.2

>=1

I0.2

Q0.0

&

I0.1

I0.0
I0.1

&
>=1

I0.1
I0.2

&

I0.3

&

I0.4

>=1

I0.3
I0.4

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XOR gate: (a) Mitsubishi, (b) Siemens


LAD

(a) Mitsubishi

(b) Siemens

In such a situation Mitsubishi uses an ORB instruction to indicate OR together


parallel branches. ORB (OR branches/blocks together)
FBD

Two branched AND gates: (a) Mitsubishi, (b) Siemens

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3.4

Addresses Used in PLC's

Each symbol on a rung will have a reference number, which is the address in
memory where the current status (1 or 0) for the referenced input is stored. When a
field signal is connected to an input or an output interface, its address will be related
to the terminal where the signal wire is connected. The address for a given
input/output can be used throughout the program as many times as required by the
control logic. This PLC feature is an advantage when compared to relay-type
hardware, where additional contacts often mean additional hardware.

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Chapter 4:
PLC Basic Instructions
4.1 Examine if Closed (Examine if ON) (XIC)
When an input device completes its circuit the input terminal wired to the device
indicates an on state. This on state is reflected in memory for the corresponding bit.
When the processor finds an XIC instruction having the same address, it determines
that the input device is on or closed and sets the instruction logic to true. When the
input device no longer completes its circuit, the processor sets the logic for this
instruction to false.
If the rung containing this instruction also contains an output instruction, the output
instruction is enabled when the XIC instruction is True (input closed); a non-retentive
output instruction is disabled when the XIC instruction is False (input open).
An input can be a connected switch closure or sensor, a contact from a
connected output, or a contact from an internal output.
Programming The XIC Instruction

Figure 4-1. Programming the XIC instruction

In Figure 4-1 note that both pushbuttons are represented by the XIC symbol. This
is because the normal state of an input (N.O or N.C) does not matter! What does
matter is that if contacts need to close to energize the output, then the XIC instruction
is used. Since both PB1 and PB2 must close to energize the PL, the XIC instruction is
used for both. Figure 4-2 show the PLC connection diagram.

Figure 4-2. PLC connection diagram

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4.2 Examine if Open (Examine if OFF) (XIO)


When an input device no longer completes its circuit, the input terminal wired to
the device indicates an off state. This off state is reflected in memory for the
corresponding bit. When the processor finds an XIO instruction having the same
address, the processor determines that the input is off (input open) and sets the
instruction logic to true. When the input device completes its circuit, the processor
sets the logic for this instruction to false.
If the rung containing this instruction also contains an output instruction, the
output instruction Is enabled when the XIO instruction is True (input open); the non
retentive output instruction is disabled when the instruction is False (input closed).
An input can be a connected switch closure or sensor, a contact from a
connected output, or a contact from an internal output.
Programming The XIO Instruction

Figure 4-3. Programming the XIO instruction

Referring to Figure 4-3 when the pushbutton is open in the hardwired circuit,
relay coil CR is de-energized and contacts CR1 close to switch the PL on. When the
pushbutton is closed, relay coil CR is energized and contacts CR1 open to switch the
PL off. The pushbutton is represented in the user program by an XIO instruction. This
is because the rung must be true when the external pushbutton is open, and false when
the pushbutton is closed. Figure 4-4. show the PLC connection diagram.

Figure 4-4. PLC connection diagram

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4.3 One-Shot Rising (OSR)


When the rung conditions preceding the OSR instruction go from false-to-true,
the OSR instruction will be true for only one scan. After one scan is complete, the
OSR instruction becomes false, even if the rung conditions preceding it remain true.
The OSR instruction will only become true again if the rung conditions preceding it
transition from false-to-true. Figure 4-5 show the OSR-instruction example.

Figure 4-5 OSR-instruction example.

The bit address you use for this instruction must be unique. Do not use it
elsewhere in the program. Do not use an input or output address to program the
address parameter of the OSR instruction.

4.4 Out Energize (OTE)

or

Use OTE instructions to set a particular bit in memory. If the address of the bit
corresponds to the address of an output module terminal, the output device wired to
this terminal is energized. The enabled status of this bit is determined by rung logic in
your application program.
If a true logic path is established with the input instructions in the rung, the OTE
instruction is enabled. If a true logic path cannot be established or rung conditions go
false, the OTE instruction is disabled. When rung conditions become false, the
associated output device de-energizes.
An OTE instruction is similar to a relay coil. The instruction is controlled by the
preceding instructions in its programmed rung. A relay coil is controlled by contacts
in its hard-wired rung. A complete logic path of true preconditions is similar to a
complete electrical circuit of closed contacts.
Your program can examine a bit controlled by these instructions as often as
necessary.
Each set of available outputs (coils) and its respective contacts in the PLC have
a unique reference address by which they are identified. For instance (Figure 4-6), coil
O:0/1 will have normally open and normally closed contacts with the same address
O:0/1 as the coil. Note that a PLC can have as many normally open and normally
closed contacts as desired; whereas in an electromechanical relay, only a fixed
number of contacts are available.
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Figure 4-6. Multiple contacts from a PLC output coil.

Properly formatted outputs

1- An output energize instruction (OTE) referencing a specific output bit should


appear only once in a ladder logic program (Figure 4-7).

Figure 4-7. Repeated output.

2- Only one output energize instruction (OTE) should appear in a rung of ladder logic
(Figure 4-8).

Figure 4-8. Series outputs.

3- If more than one output is to be controlled by a certain rung of ladder logic, the
output energize (OTE) instructions can be placed in parallel (Figure 4-9).

Figure 4-9. Parallel outputs.

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4.5 Output Latch(Set) and Output Unlatch (Reset) (OTL), (OTU)

Output latch and output unlatch instructions are retentive output instructions.
They are usually used in a pair for any data table bit they control.
When you assign an address to the OTL instruction that corresponds to the
address of an output module terminal, the output device wired to this terminal is
energized when the bit in memory is set (turned on or enabled). The enabled status of
this bit is determined by the rung logic preceding the OTL and OTU instructions.
If a true logic path is established with the input instructions in the rung, the OTL
instruction is enabled. If a true logic path is not established and the corresponding bit
in memory was not previously set, the OTL instruction is not enabled. However, if a
true logic path was previously established, the bit in memory is latched on and
remains on, or enabled, even after the rung conditions go false (Figure 4-10).

Figure 4-10. Output latch instruction.

An OTU instruction with the same address as the OTL instruction resets
(disables or turns off) the bit in memory. When a true logic path is established, the
OTU instruction resets its corresponding bit in memory (Figure 4-11).

Figure 4-11. Output latch and unlatch instruction.

4.6 Internal relay


The internal output operates just as any other output that is controlled by
programmed logic; however, the output is used strictly for internal purposes. The
internal output does not directly control an output device.

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The advantage of using internal outputs is that there are many situations where
an output instruction is required in a program, but no physical connection to a field
device is needed. Their use in this type of instance can minimize output card
requirements. Figure 4-12. show an internal-relay example using Mitsubishi and
Siemens manufacturers.

(a) Mitsubishi

(b) Siemens
Figure 4-12. internal-relay example

4.7 Data Files


The data file portion of memory stores input and output status, processor status,
the status of various bits and numerical data. Data files are organized by the type of
data they contain. Figure 4-13 show the file types for data files of SLC 500, 3
through 8 are the default values. Files 9 to 255 can be configured to be bit, timer,
counter, control, integer, floating point, or ASCII files. Figure 4-14 show data files
table. Figure 4-15. show the data files in the project tree.

Figure 4-13. File types of data files

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Figure 4-14. Data files table

Figure 4-15. Data files in the project tree.

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4.8 PLC Software and Simulator


A personal computer is most often used to enter the ladder diagram. The
computer is adapted to the particular PLC model using the relevant programmable
controller software.
The PLC simulator (LogixPro) (Figure 4-16) can be accessed from:
Start->Programs->TheLearningPit->LogixPro

Figure 4-16. PLC simulator (LogixPro).

Different screens, toolbars and windows dialog boxes are used to navigate
through the Windows environment. Ladder logic elements (instructions) (Figure 4-17).
can be dragged and dropped onto the ladder window to create a ladder logic program.

Figure 4-17. Ladder logic elements

The ladder logic program is executed by going online, downloading the PLC
program, and switching to run mode. Figure 4-18.

Figure 4-18. PLC online, download and modes of operation

The Logixpro simulator provides a set of built-in simulations, the simulations


are shown in Figure 4-19.
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Figure 4-19. Logixpro built-in simulations

The programming software needs to know what processor is being used in


conjunction with the program. Figure 4-20. show the dialog box of Select Processor
Type.

Figure 4-20. Dialog box of Select Processor Type.

Figure 4-21. show the I/O Configuration dialog box. The I/O screen lets you
click or drag-and-drop a module from an all inclusive list to assign it to a slot in your
configuration.

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Eng. Mohammad Al-Arni

Figure 4-21. show the I/O Configuration dialog box

Modes of Operation
A processor has basically two modes of operation: the program mode or some
variation of the run mode.
Program Mode may be used to
enter a new program
edit or update an existing program
upload files
download files
document programs
change software configurations
When the PLC is switched into the program mode, all outputs from the PLC are
forced off regardless of their rung logic status, and the ladder I/O scan sequence is
halted.
Variations of the Run Mode
Run Mode is used to execute the user program. Input devices are monitored and
output devices are energized accordingly.
Test Mode is used to operate, or monitor, the user program without energizing any
outputs.
Remote Mode allows the PLC to be remotely changed between program and run
mode by a personnel computer connected to the PLC processor.

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4.9 Examples:
Start-stop-seal circuits
For PLC systems without latch and unlatch instructions, a circuit is needed that
will allow a process to start, continue to run after a start button is released, and stop
under control of another button. A circuit that implements this functionality is
commonly referred to as a start-stop-seal circuit. A feedback path (i.e. a contact) that
references the output is normally used to seal around the start contact.
Ex. 1- (a) Write a program that will implement the standard STOP/START
motor control circuit shown (start-stop-seal circuit).
Inputs: Stop I:1/0, Start I:1/1

Output: M O:1/0

Solution

(b) Add the necessary programming for a motor run light (O:1/2) and a motor
standby or OFF light (O:1/3).
Solution

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(c) Add the necessary programming for a second stop pushbutton (I:1/2) and second
start pushbutton (I:1/3) (ON/OFF from two position).
In practice several start and/or several stop buttons can be used in a process
Start buttons (with XIC instructions) can be used
In series if it is required that ALL be pressed before a process starts
In parallel if pressing ANY start button is to start a process (two position)
Stop buttons are normally used in series if pressing ANY stop button is to stop a
process.
Solution

Ex. 2- Write a program that will implement relay schematic shown. This
program demonstrates that the contacts of a single-pole input device can be
programmed as a double-pole device.
Inputs: Use only N.C contact of pressure switch (I:1/1).
Outputs: L - O:1/0, H- O:1/1

Solution

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Ex. 3- Write a program that will turn ON a light if one or the other of two
switches is closed. If both switches are closed simultaneously, an alarm operates that
can only be shut OFF by pushing a reset button.
Inputs: Switch (I:1/0), Switch (I:1/1), Reset pushbutton (I:1/2).
Outputs: Light (O:1/0), Alarm (O:1/1).
Solution

Interlock circuits
Interlocks can prohibit output(s) from energizing under a certain condition
Example: O:2/0 should not energize if O:2/1 is energized (and vise-versa)
Ex. 4- Write a program that will implement the reciprocating motion machine
process control schematic shown. The sequence of operation is as follows:

The work-piece starts on the left and moves to the right when the START
button is pressed.
When it reaches the rightmost limit, the drive motor reverses and brings the
work-piece back to the leftmost position again, and the process repeats.
The reverse pushbutton provides a means of starting the motor in the reverse
so that the limit switch LS1 can take over automatic control.
Inputs: Stop (N.C) (I:1/4), Start (N.O) (I:1/2), Reverse pushbutton (N.O)
(I:1/3), Limit switch LS1 (N.O) (I:1/6), Limit switch LS2 (N.O)
(I:1/7), Overload contact OL (N.C) (I:1/5).
Outputs: F- (O:1/0), R- (O:1/1).

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Solution

Ex. 5- Write a program that will cause output pilot light PL to be latched when
pushbutton PB1 is closed and unlatched when either pushbutton PB2 or PB3 is
closed. Also, do not allow the unlatch to go true when the latch rung is true, nor allow
the latch rung to go true when the unlatch rung is true.
Inputs: PB1 (N.O) (I:1/0), PB2 (N.O) (I:1/1), PB3 (N.O) (I:1/2).
Output: Pilot Light PL (O:1/0).
Solution

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Eng. Mohammad Al-Arni

Chapter 5:
PLC Timers and Counters Functions
5.1 Introduction
Timer and counter instructions are output instructions that you can condition by
input instructions such as examine if closed and examine if open. Timers time
intervals and counters count events, as determined by your application program logic.
Each timer or counter instruction has two values associated with it. These values are:
Preset value (PRE, PR) This is your predetermined set point. You enter this
value to govern the timing or counting of the instruction. When the accumulated value
is equal to or greater than the preset value, a status bit is changed. You can use this bit
to control an output device.
Accumulated value (ACC, AC) This is the current number of ticks that have
been measured for a timer instruction; or for a counter instruction, the number of
events that has occurred.
Timer and counter instructions require three words of data table, one word each for:

Control word
Preset value
Accumulated value

5.2 Timer Information


Timer Values. A timer instruction has three important values associated with it:
the time base
the preset value
the accumulated value
Timebase: The timebase determines the duration of each timebase interval.
Example: If the timer base is set to 0.01, it would take 200 counts as the preset value
(PRE) to equal 2 seconds worth of timing.(see Figure 5-1)

Figure 5-1. Time base illustration

In this example of a timer with a 0.01 time base and a target value of 2 seconds, the
preset value would be 200. This value indicates that the timer must wait 200 time
bases before timing out. The selection of the time base depends on what is most
appropriate for the application.

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Each timers has three words associated with it (see Figure 5-2). Each of the three
words associated with a timer holds a specific kind of data (see Figure 5-3):
Word 0 holds control data about the status of the timers enable output,
whether the timer is actively timing, and the status of the timers done output.
Control-word data for timer instructions includes:
EN = Timer Enable bit
DN = Timer Done bit
TT = Timer Timing Bit

The control word stores this information in bits 15, 14, and 13, respectively.
Word 1 stores the timers preset value. This is the target timing value
specified in memory.
Word 2 holds the accumulated value. This value indicates how much time
has actually elapsed since the timer was energized.

Figure 5-2. The timer file showing the three words associated with each timer.

Figure 5-3. The data stored in each word of a timers address.

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5.3 On-Delay Timer (TON)


The format of a timer on-delay instruction is:

Figure 5-4. A timer ON-delay instruction.

A timer ON-delay instruction energizes its done output after the timer blocks
input turns on and a specified delay has occurred. (see Figure 5-4).
Following is a description of the operation of the TON instruction:

The TON instruction begins to count time-base intervals when rung conditions
become true. As long as rung conditions remain true, the timer increments its
accumulated value (AC) each scan until it reaches the preset value (PR). The
accumulated value is reset when rung conditions go false, regardless of
whether the timer has timed out.
The done bit (DN) is set when the accumulated value is equal to the preset
value. It is reset when rung conditions become false.
The timer enable (EN) bit is set when rung conditions are true; it is reset
when rung conditions become false.
The timing bit (TT) is set when rung conditions are true and the
accumulated value is less than the preset value, it is reset when rung
conditions go false or when the done bit is set.

Figure 5-5 illustrates how a timer ON-delay instruction works. When the timer
blocks input has logic continuity, the blocks enable output will turn on. As a result, a
1 will be stored in bit 15 of the timers control word. Once the timer is enabled, it will
start to time. Thus, a 1 will be stored in bit 14, which is the timer timing bit. As the
timer times, the accumulated value increases until it equals the preset value. At that
point, the timer timing bit will become a 0, and the done bit will become a 1, meaning
that the done output will turn on. This done output is the timers delay action contact.
The timers input logic must turn off and then on again before the timer will start

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timing again. The timers done output can be referenced throughout the program by
XIC and XIO contacts to implement the time delay.
In the ladder program shown in Figure 5-5, the pilot light output will turn on
four seconds after the push button (PB) input is pressed. In the ladder diagram, the
input logic to the pilot light is a contact that references the done output coil of the
timer block. The timers address is T4:18, its preset value is 4, and its time base is 1
second.

Figure 5-5. A timer ON-delay block and its associated timing diagram.

The following (Figure 5-6) shows a ladder diagram program controlling an


output device using the TON done bit. By substituting XIC or XIO instructions, you
can turn an output on or off depending on your ladder logic. In this figure, when the
TON timer enabled by I:101 pushbutton, the output O:301 set on for first 5sec and
then it is reset. The output O:300 set on after first 5sec and remain set until reset
pushbutton I:100 pressed.

Figure 5-6. A ladder diagram program controlling an output device using the TON done bit.

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5.4 Off-Delay Timer (TOF)


The format of a timer on-delay instruction is:

Figure 5-7. A timer OFF-delay instruction.

Figure 5-7 illustrates a timer OFF-delay instruction. A timer OFF-delay


instruction de-energizes its done output after the timer blocks input turns off and a
specified delay has occurred.
Use the TOF instruction to turn an output on or off after its rung has been off for
a preset time interval. The TOF instruction begins to count timebase intervals when
the rung makes a true-to-false transition. As long as rung conditions remain
false, the timer increments its accumulated value (AC) based on the timebase for
each scan until it reaches the preset value (PR). The accumulated value is reset when
rung conditions go true regardless of whether the timer has timed out.

The done bit (DN) is set when rung conditions are true. It is reset when
rung conditions go false and the accumulated value is greater than or
equal to the preset.
The timer enable (EN) bit is set when rung conditions are true; it is reset
when rung conditions become false.
The timing bit (TT) is set when rung conditions are false and the
accumulated value is less than the preset value, it is reset when rung
conditions go true or when the done bit is reset.

The ladder program in Figure 5-8 uses a timer OFF-delay instruction. This
circuit works as follows:
The done output will be off when the program is first started and the timers input
is off.
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When the input logic turns on, both the blocks enable output and done output
will turn on. However, the timer will not start timing because it is waiting for an
OFF signal instead of an ON signal.
When the blocks input turns off, the enable output will turn off and the timer will
start timing. The done output will stay on because it is waiting for the timer to
time out before it will turn off.
Once the accumulated value equals the preset value, the timer will stop timing and
the done output will turn off, implementing the OFF-delay de-energize function.
Therefore, the done bits action follows the action of the timers input signal,
except that the done bit remains on for the specified delay period after the input
turns off. All of the timers outputs will now remain off until the input logic turns
on again. At this point, the accumulated value is reset to 0.

Figure 5-8. A timer OFF-delay block and its associated timing diagram.

5.5 Retentive Timer (RTO)

The entry format of a retentive timer instruction is the same as a timer on-delay
instruction. A retentive timer, however, can stop timing and then start timing again
without its accumulated value resetting to 0.
The RTO instruction begins to count time-base intervals when rung conditions
become true. As long as rung conditions remain true, the timer increments its
accumulated value (ACC) each scan until it reaches the preset value (PRE). The
accumulated value is retained when the rung conditions become false.
When the rung conditions go true, timing continues from the retained
accumulated value. By retaining its accumulated value, retentive timers measure the
cumulative period during which rung conditions are true. You can use this instruction
to turn an output on or off depending on your ladder logic.

The accumulated value must be reset by the RES instruction. When the
RES instruction having the same address as the appropriate retentive timer is
enabled, the accumulated value and the control bits are reset if the RTO rung

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is false. The operation of a reset instruction is explained in the counter section


of this chapter.
The done bit (DN) is set when the accumulated value is equal to the preset
value. However, it is not reset when rung conditions become false; it is
reset only when the appropriate RES instruction is enabled.
The enable bit (EN) is set when rung conditions are true; it is reset when rung
conditions become false.
The timing bit (TT) is set when rung conditions are true and the
accumulated value is less than the preset value, it is reset when rung
conditions go false or when the done bit is set.

Figure 5-9 shows a retentive timer circuit and its timing diagram, which work
as follows:
When the input logic turns on, the enable output will turn on, and the timer will start
timing.
If the input logic turns off, the enable output will turn off, and the timer will stop
timing. The accumulated value, however, will not reset to 0.
When the timer starts timing again, it will pick up where it left off.
When the accumulated value finally reaches the preset value, the done output will
turn on.
Once a retentive timer has timed out, its done output will remain on even if its input
logic and enable output turn off. A reset instruction must be used to turn the done
output off and reset the timers accumulated value.

Figure 5-9. A retentive timer circuit and its associated timing diagram.

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Examples:
Ex. 1- When a switch is turned on, PL1 and PL2 go on immediately. PL1 turns
off after 4 seconds. PL2 remains on until the switch is turned off. Turning the switch
off at any time turns both lights off. Write a program that will implements this
process.
Input: Switch (I:1/0). Outputs: Pilot Light PL1 (O:1/1), Pilot Light PL2 (O:1/2).
Solution

Ex. 2- Write a program that will turn on pilot light PL1 10sec after switch S1 is
turned on. Pilot light PL2 will come on 5sec after PL1 comes on. Pilot light PL3 will
come on 8sec after PL2 comes on. Pressing PB1 will reset all the timers but only if
PL3 is on.
Inputs: Switch S1 (I:1/0), Pushbutton PB1 (I:1/4).
Outputs: Pilot Light PL1 (O:1/1), Pilot Light PL2 (O:1/2), Pilot Light PL3 (O:1/3).
Solution

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Ex. 3- When the lights are turned off in building by S1, an exit door light is to
remain on for an additional 10sec. and the parking lot lights are to remain on for an
additional 20sec after the door light goes out. Writ a program to implement this
process.
Input: Light switch (I:1/0). Outputs: Building light (O:1/0), Exit door light
(O:1/1), Parking lot light (O:1/2).
Solution

Ex. 4- Develop a ladder logic program that will control


traffic lights in one direction in the following sequence:
RED light on for 12sec.
GREEN light on for 8 sec
AMBER light on for 4sec
Sequence is repeated.
Solution

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Eng. Mohammad Al-Arni

Homework
Modify the program of Example 4 so as to control the traffic light in both
directions.
Red = O:1/00

Green = O:1/02

Green = O:1/06

Amber = O:1/05

8 Sec.

4 Sec.

Amber = O:1/01

Red = O:1/04
8 Sec.

4 Sec.

5.6 Count Up and Count Down Counters (CTU, CTD)


The formats of the CTD and CTU instructions are:

Count up and count down instructions count false-true rung transitions. These
rung transitions could be caused by events occurring in the program (from internal logic
or by external field devices) such as parts traveling past a detector or actuating a limit
switch.
Counter Values. A counter instruction has two values associated with it:
the preset value
the accumulated value
These values perform the same function as they do in timer instructions. The preset
value specifies the target number of counts, while the accumulated value indicates the
actual number of counts that have already occurred. In a counter, the preset and
accumulated values always increase or decrease in increments of one.
Each count is retained when the rung conditions again become false. The count
is retained until an RES instruction having the same address as the counter instruction
is enabled.
As with timers, each counter is allotted three words, which are numbered 0, 1,
and 2. Each of these three words stores particular data about the counter instruction
(see Figure 5-10):
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Figure 5-10. The data stored in each word of a counters address.

Word 0 is the control word, which stores data about the counter blocks
operation and status. This word holds information about the status of the count
up and count down outputs and data about the counters done, overflow, and
underflow status. This information is stored in bits 11 through 15 of the
control word.
Word 1 stores the counters preset value, which is the target count value.
Word 2 stores the counters accumulated value, which is the actual count
value. A counters preset and accumulated words, words 1 and 2, are
addressed with the labels PRE and ACC in the RSLogix software.

5.6.1 Count Up Instruction


A count up instruction is represented by the symbol shown in Figure 5-11.
The function of a count up instruction is to increase its accumulated value by one
every time the blocks input makes an OFF-to-ON transition. After a certain number
of OFF-to-ON transitions have occurred, the count up instruction will energize its
output. A count up block has two output coils:
a count up output coil (CU), which indicates that the counter block is
energized
a done output coil (DN), which indicates that the count is complete

Figure 5-11. A count up instruction.

The control word for counter instructions includes the following status bits:

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In a counter circuit, the counter will continue to count even after the
accumulated value has reached the preset value. The done output will remain on as
long as the accumulated count is greater than or equal to the preset count. The only
way to reset the accumulated value and turn off the done output is to use a reset
instruction.

5.6.2 Count Down Instruction


A count down instruction (see Figure 5-12) decreases its accumulated value
by one every time the blocks input makes an OFF-to-ON transition. When the
accumulated value becomes less than the preset value, the count down instruction deenergizes its output. When the counters accumulated value is greater than or equal to
its preset value, the counters output will be on.

Figure 5-12. A count down instruction.

Like a count up instruction, a count down instruction also has two outputs:
a count down output, which indicates that the counter is energized
a done output, which signals that the target count value has been reached
The control word for counter instructions includes the following status bits:

In practice, a count down instruction is most often used with a count up


instruction to form an up/down counter. In the up/down counter shown in Figure 5-13,
both counters share the same address and the same preset and accumulated values. As
a result, the up counter increases the accumulated value every time a certain event
occurs, while the down counter decreases the same accumulated value if another
event occurs.

Figure 5-13. Up/down counter configuration.

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5.6.3 Reset (RES)


This output instruction has the format -(RES)-. Use a RES instruction to reset a
timer or counter. When the RES instruction is enabled, it resets the Timer On Delay
(TON), Retentive Timer (RTO), Count Up (CTU), or Count Down (CTD) instruction
having the same address as the RES instruction.
When an RES instruction is enabled, it resets the following:

If the counter rung is enabled, the CU or CD bit will be reset as long as the RES
instruction is enabled. If your preset value is negative, the RES instruction sets the
accumulated value to zero. This, in turn, causes the done bit to be set by the count
down or count up instruction.
A reset instruction can be used with all types of timing and counting instructions
except a timer OFF-delay instruction. It cannot be used with a timer OFF-delay
instruction because a reset instruction resets the done, timer timing, and enable bits of
the timers control word. If the status of these bits is altered while a timer OFF-delay
instruction is timing, a machine malfunction, unpredictable machine operation or
injury to personnel may occur.

5.6.4 Special Programming Issues


When using counter instructions you must consider some special programming
issues:
using a reset instruction to implement a self-resetting counter
counting past the maximum count
reading fast input signals

Self-Resetting Counter. A self-resetting counter is a counter that resets itself in


the same scan after the accumulated value reaches the preset value. Often a reset
instruction is used in a counter circuit to implement a self-resetting action. However,
this should be avoided in some PLC's unless certain precautions are taken, because
the result will be an incorrect count value. Following is an explanation of why.
Figure 5-14 shows a reset instruction used to implement a self-resetting counter.
When the counters input turns on, the accumulated count value will increase to 1. At
the same time, the counters count up bit, bit 15, will turn on because its action
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follows that of the counters input. Since the count up bit reflects the status of the
input signal, the PLC uses it to determine if the input signal has made an OFF-to-ON
transition. It does this by comparing the current status of the input signal to the value
stored in the count up bit address.

Figure 5-14. A reset instruction used to implement a self-resetting counter.

Figure 5-15 shows the self-resetting counter circuit after several subsequent
scans. If the input remains on in the scan following the first OFF-to-ON transition
(point A), the PLC will compare this 1 value to the value stored in count up bit 15 in
scan 1. Since the count up value is already a 1, the PLC detects that the input has not
made an OFF-to-ON transition. The controller will continue to make this same
comparison every scan (points B and C). Therefore, when the input signal makes an
off-to-on transition (point D), the PLC will know it because the PLC will detect that
the current status of the input is 1 and that the previous status of the count up bit was
0. Since the PLC senses an OFF-to-ON transition, it will increase its accumulated
count value by one. In this circuit, the done bit will turn on since the accumulated
value now equals the preset value.

Figure 5-15. The self-resetting counter circuit after several subsequent scans.

Figure 5-16 shows what will happen after the counters done bit turns on. When
the done output turns on, the reset bit will also turn on since the done bit provides the
input logic to the reset coil. The reset instruction will reset the accumulated value, as
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well as the count up and done bits, to 0 at the end of the scan. The reset instruction
sets the count up bit to 0 (point A), but the input signal has not turned off (point B).
This means that in the next scan the PLC will sense an OFF-to-ON transition as it
compares the input signal to the count up value (point C), even though no transition
has occurred. As a result, the PLC will increase the counters accumulated value,
despite the fact that no actual input transition has occurred.

Figure 5-16. An illustration of what will happen after the count up instructions accumulated value is
reset.

Thus, using a reset instruction to implement a self-resetting counter will result in


an inaccurate accumulated count value. To avoid this situation, you can use one of the
following programming methods to create a self-resetting counter:
Use a clear instruction instead of a reset instruction to set the counters accumulated
value to 0.
Use a move instruction to move a value of 0 into the accumulated word at the end of
the scan.
Use a reset instruction, but with a one-shot rising instruction programmed at the input
to the counter. This one-shot instruction will ensure that the input must turn off and
then on again before the PLC will increment its count value.
Following are these methods that can be used to create a self-resetting counter

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Counting Past The Maximum Count Value. A counter instructions


accumulated value has a range from 32,768 to +32,767. Once a counter reaches a
count of +32,767, it cannot go any higher. Therefore, it wraps the accumulated count
back around to 32,768 and starts counting up again. To count past the +32,767 count
value, you must cascade two counters, making sure that they self-reset in each scan.
When two counters are cascaded, they are programmed so that one counter
provides the input to the other counter (see Figure 5-17). This way, the second
counter counts how many times the first one has reached its preset value. This figure
shows two cascaded counters that implement a count to 100,000.

Figure 5-17. Two cascaded counters that implement a count to 100,000.

Reading Fast Input Signals. If the input events to be counted are happening at a
rate faster than the scan, some of the inputs will not be counted (see Figure 5-18).
This is because a PLC only detects inputs that are valid at the beginning of each scan.
It will not detect inputs that occur during the scan. If an application requires the
counting of fast inputs, you must use a high speed counter instruction to count
them. This instruction is designed to count fast input signal pulses at a frequency of
up to 6.6 kilohertz.

Figure 5-18. If the input events to be counted are happening at a rate faster than the scan, some of the
inputs will not be counted.

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5.6.5 High-Speed Counter (HSC)


The High-Speed Counter is a variation of the CTU counter. The HSC instruction
is enabled when the rung logic is true and disabled when the rung logic is false.
The HSC instruction counts transitions that occur at specific input terminal such as
I:0/0 (In this case Do not place the XIC instruction with address I:0/0 in series with
the HSC instruction because counts will be lost). The HSC instruction does not
count rung transitions. You enable or disable the HSC rung to enable or disable the
counting of transitions occurring at input terminal I:0/0. We recommend placing the
HSC instruction in an unconditional rung.

Examples:
Example (1)
Write a program that will turn a light on when a count reaches 20. The light is
then to go off when a count of 30 is reached. The system can be reset manually at any
time by the reset button.
Inputs: Count button (N.O) (I:102), Reset button (N.O) (I:103).
Output: Light (O:100).

Example (2) (Batch Mixing Simulator)


A- Filling the Batch Mixing Tank
Using your knowledge of PLC counters, design a program to meet the
following requirements:
When switch S2 is pressed, pump P1 will be energized and the tank
will start to fill. The pulses generated by flowmeter FL1 should be
used to increment a counter.
o When the count reaches a value where the tank is approximately 90%
full, the pump is to be shut-off and the status panel FULL light is to be
energized.
o The filling operation is to halt immediately if the stop switch S1 is
pressed.
o

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B- Emptying the Batch Mix Tank


Modify your program so that:

The mixer will run for 8 seconds once the tank is full.
When the mixer stops, pump P3 is to be started and the tank is to be drained
till the counter's accumulator reaches zero.
Pressing switch S2 will cause the sequence to repeat.

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C- Continuous Operation (Homework)


Modify your program so that the filling and emptying sequence will repeat
continuously once it has been started by the initial pressing of switch S2.

Ensure that the RUN light is energized when the mixer or either pump is
running.
The STANDBY light should light and the process should halt when the Stop
button is pressed.
The process should restart where it left off if the Start button is pressed
following a Stop.

Use the PSIM or Logixpro batch mixing simulator to simulate the program.

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Example (3)
Write a program that will implement the following conveyor motor control
process:
Operational Sequence:
The start button is pressed to start the conveyor motor
Cases move past the proximity switch and increment the counter's
accumulated value.
After a count of 13 the conveyor motor stops automatically and the counter's
accumulated value is reset to 0.
The conveyor motor can be stopped and started manually at any time without
loss of the accumulated count.
The accumulated count of the counter can be reset manually at any time by
means of the count reset button.
The process is repeated when the start button is pressed.
Inputs: Stop button (N.C) (I:100), Start button (N.O) (I:101), Count reset
button (N.O) (I:102), Proximity switch (N.O) (I:103.
Output: Conveyor Motor (O:100).

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Example (4)
Write a P-SIM or Logixpro program that will simulate the parts counting
process shown.
Counter C1 count the total number of parts coming off an assembly line for final
packaging. Each package must count 10 parts. When 10 parts are detected, counter C2
sets bit B3 to initiate the box closing sequence. Counter C3 counts the total number of
packages filled in a day. The maximum number of packages per day is 300. A
pushbutton is used to restart the parts and package counters to zero. Use the silo
simulator screen and the following addresses to simulate the program.
Inputs: Stop button (N.C) (I:1/00), Start button (N.O) (I:1/01), Reset button
(N.O) (I:1/02), Proximity switch (I:1/03).
Output: Conveyor Motor (O:100), Bit B3 (O:1/04) to initiate the box closing
sequence.

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Chapter 6:
PLC Comparison and Math Instructions
6.1 Comparison Instructions
Comparison instructions are used compare the values stored in two memory
locations to condition the logical continuity of a rung. These two values can be the
data stored in two different word locations, or one can be the data stored in a word
and the other can be a constant value. These instructions are classified as input
instructions
The comparisons that may be performed are:

Most of the compare instructions use two parameters, Source A and Source B
(MEQ and LIM have an additional parameter and are described later in this chapter).
The value specified by source A must be a word location in memory (address). This
word location may specify the accumulated value for a timer or counter, the contents
of an integer file word, or any other data stored in memory. The value specified by
source B may be either a word location (address) or a constant. If source B contains a
word location, then it specifies the location of particular data in memory, just as the
source A parameter does. If source B is a constant, then this parameter contains a
fixed decimal value to which the instruction compares the source A data.
Negative integers are stored in twos complementary form. A brief description
for each instruction follows.

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Equal (EQU)
The format of the Equal instruction is:

Use the EQU instruction to test whether two values are equal. If source A and
source B are equal, the instruction is logically true. If these values are not equal, the
instruction is logically false.

Not Equal (NEQ)


The format of the Not Equal instruction is:

Use the NEQ instruction to test whether two values are not equal. If source A
and source B are not equal, the instruction is logically true. If the two values are
equal, the instruction is logically false.

Less Than (LES)


The format of the Less Than instruction is:

Use the LES instruction to test whether one value (source A) is less than another
(source B). If source A is less than the value at source B, the instruction is logically
true. If the value at source A is greater than or equal to the value at source B, the
instruction is logically false.

Less Than or Equal (LEQ)


The format of the Less Than or Equal instruction is:

Use the LEQ instruction to test whether one value (source A) is less than or
equal to another (source B). If the value at source A is less than or equal to the value
at source B, the instruction is logically true. If the value at source A is greater than the
value at source B, the instruction is logically false.

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Greater Than (GRT)


The format of the Greater Than instruction is:

Use the GRT instruction to test whether one value (source A) is greater than
another (source B). If the value at source A is greater than the value at source B, the
instruction is logically true. If the value at source A is less than or equal to the value
at source B, the instruction is logically false.

Greater Than or Equal (GEQ)


The format of the Greater Than or Equal instruction is:

Use the GEQ instruction to test whether one value (source A) is greater than or
equal to another (source B). If the value at source A is greater than or equal to the
value at source B, the instruction is logically true. If the value at source A is less than
the value at source B, the instruction is logically false.

Masked Comparison for Equal (MEQ)

The MEQ instruction is used to compare whether one value (source) is equal to
a second value (compare) through a mask. The source and the compare are logically
ANDed with the mask. Then, these results are compared to each other. If the resulting
values are equal, the rung state is true. If the resulting values are not equal, the rung
state is false.
Source is the address of the value you want to compare.
Mask is the address of the mask through which the instruction moves data. The mask is

displayed as a hexadecimal unsigned value from 0000 to FFFF FFFF.


Compare is an integer value or the address of the reference.

For example:

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The source, mask, and compare values must all be of the same data size (either word
or long word).

Limit Test (LIM)

Use the LIM instruction to test for values within or outside a specified range,
depending on how you set the limits.
Entering Parameters
The Low Limit, Test, and High Limit values can be word addresses or constants,
restricted to the following combinations:
If the Test parameter is a program constant, both the Low Limit and High Limit
parameters must be word addresses.
If the Test parameter is a word address, the Low Limit and High Limit parameters
can be either a program constant or a word address.
True/False Status of the Instruction
If the Low Limit has a value equal to or less than the High Limit, the instruction is
true when the Test value is between the limits or is equal to either limit. If the Test
value is outside the limits, the instruction is false, as shown below.

If the Low Limit has a value greater than the High Limit, the instruction is false
when the Test value is between the limits. If the Test value is equal to either limit or
outside the limits, the instruction is true, as shown below.

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Example

Indicate the observed state of the lamps, by circling the appropriate numbers
below:
Lamp 0 is On during counts:

01...2....3...4...5...6...7...8...9...10

Lamp 1 is On during counts:

01...2....3...4...5...6...7...8...9...10

Lamp 2 is On during counts:

01...2....3...4...5...6...7...8...9...10

Lamp 3 is On during counts:

01...2....3...4...5...6...7...8...9...10

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Example (Traffic Control using Comparison Instructions)


Using your knowledge of word comparison instructions, develop a traffic light control
program which operates via a single timer.
Red = O:1/00
Green = O:1/06

Amber = O:1/05

8 Sec.

4 Sec.

Green = O:1/02

Amber = O:1/01

Red = O:1/04
8 Sec.

4 Sec.

Homework
Traffic Light Control With Delayed Green

Modify your program so that there is a 1 second period when both directions will
have their RED lights illuminated. Using the timing diagram below, note that two 1
second periods are required in this sequence.

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6.2 Math Instructions


The majority of the instructions take two input values, perform the specified
arithmetic function, and output the result to an assigned memory location.
For example, both the ADD and SUB instructions take a pair of input values,
add or subtract them, and place the result in the specified destination. If the result of
the operation exceeds the allowable value, an overflow or underflow bit is set.
Entering Parameters
Source is the address(es) of the value(s) on which the mathematical, logical, or
move operation is to be performed. This can be word addresses or program
constants. An instruction that has two source operands does not accept
program constants in both operands.
Destination is the address of the result of the operation.
Signed integers are stored in twos complementary form and apply to both source and
destination parameters.

Add (ADD)

A+B
Use the ADD instruction to add one value (source A) to another value (source
B) and place the result in the destination.
After an instruction is executed, the arithmetic status bits (Carry (C), Overflow (V), Zero
(Z), Sign (S)) in the status file are updated:

Subtract (SUB)

A-B
Use the SUB instruction to subtract one value (source B) from another (source
A) and place the result in the destination.
After an instruction is executed, the arithmetic status bits (Carry (C), Overflow (V), Zero
(Z), Sign (S)) in the status file are updated.

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Multiply (MUL)

A*B
Use the MUL instruction to multiply one value (source A) by another (source
B) and place the result in the destination.
After an instruction is executed, the arithmetic status bits (Carry (C), Overflow (V), Zero
(Z), Sign (S)) in the status file are updated.

Divide (DIV)

A/B
Use the DIV instruction to divide one value (source A) by another (source B).
The rounded quotient is then placed in the destination. If the remainder is 0.5 or
greater, round up occurs in the destination. The unrounded quotient is stored in the
most significant word of the math register. The remainder is placed in the least
significant word of the math register.
After an instruction is executed, the arithmetic status bits (Carry (C), Overflow (V), Zero
(Z), Sign (S)) in the status file are updated.
Example: The remainder of 11/2 is 0.5, so the quotient is rounded up to 6 and
is stored in the destination. The unrounded quotient, which is 5, is stored in S:14 and
the remainder, which is 1, is stored at S:13.

Clear (CLR)

Use the CLR instruction to set the destination value of a word to zero.
After an instruction is executed, the arithmetic status bits (Carry (C), Overflow (V), Sign
(S)) in the status file are Reset and the status bit Zero (Z) is set.

Square Root (SQR)

A
When this instruction is evaluated as true, the square root of the absolute value
of the source is calculated and the rounded result is placed in the destination.

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The instruction calculates the square root of a negative number without


overflow or faults. In applications where the source value may be negative, use a
comparison instruction to evaluate the source value to determine if the destination
may be invalid.
After an instruction is executed, the arithmetic status bits (Carry (C), Overflow (V), Zero
(Z), Sign (S)) in the status file are updated.

Absolute (ABS)

|A|
Use the ABS instruction to calculate the absolute value of the Source and
place the result in the Destination. This instruction supports integer and floating point
values.
After an instruction is executed, the arithmetic status bits (Carry (C), Overflow (V), Zero
(Z), Sign (S)) in the status file are updated.

Sine (SIN)

Sine(A), A: in radians
Use the SIN instruction to take the sine of a number (source in radians) and store
the result in the destination.
After an instruction is executed, the arithmetic status bits (Carry (C), Overflow (V), Zero
(Z), Sign (S)) in the status file are updated.

Cosine (COS)

Cos(A), A: in radians
Use the COS instruction to take the cosine of a number (source in radians) and
store the result in the destination.
After an instruction is executed, the arithmetic status bits (Carry (C), Overflow (V), Zero
(Z), Sign (S)) in the status file are updated.

Tangent (TAN)

Tan(A), A: in radians
Use the TAN instruction to take the tangent of a number (source in radians) and
store the result in the destination.
After an instruction is executed, the arithmetic status bits (Carry (C), Overflow
(V), Zero (Z), Sign (S)) in the status file are updated.
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Log to the Base 10 (LOG)

Log10(A)
Use the LOG instruction to take the log base 10 of the value in the source and
store the result in the destination.
After an instruction is executed, the arithmetic status bits (Carry (C), Overflow
(V), Zero (Z), Sign (S)) in the status file are updated.

X to the Power of Y (XPY)

AB
Use the XPY instruction to raise a value (source A) to a power (source B) and
store the result in the destination.
After an instruction is executed, the arithmetic status bits (Carry (C),
Overflow (V), Zero (Z), Sign (S)) in the status file are updated.

Scale with Parameters (SCP)

Use the SCP instruction to produce a scaled output value that has a linear
relationship between the input and scaled values. This instruction supports integer and
floating point values. Use the following formula to convert analog input data to
engineering units:

y = mx + b
Where:
y = scaled output
m = slope = (scaled MAX. - scaled MIN.) / (input MAX. input MIN.)
x = input value
b = offset (y intercept) = scaled MIN - (input MIN. * m)
The Input Minimum, Input Maximum, Scaled Minimum, and Scaled
Maximum are used to determine the slope and offset values. The input value can go
outside of the specified input limits and no ordering is required. For example, the
scaled output value is not necessarily clamped between the scaled minimum and
scaled maximum values.
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Entering Parameters
Enter the following parameters when programming this instruction:
Input value can be a word address or an address of floating point data elements.
Input Minimum and Input Maximum values determine the range of data that
appears in the Input Value parameter. The value can be a word address, an integer
constant, floating point data element, or a floating point constant.
Scaled Minimum and Scaled Maximum values determine the range of data that
appears in the Scaled Output parameter. The value can be a word address, an integer
constant, floating point data element, or a floating point constant.
Scaled Output value can be a word address or an address of floating point data
elements.
After an instruction is executed, the arithmetic status bits (Carry (C), Overflow
(V), Zero (Z), Sign (S)) in the status file are updated.

Application Examples
Example 1
In the first example, an analog I/O combination module is in slot 1 of the chassis. A
pressure transducer is connected to input 0 and we want to read the value in
engineering units. The pressure transducer measures pressures from 0 to 1000 psi and
provides a 0 to 10V signal to the analog module. For a 0 to 10V signal, the analog
module provides a range between 0 to 32,767. The following program rung places a
number between 0 and 1000 into N7:20 based on the input signal coming from the
pressure transducer into the analog module.

Example 2
In the second example, an analog I/O combination module is in slot 1 of the chassis.
We want to control the proportional valve connected to output 0. The valve takes a 4
to 20 mA signal to control how far it opens (0 to 100%). (Assume that additional logic
is present in the program that calculates how far to open the valve in percent and
places a number between 0 and 100 into N7:21.) The analog module provides a 4 to
20mA output signal for a number between 6242 to 31,208. The following program
rung directs an analog output to provide a 4 to 20 mA signal to the proportional valve
(N7:21), based on a number between 0 and 100.
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Scale Data (SCL)

When this instruction is true, the value at the source address is multiplied by the
rate value. The rounded result is added to the offset value and placed in the
destination.

Note that the term rate is sometimes referred to as slope. This instruction can
overflow before the offset is added.
Entering Parameters
The value for the following parameters is between -32,768 to 32,767.
Source can be either a constant or a word address.
Rate (or slope) is the positive or negative value you enter divided by 10,000. It can
be either a constant or a word address.
Offset can be either a constant or a word address.
After an instruction is executed, the arithmetic status bits (Carry (C), Overflow
(V), Zero (Z), Sign (S)) in the status file are updated.
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Application Example 1 - Converting 4 to 20 mA Analog Input Signal


to PID Process Variable

Calculating the Linear Relationship


Use the following equations to express the linear relationship between the input value
and the resulting scaled value:

Application Example 2 - Scaling an Analog Input to Control an


Analog Output

Calculating the Linear Relationship


Use the following equations to calculate the scaled units:
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The above offset and rate values are correct for the SCL instruction. However, if the
input exceeds 13,107, the instruction overflows and sets S:5/0 math overflow bit. For
example:

To avoid an overflow, we recommend shifting the linear relationship along the input
value axis and reduce the values.
Notice that an overflow occurred even though the final value was correct. This
happens because the overflow condition occurred during the rate calculation.
The following graph shows the shifted linear relationship. The input minimum value
of 3,277 is subtracted from the input maximum value f 16,384, resulting in the value
of 13,107.

Calculating the Shifted Linear Relationship


Use the following equations to calculate the scaled units:

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In this example, the SCL instruction is entered in the ladder logic program as follows:

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Chapter 7:
PLC Move, Logical and Program Flow
Instructions
7.1 Move and Logical Instructions
The following general information applies to move and logical instructions.
Entering Parameters
Source is the address of the value on which the logical or move operation is to be
performed. The source can be a word address or a program constant, unless otherwise
described. If the instruction has two source operands, it does not accept program
constants in both operands.
Destination is the result address of a move or logical operation. It must be a word
address.
After an instruction is executed, the arithmetic status bits (Carry (C), Overflow
(V), Zero (Z), Sign (S)) in the status file are updated.

Move (MOV)

This output instruction moves the source value to the destination location. As
long as the rung remains true, the instruction moves the data each scan.
Entering Parameters
Enter the following parameters when programming this instruction:
Source is the address or constant of the data you want to move.
Destination is the address where the instruction moves the data.

Masked Move (MVM)

The MVM instruction is a word instruction that moves data from a source
location to a destination, and allows portions of the destination data to be masked by a
separate word. As long as the rung remains true, the instruction moves the data each
scan.
Entering Parameters
Enter the following parameters when programming this instruction:
Source is the address of the data you want to move.
Mask is the address of the mask through which the instruction moves data; the mask
can also be a hexadecimal value (constant).
Destination is the address where the instruction moves the data.
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Operation
When the rung containing this instruction is true, data at the source address
passes through the mask to the destination address. See the figure below.

Mask data by resetting bits in the mask; pass data by setting bits in the mask to
one. The bits of the mask can be fixed by a constant value, or you can vary them by
assigning the mask a direct address. Bits in the destination that correspond to zeros in
the mask are not altered.

And (AND)

This instruction performs a bit-by-bit logical AND. The operation is performed


using the value at source A and the value at source B. The result is stored in the
destination. Source A and B can either be a word address or a constant; however, both
sources cannot be a constant. The destination must be a word address.

Or (OR)

This instruction performs a bit-by-bit logical OR. The operation is performed


using the value at source A and the value at source B. The result is stored in the
destination. Source A and B can either be a word address or a constant; however, both
sources cannot be a constant. The destination must be a word address.

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Exclusive Or (XOR)

This instruction performs a bit-by-bit logical XOR. The operation is performed


using the value at source A and the value at source B. The result is stored in the
destination. Source A and B can either be a word address or a constant; however, both
sources cannot be a constant. The destination must be a word address.

Not (NOT)

This instruction performs a bit-by-bit logical NOT. The operation is performed


using the value at source A. The result (ones complement of A) is stored in the
destination. The source and destination must be word addresses.

Negate (NEG)

Use the NEG instruction to change the sign of the source and then place it in the
destination. The destination contains the twos complement of the source. For
example, if the source is 5, the destination would be -5. The source and destination
must be word addresses.

7.2 Program Flow Control Instructions


Use these instructions to control the sequence in which your program is
executed.
Control instructions allow you to change the order in which the processor scans
a ladder program. Typically, these instructions are used to minimize scan time, create
a more efficient program, and troubleshoot a ladder program.

7.2.1 Jump Instructions


Jump (JMP) and Label (LBL)

Use these instructions in pairs to skip portions of the ladder program. The JMP
instruction causes the controller to change the order of ladder execution. Jumps cause
program execution to go to the rung marked LBL label number. Jumps can be
forward or backward in ladder logic within the same program file. Multiple JMP
instructions may cause execution to proceed to the same label.
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Jumping forward to a label saves program scan time by omitting a program


segment until needed. Jumping backward lets the controller execute program
segments repeatedly.
Be careful not to jump backwards an excessive number of times. Use a counter,
timer, or the program scan register to limit the amount of time you spend looping
inside of JMP/LBL instructions.
Entering Parameters
Enter a decimal label number from 0 to XXX (for Example 255) in each
subroutine file.
Using JMP
The JMP instruction causes the controller to skip rungs. You can jump to the
same label from one or more JMP instructions.
Using LBL
This input instruction is the target of JMP instructions having the same label
number. You must program this instruction as the first instruction of a rung. This
instruction has no control bits.
Figure 7-1 illustrates how a jump instruction works. In this program, the output
of the first rung is a jump coil with address 10. The fourth rung begins with a label
contact that shares the jump coils address. If input I:0.0/0 is true, jump coil 10 will be
energized. This will cause the PLC to jump to the rung containing the label instruction
with address 10 and resume program execution from there. Thus, the jump instruction
causes the PLC to skip the execution of rungs two and three. If the jump instruction is
not energized, then the PLC will evaluate all the rungs of the ladder program as it
would normally.

Figure 7-1. A ladder program containing a jump instruction.

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Jump to Subroutine (JSR), Subroutine (SBR), and Return


(RET)

The JSR, SBR, and RET instructions are used to direct the controller to execute
a separate subroutine file within the ladder program and return to the instruction
following the JSR instruction.
If you use the SBR instruction, the SBR instruction must be the first
instruction on the first rung in the program file that contains the subroutine.
Use a subroutine to store recurring sections of program logic that must be
executed from several points within your application program. A subroutine saves
memory because you program it only once.
Nesting Subroutine Files
Nesting subroutines allows you to direct program flow from the main program
to a subroutine and then on to another subroutine.
The following Figure 7-2 illustrates how subroutines may be nested (Example
of Nesting Subroutines to Level 3).

Figure 7-2. Nested subroutines program.

An error occurs if more than the allowable levels of subroutines are called
(subroutine stack overflow) or if more returns are executed than there are call levels
(subroutine stack underflow).
Using JSR
When the JSR instruction is executed, the controller jumps to the subroutine
instruction (SBR) at the beginning of the target subroutine file and resumes
execution at that point. You cannot jump into any part of a subroutine except the
first instruction in that file. You must program each subroutine in its own program file
by assigning a unique file number.
Using SBR
The target subroutine is identified by the file number that you entered in the JSR
instruction. This instruction serves as a label or identifier for a program file as a
regular subroutine file. This instruction has no control bits. It is always evaluated
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as true. The instruction must be programmed as the first instruction of the first rung
of a subroutine.
The first instruction in the first rung of a subroutine file must be a Subroutine
instruction. The sole purpose of this instruction is to indicate the subroutine files
beginning. It does not cause its rung to be true or false.
Using RET
This output instruction marks the end of subroutine execution or the end of the
subroutine file. It causes the controller to resume execution at the instruction
following the JSR instruction. If a sequence of nested subroutines is involved, the
instruction causes the processor to return program execution to the previous
subroutine.
The rung containing the RET instruction may be conditional if this rung
precedes the end of the subroutine. In this way, the controller omits the balance of a
subroutine only if its rung condition is true.
Without an RET instruction, the END instruction (always present in the
subroutine) automatically returns program execution to the instruction following
the JSR instruction in your calling ladder file.
Jump to Subroutine Operation
When a jump to subroutine instruction is enabled, the controller will jump to
the subroutine specified and start executing it (see Figure 7-3). If the PLC encounters
an energized return instruction in the subroutine, it will jump back to the main
program and pick up where it left off. If it does not find an energized return
instruction, the controller will wait until it gets to the end of the subroutine before
jumping back to the main ladder program. When a subroutine is executed, its outputs
remain in their last state, either on or off, until the subroutine is executed again.

Figure 7-3. A jump to subroutine instruction that jumps to subroutine 6.

Example: ( Jump Instructions)


Figure 7-4 illustrates a ladder logic program to count parts and their values.
Input I:2/1 is a sensor detecting part A, which is worth $10. Input I:2/2 is a sensor
detecting part B, which is worth $20. Counter C5:1 counts the number of part A while
memory location B3:10 (a word) keeps the total value associated with part A. Counter
C5:2 counts the number of part B while memory location B3:11 keeps the total value
associated with part B. When a piece of part A or part B comes down a conveyer, a
corresponding sensor sends a high signal to the PLC and the corresponding counter
and memory word are updated. When a piece of part A is detected by the sensor, the
input I:2/1 in the program of Figure 7-4 causes the Jump to Label instruction in the
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rung 0000 to be activated. Instead of executing the next rung, the PLC moves to rung
0003 that has a Label instruction with number Q2:1. The PLC executes rung 0003 and
0004. The Jump to Label instruction in rung 0004 causes the PLC to move back to
rung 0001. The relations of input statuses and program execution sequences in a scan
cycle are listed in Table 7-1. Using jump instructions may eliminate the unnecessary
rung execution and reduce the time of a scan cycle.

Figure 7-4: A ladder logic program using Jump to Label and Label instructions

Input Status
I:2/1 = Low and I:2/2 = Low
I:2/1 = Low and I:2/2 = High
I:2/1 = High and I:2/2 = Low
I:2/1 = High and I:2/2 = High

Program scan sequence in rung number


0000, 0001, 0002, 0000
0000, 0001, 0005, 0006, 0000
0000, 0003, 0004, 0001, 0002, 0000
0000, 0003, 0004, 0001, 0005, 0006,
0000

Table 7-1 Ladder logic program execution sequence

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Example: ( Jump and Subroutine Instructions)


The ladder logic program in Figure 7-4 can be replaced by a program with
subroutines. Figure 7-5 shows the new main program and subroutines. Not counting
the rung for the END statement, the main program has only two rungs. When the
input I:2/1 is high, subroutine 11 is called. The execution of subroutine 11 causes the
number and value of part A to be updated. Then the PLC returns to the second rung in
the main program. When the input I:2/2 is high, subroutine 12 is called. The execution
of subroutine 12 causes the number and value of part B to be updated. Then the PLC
returns to the third rung in the main program, which is the end of the program. When
the input I:2/1 or I:2/2 is low, or both of them are low, the corresponding subroutine is
not called. The PLC executes the next rung in the main program.

(a) Main program

(b) First subroutine

(c) Second subroutine


Figure 7-5 A ladder logic program using subroutines

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7.2.2 Master Control Reset (MCR)

A master control reset instruction, which is also called an MCR instruction,


creates a fence around a group of ladder rungs. If the MCR instruction is energized,
then the controller will execute the fenced instructions. If not energized, the controller
will not execute the fenced instructions.
This instruction defines the boundaries of an MCR Zone. An MCR Zone is the
set of ladder logic instructions bounded by an MCR instruction pair. The start of an
MCR zone is defined to be the rung that contains an MCR instruction preceded by
conditional logic. The end of an MCR zone is defined to be the first rung containing
just an MCR instruction following a start MCR zone rung as shown Figure 7-6
below.

Figure 7-6. A master control reset instruction.

MCR zones let you enable or inhibit segments of your program, such as for recipe
applications.
When you program MCR instructions, note that:
You must end the zone with an unconditional MCR instruction.
You cannot nest one MCR zone within another.
Do not jump into an MCR zone. If the zone is false, jumping into it activates
the zone.
Always place the MCR instruction as the last instruction in a rung.
Master control reset instructions are always used in pairs to form a conditional
fence around a group of rungs. If the input logic to the first MCR is energized, the
programmed logic within the fence will be executed. If the input logic to the first
MCR is not satisfied, then the controller will skip the fenced logic and resume
program execution after the second MCR instruction. This second MCR instruction
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must be unconditional, meaning that it is always active because it has no driving input
logic.
When an MCR fence is deactivated, all of the non-retentive outputs within the
MCR fence will turn off, regardless of the status of their input conditions. Only the
retentive outputs will retain their last status, either ON or OFF.
Figure 7-7 shows a ladder program with two fenced timers to demonstrate how
MCRs work. One of these timers is an ON-delay timer; the other is a retentive timer.
Both timers are located within the MCR fence. This means that neither timer will start
timing, even if its input is on, unless the first MCR instruction is on. When the first
MCR instruction turns on, both timers will be enabled if their inputs are on. Thus, the
timers will start timing, and if the MCR zone stays on long enough, both timers will
time out. When the first MCR eventually turns off, the ON-delay timers output will
turn off, since all non-retentive outputs in an MCR fence are reset when the fence
turns off. The retentive timers output will remain on.

Figure 7-7. A ladder program with two fenced timers.

The circuit in Figure 7-7 works much the same way if the timers start timing
and then the MCR fence turns off before either timer has timed out. In this situation,
the timers will start timing when the first MCR instruction turns on. However, when
the MCR turns off, the timers will turn off too, even though their inputs may still be
on. As a result, the accumulated value of the ON-delay timer will be reset to 0. The
retentive timer, however, will retain its accumulated value. To reset the retentive
timers accumulated value, you would need to add a reset instruction outside of the
MCR fence (see Figure 7-8). If this reset instruction was located inside the fence, it
could only reset the retentive timer when the MCR zone was activated.

Figure 7-8. A ladder program with two fenced timers that uses a reset instruction to reset the RTO
instruction.

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When using MCR instructions, you should never use a jump instruction to jump
inside an MCR zone. Instructions that are programmed within the MCR zone starting
at the LBL instruction and ending at the END MCR instruction are always evaluated
as though the MCR zone is true, regardless of the true state of the Start MCR
instruction. If the zone is false, jumping into it activates the zone from the LBL to the
end of the zone.

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Chapter 8:
PLC Bit Shift and Sequencer Instructions
8.1

Bit Shift Instructions

Bit Shift Left (BSL)


Bit Shift Right (BSR)
BSL and BSR are output instructions that
load data into a bit array one bit at a time. The
data is shifted through the array, then unloaded
one bit at a time.
Using BSL
When the rung goes from false-to-true, the
processor sets the enable bit (EN bit 15) and the
data block is shifted to the left (to a higher bit
number) one bit position. The specified bit at the bit address is shifted into the first bit
position. The last bit is shifted out of the array and stored in the unload bit (UL bit
10). The shift is completed immediately.
For wraparound operation, set the position of the bit address to the last bit of the
array or to the UL bit, whichever applies.
The figure below illustrates how the Bit Shift Left instruction works.

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Using BSR
When the rung goes from false-to-true, the enable bit (EN bit 15) is set and the
data block is shifted to the right (to a lower bit number) one bit position. The specified
bit at the bit address is shifted into the last bit position. The first bit is shifted out of
the array and stored in the unload bit (UL bit 10) in the status byte of the control
element. The shift is completed immediately.
For wraparound operation, set the position of the bit address to the first bit of the
array or to the UL bit, whichever applies.
The figure below illustrates how the Bit Shift Right instruction works.

If you wish to shift more than one bit per scan, you must create a loop in your
application using the JMP, LBL, and CTU instructions.

Entering Parameters
These instructions use the following operands:
File is the address of the bit array you want to manipulate. You must use the file
indicator (#) in the bit array address.
Control is the control element that stores the status byte of the instruction and the
size of the array (in number of bits). Note that the control address should not be used
for any other instruction.
The control element is shown below.

Status bits of the control element may be addressed by mnemonic. They include:
Unload Bit UL (bit 10) stores the status of the bit exited from the array each time the
instruction is enabled.
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Error Bit ER (bit 11), when set, indicates the instruction detected an error such as
entering a negative number for the length or position. Avoid using the output bit when
this bit is set.
Done Bit DN (bit 13), when set, indicates the bit array has shifted one position.
Enable Bit EN (bit 15) is set on a false-to-true transition of the rung and indicates
the instruction is enabled.
When the register shifts and input conditions go false, the enable, done, and error bits
are reset.
Bit Address is the address of the source bit that the instruction inserts in the first
(lowest) bit position (BSL) or the last (highest) bit position (BSR).
Length (size of bit array) is the number of bits in the bit array, up to 2048 bits. A
length value of 0 causes the input bit to be transferred to the UL bit.

The instruction invalidates all bits beyond the last bit in the array (as defined by
the length) up to the next word boundary.

8.2

Sequencer Instructions

Sequencer instructions are used to control automatic assembly machines or


processes that have a consistent and repeatable operation. They are typically time
based or event driven.

The primary advantage of sequencer instructions is to conserve program


memory. These instructions monitor and control 16 (word) or 32 (long word) discrete
outputs at a time in a single rung.

Sequencer Compare (SQC)


On a false-to-true rung transition, the SQC
instruction is used to compare masked source
words or long words with the masked value at a
reference address (the sequencer file) for the
control of sequential machine operations.
When the status of all non-masked bits in the
source word match those of the corresponding
reference word, the instruction sets the found bit (FD) in the control word. Otherwise,
the found bit (FD) is cleared.
The bits mask data when reset (0) and pass data when set (1).
The mask can be fixed or variable. If you enter a hexadecimal code, it is fixed. If
you enter an element address or a file address (direct or indirect) for changing the
mask with each step, it is variable.
When the rung goes from false-to-true, the instruction increments to the next
step (word) in the sequencer file. Data stored there is transferred through a mask and
compared against the source for equality. While the rung remains true, the source is

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compared against the reference data for every scan. If equal, the FD bit is set in the
SQCs control counter.
The following figure explains how the SQC instruction works.

SQC FD bit is set when the instruction detects that an input word matches (through
mask) its corresponding reference word.
The FD bit R6:21/FD is set in the example, since the input word matches the
sequencer reference value using the mask value.
This instruction uses the following operands:
File is the address of the sequencer file. You must use the file indicator (#) for this
address. Sequencer file data is used to stores reference data for monitoring inputs.
Mask (SQO, SQC) is a hexadecimal code or the address of the mask word or file
through which the instruction moves data. Set mask bits to pass data and reset mask
bits to mask data. Use a mask word or file if you want to change the mask according
to application requirements.
If the mask is a file, its length will be equal to the length of the sequencer file. The
two files track automatically.
Source is the address of the input word or file for a SQC from which the instruction
obtains data for comparison to its sequencer file.
Control (SQO, SQC) is the control structure that stores the status byte of the
instruction, the length of the sequencer file, and the instantaneous position in the file.
You should not use the control address for any other instruction.

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Status bits of the control structure include:


Found

Bit FD (bit 08) - SQC only. When the status of all non-masked bits in the
source address match those of the corresponding reference word, the FD bit is set.
This bit is assessed each time the SQC instruction is evaluated while the rung is true.
Error Bit ER (bit 11) is set when the processor detects a negative position value, or a
negative or zero length value.
Done Bit DN (bit 13) is set by the SQO or SQC instruction after it has operated on
the last word in the sequencer file. It is reset on the next false-to-true rung transition
after the rung goes false.
Enable EN (bit 15) is set by a false-to-true rung transition and indicates the SQO or
SQC instruction is enabled.
Length is the number of steps of the sequencer file starting at position 1. The
maximum number you can enter is 255 words. Position 0 is the startup position. The
instruction resets (wraps) to position 1 at each cycle completion.
The address assigned for a sequencer file is step zero. Sequencer instructions use
length 1 word of data table files for each file referenced in the instruction. This
applies to the source, mask, and/or destination if addressed as files.
Position is the word location or step in the sequencer file from/to which the
instruction moves data.
You may use the reset (RES) instruction to reset a sequencer. All control bits (except
FD go to last state) will be reset to zero. The Position will also be set to zero. Program
the address of your control register in the RES (e.g.,R6:0).

Sequencer Output (SQO)


This output instruction steps through the
sequencer file whose bits have been set to control
various output devices.
On a false-to-true rung transition, the SQO
instruction transfers masked source reference words
or long words to the destination for the control of
sequential machine operations. When the rung goes from false-to-true, the instruction
increments to the next step (word) in the sequencer file. Data stored there is
transferred through a mask to the destination address specified in the instruction. Data
is written to the destination word every time the instruction is executed.
The done bit is set when the last word of the sequencer file is transferred. On the
next false-to-true rung transition, the instruction resets the position to step one.
If the position is equal to zero at start-up, when you switch the controller from
the program mode to the run mode, the instruction operation depends on whether the
rung is true or false on the first scan.
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If true, the instruction transfers the value in step zero.


If false, the instruction waits for the first rung transition from false-to-true and
transfers the value in step one.
The bits mask data when reset (0) and pass data when set (1). The instruction will not
change the value in the destination word unless you set mask bits.
The mask can be fixed or variable. It is fixed if you enter a hexadecimal code. It is
variable if you enter an element address or a file address (direct or indirect) for
changing the mask with each step.
The following figure indicates how the SQO instruction works.

Destination in this instruction is the address of the output word or file for a SQO to

which the instruction moves data from its sequencer file.

Sequencer Load (SQL)


The SQL instruction stores 16-bit data into a
sequencer load file at each step of sequencer operation.
The source of this data can be an I/O or storage word
address, a file address, or a constant.
On a false-to-true rung transition, the SQL
instruction loads words or long words into a sequencer
file at each step of a sequencer operation. This instruction uses the following
operands:
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File is the address of the sequencer file. You must use the indexed file indicator (#)

for this address.


Source can be a word address, file address, or a constant (-32768 to 32767).
If the source is a file address, the file length equals the length of the sequencer load
file. The two files will step automatically, per the position value.
Length is the number of steps of the sequencer load file (and also of the source if
the source is a file address), starting at position 1. The maximum number you can
enter is 255 words. Position 0 is the startup position. The instruction resets (wraps) to
position 1 at each cycle completion.
The position address assigned for a sequencer file is step zero. Sequencer instructions
use length plus one word of data for each file referenced in the instruction. This
applies to the source if addressed as a file.
Position is the word location or step in the sequencer file to which data is moved.
Control is a control file address. The status bits, length value, and position value are
stored in this element. Do not use the control file address for any other instruction.
Operation
Instruction parameters have been programmed in the SQL instruction shown
below. Input word I:1.0 is the source. Data in this word is loaded into integer file
#N7:30 by the sequencer load instruction.

When rung conditions change from false-to-true, the SQL enable bit (EN) is set.
The control element R6:4 increments to the next position in the sequencer file, and
loads the contents of source I:1.0 into this location. The SQL instruction continues to
load the current data into this location each scan that the rung remains true. When the
rung goes false, the enable bit (EN) is reset.
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The instruction loads data into a new file element at each false-to-true transition
of the rung. When step 4 is completed, the done bit (DN) is set. Operation cycles to
position 1 at the next false-to-true transition of the rung after position 4.
If the source were a file address such as #N7:40, files #N7:40 and #N7:30 would
both have a length of 5 (0 to 4) and would track through the steps together per the
position value.

Examples:
Example (1):
Create (on paper) a ladder diagram that will control the activation of PLC outputs 0
through 7 in the following way:

Upon startup, all the PLC outputs are deactivated.


When PLC input 0 is activated, PLC output 0 is activated (step 1);
5 seconds later, PLC outputs 0 through 3 are activated (step 2);
5 seconds later, PLC outputs 0 through 3 are deactivated, while PLC outputs 4
through 7 are activated (step 3);
5 seconds later, PLC outputs 0 through 7 are activated (step 4);
5 seconds later, the cycle automatically repeats, starting from step 1, causing PLC
output 0 to be activated.
If PLC input 0 is deactivated, the PLC outputs that are activated at that moment
remain activated. When PLC input 0 is reactivated, the cycle resumes from the step
following the one at which it was interrupted.
Hints: use a sequencer output (SQO) instruction and a timer-on-delay (TON)
instruction in your program. Use timer status bits to create transitions on the rung
containing the SQO instruction and to reset the TON instruction.

Solution:

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Example (2):
The following application example illustrates the use of the TON and SQO
instructions in a traffic signal at an intersection. The timing requirements are:
R1 = O:1/00
G2 = O:1/06

A2 = O:1/05

8 Sec.

4 Sec.

G1 = O:1/02

A1 = O:1/01

R1

4 Sec.

R2 = O:1/04

8 Sec.

The rung 000 resets the control register's position, T4:1.ACC and T4:1.PRE Due
to this the following rung sees a false-to-true transition and asserts step (position) 1 on
the first scan.
The function of rung 002 called a regenerative timer. Every time the timer
reaches its preset, the DONE bit is set for one scan, this causes this rung to become
FALSE for one scan and resets the timer. On the following scan, when this rung
becomes TRUE again, the timer begins timing.
When the rung 001 goes from false-to-true (by the timer reaching its preset), the
first sequencer changes which traffic lights are illuminated, and the second sequencer
changes the preset of the timer to determine how long these next lights are
illuminated.

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Chapter 9:
PLC Applications and Examples
9.1 NPN and PNP Sensors
Sinking/Sourcing
Sinking sensors allow current to flow into the sensor to the voltage common,
while sourcing sensors allow current to flow out of the sensor from a positive source.
For both of these methods the emphasis is on current flow, not voltage. By using
current flow, instead of voltage, many of the electrical noise problems are reduced.
When discussing sourcing and sinking we are referring to the output of the
sensor that is acting like a switch. In fact the output of the sensor is normally a
transistor that will act like a switch (with some voltage loss). A PNP transistor is used
for the sourcing output, and an NPN transistor is used for the sinking input. When
discussing these sensors the term sourcing is often interchanged with PNP, and
sinking with NPN. A simplified example of a sinking output sensor is shown in the
Figure 9-1. The sensor will have some part that deals with detection, this is on the
left. The sensor needs a voltage supply to operate, so a voltage supply is needed for
the sensor. If the sensor has detected some phenomenon then it will trigger the active
line. The active line is directly connected to an NPN transistor. (Note: for an NPN
transistor the arrow always points away from the center.) If the voltage to the
transistor on the active line is 0V, then the transistor will not allow current to flow
into the sensor. If the voltage on the active line becomes larger (say 12V) then the
transistor will switch on and allow current to flow into the sensor to the common.

Figure 9-1. Simplified NPN/Sinking Sensor.

The sensor responds to a physical phenomenon. If the sensor is inactive (nothing


detected) then the active line is low and the transistor is off, this is like an open
switch. That means the NPN output will have no current in/out. When the sensor is
active, it will make the active line high. This will turn on the transistor, and
effectively close the switch. This will allow current to flow into the sensor to ground
(hence sinking).
Sourcing sensors are the complement to sinking sensors. The sourcing sensors
use a PNP transistor. A simplified sourcing/PNP sensor is shown in the Figure 9-2.
(Note: PNP transistors are always drawn with the arrow pointing to the center.) When
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the sensor is inactive the active line stays at the V+ value, and the transistor stays
switched off. When the sensor becomes active the active line will be made 0V, and
the transistor will allow current to flow out of the sensor.

Figure 9-2. Simplified Sourcing/PNP Sensor.

The sensor responds to the physical phenomenon. If the sensor is inactive


(nothing detected) then the active line is high and the transistor is off, this is like an
open switch. That means the PNP output will have no current in/out. When the sensor
is active, it will make the active line high. This will turn on the transistor, and
effectively close the switch. This will allow current to flow from V+ through the
sensor to the output (hence sourcing).
NPN and PNP Sensors connected to PLC
There are two viable approaches for connecting sensors to PLCs. The first is to
always use PNP sensors and normal voltage input cards. The second option is to
purchase input cards specifically designed for sourcing or sinking sensors. An
example of a PLC card for sinking sensors is shown in Figure 9-3.

Figure 9-3. PLC Input Card for Sinking Sensors.

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The dashed line in the figure represents the circuit or current flow path when the
sensor is active. This path enters the PLC input card first at a V+ terminal (Note: there
is no common on this card) and flows through an optocoupler. This current will use
light to turn on a phototransistor to tell the computer in the PLC the input current is
flowing. The current then leaves the card at input 00 and passes through the sensor to
V-. When the sensor is inactive the current will not flow, and the light in the
optocoupler will be off. The optocoupler is used to help protect the PLC from
electrical problems outside the PLC.
The input cards for PNP sensors are similar to the NPN cards, as shown in
Figure 9-4.

Figure 9-4. PLC Input Card for Sourcing Sensors.

The current flow loop for an active sensor is shown with a dashed line.
Following the path of the current we see that it begins at the V+, passes through the
sensor, in the input 00, through the optocoupler, out the common and to the V-.

9.2 Analog Input /Analog Output Modules


Analog input/output modules are used in applications where the field devices
signal is continuous (see Figure 9-5). Unlike discrete signals, which possess only two
states (ON and OFF), analog signals have an infinite number of states. Temperature,
for example, is an analog signal because it continuously changes by infinitesimal
amounts.

Figure 9-5. Representation of a continuous analog signal.

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Typical analog inputs and outputs for PLCs are listed below:

To input an analog voltage (into a PLC or any other computer) the continuous
voltage value must be sampled and then converted to a numerical value by an A/D
(ADC) converter. Analog input modules digitize analog input signals, thereby
bringing analog information into the PLC (see Figure 9-6). The modules store this
multibit information in register locations inside the PLC. The analog instructions used
with analog input modules are similar to, if not the same as, the instructions used with
multibit discrete inputs. The only difference between them is that analog multibit
instructions are the result of a digital transformation of the analog signal, while
discrete multibit instructions are the result of many multibit devices (or separate
signals) connected to the same number of discrete input connections.

Figure 9-6. Digitization of an analog signal.

Analog output interfaces are used in applications requiring the control of field
devices that respond to continuous voltage or current levels. Multibit output
instructions, which are similar to those used with multibit discrete outputs, are used to
send analog information to field devices. The controller transfers the contents of a
register, generally specified by 12 bits, to the output module upon the execution of the
instruction (see Figure 9-7). The module then transforms this value, whether BCD or
binary, from digital to analog and passes it to the field control device.
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Figure 9-7. Conversion of register data to an analog signal.

Since there are many types of transducers available and many types of controlling
devices, analog I/O modules have several standard electrical input and output ratings.
Following lists of the standard current and voltage ratings for analog interfaces.

Analog Input/Output Connections


Analog input interfaces can receive either single-ended or differential inputs.
The commons in single-ended inputs are electrically tied together, whereas
differential inputs have individual return or common lines for each channel. Figure 98 illustrates typical analog connections for single ended and differential inputs.

Figure 9-8. Connection diagrams for (a) single-ended and (b) differential analog input modules.

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Analog output interfaces are available in configurations ranging from 2 to 8 outputs


per module, but on average, most modules have 4 to 8 analog output channels. These
channels can be configured as either single-ended or differential outputs. Differential
is the most common configuration when individually isolated outputs are required.
Figure 9-9 illustrates typical connections for both single-ended and differential
analog output modules.

Figure 9-9. Connection diagrams for (a) single-ended and (b) differential analog output modules.

Analog I/O Configuration


As example of Analog I/O Configuration lets take Allen-Bradley 1762-IF2OF2
analog module. This module has 2 analog inputs and 2 analog outputs, for this module
the data ranges for 0 to 10V dc and 4 to 20 mA are shown in the following table:

1762-IF2OF2 Input Data File


For each input module, slot x, words 0 and 1 contain the analog values of the
inputs. The module can be configured to use either raw/proportional data or scaledfor-PID data. The input data file for each configuration is shown below.

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The bits are defined as follows:


Sx = General status bits for channels 0 and 1. This bit is set when an error (over- or
under-range) exists for that channel, or there is a general module hardware error.
Ox = Over-range flag bits for channels 0 and 1. These bits can be used in the control
program for error detection.
Ux = Under-range flag bits for channels 0 and 1. These bits can be used in the
control program for error detection.
1762-IF2OF2 Output Data File
For each module, slot x, words 0 and 1 contain the channel output data.

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Example 9-1
A temperature transducer/transmitter (see Figure 9-10) provides a 010 VDC voltage
signal that is proportional to the temperature variable being measured. The
temperature measurement ranges between 0 and 1000C. The analog input module
accepts a 010 VDC unipolar signal range and converts it to a range of 04095 counts
(12 bits) . The process application where this signal is being used detects low and high
alarms at 100C and 500C, respectively.

Figure 9-10. Temperature transducer/transmitter connected to an input module.

Find (a) the relationship (i.e., equation of the line) between the input variable signal
(temperature) and the counts being measured by the PLC module and (b) the
equivalent number of counts for each of the alarm temperatures specified.
Solution
(a) Figure 9-11 shows the relationship between counts and the input signal in volts

and degrees Celsius. Line Y describes the numerical relationship between the input
signal and the number of counts (assuming a linear relationship).

Figure 9-11. Relationship between counts and input signal.

To find the relationship between temperature and counts, find the numerical
representation of the equation for line Y. This equation takes the form Y = mX + b,
where m is the slope of the line and is described by:

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and Y2, Y1, X2, and X1 are known points. The value b is the offset (value of Y, or
C, when X, or counts, equals 0). This value can be computed as:
where Y and X are values at known points (i.e., at 0C and 0 counts). When X is at 0
counts, Y is at 0C; therefore:

Substituting the derived values for m and b into the equation Y = mX + b produces
the equation of line Y:

Using 4095 counts and 1000C as the X and Y values when computing b would have
derived the same equation (try it as an exercise).
(b) Based on the equation of line Y, the number of counts for each alarm range is:

So, for the YC values of 100C and 500C, the X values are:\

Thus, the count value for 100C is 409.5 counts and for 500C is 2047.5 counts. Since
count values must be whole numbers, rounding these values off yields 410 and 2048
counts, respectively. Therefore, at a count of 410, the low-level temperature alarm
would be enabled; and at a count of 2048, the high-level temperature alarm would be
enabled.
Another method for solving this problem is to determine the number of counts that are
equivalent to 1C. A change of 1000C per 4095 counts can be expressed as:

Therefore, each degree is equivalent to 4.095 counts. The count value for 500C
would be (500)(4.095) = 2047.5 and for 100C would be (100)(4.095) = 409.5.
Rounding off these values yields 2048 and 410 counts, respectively the same values
we computed before. If the counts had not started at 0, an offset count addition would
have been necessary for computing the number of counts per degree.
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Example 9-2
A D/A (DAC) with a 12-bit resolution creates an analog signal ranging from 0 to
4095 counts (4096 total values), which is proportional to a 12-bit digital signal (212 =
4096).
Find the analog value 2047 (i) for an analog field device with a range of 0 VDC to 10
VDC. and (ii) for an analog field device with a range of 4mA to 20mA.
Solution
A 2047 analog value would be equal to a 5 VDC signal for an analog field device
with a range of 0 VDC to 10 VDC, and 12mA for an analog field device with a range
of 4mA to 20mA as shown in the following table:

9.3 Motors Control Applications


9.3.1 Start/Stop Operation Of Three Phase Induction Motor:
L

L1
L2
L3
F2..4

Off

O.L
C1

On
C1

O.L

C1

N
Figure 9-12. Control and Power circuits of 3 induction motor.

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+24
O.L

Off

I0.
I/P Leds

O/P Leds

Q0.

On

C1
Figure 9-13. PLC Connection Diagram for Start/Stop operation of 3 induction motor.

Figure 9-14. PLC Ladder program for Start/Stop operation of 3 induction motor.

Note: For safety reasons, all STOP buttons must be wired so that a failure of the
switch or a broken wire will automatically break logic continuity and turn the circuit
OFF (wired as N.C.). A good programmer should always wire the devices and
program the circuit so that if the real-world device fail, it creates a safe condition, not
a safety hazard.

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9.3.2 Bidirectional Operation Of Three Phase Induction Motor:

Figure 9-15. Power and Control circuits of bidirectional operation of 3 induction motor.

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+24
O.L

Off

I0.
I/P Leds

O/P Leds

Q0.

On F

On R

CF

CR

0
Figure 9-16. PLC Connection Diagram for Forward/Reverse operation of 3 induction motor.

Figure 9-17. PLC Ladder program for Forward/Reverse operation of 3 induction motor.

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9.3.3 Star/Delta Starting Method Of Three Phase Induction Motor:

Figure 9-18. Power and Control circuits for Star/Delta Starting Method.

PLC-2012

Eng. Mohammad Al-Arni

+24
O.L

Off

I0.
I/P Leds

O/P Leds

Q0.

On

CM

CY

0
Figure 9-19. PLC Connection Diagram for Star/Delta Starting Method.

Figure 9-20. PLC Ladder program for Star/Delta Starting Method.

PLC-2012

Eng. Mohammad Al-Arni