ISDRS 2009, December 9-11, 2009, College Park, MD, USA

Student Paper

A new SiGe Stepped Gate (SSG) Thin Film SOI LDMOS for enhanced breakdown voltage and reduced delay
Radhakrishnan Sithanandam and M. Jagadesh Kumar Department of Electrical Engineering, Indian Institute of Technology Delhi, India, mamidala@ieee.org

This paper introduces a new SiGe Stepped Gate (SSG) thin film SOI LDMOS for enhanced performance. The proposed device eliminates the premature breakdown of the device due to floating body effects, which is one major problem of the thin film SOI LDMOS. The most common technique used to eliminate the floating body effects in SOI power device is the source tied body contact. Though this technique is successful in thick film devices, its effectiveness to thin film LDMOS is questionable, and also it imposes area penalty. Without a body contact, the floating body effects can be also reduced by decreasing the drift region doping [1]. But increased drift region resistance degrades the on-resistance of the device. The proposed device, SSG LDMOS circumvents the above challenges. It has a germanium implanted source and stepped field plate in the drift region. The SSG LDMOS reduces floating body effects in two ways. The SiGe source offers low potential to the excess holes generated due to the impact ionization [2]. The stepped gate reduces gate-drain capacitance improving the switching speed. The combined effect of (i) SiGe in the source and (ii) the stepped gate, improves the breakdown voltage and also allows us to increase the drift doping levels resulting in a reduced on-resistance. Using two dimensional device simulation [3], the proposed device is simulated and compared with the conventional thin film LDMOS. The cross-sectional view of both the devices is shown in Fig. 1. The conventional LDMOS has a uniform gate oxide thickness of 50 nm with a field plate. The drift region doping in both the devices is chosen for maximum breakdown voltage and is found to be 9×1016 cm-3 (which is higher than the conventional device doping 3×1016 cm-3). The germanium mole fraction in the SiGe source of the SSG LDMOS is chosen to be 0.2. The device parameters used in our simulation are given in Table 1. Figs. 2 and 3 show the breakdown characteristics and the on-resistance variation of the SSG LDMOS and the conventional LDMOS. The SSG LDMOS exhibits a 97% improvement in breakdown voltage and a 61% reduction in onresistance compared to the convetional LDMOS. Figs. 4 and 5 show the switching delay and the gate-charge behaviour. We observe that the SSG LDMOS exhibits a 57% reduction in switching delay and a 50% reduction in gate-drain charge compared to the conventional LDMOS. This work clearly demonstrates the application of SiGe source and a stepped oxide gate in improving the performance of the LDMOS making this device more useful in both RF and wireless system-onchip applications. References
[1] M. Bawedin, C. Renaux and D. Flandre, “LDMOS in SOI technology with very-thin silicon film,” Solid State Electronics, vol. 48, pp. 2263-2270, Dec 2004. [2] M. J. Kumar and V. Verma, "Elimination of Bipolar Induced Drain Breakdown and Single Transistor Latch in Submicron PD SOI MOSFET," IEEE Transactions on Reliability, vol. 51, no. 3, pp. 367-370, Sep. 2002. [3] ATLAS user's manual : Device simulation software. Santa Clara, CA: Silvaco International, 2007.

ISDRS 2009 – http://www.ece.umd.edu/ISDRS2009

978-1-4244-6031-1/09/$26.00 ©2009 IEEE

Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY DELHI. Downloaded on January 31, 2010 at 04:39 from IEEE Xplore. Restrictions apply.

ISDRS 2009, December 9-11, 2009, College Park, MD, USA

Table. 1 Device parameters used in simulation. Gate oxide thickness, 50 nm, 100 nm and (tox1, tox2 and tox3) 300 nm Gate length, 1 μm, 0.5 μm and (LG1, LG2 and LG3) 0.5 μm Channel length, L 0.5 μm Source/Drain doping 1×1019 cm-3 Channel doping 1×1017 cm-3 Buried oxide 400 nm thickness Silicon thickness 200 nm Drift region length 3.5 μm Threshold voltage of conventional and SSG LDMOS 1.85 V

Fig. 1 Cross sectional view of (a) the conventional LDMOS (b) the SSG LDMOS.

Fig. 2 Breakdown voltage characteristics of the conventional and SSG LDMOS.

Fig. 3 On-resistance of the conventional and SSG LDMOS.

Fig. 4 Switching characteristics of conventional and SSG LDMOS.

Fig. 5 Gate charging curve of conventional and SSG LDMOS.

ISDRS 2009 – http://www.ece.umd.edu/ISDRS2009

Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY DELHI. Downloaded on January 31, 2010 at 04:39 from IEEE Xplore. Restrictions apply.

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