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Questa Verification Library

Monitors Data Book


Software Version 2010.2

1991-2010 Mentor Graphics Corporation


All rights reserved.
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Table of Contents
Chapter 1
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Syntax Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mentor Graphics Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

23
23
24

Chapter 2
QVL Monitors Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
QVL Use Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifying Global Defines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instantiate QVL Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instance Templates Directory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compile QVL Monitor Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compile and Simulate the DUT with the QVL Monitor . . . . . . . . . . . . . . . . . . . . . . . . . .
Verify and Troubleshoot the QVL Monitor Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Review and Debug Simulation QVL Monitor Results . . . . . . . . . . . . . . . . . . . . . . . . . . . .
QVL Monitor Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Run Formal Verification with QVL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connectivity on the Bi-Directional/Tri-State Buffer Signals . . . . . . . . . . . . . . . . . . . . . . . .

25
25
26
28
28
32
33
34
35
36
39
39

Chapter 3
Advanced Microcontroller Bus Architecture (AMBA) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AHB Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
APB Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AHB Master Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AHB Master Monitor Instantiation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AHB Master Monitor FAQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AHB Target Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AHB Target Monitor Instantiation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

41
41
41
41
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51
52
52
52
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54
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AHB Target Monitor FAQ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


APB Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
APB Monitor Instantiation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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62
62
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64
65
65

Chapter 4
AMBA 3 Advanced Peripheral Bus (APB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AMBA 3 APB Monitor Instantiation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

67
67
67
67
67
68
69
69
71
71

Chapter 5
AMBA AXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Reference Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Supported Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Unsupported Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Monitor Connectivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Monitor Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
AMBA AXI Monitor Instantiation Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Chapter 6
Double Data Rate SDRAM (DDR SDRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V1.0 Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Mode Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization Sequence Bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DDR SDRAMs Stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4

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Instantiation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V2.0 Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Mode Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data interface and Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization Sequence Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instantiation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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132
133
134
134
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135
135
135
136
139
145
154
165
167

Chapter 7
Double Data Rate-II SDRAM (DDR-II SDRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V1.0 Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Mode Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DDR-II SDRAMs Stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instantiation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V2.0 Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Mode Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization Sequence Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instantiation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Table of Contents

Chapter 8
Gigabit Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supported Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gigabit Media Independent Interface (GMII). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reduced Gigabit Media Independent Interface (RGMII). . . . . . . . . . . . . . . . . . . . . . . . . .
Media Independent Interface (MII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reduced Media Independent Interface (RMII). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10 Gigabit Media Independent Interface (XGMII). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40/100 Gigabit Media Independent Interface (XLGMII/CGMII) . . . . . . . . . . . . . . . . . . .
1000BASE-X Ten bit Interface (TBI) between PCS and PMA . . . . . . . . . . . . . . . . . . . . .
Reduced Ten bit Interface (RTBI) between PCS and PMA . . . . . . . . . . . . . . . . . . . . . . . .
10 Gigabit Attachment Unit Interface (XAUI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XAUI Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10 Gigabit Sixteen Bit Interface (XSBI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40G/100G Attachment Unit Interface (XLAUI, CAUI). . . . . . . . . . . . . . . . . . . . . . . . . . .
40G or 100G Auto Negotiation Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supported Control Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unsupported Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instantiation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

223
223
224
224
224
224
225
225
225
226
226
226
227
227
227
228
228
229
229
229
230
238
249
249
250
251
251
252
252
253
253
254
255
255
256
256
285
287

Chapter 9
High-Definition Multimedia Interface (HDMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supported Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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289
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HDMI Monitor Instantiation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


Compiler Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Coverage Count Totals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

295
296
297
303
307

Chapter 10
I2C (Inter-IC) Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Monitor Instantiation Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Master Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Slave Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Master/Slave Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slave Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Assertion Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slave Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slave Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

309
309
310
310
311
313
313
313
314
314
315
318
319
320
320
321
321

Chapter 11
Low Pin Count (LPC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instantiation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

323
323
323
323
323
324
325
326
329
329

Chapter 12
Open Core Protocol (OCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supported Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Response Signaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Threads and Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Data buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sideband Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCP Disconnect Proposal Revision 0.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unsupported Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instantiation Modification is Required for OCP 2.1 Users. . . . . . . . . . . . . . . . . . . . . . . . .
Instantiation Modification is Required for OCP 2.1 and 2.2 Users . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instantiation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

332
332
332
333
333
333
334
338
340
350
352
352
354
356
395
397

Chapter 13
Peripheral Component Interconnect (PCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instantiation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initiator (Master) Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Target Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Top-level Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

399
399
399
399
400
402
402
403
404
407
412
414
414

Chapter 14
PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supported Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unsupported Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standard Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connectivity Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instantiation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PIPE Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity (PIPE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connectivity Notes (PIPE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters (PIPE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

415
415
415
415
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418
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Questa Verification Library Monitors Data Book, v2010.2

Table of Contents

Instantiation Examples (PIPE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Physical Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Link Layer Check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transaction Layer Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PIPE Interface Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compliance Rules Cross-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Checks Not Performed by the Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Gen2 Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Gen2 Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor FAQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

438
442
442
458
466
487
493
504
505
613
615
616
617
619

Chapter 15
Serial Attached SCSI (SAS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supported Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unsupported Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connectivity Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instantiation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connecting Clocks in Serial Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Recovery Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Physical Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transport Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SMP, SSP and STP Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor FAQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

623
623
623
623
624
624
626
630
630
635
635
637
638
639
640
640
642
642
647
659
662
663
664

Chapter 16
SERIAL ATA (SATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supported Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

671
671
671
671
672
673
676

Questa Verification Library Monitors Data Book, v2010.2

Table of Contents

Instantiation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power on Sequence Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phy Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Link Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transport Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SAPIS Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Link Layer Normal and Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transport Layer Normal and Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor FAQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

680
683
683
686
688
700
707
708
711
714

Chapter 17
Serial Parallel Interface (SPI) Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supported Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Monitor Instantiation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

719
719
719
719
719
720
721
721
722

Chapter 18
System Packet Interface Level 4 Phase 2 (SPI4-2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instantiation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instantiation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

723
723
723
724
724
724
728
730
734
741
741
743
743
743
747
749
749
750
751
753
759
760

10

Questa Verification Library Monitors Data Book, v2010.2

Table of Contents

Chapter 19
Universal Serial Bus 2.0 (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supported Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB 2.0 Monitor Instantiated on the Host or Hub . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB 2.0 (Standard) Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connectivity Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instantiation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB 2.0 UTMI Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connectivity Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instantiation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB 2.0 ULPI Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connectivity Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instantiation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB 2.0 Standard Monitor Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB 2.0 UTMI Monitor Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB 2.0 ULPI Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

761
761
761
762
763
763
764
764
765
767
768
768
769
770
770
772
774
779
781
781
782
783
788
790
790
804
824
846
849

Appendix 20
QVL Defines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Global Defines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Global Defines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Defines Common to All Assertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

851
851
851
852

End-User License Agreement

Questa Verification Library Monitors Data Book, v2010.2

11

List of Examples
Example 2-1. Verilog AHB Master Monitor Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Example 2-2. VHDL AHB Master Monitor Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Example 2-3. Binding an Assertion Module to the DUT in SVA . . . . . . . . . . . . . . . . . . . . . 31
Example 2-4. Verilog Simulator Argument Sample File. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Example 3-1. AHB Master Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Example 3-2. AHB Target Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Example 3-3. APB Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Example 4-1. AMBA 3 APB Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Example 5-1. AMBA AXI Monitor Instantiation for Example 1 . . . . . . . . . . . . . . . . . . . . . 79
Example 5-2. AMBA AXI Monitor Instantiation for Example 2 . . . . . . . . . . . . . . . . . . . . . 81
Example 6-1. DDR SDRAM Monitor Instantiated in the Controller . . . . . . . . . . . . . . . . . . 113
Example 6-2. Two DDR SDRAM Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Example 6-3. DDR SDRAM Monitor Instantiated in the Controller . . . . . . . . . . . . . . . . . . 116
Example 6-4. DDR SDRAM Monitor Instantiated with NON JEDEC Timing Parameter Values
117
Example 6-5. DDR SDRAM 2.0 Monitor Instantiated in the Controller . . . . . . . . . . . . . . . 145
Example 6-6. Two DDR SDRAM 2.0 Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Example 6-7. DDR SDRAM 2.0 Monitor Instantiated in the Controller . . . . . . . . . . . . . . . 149
Example 6-8. DDR SDRAM 2.0 Monitor Instantiated with NON JEDEC Timing Values
Configured Through Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Example 6-9. DDR SDRAM 2.0 Monitor Instantiated with NON JEDEC Timing Values
Configured Through Input Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Example 7-1. DDR-II SDRAM 1.0 Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Example 7-2. DDR-II SDRAM 1.0 Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Example 7-3. DDR-II SDRAM 2.0 Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Example 7-4. DDR-II SDRAM 2.0 Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Example 8-1. 1 Gigabit Ethernet GMII Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . 249
Example 8-2. Reduced Gigabit Ethernet RGMII Monitor Instantiation . . . . . . . . . . . . . . . . 250
Example 8-3. 10/100M Gigabit Ethernet MII Monitor Instantiation . . . . . . . . . . . . . . . . . . 251
Example 8-4. 10/100M Gigabit Ethernet RMII Monitor Instantiation . . . . . . . . . . . . . . . . . 251
Example 8-5. 10 Gigabit Ethernet XGMII Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . 252
Example 8-6. 40/100 Gigabit Ethernet XLGMII/CGMII Monitor Instantiation. . . . . . . . . . 252
Example 8-7. 1000BASE-X TBI Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Example 8-8. Reduced Ten bit Interface Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Example 8-9. 10 Gigabit Ethernet XAUI Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . 254
Example 8-10. 10 Gigabit Ethernet XSBI Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . 255
Example 8-11. 100 Gigabit Ethernet CAUI Monitor Instantiation . . . . . . . . . . . . . . . . . . . . 255
Example 8-12. 100 Gigabit Ethernet Auto-Negotiation Monitor Instantiation . . . . . . . . . . . 256
Example 9-1. HDMI Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Example 10-1. I2C Master Monitor Instantiation for a Master Only Design . . . . . . . . . . . . 314
12

Questa Verification Library Monitors Data Book, v2010.2

List of Examples

Example 10-2. I2C Slave Monitor Instantiation for a Slave Only Design . . . . . . . . . . . . . .
Example 10-3. I2C Master/Slave Monitor Instantiation for a Master/Slave Design. . . . . . .
Example 11-1. LPC Monitor Instantiation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 12-1. OCP Monitor Instantiation for Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 12-2. OCP Monitor Instantiation for Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 13-1. PCI Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 14-1. PCI Express Monitor Instantiation Example 1 . . . . . . . . . . . . . . . . . . . . . . .
Example 14-2. PCI Express Monitor Instantiation Example 2 . . . . . . . . . . . . . . . . . . . . . . .
Example 14-3. PCI Express Gen2 Monitor Instantiation Example 3 . . . . . . . . . . . . . . . . . .
Example 14-4. PIPE Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 14-5. PIPE Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 14-6. PIPE Monitor Instantiation Example 3 (9Bit Mode). . . . . . . . . . . . . . . . . . .
Example 14-7. PIPE Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 15-1. SAS Monitor Within an SAS Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 15-2. SAS Monitor Within an Expander Device . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 15-3. SAS Monitor Within a SAS Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 15-4. SAS Monitor Within an Expander Device . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 15-5. Clock Recovery Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 16-1. SATA Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 16-2. SATA Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 16-3. SATA Monitor Instantiation for Example 3 . . . . . . . . . . . . . . . . . . . . . . . . .
Example 16-4. SATA Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 17-1. SPI Monitor Master Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 18-1. SPI4-2 Receive Monitor Instantiation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 18-2. SPI4-2 Receive Monitor Instantiation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 18-3. SPI4-2 Receive Monitor Instantiation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 18-4. SPI4-2 Transmit Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 18-5. SPI4-2 Transmit Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 18-6. SPI4-2 Transmit Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 19-1. USB Monitor on the Downstream Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 19-2. USB Monitor on the Upstream Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 19-3. USB Monitor to Track an 8-bit UTM Interface . . . . . . . . . . . . . . . . . . . . . .
Example 19-4. USB Monitor on the Upstream Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 19-5. USB Monitor to Track an 4-bit ULP Interface . . . . . . . . . . . . . . . . . . . . . . .
Example 19-6. USB Monitor on the Upstream Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Questa Verification Library Monitors Data Book, v2010.2

314
314
325
352
354
403
427
428
429
438
439
440
441
636
637
638
639
642
680
681
682
682
721
731
732
733
749
751
752
768
769
779
780
788
789

13

List of Figures
Figure 2-1. RTL Signals and Tri-State Buffer (I/O Structure) . . . . . . . . . . . . . . . . . . . . . . .
Figure 3-1. AHB-Based System Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3-2. APB-Based System Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3-3. AHB Master Monitor Pins Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3-4. AHB Target Monitor Pins Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3-5. APB Monitor Pins Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-1. AMBA 3 APB Monitor Pins Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 5-1. AMBA AXI Monitor Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 5-2. AMBA AXI Monitor Pins Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6-1. DDR SDRAM System Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6-2. DDR SDRAM Monitor Pin-Out Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6-3. Stacking DDR SDRAMs by Data Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6-4. Stacking DDR SDRAMs by Address Width . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6-5. DDR SDRAM System Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6-6. DDR SDRAM 2.0 Monitor Pin-Out Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7-1. DDR-II SDRAM 1.0 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7-2. DDR-II SDRAM 1.0 Monitor Pin-Out Diagram . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7-3. Stacking DDR-II SDRAMs by Data Width . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7-4. Stacking DDR-II SDRAMs by Address Width . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7-5. DDR-II SDRAM 2.0 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7-6. DDR-II SDRAM 2.0 Monitor Pin-Out Diagram . . . . . . . . . . . . . . . . . . . . . . . .
Figure 8-1. Gigabit Ethernet Monitor Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 8-2. Gigabit Ethernet Monitor Pin-Out Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 9-1. HDMI Monitor Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 9-2. HDMI Monitor Pins Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-1. I2C System Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-2. I2C Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-3. I2C Master Monitor Pins Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-4. I2C Slave Monitor Pins Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-5. I2C Master/Slave Monitor Pins Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 11-1. LPC Monitor Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 11-2. LPC Monitor Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-1. OCP Monitor Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-2. OCP Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-3. OCP Monitor Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 13-1. PCI Monitor Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 13-2. PCI Monitor Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 14-1. PCI Express Gen1 Monitor Implementation . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 14-2. PCI Express Gen2 Monitor Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 14-3. PCI Express Monitor Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14

40
42
42
43
52
62
67
74
75
105
106
108
108
136
137
171
171
173
173
192
193
230
231
290
291
309
310
311
311
311
323
324
338
340
341
399
400
419
420
421

Questa Verification Library Monitors Data Book, v2010.2

List of Figures

Figure 14-4. Gen1 PIPE Monitor Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


Figure 14-5. Gen2 PIPE Monitor Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 14-6. PIPE Monitor Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 15-1. SAS Monitor Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 15-2. SAS Monitor (dynamic timer values) Implementation . . . . . . . . . . . . . . . . . .
Figure 15-3. SAS Monitor Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 15-4. Connecting Clocks in Serial Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 15-5. Connecting Clock Recovery Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 15-6. Examples of Single- and Multi-PHY Devices . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 16-1. SATA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 16-2. SATA Monitor Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 17-1. SPI Monitor Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 17-2. SPI Monitor Pins Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 18-1. SPI4-2 Receive Monitor Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 18-2. SPI4-2 Receive Monitor Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 18-3. SPI4-2 Transmit Monitor Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 18-4. SPI4-2 Transmit Monitor Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 19-1. USB 2.0 Monitor Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 19-2. USB 2.0 (standard) Monitor Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 19-3. USB 2.0 UTMI Monitor Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 19-4. USB 2.0 ULPI Monitor Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Questa Verification Library Monitors Data Book, v2010.2

430
430
431
625
626
627
640
641
664
673
674
720
720
724
725
743
744
764
765
770
781

15

List of Tables
Table 1-1. Conventions for Command Line Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-1. AHB Master Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-2. AMBA AHB Master Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-3. AMBA AHB Master Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-4. AMBA AHB Master Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-5. AMBA AHB Master Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-6. AHB Target Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-7. AMBA AHB Target Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-8. AMBA AHB Target Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-9. AMBA AHB Target Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-10. AMBA AHB Target Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-11. APB Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-12. AMBA APB Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-13. AMBA APB Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-14. AMBA APB Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-15. AMBA APB Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4-1. AMBA 3 APB Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4-2. AMBA 3 APB Monitor Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4-3. AMBA 3 APB Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4-4. AMBA 3 APB Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4-5. AMBA 3 APB Protocol Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5-1. AMBA AXI Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5-2. AMBA AXI Monitor Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5-3. AMBA AXI Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5-4. AMBA AXI Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5-5. AMBA AXI Protocol Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-1. DDR SDRAM Monitor Pin-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-2. DDR SDRAM Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-3. JEDEC Mode Burst Length Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-4. JEDEC Mode CAS Latency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-5. JEDEC Standard Compliant Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-6. DDR SDRAM Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-7. DDR SDRAM Monitor Checks for Each Bank . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-8. Calculate Minimum Delay From a Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-9. DDR SDRAM Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-10. DDR SDRAM Monitor Corner Cases Maintained for Each Bank . . . . . . . . . .
Table 6-11. DDR SDRAM Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-12. DDR SDRAM Monitor Statistics Maintained for Each Bank . . . . . . . . . . . . . .
Table 6-13. DDR SDRAM 2.0 Monitor Pin-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-14. DDR SDRAM 2.0 Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Questa Verification Library Monitors Data Book, v2010.2

23
43
44
46
50
51
52
53
55
60
61
62
63
64
65
65
68
68
69
71
71
75
77
82
99
102
106
108
112
112
113
119
123
131
132
132
133
133
137
140
16

List of Tables

Table 6-15. JEDEC Mode Burst Length Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .


Table 6-16. JEDEC Mode CAS Latency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-17. JEDEC Compliant Min. Timing for DDR SDRAM Speed Grade 266 . . . . . . .
Table 6-18. DDR SDRAM 2.0 Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-19. DDR SDRAM 2.0 Monitor Checks for Each Bank . . . . . . . . . . . . . . . . . . . . .
Table 6-20. Calculate Minimum Delay From a read/Write . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-21. DDR SDRAM 2.0 Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-22. DDR SDRAM 2.0 Monitor Corner Cases Maintained for Each Bank . . . . . . .
Table 6-23. DDR SDRAM 2.0 Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-24. DDR SDRAM 2.0 Monitor Statistics Maintained for Each Bank . . . . . . . . . . .
Table 7-1. DDR-II SDRAM 1.0 Monitor Pin-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-2. DDR-II SDRAM 1.0 Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-3. JEDEC Standard Compliant Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-4. Checks Performed by a DDR-II SDRAM 1.0 Monitor . . . . . . . . . . . . . . . . . . . .
Table 7-5. DDR-II SDRAM 1.0 Monitor Bank Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-6. DDR-II SDRAM 1.0 Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-7. DDR-II SDRAM 1.0 Bank Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-8. DDR-II SDRAM 1.0 Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-9. DDR-II SDRAM 1.0 Bank Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-10. DDR-II SDRAM 2.0 Monitor Pin-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-11. DDR-II SDRAM 2.0 Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-12. JEDEC Standard Compliant Timing for DDR2 400 Speed Grade . . . . . . . . . .
Table 7-13. DDR-II SDRAM 2.0 Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-14. DDR-II SDRAM 2.0 Monitor Bank Checks . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-15. DDR-II SDRAM 2.0 Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-16. DDR-II SDRAM 2.0 Bank Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-17. DDR-II SDRAM 2.0 Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7-18. DDR-II SDRAM 2.0 Bank Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-1. GMII Monitor Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-2. RGMII Monitor Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-3. MII Monitor Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-4. RMII Monitor Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-5. XGMII Monitor Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-6. XLGMII/CGMII Monitor Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-7. 1000BASE-X Ten bit Interface Monitor Pin Descriptions . . . . . . . . . . . . . . . . .
Table 8-8. Reduced Ten bit Interface Monitor Pin Descriptions . . . . . . . . . . . . . . . . . . . . .
Table 8-9. XAUI Monitor Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-10. XSBI Monitor Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-11. XLAUI/CAUI Monitor Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-12. 40/100G Auto-Negotiation Monitor Pin Descriptions . . . . . . . . . . . . . . . . . . .
Table 8-13. GMII Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-14. RGMII Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-15. MII Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-16. RMII Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-17. XGMII Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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List of Tables

Table 8-18. XLGMII/CGMII Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


Table 8-19. TBI Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-20. RTBI Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-21. XAUI Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-22. XSBI Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-23. XLAUI/CAUI Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-24. 40/100G Auto-Negotiation Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-25. MAC Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-26. GMII Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-27. RGMII Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-28. MII Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-29. RMII Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-30. XGMII Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-31. XLGMII/CGMII Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-32. TBI Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-33. XAUI Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-34. BASER Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-35. XLAUI/CAUI Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-36. 40/100G Auto-Negotiation Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-37. Gigabit Ethernet Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8-38. Gigabit Ethernet Protocol Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-1. HDMI Monitor Pins Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-2. HDMII Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-3. Verilog and SystemVerilog Compiler Directives . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-4. HDMI Data Channel Unknown Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-5. HDMI Data Integrity Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-6. HDMI Protocol Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-7. HDMI Programming Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-8. HDMI Cover Basic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-9. HDMI Cover Corner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-10. HDMI Packet Cover Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-11. HDMI Programming Cover Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-12. Coverage Count Totals for HDMI 1.3a Monitor . . . . . . . . . . . . . . . . . . . . . . . .
Table 9-13. Statistics Count Totals for HDMI 1.3a Monitor . . . . . . . . . . . . . . . . . . . . . . . .
Table 10-1. I2C Monitor PINs Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 10-2. I2C Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 10-3. I2C Master Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 10-4. I2C Slave Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 10-5. I2C Assertion Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 10-6. I2C Master Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 10-7. I2C Master Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 10-8. I2C Slave Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 10-9. I2C Slave Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-1. LPC Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-2. LPC Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Table 11-3. LPC Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


Table 11-4. LPC Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-5. LPC Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 12-1. OCP Monitor Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 12-2. OCP Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 12-3. OCP Monitor Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 12-4. OCP Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 12-5. OCP Protocol Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 13-1. PCI Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 13-2. PCI Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 13-3. PCI Initiator Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 13-4. PCI Target Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 13-5. PCI Top-Level Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 13-6. PCI Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 13-7. PCI Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-1. PCI Express Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-2. PCI Express Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-3. PIPE Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-4. PIPE Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-5. PCI Express Monitor Physical Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-6. Link Training and Width Negotiation Checks . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-7. PCI Express Monitor Data Link Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-8. PCI Express Monitor Transaction Layer Transmit Checks . . . . . . . . . . . . . . . .
Table 14-9. PCI Express Monitor Power Management Checks . . . . . . . . . . . . . . . . . . . . . .
Table 14-10. Receive Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-11. PIPE Interface Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-12. PCI Express Gen2 Physical Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-13. PCI Express Gen2 Link Training and Width Negotiation Checks . . . . . . . . .
Table 14-14. PCI Express Gen2 Transaction Layer Transmit Checks . . . . . . . . . . . . . . . .
Table 14-15. PCI Express Gen2 Power Management Checks . . . . . . . . . . . . . . . . . . . . . . .
Table 14-16. PCI Express Gen2 PIPE Interface Checks . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-17. PCI Express Compliance Checklist: Topology . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-18. PCI Express Compliance Checklist: Transaction Protocol . . . . . . . . . . . . . . .
Table 14-19. PCI Express Compliance Checklist: Link Protocol . . . . . . . . . . . . . . . . . . . . .
Table 14-20. PCI Express Compliance Checklist: Link-Physical Layer Interface . . . . . . . .
Table 14-21. PCI Express Compliance Checklist: Electrical . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-22. PCI Express Compliance Checklist: Power Management . . . . . . . . . . . . . . . .
Table 14-23. PCI Express Compliance Checklist: System Architecture . . . . . . . . . . . . . . .
Table 14-24. PCI Express Compliance Checklist: Configuration . . . . . . . . . . . . . . . . . . . .
Table 14-25. PCI Express Compliance Checklist: Isochronous Applications . . . . . . . . . . .
Table 14-26. PCI Express Compliance Checklist: Electromechanical . . . . . . . . . . . . . . . . .
Table 14-27. Checklist Applicable for End Point Only . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-28. Checklist Applicable for Root Complex Only . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-29. Checklist Applicable for Switch Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-30. Physical Layer Corner Cases Maintained by the PCI Express Monitor . . . . .

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19

List of Tables

Table 14-31. Data Link Layer Corner Cases Maintained by the PCI Express Monitor . . . .
Table 14-32. Transaction Layer Corner Cases Maintained by the PCI Express Monitor . .
Table 14-33. Physical Layer Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-34. Data Link Layer Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-35. Transaction Layer Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-36. Physical Layer Corner Cases PCI Express Monitor Gen2 . . . . . . . . . . . . . . .
Table 14-37. Data Link Layer Corner Cases PCI Express Monitor Gen2 . . . . . . . . . . . . . .
Table 14-38. Transaction Layer Corner Cases PCI Express Monitor Gen2 . . . . . . . . . . . . .
Table 14-39. Physical Layer Statistics PCI Express Monitor Gen2 . . . . . . . . . . . . . . . . . . .
Table 14-40. Data Link Layer Statistics PCI Express Monitor Gen2 . . . . . . . . . . . . . . . . . .
Table 14-41. Transaction Layer Statistics PCI Express Monitor Gen2 . . . . . . . . . . . . . . . .
Table 15-1. SAS Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15-2. SAS Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15-3. SAS Monitor (dynamic timer values) Parameters . . . . . . . . . . . . . . . . . . . . . . .
Table 15-4. Clock Recovery Module Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15-5. SAS Monitor Physical Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15-6. SAS Monitor Transport Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15-7. SMP Transport Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15-8. SSP Transport Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15-9. STP Transport Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15-10. SAS Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15-11. SAS Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15-12. Bit Order for TX and RX Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-1. SATA - Serial and parallel 10B Interface Monitor Pins . . . . . . . . . . . . . . . . . .
Table 16-2. SAPIS Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-3. SATA Monitor Parameters - Serial / Parallel10B Interfaces . . . . . . . . . . . . . .
Table 16-4. SATA Monitor Parameters - SAPIS Interface . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-5. Power on Sequence Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-6. Phy Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-7. Link Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-8. Transport Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-9. SAPIS Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-10. Link Layer Normal Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-11. Link Layer Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-12. Transport Layer Normal Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-13. Transport Layer Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 17-1. SPI Monitor Pins Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 17-2. SPI Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 17-3. SPI Master Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 18-1. SPI4-2 Receive Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 18-2. SPI4-2 Receive Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 18-3. SPI4-2 Receive Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 18-4. SPI4-2 Receive Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 18-5. SPI4-2 Receive Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 18-6. SPI4-2 Transmit Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

20

613
614
615
615
615
616
617
617
617
618
618
628
630
633
641
642
647
659
660
661
662
663
665
674
675
676
678
683
686
688
700
707
708
709
711
711
720
721
722
725
728
734
741
741
744

Questa Verification Library Monitors Data Book, v2010.2

List of Tables

Table 18-7. SPI4-2 Transmit Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


Table 18-8. SPI4-2 Transmit Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 18-9. SPI4-2 Transmit Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 18-10. SPI4-2 Transmit Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 19-1. USB 2.0 (standard) Monitor Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 19-2. USB 2.0 Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 19-3. USB 2.0 UTMI Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 19-4. USB 2.0 UTMI Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 19-5. USB 2.0 ULPI Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 19-6. USB2.0 ULPI Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 19-7. USB 2.0 Standard Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 19-8. USB 2.0 UTMI Monitor UTMI Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 19-9. USB 2.0 UTMI Monitor USB 2.0 Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 19-10. USB 2.0 ULPI Monitor ULPI Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 19-11. USB 2.0 ULPI Monitor USB 2.0 Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 19-12. USB 2.0 Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 19-13. USB 2.0 Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Questa Verification Library Monitors Data Book, v2010.2

747
753
759
760
765
767
770
774
781
783
790
804
812
824
835
846
849

21

List of Tables

22

Questa Verification Library Monitors Data Book, v2010.2

Chapter 1
Introduction
Syntax Conventions
This manual uses the following command usage line syntax conventions.
Table 1-1. Conventions for Command Line Syntax
Convention

Example

Usage

Boldface

SET COMmand Editing


A boldface font indicates a required argument.
-Off | -Vi | -Emacs | -Gmacs

[ ]

EXIt [-Discard]

Square brackets enclose optional arguments. Do


not enter the brackets.

Italic

DOFile filename

An italic font indicates a user-supplied


argument.

{ }

ADD LFsrs lfsr_name


{Prpg | Misr} length seed
[-Out | -In]

Braces enclose arguments to show grouping. Do


not enter the braces.

ADD LFsrs lfsr_name


{Prpg | Misr} length seed
[-Out | -In]

The vertical bar indicates an either/or choice


between items. Do not include the bar in the
command.

ADD LFsr Connections


primary_pin lfsr_name
position

An ellipsis follows an argument that may appear


more than once. Do not include the ellipsis when
entering commands.

The following examples demonstrate these syntax conventions.


signal

One or more occurrences of signal.

[-var req_signal]

Zero or one occurrences of -var


req_signal.

-var {req_signal}

-var followed by one or more occurrences


of req_signal.

[std_option]

Zero or more occurrences of std_option.

Questa Verification Library Monitors Data Book, v2010.2

23

Introduction
Mentor Graphics Support

{arg1 arg2}

One or more occurrences of arg1 arg2.

var1 | var2 | var3

One occurrence of var1or var2 or var3.

constant | val1 val2

One occurrence of constant or val1 val2.

{[var1][var2][var3]}

Zero or more occurrences of any of var1,


var2, and var3.

Mentor Graphics Support


Mentor Graphics software support includes software enhancements, technical support, access to
comprehensive online services with SupportNet, and the optional On-Site Mentoring service.
For details, see:
http://www.mentor.com/supportnet/options

If you have questions about this software release, please log in to SupportNet. You may search
thousands of technical solutions, view documentation, or open a Service Request online at:
http://www.mentor.com/supportnet

If your site is under current support and you do not have a SupportNet login, you may easily
register for SupportNet by filling out the short form at:
http://www.mentor.com/supportnet/quickaccess/SelfReg.do

All customer support contact information can be found on our web site at:
http://www.mentor.com/supportnet/support_offices.html

24

Questa Verification Library Monitors Data Book, v2010.2

Chapter 2
QVL Monitors Basics
The Questa Verification Library Monitors (QVL monitors) is a set of monitors that validate
specific industry-standard interface protocols and verify specific interface behaviors.
The QVL monitors are supported by the 0-In Formal Verification tool suite. In addition, the
QVL monitors are licensed for the Questa product.
Interface protocol monitors are modules that include QVL assertion checkers. A monitor
performs its verification functions using checkers embedded in the monitor itself. The monitor
is, in essence, a compound checker. QVL monitors are instantiated directly by identifying the
connections to the monitor inputs.
QVL monitors are SystemVerilog components that are wired to probe your design during
simulation and do the following as simulation progresses:

They warn of violations of the interface protocol through SystemVerilog assertion


failures.

They accumulate and maintain cover point data relevant to the protocol.

A QVL monitor can be configured to act as a formal constraint. Here, specific protocol rules are
turned into constraints (with the SystemVerilog assume construct) that constrain the formal
engines to restrict analysis to states that do not violate the monitors interface protocol.

QVL Use Model


The appropriate placement of the QVL monitor in the simulation environment depends on the
standard protocol being verified. Refer to the specific monitor in this manual for the
recommended monitor placement in your design.
Following are the steps to use QVL monitors:
1. Specifying Global Defines on page 26
2. Instantiate QVL Monitors on page 28
3. Compile QVL Monitor Libraries on page 32
4. Compile and Simulate the DUT with the QVL Monitor on page 33
5. Verify and Troubleshoot the QVL Monitor Setup on page 34
6. Review and Debug Simulation QVL Monitor Results on page 35

Questa Verification Library Monitors Data Book, v2010.2

25

QVL Monitors Basics


QVL Use Model

7. QVL Monitor Coverage on page 36


8. Run Formal Verification with QVL on page 39

Specifying Global Defines


You specify preferred control settings with standard global defines in either of the following
ways:

Specify settings using the standard +define options in the simulation argument file or at
the command line.

Specify settings in a Verilog file loaded before the libraries.


Note
If you reference QVL_ defines in a Verilog file, you should have a `include
"<qvl_install_dir>/qvl_src/qvl_checkers/std_qvl_defines.h" statement in the file.
Otherwise, you must specify the -mfcu option to vlog.

Enabling Assertion and Coverage Logic


The QVL consists of two types of logic: assertion logic and coverage logic. These capabilities
are enabled by defining the following standard global defines:
QVL_ASSERT_ON

Activates QVL assertion logic. Default: not defined.

QVL_COVER_ON

Activates QVL coverage logic. Default: not defined.

If neither of these constants is defined, then the QVL checkers are not activated. The
instantiations of these checkers has no influence on the verification performed.
Following is an example of using global defines:
vlog +define+QVL_ASSERT_ON+QVL_COVER_ON ...

Creating Cover Groups


By default, when QVL coverage logic is enabled (by specifying QVL_COVER_ON),
SystemVerilog cover groups are created. To disable cover groups, specify the following global
macro:
QVL_SV_COVERGROUP_OFF

26

Disables creation of SystemVerilog covergroup logic. Default:


not defined.

Questa Verification Library Monitors Data Book, v2010.2

QVL Monitors Basics


QVL Use Model

Displaying Final Coverage Information


When QVL coverage logic is enabled (by specifying QVL_COVER_ON), accumulated cover point
data can be displayed for each QVL checker and monitor at the end of simulation. For example,
the following output shows a sample AMBA AHB Master Monitor final coverage information:
----------------- Coverage for AMBA AHB Master Monitor ---------------Monitor instance
: ahb_master_tb.DUT.mas_mon
----------------- Statistics for AMBA AHB Master Monitor -------------Total Transfers
: 3324
----------------- Cornercases for AMBA AHB Master Monitor ------------Read Transfers
: 1274
Write Transfers
: 1517
IDLE Transfers
: 222
BUSY Transfers
: 311
OKAY Responses
: 3210
ERROR Responses
: 19
RETRY Responses
: 45
SPLIT Responses
: 50
SINGLE Burst Type
: 47
INCR Burst Type
: 112
WRAP4 Burst Type
: 51
INCR4 Burst Type
: 85
WRAP8 Burst Type
: 67
INCR8 Burst Type
: 115
WRAP16 Burst Type
: 960
INCR16 Burst Type
: 1354
Byte (8 bits) Transfer Size
: 100
Half Word (16 bits) Transfer Size
: 84
Word (32 bits) Transfer Size
: 2607
Double Word (64 bits) Transfer Size : 0
4 Word (128 bits) Transfer Size
: 0
8 Word (256 bits) Transfer Size
: 0
512 Bits Transfer Size
: 0
1024 Bits Transfer Size
: 0

By default, final coverage information is displayed for monitors, but not for checkers. To
change this behavior, specify one or both of the following global defines:
QVL_CW_FINAL_COVER

Turns on the display of final coverage information for QVL


checkers. Default: final coverage not displayed.

QVL_MW_FINAL_COVER_OFF

Turns off the display of final coverage information for QVL


monitors. Default: final coverage is displayed.

X/Z Checks
Assertion checkers can produce indeterminate results if a checker port value contains an X or Z
bit when the checker samples the port. (Note that a checker does not necessarily sample every
port at every active clock edge.) To assure determinate results, QVL monitors have special
assertions for X/Z checks (see Global Defines on page 851).

Questa Verification Library Monitors Data Book, v2010.2

27

QVL Monitors Basics


QVL Use Model

By default, QVL assertion checker logic includes logic implementing assertion checks for X
and Z bits in the values of checker ports when they are sampled. To exclude all X/Z checking
logic, specify the following global variable:
QVL_XCHECK_OFF

Turns off all X/Z checks.

Instantiation in an SVA Interface Construct


If QVL checkers are instantiated in a SystemVerilog interface construct, then define the
following global variable:
QVL_SVA_INTERFACE

Instantiates QVL assertion checkers in a SystemVerilog interface


construct. Default: not defined.

Resolving Race Conditions at QVL Inputs


By default, the input signals of QVL monitors are sampled directly. In some cases, this results
in race conditions on the sampled data. To resolve this problem, define the following global
variable:
QVL_RACE_AVOID

Adds one resolution unit of delay (that is, Verilog #1) to all QVL
input signals. Default: zero delay.

Instantiate QVL Monitors


To instantiate a QVL monitor into a design, it is easiest to cut and paste the monitor
instantiation from the associated template. The template lists the instances available ports on
the monitor and the available Verilog parameters or VHDL generics.
Starting from the QVL template, the user can modify the parameters or generic mapping as
appropriate, and also modify the port mapping to point to the relevant local signals.

Instance Templates Directory


Verilog and VHDL templates for the QVL monitors are located in the following directories,
respectively:
questasim_install_dir/qvl_src/templates/verilog/qvl_monitors/<monitor>
questasim_install_dir/qvl_src/templates/vhdl/qvl_monitors/<monitor>
Example 2-1 is a sample Verilog template and Example 2-2 is a sample VHDL template.

28

Questa Verification Library Monitors Data Book, v2010.2

QVL Monitors Basics


QVL Use Model

Example 2-1. Verilog AHB Master Monitor Template


qvl_ahb_master_monitor #(
.Constraints_Mode(0),
.DATA_BUS_WIDTH(32),
.CANCEL_FOLLOWING_TRANSFER_ON_ERROR_RESPONSE(0),
.Over_Constraints_Mode(0),
.DISABLE_CHKS_ON_IDLE(0) )
qvl_ahb_master_monitor_instance (
.hgrantx(dut_hgrantx),
.hready(dut_hready),
.hresp(dut_hresp),
.hresetn(dut_hresetn),
.hclk(dut_hclk),
.hrdata(dut_hrdata),
.htrans(dut_htrans),
.haddr(dut_haddr),
.hwrite(dut_hwrite),
.hsize(dut_hsize),
.hburst(dut_hburst),
.hprot(dut_hprot),
.hwdata(dut_hwdata)
);

Example 2-2. VHDL AHB Master Monitor Template


qvl_ahb_master_monitor_instance: qvl_ahb_master_monitor
generic map(
Constraints_Mode => 0,
DATA_BUS_WIDTH => 32,
CANCEL_FOLLOWING_TRANSFER_ON_ERROR_RESPONSE => 0,
Over_Constraints_Mode => 0,
DISABLE_CHKS_ON_IDLE => 0)
port map (
hgrantx => dut_hgrantx,
hready => dut_hready,
hresp => dut_hresp,
hresetn => dut_hresetn,
hclk => dut_hclk,
hrdata => dut_hrdata,
htrans => dut_htrans,
haddr => dut_haddr,
hwrite => dut_hwrite,
hsize => dut_hsize,
hburst => dut_hburst,
hprot => dut_hprot,
hwdata => dut_hwdata
);

Adding Monitors to the Simulation Environment


A QVL monitor instance can be added to the simulation environment using any of the following
processes:
Questa Verification Library Monitors Data Book, v2010.2

29

QVL Monitors Basics


QVL Use Model

Specify the QVL instance in the testbench or design under test (DUT). To make the
monitor visible only during simulation, use the following:
o

Verilog use an `ifdef.

VHDL use a conditional generate or an empty architecture.

Specify the QVL instance as a separate module, then use SVA bind to wire the monitor
signals to your DUT (see Example 2-3 on page 31 and SystemVerilog Bind on
page 32). SystemVerilog declares that by default, each file is a separate compilation
unit.
When bind is specified outside the module file that the program instance is being bound
to, the elaboration process does not recognize the dependency to the bound module and
the bind is not elaborated with the bound module. Therefore, you must use the -cuname
option to name the compilation unit. Then, specify the compilation unit name to vsim to
enable the bind statements to be elaborated, as shown in the following example:
vlog assertion_module.sv bind.v -cuname bind_cu
vsim top bind_cu

Specify the QVL instance in a PSL vunit, and then bind the vunit to the target module to
connect the signals from the target module to the monitor instance. Refer to the Questa
SV/AFV Users Manual, Chapter 18: Verification with Assertions and Cover Directives
for detailed information. This manual is available on the Mentor Graphics SupportNet.

Specify the QVL instance in a separate module, and connect the DUT to the instances
ports using one of the following methods:
o

Verilog hierarchical reference in wire declaration example:


wire
wire
wire
wire [2:0]

clk
reset_n
wr_en
max

=
=
=
=

TB.DUT.clk;
TB.DUT.reset_n;
TB_DUT.wr_en;
TB.DUT.wr_hold_max;

VHDL signal spy example:


init_signal_driver
init_signal_driver
init_signal_driver
init_signal_driver

("/TB/DUT/clk", "/clk", open, open, 0);


("/TB/DUT/reset_n", "/reset_n", open, open, 0);
("/TB/DUT/wr_en", "/wr_en", open, open, 0);
("/TB/DUT/wr_hold_max", "/max", open, open, 0);

Whenever a signal spy command is used, the ModelSim library and package must be
specified as follows:
library modelsim_lib;
use modelsim_lib.util.all;

30

Questa Verification Library Monitors Data Book, v2010.2

QVL Monitors Basics


QVL Use Model

Specify the instance as a SystemVerilog interface.

Set the +define+QVL_SVA_INTERFACE macro in the filelist.qvl file list or on the


simulator command line. For example:
vlog +define+QVL_SVA_INTERFACE...

This replaces the instances module keyword with the interface keyword.

Add the QVL instance to a ANSI port declaration. and use hierarchical port
references to wire the port signals to your DUT. For example:
module cpu_top (
qvl_pci_monitor pci_mon_if,
. . .
assign pci_mon_if.pci_ad_en_n
assign pci_mon_if.pci_cbe_en_n

= AD_enb;
= 1'b0;

Note that whenever a QVL monitor is instantiated in a VHDL design, the QVL library and the
QVL packages must be specified as follows:
library qvl_lib;
use qvl_lib.qvl_chechers.all;
use qvl_lib.qvl_monitors.all;

Exclude the QVL components from code coverage by adding source code pragmas (coverage
off/coverage on) around the QVL component instantiations as described in the Questa SV/AFV
Users Manual, chapter 16: Coverage.
Example 2-3. Binding an Assertion Module to the DUT in SVA
module assertion_module (clk, reset_n, wr_en, wr_hold_max);
input
clk;
input
reset_n;
input
wr_en;
input [2:0] wr_hold_max;
wire
qvl_clk
= clk;
wire
qvl_reset_n
= reset_n;
wire
qvl_wr_en
= wr_en;
wire [2:0] qvl_max
= wr_hold_max;
// include define file to allow use of QVL defines
include "std_qvl_defines.h"
qvl_change_timer #(
.severity_level(QVL_ERROR),
.property_type(QVL_ASSERT),
.msg("QVL_VIOLATION : "),
.coverage_level(QVL_COVER_ALL),
.width(1),
.min_check(1),
.max_check(1))
qvl_change_timer_instance(

Questa Verification Library Monitors Data Book, v2010.2

31

QVL Monitors Basics


QVL Use Model
.clk(qvl_clk),
.reset_n(qvl_reset_n),
.active(1b1),
.test_expr(qvl_wr_en),
.max(qvl_max),
.min(1));
endmodule
// Bind assertion_module to DUT with implicit port connections (.* syntax)
module sample_bind;
bind DUT assertion_module bind_instance (.*);
endmodule

SystemVerilog Bind
Many users prefer to instantiate assertions without modifying their RTL. A common way to
define or instantiate assertions into a separate module is to define your assertions in a separate
assertion module and use SystemVerilog bind to wire the assertion (monitor) signals to your
design module:
1. Create a separate assertion module.
2. Instantiate assertions in assertion module.
Note: When using a signal or port from the targeted design module, the signal and port
names must be added to the assertion module port list. Use the same signal and port
name as the design module, so implicit port instantiation can be used with the
SystemVerilog bind.
3. Create the SystemVerilog bind instance to connect the assertion module to the target
module.

Compile QVL Monitor Libraries


VHDL simulation environments require a compiled version of the QVL checker/monitor
library. This step is optional for Verilog simulation environments. To compile a version of the
QVL library, modify and run the standard compile_qvl_lib C-shell script:
questasim_dir/qvl_src/bin/compile_qvl_lib
#!/bin/csh
# Compile QVL packages into qvl_lib
vlib qvl_lib
vcom -work qvl_lib questasim_dir/qvl_src/vhdl_pkgs/qvl_checkers.vhd
questasim_dir/qvl_src/vhdl_pkgs/qvl_monitors.vhd
# Compile Verilog QVL Checker components into qvl_lib
vlog -work qvl_lib +define+QVL_ASSERT_ON+QVL_COVER_ON
+incdir+questasim_dir/qvl_src/qvl_checkers
questasim_dir/qvl_src/qvl_checkers/*.sv
# Compile Verilog QVL Monitor components into qvl_lib

32

Questa Verification Library Monitors Data Book, v2010.2

QVL Monitors Basics


QVL Use Model
foreach mon ( questasim_dir/qvl_src/qvl_monitors/* )
vlog -work qvl_lib +define+QVL_ASSERT_ON+QVL_COVER_ON
+incdir+questasim_dir/qvl_src/qvl_checkers
questasim_dir/qvl_src/qvl_checkers/std_qvl_defines.h +incdir+$mon
$mon/*.sv
end

To compile a protected (read-only) QVL library to be shared by your project team, add the
-novopt option to the vlog and vcom commands. Users can then compile simulation
environments both with, and without, vopt. Typically, questasim_dir is the same as the install
directory of the Questa executables. However, it can be the install directory of a later Questa
release (for example, if you are frozen into a particular Questa release, but want to use
features/enhancements of the later QVL release).
Caution
Starting with QVL 2009.1, QVL was decoupled from Questa releases. From this release
onward, QVL directs vlog to print the QVL version. However, when using QVL with
vlog version 6.5c (or earlier), you must specify +define+QVL_VERSION_PRINT_OFF
as a vlog argument to prevent a vlog error.

Compile and Simulate the DUT with the QVL Monitor


VHDL
Compile your simulation environment, as you would normally, using the QuestaSim vcom and
vlog commands. Then add references to the QVL library to your simulation arguments. For
example,
vsim <simulation_arguments> L qvl_lib

Run your vsim simulation command and the monitor is run in simulation in a similar way to
other SVA assertions.

Verilog
Add the QVL Verilog arguments to your Verilog compilation arguments. Example 2-4 shows a
sample simulator argument file that references the QVL checkers and the AMBA monitor. The
checkers are located in a single directory (qvl_src/qvl_checkers), but each monitor directory
must be specified separately (for example, qvl_src/qvl_monitors/amba,
qvl_src/qvl_monitors/axi, etc.). For example,
vlog <compile_arguments> -f filelist.qvl

In the QVL Monitors sections of the arguments filelist (see Example 2-4), update the -y and
+incdir options to refer to the appropriate monitor directories. By default, all QVL checkers are
specified through the -y option.

Questa Verification Library Monitors Data Book, v2010.2

33

QVL Monitors Basics


QVL Use Model

Once the design and testbench are compiled, your vsim simulation command needs no
modifications. Run your vsim simulation command and the QVL components run in simulation
similar to other SVA assertions.
Example 2-4. Verilog Simulator Argument Sample File
// Command line switches
// `DEFINES
+define+QVL_ASSERT_ON
+define+QVL_COVER_ON
//+define+QVL_SV_COVERGROUP_OFF
//+define+QVL_CW_FINAL_COVER
//+define+QVL_MW_FINAL_COVER_OFF

//
//
//
//
//

// File extensions
+libext+.v
+libext+.sv

// Verilog wrapper files


// SystemVerilog wrapper files

Turn on QVL assertions


Turn on QVL coverage
Turn off SV cover groups
Display final checker cover info
Dont display final monitor cover info

// Include directories
// -- QVL checkers
+incdir+<questasim_install_dir>/qvl_src/qvl_checkers
// -- QVL monitors
+incdir+<questasim_install_dir>/qvl_src/qvl_monitors/amba
//
//
-y
//
-y

Library directories
-- QVL checkers
<questasim_install_dir>/qvl_src/qvl_checkers
-- QVL monitors
<questasim_install_dir>/qvl_src/qvl_monitors/amba

Verify and Troubleshoot the QVL Monitor Setup


The easiest way to check that you have correctly setup the QVL monitor in simulation is to
verify that the monitor is recognizing transactions on the protocol interface. The monitor
transactions are tracked in SystemVerilog covergroups and can be reviewed from the coverage
report (see Generate a Coverage Report on page 37).
If the monitor is not recognizing protocol transactions, then troubleshoot the setup are as
follows:
1. Check that the connections to the monitor as well as the monitor generics or parameters
are specified correctly. Check that the two monitor resets (asynchronous and
synchronous) are connected with the correct polarity. Typically, the designs reset signal
is connected to one reset and the other reset is tied to an inactive value.
2. View the resets and clocks in the simulation waveform for the monitor instance. Check
that the reset polarity is correct and the resets are de-asserting properly. Also, check that
the clock is toggling.

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QVL Use Model

3. View all connections to the monitor in the simulation waveforms for the monitor
instance. Check that the monitor signals are not unknown.
4. Recheck the monitor coverage. Verify that the protocol transactions exercised in
simulation are consistent with the transactions recorded by the monitor.
If you are still having setup problems, please send the following to support@mentor.com:

For Verilog designs, the QVL argument list.

QVL monitor instantiation, including generics or parameters.

QuestaSim compilation and simulation log files.

Waveforms that trace the monitor instance with debug access enabled. Use the
+acc vopt argument to enable debug command access to monitor objects (see View
and Debug QVL Monitor Protocol Violations on page 35).

Review and Debug Simulation QVL Monitor Results


Note that the assertion and coverage information is saved to the Unified Coverage Database
(UCDB) and is not saved to the wlf file.

QVL Monitor Protocol Violations Reporting


During simulation, the monitor protocol violations are written to the simulation log file. The
violation messages detail the time, instance, and violation description. Violation messages are
not generated for SVA assume properties that are constraints for formal verification.

View and Debug QVL Monitor Protocol Violations


From the QuestaSim viewer, the monitor protocol violations identified by the QVL monitor can
be reviewed by checking the Assertions tab in the Analysis window. This tab can be invoked
by selecting View > Coverage > Assertions. The enabled value in the Failure column
indicates that the failures are being tracked. The number of protocol violations can be viewed in
the Failure Count column.
To view the waveforms associated with a specific protocol violation, right-click on the
violation in the Assertions tab and select Add to Wave > Selected Objects.
Additionally, find the instance name of the violation in the Assertion tab and select the same
instance in the Workspace window. Right-click in the Objects window and select
Add to Wave > Signals in Region.
In order to view internal signals for the monitor, QuestaSim (vopt) global optimizations should
be disabled. The QuestaSim optimizations should be disabled during vopt using the +acc
option or during vsim using the +acc or -novopt options.

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QVL Use Model

Note that in order to run vsim with the -novopt option and with precompiled libraries, the
libraries must have been compiled with the -novopt option or a user must have write privileges
to the compiled libraries. If the library was not compiled with the -novopt option and the user
does not have write privileges to the compiled libraries, then vsim generates the vcom-19
(Failed to access library) error.
Following is an example for disabling QuestaSim optimizations during vopt for all instances of
a QVL monitor:
vopt +acc+qvl_amba_axi_monitor ...

Following is an example for disabling QuestaSim optimizations during vsim for all instances of
a QVL monitor:
vsim -voptargs="+acc+qvl_amba_axi_monitor" ...

Following is an example for disabling QuestaSim optimizations for the entire simulation
environment (note that it is not recommended to disable all optimizations):
vsim -novopt ...

Disable QVL Monitor Violations


The QVL monitors use SVA properties, so disabling violations is consistent with how
QuestaSim handles SVA properties.
From the QuestaSim command line, disable specific monitor violations using the
assertion fail command as follows (see the Questa AFV Users Manual):
assertion fail [-action {continue | break | exit}] [-enable | -disable]
[-limit {none |<count>}] [-log {on | off}] [-recursive] <path> [<path>...]

For example, if you receive the following error:


# ** Error: Assertion error.
#
Time: 140 ns Started: 140 ns Scope:
ahb_tb.ahb_master_mon.qvl_ahb_master.qvl_assume_ASSERT_NEVER.M_AHB_M17
File: /questasim/qvl_src/qvl_monitors/amba/qvl_ahb_master_monitor_assertions.inc
Line: 365

You can disable this error with the following command:


assertion fail -disable \
/ahb_tb/ahb_master_mon/qvl_ahb_master/qvl_assume_ASSERT_NEVER/M_AHB_M17 -r

QVL Monitor Coverage


The assertion and coverage information is saved to the UCDB and is not saved to the wlf file.

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QVL Use Model

Generate a Coverage Report


When running the QVL monitors in simulation, a text report of the assertion coverage results
can be generated. Use the vsim command coverage report to generate a text report of the
SystemVerilog and PSL assertion coverage. For example,
coverage report -details -file -coverage.rpt -r /*

For Verilog designs using $finish, the simulation might exit before the coverage report
command executes. Add vsim commands that prevent simulation exit and resume vsim
command execution. For example,
set NoQuitOnFinish 1;
onbreak {resume};
run -all;
coverage report -details -file -coverage.rpt -r /*

Refer to the Questa SV/AFV Reference Manual for information on the coverage command.

Save Coverage Results to a Database


Once the simulation has been run, the assertions and coverage results can also be viewed in the
QuestaSim viewer or saved to a Unified Coverage Database (UCDB) for later viewing. For
example,
coverage save coverage.ucdb

View a Coverage Database


Once the coverage information has been saved to a UCDB file, this file can be viewed by the
QuestaSim viewer. For example,
vsim -viewcov coverage.ucdb

View the Monitor Coverage and Statistics


From the QuestaSim viewer, coverage and statistics information specific to the QVL monitor
can be viewed by selecting the monitor instance in the Workspace window, then select
View > Coverage > Covergroups.

Disabling QVL Cover Points


The QVL checkers and monitors use SVA cover points to track coverage, so the mechanism for
controlling coverage collection is consistent with all SVA cover points in Questa. To turn off
specific cover points for a QVL checker, set their weights and goals to 0. For example, suppose
tb/dut contains the following qvl_fifo instantiation:
qvl_fifo #(
.severity_level(QVL_ERROR),

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QVL Monitors Basics


QVL Use Model
.property_type(QVL_ASSERT),
.msg("QVL_VIOLATION : "),
.coverage_level(QVL_COVER_NONE),
.depth(2**DEPTH_POWER),
.width(WIDTH),
.pass(1),
.registered(1),
.high_water(15),
.full_check(1),
.empty_check(1),
.value_check(1),
.latency(0),
.preload_count(0))
fifo_valid(
.clk(CLK),
.reset_n(reset_n),
.active(1b1),
.enq(DIN_VALID),
.deq(rd_en_i),
.full(full_i),
.empty(empty_i),
.enq_data(din_un_i),
.deq_data(dout_un_i),
.preload(24b0));

The cover groups for the qvl_fifo checker type are defined in the following file:
questasim_dir/qvl_src/qvl_checkers/qvl_fifo_cover.svh

This file shows the Simultaneous Enqueues and Dequeues cover point is defined in the
fifo_cornercases cover group and has the name C3:
covergroup fifo_cornercases @ (posedge clock);
. . .
C3 : coverpoint
(!($stable(simultaneous_enq_deq, @ (posedge clock))))
iff (enable_coverpoint){
bins Simultaneous_Enqueues_and_Dequeues = {1};
type_option.comment = "Simultaneous Enqueues and Dequeues";
}
endgroup : fifo_cornercases

For this example, assume the logic driving the FIFO cannot produce a simultaneous
enqueue/dequeue. So, the fifo_cornercases.C3 cover point for fifo_valid always has coverage
0% and the maximum possible coverage for the fifo_cornercases cover group is 75% (i.e., at
most 3 out of 4 cover points can be hit).
The following code in tb disables the Simultaneous Enqueues and Dequeues cover point
(qvl_fifo_chx is the instance in the qvl_fifo module used to configure an internal version of the
checker):
initial begin
dut.fifo_valid.qvl_fifo_chx.fifo_cornercases.C3.type_option.goal = 0;
dut.fifo_valid.qvl_fifo_chx.fifo_cornercases.C3.type_option.weight = 0;

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Connectivity on the Bi-Directional/Tri-State Buffer Signals
end

Setting the cover point weight to 0 removes the cover point from the calculation of the coverage
for the parent cover group, so fifo_cornercases can attain 100% coverage. Setting the cover
point goal to 0 makes the % of goal measure for the cover point 100% (instead of 0%).
You should not disable all the cover points for a particular cover group. In this case, the weights
of all the cover groups cover points are 0. The calculation for cover group coverage divides by
the total weight of the cover points (in this case 0), which results in a NaN value for the
coverage.

Run Formal Verification with QVL


The QVL monitors are used as assumptions and assertion targets in formal verification (see the
0-In Formal Verification User Guide). The 0-In formal tool supports the inline specification,
SVA bind and PSL vunit methods of QVL monitor instantiation specified in Instantiate QVL
Monitors on page 28 (that is, it does not support hierarchical references and VHDL signal spy
connections).
QVL components are precompiled in the 0-In formal verification tool installation, so the user
does not need to compile the QVL libraries. To compile a DUT with QVL components, add the
-qvl option to the csl command line.
The following example compiles a SystemVerilog bind module with the DUT using single-step
compilation:
0in -cmd csl -d DUT DUT.v assertion_module.v bind.sv . . .

The following example compiles a SystemVerilog bind module with the DUT using 2-step
compilation:
0in -cmd analyze -vhdl DUT.vhdl -work work
0in -cmd analyze \
assertion_module.v bind.sv -cuname bind_cu -work work -qvl
0in -cmd csl -d DUT -cuname bind_cu -work work -qvl

Connectivity on the Bi-Directional/Tri-State


Buffer Signals
RTL designed for a shared BUS environment such as PCI, or for the point-to-point interfaces
such as DDR SDRAM and DDR2 SDRAM, there are many bi-directional signals on the
interface.
For such bi-directional signals, the RTL has three split signals with the following names:

<sig_name>_out/<sig_name>_out_n

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Connectivity on the Bi-Directional/Tri-State Buffer Signals

<sig_name>_out_en/<sig_name>_out_en_n

<sig_name>_in/<sig_name>_in_n

These signals are connected to the tri-state I/O structure on the final chip. To connect to the such
interfaces, the QVL monitors are also designed with split signals (see Figure 2-1 on page 40).
Following is the typical structure and the naming convention:

<sig_name>_out Output signals from the RTL, Active High.

<sig_name>_out_n Output signal from the RTL, Active Low.

<sig_name>_in Input signal to RTL, Active High.

<sig_name>_in_n Input signal to the RTL, Active Low.

<sig_name>_out_en Output enable; output signal from the RTL, Active High.

<sig_name>_out_en_n Output enable; output signal from the RTL, Active Low.

<sig_name> Shared bus signal.


Figure 2-1. RTL Signals and Tri-State Buffer (I/O Structure)

Monitor

<sig_name>_out

<sig_name>_out_en

<sig_name>_in

Tri-State Buffer

<sig_name>_out

<sig_name>

RTL
<sig_name>_out_en

<sig_name>_in

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Chapter 3
Advanced Microcontroller Bus Architecture
(AMBA)
Introduction
The Advanced Microcontroller Bus Architecture (AMBA), from ARM Limited, is an on-chip
communications standard for designing high-performance embedded microcontrollers. There
are three distinct buses defined within the AMBA specification: Advanced High-performance
Bus, Advanced System Bus, and Advanced Peripheral Bus.
QVL monitors are available for the following:

Advanced High-performance Bus (AHB)

Advanced Peripheral Bus (APB)

Note the following:

AHB monitors are compatible with AHB-Lite, and they also can be used in multilayer
interconnection schemes.

The AHB monitor(s) cannot be used with the ASB.

Reference Documentation
This version of the QVL AMBA monitor is modeled from the requirements provided in the
following documents:

AMBA Specification, Rev 2.0, May 13, 1999, Issue A, ARM IHI0011A.

AMBA FAQ, January 23, 2001.

AHB Monitors
The Advanced High-performance bus (AHB) protocol defines communication between master
and target devices. A typical AHB system design contains the following components: master,
target, arbiter, and decoder. QVL monitors are available for the AHB master and AHB target
components.
Examples of AHB masters are: high-performance ARM processors, DMA bus masters, and so
on. Examples of AHB targets are: high-bandwidth memory interfaces, high-bandwidth on-chip

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Advanced Microcontroller Bus Architecture (AMBA)


APB Monitor

RAMs, and so on. The APB bridge is also a target on the AHB bus. Figure 3-1 illustrates a
block diagram of an AHB-based system.
Figure 3-1. AHB-Based System Implementation
AHB Master

AHB Target
AHB
Bridge

AHB Bus

AHB Target

AHB Master

APB Monitor
AMBA Advanced Peripheral Bus (APB) is for low power peripherals. AMBA APB is
optimized for minimal power consumption and reduced interface complexity to support
peripheral functions. APB can be used in conjunction with the AHB system bus. The devices on
the APB bus are lower bandwidth peripheral devices such as UARTs, Timers, parallel I/O ports,
etc. Figure 3-2 illustrates a block diagram of an AHB-based system.
Figure 3-2. APB-Based System Implementation
Device 2

Device 1

Bridge

APB Bus

AHB Bus
Device 3
The APB monitor can be instantiated in the
bridge to specify targets and constraints while
searching the bridge. The AHB interface must
be constrained to do this search.

Device 4
The APB monitor can be instantiated in
the peripheral devices to run formal
analysis on these designs.

AHB Master Monitor


The Advanced High-performance bus (AHB) protocol defines communication between master
and target devices.

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AHB Master Monitor

Monitor Placement and Instantiation


The user can place AHB master monitors inside the AHB master devices to provide interface
checks. Also, the user can use the AHB master monitors checks as search targets and check
constraints for running formal analysis on the AHB master device.

Monitor Connectivity
Connect the AHB master monitor pins to internal signals as specified in the pin-out Table 3-1
and illustrated in Figure 3-3. Note that hbusreqx and hlockx are not part of the AHB master
monitor because these signals are not used by the monitor.
Figure 3-3. AHB Master Monitor Pins Diagram
hresetn
hclk
haddr[31:0]
hwrite
htrans[1:0]
hsize[2:0]
hburst[2:0]
hwdata[DATA_BUS_WIDTH 1:0]
hrdata[DATA_BUS_WIDTH 1:0]
hready
hresp[1:0]
hprot[3:0]
hgrantx

AMBA
AHB Master
Monitor

Table 3-1. AHB Master Monitor Pins


Pin

Description

haddr[31:0]

32-bit system address bus.

hburst[2:0]

Encoding that indicates if the transfer is a part of a burst and if


so, the type of burst.

hclk

Clock. Times all bus transfers on the rising edge.

hgrantx

Indicates whether the monitored device is currently the highest


priority master.

hprot[3:0]

Encoding for protocol control information about the current


transfer.

hrdata[DATA_BUS_WIDTH 1:0]

Read data bus. Transfers data from target to master via a read
operation.

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AHB Master Monitor

Table 3-1. AHB Master Monitor Pins (cont.)


Pin

Description

hready

Indicates whether the currently selected target device is ready to


perform the current transfer.

hresetn

Active low bus reset signal. Resets the system and the bus.

hresp[1:0]

Encoding for the response from the target indicating the status
of the current transfer.

hsize[2:0]

Encoding for the size of the transfer.

htrans[1:0]

Encoding for the type of the current transfer.

hwdata[DATA_BUS_WIDTH 1:0]

Write data bus. Transfers data from master to target via a write
operation.

hwrite

Encoding for the type of transfer: HIGH for write transfers and
LOW for read transfers.

Monitor Parameters
The parameters shown in Table 3-2 configure the corresponding AHB master monitor.
Table 3-2. AMBA AHB Master Monitor Parameters
Order Parameter

Default Description

1.

Constraints_Mode

Set to 1 if the checks in the monitor are to be used as


constraints for formal analysis.

2.

DATA_BUS_WIDTH

32

Width of AHB data bus. The protocol allows widths of: 8,


16, 32, 64, 128, 256, 512, and 1024 bits.

3.

CANCEL_FOLLOWING_
TRANSFER_ON_ERROR_
RESPONSE

Indicates how AHB masters handle ERROR responses:


1 - On an ERROR response, the master cancels the
following transfer (and immediately performs an
IDLE transfer).
0 - Otherwise.

4.

Over_Constraints_Mode 0

5.

DISABLE_CHKS_ON_IDLE

Set to 1 if additional constraints are needed for formal


analysis. See note below.
AHB_M3, AHB_M4, and AHB_M6_control checks are
also performed on IDLE transfers by default. To disable
these checks on IDLE transfer, set this parameter to 1.

The parameters must be specified in the above order.

Note:
For the Over_Constraints_Mode set to 1, the AMBA AHB master monitor has the following
additional constraints:

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AHB Master Monitor

AHB_NO_ERROR_RESPONSE Formal verification must not introduce error


responses.

AHB_NO_RETRY_RESPONSE Formal verification must not introduce retry


responses.

AHB_NO_SPLIT_RESPONSE Formal verification must not introduce split


responses.

AHB_NO_TWO_CYCLE_RESPONSE Formal verification must not introduce two


cycle responses.

AHB_NO_WAIT_STATES Formal verification must not introduce wait states.

For additional information on Over_Constraints_Mode, see AHB Master Monitor FAQ on


page 51.

AHB Master Monitor Instantiation Example


Example 3-1 instantiates an AHB master monitor with the default parameters
(DATA_BUS_WIDTH set to 32 and CANCEL_FOLLOWING_TRANSFER_ON_ERROR_RESPONSE set to 0).
Example 3-1. AHB Master Monitor Instantiation
qvl_ahb_master_monitor mas_mon (
.hgrantx
(hgrntx),
.hready
(hrdy),
.hresp
(hrsp),
.hresetn
(hrstn),
.hclk
(hclk),
.hrdata
(hrdt),
.htrans
(htrns),
.haddr
(hddr),
.hwrite
(hwrt),
.hsize
(hsz),
.hburst
(hbrst),
.hprot
(hprt),
.hwdata
(hwdt) );

Note that if using the AHB master monitor with an AHB-Lite master, then the user is required
to tie the hgrantx signal to high (1'b1) and the hresp[1] signal to low (1'b0).

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Monitor Checks

Monitor Checks
Table 3-3 shows the checks performed by an AHB master monitor.
Table 3-3. AMBA AHB Master Checks

46

Check ID

Violation

Description

AHB_M1

A BUSY transfer type was issued when


there was no burst in progress.

The first transfer of a burst or single transfer


must be a NONSEQUENTIAL transfer.

AHB_M2

The first transfer of a burst or a single


transfer cannot have a transfer type of
SEQUENTIAL.

The first transfer of a burst or single transfer


must be a NONSEQUENTIAL transfer.

AHB_M3

The master must never attempt a


transfer where the width (as encoded
by hsize) is wider than the data bus to
which it is connected.

The encoded width of the data being


transferred is larger than the width of the
physical data bus. Although a bus master can
be modified to operate on a bus that is wider
than originally intended, it cannot operate on a
narrower bus.

AHB_M4

All transfers must be aligned to the


address boundary equal to the size of
the transfer.

The transfer must be aligned to the address


boundary equal to the size of the transfer. For
example, word transfers must be aligned to
word address boundaries (i.e., A[1:0] = 00),
halfword transfers must be aligned to halfword
address boundaries (i.e., A[0] = 0).

AHB_M5

The master was granted the bus, but it


did not perform any data transfer
including IDLE. When a master is
granted the bus and it does not wish to
perform any data transfer, then it must
issue an IDLE transfer.

IDLE transfer indicates no data transfer is


required. It is used when a bus master is
granted the bus, but does not wish to perform a
transfer.

AHB_M6_address

The master did not hold the address


(haddr) stable when the target was
inserting wait states.

The bus master holds the address stable


throughout extended cycles.

AHB_M6_control

The master did not hold the control


(htrans, hwrite, hsize, hburst, and
hprot) stable when the target was
inserting wait states.

The bus master holds the control information


stable throughout extended cycles.

AHB_M7

The control information (hwrite, hsize,


hburst, and hprot) of the current
transfer was not identical to the control
information of the previous transfer.

The control information for a BUSY or


SEQUENTIAL transfer is identical to the
control information of the previous transfer.

AHB_M8

The master used a BUSY transfer type.


The address did not reflect the next
transfer in the burst.

The BUSY transfer type indicates that the


master is continuing with a burst of transfers,
but the next transfer cannot take place
immediately. When a master uses the BUSY
transfer type, the address must reflect the next
transfer in the burst.

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Advanced Microcontroller Bus Architecture (AMBA)


Monitor Checks

Table 3-3. AMBA AHB Master Checks (cont.)


Check ID

Violation

Description

AHB_M9

The address of the current transfer with


a transfer type of SEQUENTIAL was
not related to the address of the
previous transfer.

The address in a SEQUENTIAL transfer is


related to the address of the previous transfer.
The address is equal to the address of the
previous transfer plus the size (in bytes). In the
case of a wrapping burst, the address of the
transfer wraps at the address boundary equal
to the size (in bytes) multiplied by the number
of beats in the transfer.

AHB_M10

The address of the current transfer was


not equal to the address of the previous
transfer. The address must be the same
on consecutive BUSY(s) or on a
BUSY-SEQ.

The address must be the same on consecutive


BUSY(s) or on a BUSY-SEQ.

AHB_M11

The master did not perform an IDLE


transfer immediately after receiving an
ERROR response.

ERROR response requires at least two cycles.


The two-cycle response is required because of
the pipelined nature of the bus. By the time a
target starts to issue an ERROR response, the
address of the following transfer has already
been broadcast onto the bus. The two-cycle
response allows sufficient time for the master
to cancel this address and drive HTRANS[1:0]
to IDLE before the start of the next transfer.
This check is active and applicable only when
the CANCEL_FOLLOWING_TRANSFER_
ON_ERROR_RESPONSE parameter is set to
1.

AHB_M12

The master did not perform an IDLE


transfer immediately after receiving a
RETRY response.

RETRY response requires at least two cycles.


The two-cycle response is required because of
the pipelined nature of the bus. By the time a
target starts to issue a RETRY response, the
address of the following transfer has already
been broadcast onto the bus. The two-cycle
response allows sufficient time for the master
to cancel this address and drive HTRANS[1:0]
to IDLE before the start of the next transfer.
The protocol requires that a master performs
an IDLE transfer immediately after receiving a
RETRY response.

AHB_M13

The master did not perform an IDLE


transfer immediately after receiving a
SPLIT response.

SPLIT response requires at least two cycles.


The two-cycle response is required because of
the pipelined nature of the bus. By the time a
target starts to issue a SPLIT response, the
address of the following transfer has already
been broadcast onto the bus. The two-cycle
response allows sufficient time for the master
to cancel this address and drive HTRANS[1:0]
to IDLE before the start of the next transfer.
The protocol requires that a master performs
an IDLE transfer immediately after receiving a
SPLIT response.

AHB_M14

The master continued to retry the


transfer that is responded with an
ERROR response. For the ERROR
response, the current transfer is not
repeated.

For an ERROR response, the current transfer


is not repeated. To determine if a master is
repeating a transfer, address (haddr) and
htrans are considered.

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Advanced Microcontroller Bus Architecture (AMBA)


Monitor Checks

Table 3-3. AMBA AHB Master Checks (cont.)

48

Check ID

Violation

Description

AHB_M15

The bus master did not continue to


retry the transfer that was responded
with a RETRY response.

The RETRY response shows the transfer has


not yet completed; therefore, the bus master
should retry the transfer. The master should
continue to retry the transfer until it completes
successfully or terminates with an ERROR
response.
Note that address (haddr) is the only factor
taken into consideration in determining if the
master is continuing to retry a transfer.

AHB_M16

The bus master did not continue to


retry the transfer that was responded
with a SPLIT response.

The SPLIT response shows the transfer has


not yet completed; therefore, the bus master
should retry the transfer when it is next
granted access to the bus. The master should
continue to retry the transfer until it completes
successfully or terminates with an ERROR
response.
Note that address (haddr) is the only factor
taken into consideration in determining if the
master is continuing to retry a transfer.

AHB_M17

Target did not provide a zero wait state


OKAY response to IDLE transfer.

IDLE transfer indicates that no data transfer is


required. It is used when a bus master is
granted the bus, but does not wish to perform a
data transfer. Targets must always provide a
zero wait state OKAY response to IDLE
transfers and the transfer should be ignored by
the target.

AHB_M18

Target did not provide a zero wait state


OKAY response to BUSY transfer.

BUSY transfer allows a bus master to insert


idle cycles in the middle of bursts of transfers.
This transfer should be ignored by the target
and must always provide a zero wait state
OKAY response.

AHB_M19

Target did not drive the response to


OKAY while inserting wait states prior
to deciding its response.

If the target needs more than two cycles to


provide the ERROR, SPLIT, or RETRY
response, then additional wait states may be
inserted at the start of the transfer. During this
time, the HREADY signal is LOW and the
response must be set to OKAY.

AHB_M20

Target violated the two cycle


requirement on the ERROR response.

The ERROR response requires at least two


cycles. To complete with this response, in the
penultimate (one before last) cycle, the target
drives HRESP[1:0] to indicate ERROR while
driving HREADY LOW to extend the transfer
for an extra cycle. In the final cycle,
HREADY is driven HIGH to end the transfer,
while HRESP[1:0] remains driven to indicate
ERROR.

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Advanced Microcontroller Bus Architecture (AMBA)


Monitor Checks

Table 3-3. AMBA AHB Master Checks (cont.)


Check ID

Violation

Description

AHB_M21

Target violated the two cycle


requirement on RETRY response.

The RETRY response requires at least two


cycles. To complete with this response, in the
penultimate (one before last) cycle, the target
drives HRESP[1:0] to indicate RETRY while
driving HREADY LOW to extend the transfer
for an extra cycle. In the final cycle,
HREADY is driven HIGH to end the transfer,
while HRESP[1:0] remains driven to indicate
RETRY.

AHB_M22

Target violated the two cycle


requirement on SPLIT response.

The SPLIT response requires at least two


cycles. To complete with this response, in the
penultimate (one before last) cycle, the target
drives HRESP[1:0] to indicate SPLIT while
driving HREADY LOW to extend the transfer
for an extra cycle. In the final cycle,
HREADY is driven HIGH to end the transfer,
while HRESP[1:0] remains driven to indicate
SPLIT.

AHB_M23

Width of the data bus must be either 8,


16, 32, 64, 128, 256, 512, or 1024.

The AHB standard requires that the width of


the data bus must be either 8, 16, 32, 64, 128,
256, 512, or 1024.

AHB_M24_hgrantx,
AHB_M24_hready,
AHB_M24_hresp,
AHB_M24_htrans,
AHB_M24_hwrite,
AHB_M24_hsize,
AHB_M24_hburst,
AHB_M24_hprot

Control signal should not be X or Z.

Control signals should not have a X or Z


value.

AHB_M25_haddr

Address signal should not be X or Z.

Address signal should not have a X or Z value.

AHB_M26

The address for any burst must not


cross a 1 KB boundary.

Burst must not cross a 1 KB address boundary.


Therefore, it is important that masters do not
attempt to start a fixed-length incrementing
burst that would cause this boundary to be
crossed.

AHB_M27

The master must drive either IDLE or


NONSEQUENTIAL on HTRANS
when it is not granted the bus.

When a master is not granted the bus, it is not


performing any transfer. However, it cannot
signal SEQ or BUSY as those transfers are
only valid during bursts. Therefore, it must
drive either IDLE or NONSEQUENTIAL
when not granted the bus.

AHB_MX

The ahb master monitor should not be


in an unknown state.

If any of the checks AHB_M1 through


AHB_M22 is fired, then the ahb master
monitor goes into an unknown state. It comes
back into a known state when it detects a low
on the hgrantx.

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49

Advanced Microcontroller Bus Architecture (AMBA)


Monitor Corner Cases

Monitor Corner Cases


Table 3-4 shows the corner cases maintained by the AHB master monitor.
Table 3-4. AMBA AHB Master Monitor Corner Cases

50

Corner Case

Description

Read Transfers

Number of read transfer operations.

Write Transfers

Number of write transfer operations.

IDLE Transfers

Number of IDLE transfers.

BUSY Transfers

Number of BUSY transfers.

OKAY Responses

Number of OKAY responses.

ERROR Responses

Number of ERROR responses.

RETRY Responses

Number of RETRY responses.

SPLIT Responses

Number of SPLIT responses.

SINGLE Burst Type

Number of SINGLE burst transfers.

INCR Burst Type

Number of INCR burst transfers.

WRAP4 Burst Type

Number of WRAP4 burst transfers.

INCR4 Burst Type

Number of INCR4 burst transfers.

WRAP8 Burst Type

Number of WRAP8 burst transfers.

INCR8 Burst Type

Number of INCR8 burst transfers.

WRAP16 Burst Type

Number of WRAP16 burst transfers.

INCR16 Burst Type

Number of INCR16 burst transfers.

Byte (8 Bits) Transfer Size

Number of 8-bit transfers.

Half Word (16 Bits) Transfer Size

Number of 16-bit transfers.

Word (32 Bits) Transfer Size

Number of 32-bit transfers.

Double Word (64 Bits) Transfer Size

Number of 64-bit transfers.

4-Word (128 Bits) Transfer Size

Number of 128-bit transfers.

8-Word (256 Bits) Transfer Size

Number of 256-bit transfers

512 Bits Transfer Size

Number of 512-bit transfers.

1024 Bits Transfer Size

Number of 1024-bit transfers.

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Advanced Microcontroller Bus Architecture (AMBA)


Monitor Statistics

Monitor Statistics
Table 3-5 shows the statistics maintained by the AHB master monitor.
Table 3-5. AMBA AHB Master Monitor Statistics
Statistic

Description

Total Transfers

Total number of transfer operations.

AHB Master Monitor FAQ


Following are answers to frequently asked questions (FAQ) about the AHB master monitor.
How do I use the Over_Constraints_Mode in formal verification?
The AHB monitor has an Over_Constraints_Mode parameter for use in formal
verification. The Over_Constraints_Mode parameter will add additional constraints
that can be used to prevent formal verification from introducing the behavior listed
below:

Using the Over_Constraints_Mode parameter in simulation will produce incorrect


AHB violations.

Note that the Over_Constraints_Mode parameter will prevent formal verification


from exercising the full set of legal AHB transactions.
In order to verify your design for all legal AHB transactions, formal verification should
also be run with the Over_Constraints_Mode parameter disabled (set to 0).
How do I use only a subset of the Over_Constraints_Mode constraints?
A subset of the Over_Constraints_Mode constraints can be used by disabling
unwanted constraints.
To remove unwanted constraints, add exclude_checker directives to a checker
control file or your monitor instantiation file as follows:
// Remove error response constraint
// 0in exclude_checker -name *AHB_NO_ERROR_RESPONSE

// Remove retry response constraint


// 0in exclude_checker -name *AHB_NO_RETRY_RESPONSE

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51

Advanced Microcontroller Bus Architecture (AMBA)


AHB Target Monitor

AHB Target Monitor


The Advanced High-performance bus (AHB) protocol defines communication between master
and target devices. A typical AHB system design contains the following components.

Monitor Placement and Instantiation


The user can place AHB target monitors inside the AHB target devices to provide interface
checks. Also, the AHB target monitors checks can be used as search targets and check
constraints for running formal analysis on the AHB target device.

Monitor Connectivity
Connect the AHB target monitor pins to internal signals as specified in the pin-out Table 3-6
and illustrated in Figure 3-4.
Note that the AHB target monitor does not support locked transfers.
Figure 3-4. AHB Target Monitor Pins Diagram
hresetn
hclk
hselx
haddr[31:0]
hwrite
htrans[1:0]
hsize[2:0]
hburst[2:0]
hwdata[DATA_BUS_WIDTH 1:0]
hrdata[DATA_BUS_WIDTH 1:0]
hready_in
hready_out
hresp[1:0]
hmaster[3:0]
hmastlock
hsplitx[NUMBER_OF_MASTERS 1:0]

AMBA
AHB Target
Monitor

Table 3-6. AHB Target Monitor Pins

52

Pin

Description

haddr[31:0]

32-bit system address bus.

hburst[2:0]

Encoding that indicates if the transfer is a part of a burst and


if so, the type of burst.

hclk

Clock. Times all bus transfers on the rising edge.

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Advanced Microcontroller Bus Architecture (AMBA)


AHB Target Monitor

Table 3-6. AHB Target Monitor Pins (cont.)


Pin

Description

hmaster[3:0]

Encoding that indicates the master that is currently accessing


the target device.

hmastlock

Indicates the current master is performing a locked transfer.

hrdata[DATA_BUS_WIDTH 1:0]

Read data bus. Transfers data from target to master via a read
operation.

hready_in

Indicates whether the currently selected target device is


ready to perform the current transfer (hready on the bus).

hready_out

Signal (hready) driven by the monitored target device.

hresetn

Active low bus reset signal. Resets the system and the bus.

hresp[1:0]

Encoding for the response from the target indicating the


status of the current transfer.

hselx

AHB target device select.

hsize[2:0]

Encoding for the size of the transfer.

hsplitx[NUMBER_OF_MASTERS 1:0]

Signal used by the target device to indicate to the arbiter


which bus masters can attempt a split transaction. Each bit
corresponds to a single bus master.

htrans[1:0]

Encoding for the type of the current transfer.

hwdata[DATA_BUS_WIDTH 1:0]

Write data bus. Transfers data from master to target via a


write operation.

hwrite

Encoding for the type of transfer: HIGH for write transfers


and LOW for read transfers.

Monitor Parameters
The parameters shown in Table 3-7 configure the corresponding AHB target monitor.
Table 3-7. AMBA AHB Target Monitor Parameters
Order Parameter

Default Description

1.

Constraints_Mode

Set to 1 if the checks in the monitor are to be used as


constraints for formal analysis.

2.

DATA_BUS_WIDTH

32

Width of AHB data bus. The protocol allows widths


of: 8, 16, 32, 64, 128, 256, 512, and 1024 bits.

3.

NUMBER_OF_MASTERS

16

Number of AHB bus masters in the system (used to


configure the HSPLIT bus width).

4.

CANCEL_FOLLOWING_
TRANSFER_ON_ERROR_
RESPONSE

Indicates how AHB masters handle ERROR


responses:
1- On an ERROR response, the master cancels the
following transfer (and immediately performs
an IDLE transfer).
0 - Otherwise.

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53

Advanced Microcontroller Bus Architecture (AMBA)


AHB Target Monitor

Table 3-7. AMBA AHB Target Monitor Parameters (cont.)


Order Parameter

Default Description

5.

Over_Constraints_Mode

Set to 1 if additional constraints are needed for formal


analysis. See note below.

6.

DISABLE_CHKS_ON_IDLE

AHB_T14, AHB_T15, and AHB_T17 checks are also


performed on IDLE transfers by default. To disable
these checks on IDLE transfer, set this parameter to 1.

The parameters must be specified in the above order.

Note:
For the Over_constraints_Mode set to 1, the AMBA AHB target monitor has the following
additional constraints:

AHB_NO_BURST Formal verification must not introduce burst transfers.

AHB_NO_WRAP Formal verification must not introduce wrap transfers.

AHB_NO_BUSY Formal verification must not introduce busy responses.

AHB_NO_EARLY_BURST_TERMINATION Formal verification must not


terminate burst transfers.

For additional information on Over_Constraints_Mode, see AHB Target Monitor FAQ on


page 61.

AHB Target Monitor Instantiation Example


Example 3-2 instantiates an AHB target monitor with the default data width (32) and the default
number of masters (16).
Example 3-2. AHB Target Monitor Instantiation
qvl_ahb_target_monitor tar_mon (
.hselx
(hslx),
.haddr
(hddr),
.hwrite
(hwrt),
.htrans
(htrns),
.hsize
(hsz),
.hburst
(hbrst),
.hwdata
(hwdt),
.hresetn
(hrstn),
.hclk
(hclk),
.hmaster
(hmstr),
.hmastlock (hmstlck),
.hready_in (hrdy_in),
.hready_out (hrdy_out),
.hresp
(hrsp),
.hrdata
(hrdt),
.hsplitx
(hspltx) );

54

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Advanced Microcontroller Bus Architecture (AMBA)


Monitor Checks

Note that if using the AHB target monitor with an AHB-Lite target, then the user must tie the
hresp[1] signal to low (1'b0).

Monitor Checks
Table 3-8 shows the checks performed by an AHB target monitor.
Table 3-8. AMBA AHB Target Checks
Check ID

Violation

Description

AHB_T1

Target did not provide a zero


wait state OKAY response to
IDLE transfer.

IDLE transfer indicates that no data transfer is


required. It is used when a bus master is granted
the bus, but does not wish to perform a data
transfer. Targets must always provide a zero wait
state OKAY response to IDLE transfers, and the
transfer should be ignored by the target.

AHB_T2

Target did not provide a zero


wait state OKAY response to
BUSY transfer.

BUSY transfer allows a bus master to insert idle


cycles in the middle of bursts of transfers. This
transfer should be ignored by the target, and must
always provide a zero wait state OKAY response.

AHB_T3

Target inserted more than 16


wait states. It is recommended
(but not mandatory) that
targets do not insert more than
16 wait states to prevent any
single access locking the bus
for a large number of clock
cycles.

The HREADY signal is used to extend the data


portion of an AHB transfer. When LOW, it
indicates the transfer is to be extended. When
HIGH it indicates that the transfer can complete.
Every target must have a predetermined maximum
number of wait states that it inserts before it backs
off the bus, in order to allow the calculation of the
latency of accessing the bus. It is recommended
(but not mandatory) that targets do not insert more
than 16 wait states to prevent any single access
locking the bus for a large number of clock cycles.

AHB_T4

Target did not drive the


response to OKAY while
inserting wait states prior to
deciding its response.

If the target needs more than two cycles to provide


the ERROR, SPLIT, or RETRY response, then
additional wait states may be inserted at the start of
the transfer. During this time, the HREADY signal
is LOW and the response must be set to OKAY.

AHB_T5

Target violated the two cycle


requirement on ERROR
response.

The ERROR response requires at least two cycles.


To complete with this response, in the penultimate
(one before last) cycle, the target drives
HRESP[1:0] to indicate ERROR while driving
HREADY LOW to extend the transfer for an extra
cycle. In the final cycle, HREADY is driven HIGH
to end the transfer, while HRESP[1:0] remains
driven to indicate ERROR.

AHB_T6

Target violated the two cycle


requirement on RETRY
response.

The RETRY response requires at least two cycles.


To complete with this response, in the penultimate
(one before last) cycle, the target drives
HRESP[1:0] to indicate RETRY while driving
HREADY LOW to extend the transfer for an extra
cycle. In the final cycle, HREADY is driven HIGH
to end the transfer, while HRESP[1:0] remains
driven to indicate RETRY.

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55

Advanced Microcontroller Bus Architecture (AMBA)


Monitor Checks

Table 3-8. AMBA AHB Target Checks (cont.)

56

Check ID

Violation

Description

AHB_T7

Target violated the two cycle


requirement on SPLIT
response.

The SPLIT response requires at least two cycles.


To complete with this response, in the penultimate
(one before last) cycle, the target drives
HRESP[1:0] to indicate SPLIT while driving
HREADY LOW to extend the transfer for an extra
cycle. In the final cycle, HREADY is driven HIGH
to end the transfer, while HRESP[1:0] remains
driven to indicate SPLIT.

AHB_T8

Target had issued an ERROR


response. It is now being
accessed by the same master
(that received the ERROR
response) and with the same
address. For ERROR
response, the current transfer
is not repeated.

For an ERROR response, the current transfer is not


repeated. To determine if a master is repeating a
transfer, address (haddr) and htrans are considered.

AHB_T9

Target had issued a RETRY


response. It is now being
assessed by a different master
before completion of the
transfer for which RETRY
response was issued.

A slave that issues RETRY responses must only be


accessed by one master at a time. When a slave
issues a RETRY, it can sample the master number.
Between that point and the time when the transfer
is finally completed, the RETRY slave can check
every transfer attempt that is made to ensure the
master number is the same.

AHB_T10

The bus protocol allows only a


single outstanding transaction
per bus master. A Bus master
received a split response from
the target when it tried to
access the target the last time.
The target has not yet issued a
split completion request to this
master yet. The master must
not access the target until then.

The bus protocol allows only a single outstanding


transaction per bus master. When a target issues a
SPLIT, it can sample the master number. Between
that point and the time when the transfer is finally
completed, the SPLIT target can check every
transfer attempt that is made to ensure the master is
not the same, unless all other masters are waiting
for SPLIT transfers to complete in which case the
default master could be granted the bus.

AHB_T11

Target issued a split


completion request for a
master, even though it did not
issue a split response for that
master.

The target asserted a bit of hsplitx that identified a


master with which the target device does not have
a split transaction pending.

AHB_T12

A BUSY transfer type was


issued when there was no
burst in progress.

The first transfer of a burst or single transfer must


be a NONSEQUENTIAL transfer.

AHB_T13

The first transfer of a burst or


a single transfer cannot have a
transfer type of
SEQUENTIAL.

The first transfer of a burst or single transfer must


be a NONSEQUENTIAL transfer.

AHB_T14

A master must never attempt a


transfer where the width (as
encoded by hsize) is wider
than the data bus to which it is
connected.

The encoded width of the data being transferred is


larger than the width of the physical data bus.
Although a bus master can be modified to operate
on bus that is wider than originally intended, it
cannot operate on a narrower bus.

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Advanced Microcontroller Bus Architecture (AMBA)


Monitor Checks

Table 3-8. AMBA AHB Target Checks (cont.)


Check ID

Violation

Description

AHB_T15

All transfers must be aligned


to the address boundary equal
to the size of the transfer.

The transfer must be aligned to the address


boundary equal to the size of the transfer. For
example, word transfers must be aligned to word
address boundaries (i.e., A[1:0] = 00), halfword
transfers must be aligned to halfword address
boundaries (i.e., A[0] = 0).

AHB_T16

A master was granted the bus,


but it did not perform any data
transfer including IDLE.
When a master is granted the
bus and it does not wish to
perform any data transfer, it
must issue an IDLE transfer.

IDLE transfer indicates no data transfer is required.


It is used when a bus master is granted the bus, but
does not wish to perform a transfer.

AHB_T17

Master did not hold the


address (haddr) and control
(htrans, hwrite, hsize, hburst,
and hmaster) stable when the
target was inserting wait
states.

The bus master holds the address and control


information stable through out extended cycles.

AHB_T18

The control information


(hwrite, hsize, hburst, and
hmaster) of the current
transfer was not identical to
the control information of the
previous transfer.

The control information for a BUSY or


SEQUENTIAL transfer is identical to the control
information of the previous transfer.

AHB_T19

A master used a BUSY


transfer type. The address did
not reflect the next transfer in
the burst.

The BUSY transfer type indicates that the master is


continuing with a burst of transfers, but the next
transfer cannot take place immediately. When a
master uses the BUSY transfer type, the address
must reflect the next transfer in the burst.

AHB_T20

The address of the current


transfer with a transfer type of
SEQUENTIAL was not
related to the address of the
previous transfer.

The address in a SEQUENTIAL transfer is related


to the address of the previous transfer. The address
is equal to the address of the previous transfer plus
the size (in bytes). In the case of a wrapping burst,
the address of the transfer wraps at the address
boundary equal to the size (in bytes) multiplied by
the number of beats in the transfer.

AHB_T21

The address of the current


The address must be the same on consecutive
transfer was not equal to the
BUSY(s) or on a BUSY-SEQ.
address of the previous
transfer. The address must be
the same on consecutive
BUSY(s) or on a BUSY-SEQ.

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Advanced Microcontroller Bus Architecture (AMBA)


Monitor Checks

Table 3-8. AMBA AHB Target Checks (cont.)

58

Check ID

Violation

Description

AHB_T22

Master did not perform an


IDLE transfer immediately
after receiving a ERROR
response.

ERROR response requires at least two cycles. The


two-cycle response is required because of the
pipelined nature of the bus. By the time a target
starts to issue a ERROR response, the address of
the following transfer has already been broadcast
onto the bus. The two-cycle response allows
sufficient time for the master to cancel this address
and drive HTRANS[1:0] to IDLE before the start
of the next transfer.
Note that this check is active and applicable only
when the CANCEL_FOLLOWING_TRANSFER
_ON_ERROR_RESPONSE parameter is set to 1.

AHB_T23

Master did not perform an


IDLE transfer immediately
after receiving a RETRY
response.

RETRY response requires at least two cycles. The


two-cycle response is required because of the
pipelined nature of the bus. By the time a target
starts to issue a RETRY response, the address of
the following transfer has already been broadcast
onto the bus. The two-cycle response allows
sufficient time for the master to cancel this address
and drive HTRANS[1:0] to IDLE before the start
of the next transfer.
The protocol requires that a master performs an
IDLE transfer immediately after receiving a
RETRY response.

AHB_T24

Master did not perform an


IDLE transfer immediately
after receiving a SPLIT
response.

SPLIT response requires at least two cycles. The


two-cycle response is required because of the
pipelined nature of the bus. By the time a target
starts to issue a SPLIT response, the address of the
following transfer has already been broadcast onto
the bus. The two-cycle response allows sufficient
time for the master to cancel this address and drive
HTRANS[1:0] to IDLE before the start of the next
transfer.
The protocol requires that a master performs an
IDLE transfer immediately after receiving a SPLIT
response.

AHB_T25

A bus master did not continue


to retry the transfer that was
responded with a RETRY
response.

The RETRY response shows the transfer has not


yet completed, so the bus master should retry the
transfer. The master should continue to retry the
transfer until it completes successfully or
terminates with an ERROR response.
Note that address (haddr) and htrans are taken into
consideration in determining if a master is
continuing to retry a transfer.

AHB_T26

A bus master did not continue


to retry the transfer that was
responded with a SPLIT
response.

The SPLIT response shows the transfer has not yet


completed, so the bus master should retry the
transfer when it is next granted access to the bus.
The master should continue to retry the transfer
until it completes successfully or terminates with
an ERROR response.
Note that address (haddr) and htrans are taken into
consideration in determining if a master is
continuing to retry a transfer.

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Advanced Microcontroller Bus Architecture (AMBA)


Monitor Checks

Table 3-8. AMBA AHB Target Checks (cont.)


Check ID

Violation

Description

AHB_T27

Width of the data bus must be


either 8, 16, 32, 64, 128, 256,
512, or 1024.

The AHB standard requires that the width of the


data bus must be either 8, 16, 32, 64, 128, 256, 512,
or 1024.

AHB_T28

Illegal number of masters on


the bus.

The AHB standard requires a minimum of 1 master


and a maximum of 16 masters on the bus.

AHB_T29_hselx,
AHB_T29_hwrite,
AHB_T29_htrans,
AHB_T29_hsize,
AHB_T29_hburst,
AHB_T29_hmaster,
AHB_T29_hmastlock,
AHB_T29_hready_in,
AHB_T29_hready_out,
AHB_T29_hresp,
AHB_T29_hsplitx

Control signal should not be X


or Z.

Control signals should not have a X or Z value.

AHB_T30_haddr

Address signal should not be


X or Z.

Address signal should not have a X or Z value.

AHB_T31

hselx was not stable when the


target was inserting wait
states.

The bus master holds hselx stable throughout


extended cycles.

AHB_T32

hmaster was not stable when


the target was inserting wait
states.

The bus master holds hselx stable throughout


extended cycles.

AHB_T33

hready_in was not equal to


hready_out when this target
device was active.

When a ahb target is involved in a transaction, no


other ahb target should drive hready.

AHB_T34

Target asserted hready_out


low (inserted wait states)
when it was not selected.

When a ahb target is not involved in a transaction,


it must not drive hready_out.

AHB_T35

The hmaster encoding must


always be less than the
number of masters in the
system.

The hmaster[3:0] encoding indicates the master


that is currently accessing the target device.

AHB_T36

Target must drive HRESP as


When an ahb target is not selected, it must drive
OKAY when it is not selected. HRESP as OKAY.

AHB_T37

Target must not assert


HSPLITx signal for more than
one cycle.

An ahb target must assert HSPLITx only for one


cycle.

AHB_TX

The ahb target monitor should


not be in an unknown state.

If any of the above checks AHB_T1 through


AHB_T26, AHB_T31, or AHB_T32 fires, the ahb
target monitor goes into an unknown state. It
comes back into a known state when it detects a
low on the hselx.

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59

Advanced Microcontroller Bus Architecture (AMBA)


Monitor Corner Cases

Monitor Corner Cases


Table 3-9 shows the corner cases maintained by the AHB target monitor.
Table 3-9. AMBA AHB Target Monitor Corner Cases
Corner Case

Description

Read Transfers

Number of read transfer operations.

Write Transfers

Number of write transfer operations.

IDLE Transfers

Number of IDLE transfers.

BUSY Transfers

Number of BUSY transfers.

OKAY Responses

Number of OKAY responses.

ERROR Responses

Number of ERROR responses.

RETRY Responses

Number of RETRY responses.

SPLIT Responses

Number of SPLIT responses.

SINGLE Burst Type

Number of SINGLE burst transfers.

INCR Burst Type

Number of INCR burst transfers.

WRAP4 Burst Type

Number of WRAP4 burst transfers.

INCR4 Burst Type

Number of INCR4 burst transfers.

WRAP8 Burst Type

Number of WRAP8 burst transfers.

INCR8 Burst Type

Number of INCR8 burst transfers.

WRAP16 Burst Type

Number of WRAP16 burst transfers.

INCR16 Burst Type

Number of INCR16 burst transfers.

Byte (8 Bits) Transfer Size

Number of 8-bit transfers.

Half Word (16 Bits) Transfer Size

Number of 16-bit transfers.

Word (32 Bits) Transfer Size

Number of 32-bit transfers.

Double Word (64 Bits) Transfer Size Number of 64-bit transfers.

60

4-Word (128 Bits) Transfer Size

Number of 128-bit transfers.

8-Word (256 Bits) Transfer Size

Number of 256-bit transfers

512 Bits Transfer Size

Number of 512-bit transfers.

1024 Bits Transfer Size

Number of 1024-bit transfers.

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Advanced Microcontroller Bus Architecture (AMBA)


Monitor Statistics

Monitor Statistics
Table 3-10 shows the statistics maintained by the AHB target monitor.
Table 3-10. AMBA AHB Target Monitor Statistics
Statistic

Description

Total Transfers

Total number of transfer operations.

AHB Target Monitor FAQ


Following are answers to frequently asked questions (FAQ) about the AHB target monitor.
How do I use the Over_Constraints_Mode in formal verification?
The AHB monitor has an Over_Constraints_Mode parameter for use in formal
verification. The Over_Constraints_Mode parameter will add additional constraints
that can be used to prevent formal verification from introducing the behavior listed
below:

Using the Over_Constraints_Mode parameter in simulation will produce incorrect


AHB violations.

Note that the Over_Constraints_Mode parameter will prevent formal verification


from exercising the full set of legal AHB transactions.
In order to verify your design for all legal AHB transactions, formal verification should
also be run with the Over_Constraints_Mode parameter disabled (set to 0).
How do I use only a subset of the Over_Constraints_Mode constraints?
A subset of the Over_Constraints_Mode constraints can be used by disabling
unwanted constraints.
To remove unwanted constraints, add exclude_checker directives to a checker
control file or your monitor instantiation file as follows:
// Remove burst transfer constraint
// 0in exclude_checker -name *AHB_NO_BURST

// Remove wrap transfer constraint


// 0in exclude_checker -name *AHB_NO_WRAP

// Remove busy response constraint


// 0in exclude_checker -name *AHB_NO_BUSY

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Advanced Microcontroller Bus Architecture (AMBA)


APB Monitor

APB Monitor
AMBA Advanced Peripheral Bus (APB) is for low power peripherals. AMBA APB is
optimized for minimal power consumption and reduced interface complexity to support
peripheral functions. APB can be used in conjunction with the AHB system bus.

Monitor Placement and Instantiation


Place the APB monitor inside the APB peripheral device or inside the bridge to the AHB bus.
The monitor can be instantiated in a checker control file. The APB monitors checks can be
used to search targets and check constraints for running formal analysis.

Monitor Connectivity
Connect the APB monitor pins to internal signals as specified in the pin-out Table 3-11 and
illustrated in Figure 3-5.
Figure 3-5. APB Monitor Pins Diagram

pclk
presetn
paddr[ADD_BUS_WIDTH 1:0]
pwrite
pselx
penable
pwdata[DATA_BUS_WIDTH 1:0]
prdata[DATA_BUS_WIDTH 1:0]

AMBA
APB Monitor

Table 3-11. APB Monitor Pins

62

Pin

Description

paddr

Address lines for the bus (maximum width = 32-bits).

pclk

APB clock.

penable

Active high device enable signal.

prdata

Read data bus (maximum width = 32bits).

presetn

Active low APB reset.

pselx

Active high device select signal.

pwdata

Write data bus (maximum width = 32-bits).

pwrite

Encoding for the type of transfer: HIGH for write transfers and LOW
for read transfers.

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Advanced Microcontroller Bus Architecture (AMBA)


APB Monitor

Note that the pwdata and prdata buses can be implemented together as a single bidirectional
bus with tri-state capability. Under this configuration, connect the single data bus to both the
pwdata and prdata inputs of the interface monitor.

Monitor Parameters
The parameters shown in Table 3-12 configure the corresponding APB monitor.
Table 3-12. AMBA APB Monitor Parameters
Order

Parameter

Default

Description

1.

Constraints_Mode

Set to 1 if the checks in the monitor are to be used as


constraints for formal analysis.

2.

ADD_BUS_WIDTH

32

Width of PADDR bus. The default (32-bits) is the


maximum width supported by the APB interface.

3.

DATA_BUS_WIDTH

32

Width of PRDATA and PWDATA buses. The default (32bits) is the maximum width supported by the APB
interface.

The parameters must be specified in the above order.

APB Monitor Instantiation Example


Example 3-3 instantiates an APB monitor with an address width of 24 and a data width of 16.
Example 3-3. APB Monitor Instantiation
qvl_apb_monitor
#( /* Constraints_Mode */
/* ADD_BUS_WIDTH */
/* DATA_BUS_WIDTH */
)
APB_MONITOR
(.pclk(pclk),
.presetn(presetn),
.paddr(paddr),
.pselx(pselx),
.penable(penable),
.pwrite(pwrite),
.pwdata(pwdata),
.prdata(prdata)
);

0,
24,
16

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Advanced Microcontroller Bus Architecture (AMBA)


APB Monitor

Monitor Checks
Table 3-13 shows the checks performed by the APB monitor.
Table 3-13. AMBA APB Checks

64

Check ID

Violation

Description

APB_01

The bus should advance to


SETUP state or remain in IDLE
state, but went to ENABLE state.

When the bus is in the IDLE state, it can advance to


the SETUP state or remain in the IDLE state.
Advancing to ENABLE state causes this check to
fire.

APB_02

The bus did not advance to


ENABLE state in one clock
cycle, instead went to an
unknown state.

When the bus is in the SETUP state, it should


advance to the ENABLE state in one clock cycle.
Any other behavior causes this check to fire.

APB_03

The bus should advance to IDLE


or SETUP state, but went to an
unknown state.

When the bus is in the ENABLE state, it should


advance either to the IDLE state or to the SETUP
state (to perform back to back cycles) in one clock
cycle. Any other behavior causes this check to fire.

APB_04

The bus should advance to IDLE


state, but remained in an
unknown state.

When the bus encounters an error condition, it is


required to return to the IDLE state before
attempting subsequent operations. This is enforced
to track accurately any further operation on the bus.
The check fires until the bus transitions from an
UNKNOWN state to the IDLE state.

APB_06

The PADDR address should be


The PADDR signal should be stable when the bus
stable while transitioning from
transitions from SETUP to the ENABLE state.
SETUP to ENABLE state, but has
changed.

APB_07

The PWRITE signal should be


The PWRITE signal should be stable when the bus
stable while transitioning from
transitions from SETUP to the ENABLE state.
SETUP to ENABLE state, but has
changed.

APB_08

The PWDATA should be stable


while transitioning from SETUP
to ENABLE state during write
cycles, but has changed.

The PWDATA signal should be stable when the


bus transitions from SETUP to the ENABLE state.

APB_09_pselx
APB_09_penable
APB_09_pwrite

Control signals should not be X


or Z.

None of the control signals should have a X or Z


value at any time.

APB_10

Width of the APB Address bus is


at most 32.

The AMBA standard requires that the maximum


width of the APB Address bus is 32.

APB_11

Width of the APB Data bus is at


most 32.

The AMBA standard requires that the maximum


width of the APB Data bus is 32.

APB_12_paddr

To reduce power consumption,


PADDR must not change after a
transfer until the next access
occurs.

In order to reduce power consumption, the address


signal will not change after a transfer until the next
access occurs.

APB_12_pwrite

To reduce power consumption,


PWRITE must not change after a
transfer until the next access
occurs.

In order to reduce power consumption, the write


signal will not change after a transfer until the next
access occurs.

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Advanced Microcontroller Bus Architecture (AMBA)


APB Monitor

Monitor Corner Cases


Table 3-14 shows the corner cases maintained by the APB monitor.
Table 3-14. AMBA APB Monitor Corner Cases
Corner Cases

Description

Read Transfers

Number of read transfer operations.

Write Transfers

Number of write transfer operations.

Back-to-back Transfers

Number of consecutive read or write transfer operations.

Monitor Statistics
Table 3-15 shows the statistics maintained by the APB monitor.
Table 3-15. AMBA APB Monitor Statistics
Statistic

Description

Total Transfers

Total number of transfer operations.

Idle State Count

Number of cycles in the IDLE state.

Setup State Count

Number of cycles in the SETUP state.

Enable State Count

Number of cycles in the ENABLE state.

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Advanced Microcontroller Bus Architecture (AMBA)


APB Monitor

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Chapter 4
AMBA 3 Advanced Peripheral Bus (APB)
Introduction
AMBA 3 Advanced Peripheral Bus (APB) is for low power peripherals. AMBA 3 APB is
optimized for minimal power consumption and reduced interface complexity to support
peripheral functions. AMBA 3 APB can be used in conjunction with the AHB and the AXI
system bus.

Reference Documentation
This version of the AMBA 3 APB monitor is modeled from the requirements provided in the
following document:

AMBA 3 APB Protocol Specification, IHI 0024B, v1.0, 17 August 2004

Monitor Placement and Instantiation


Place the AMBA 3 APB monitor inside the APB peripheral device or inside the bridge to the
AHB bus. The AMBA 3 APB monitors checks can be run in simulation and can be used as
search targets and check constraints for running formal analysis.

Monitor Connectivity
Connect the AMBA 3 APB monitor pins as specified in the pin out Table 4-1 and illustrated in
Figure 4-1.
Figure 4-1. AMBA 3 APB Monitor Pins Diagram
pclk
presetn
paddr[ADD_BUS_WIDTH 1:0]
pwrite
pselx
penable
pwdata[DATA_BUS_WIDTH 1:0]
prdata[DATA_BUS_WIDTH 1:0]
pready
pslverr

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AMBA 3
APB Monitor

67

AMBA 3 Advanced Peripheral Bus (APB)


Monitor Connectivity

Table 4-1. AMBA 3 APB Monitor Pins


Port

Description

paddr

Address lines for the bus (maximum width = 32-bits).

pclk

AMBA 3 APB clock.

penable

Active high device enable signal.

prdata

Read data bus (maximum width = 32-bits).

presetn

Active low AMBA 3 APB reset.

pselx

Active high device select signal.

pwdata

Write data bus (maximum width = 32-bits).

pwrite

Encoding for the type of transfer: HIGH for write transfers and LOW for read
transfers.

pready

Signal to extend an AMBA 3 APB transaction.

pslverr

Signal to indicate a failure of a transfer.

Note that the pwdata and prdata buses can be implemented together as a single bidirectional
bus with tri-state capability. Under this configuration, connect the single data bus to both the
pwdata and prdata inputs of the interface monitor.

Monitor Parameters
The parameters shown in Table 4-2 configure the AMBA 3 APB monitor.
Table 4-2. AMBA 3 APB Monitor Parameter
Order Parameter

Default Description

1.

Constraints_Mode

Set to 1 if the checks in the monitor are to be used as


constraints for formal analysis of the APB slave.

2.

ADD_BUS_WIDTH

32

Width of PADDR bus. The default (32-bits) is the


maximum width supported by the AMBA 3 APB
interface.

3.

DATA_BUS_WIDTH

32

Width of PRDATA and PWDATA buses. The default


(32-bits) is the maximum width supported by the
AMBA 3 APB interface.

4.

INTERFACE_TYPE

Set this parameter depending on the interface on


which the monitor is instantiated:
0 => Master interface
1 => Slave interface
To verify a master DUT, this parameter must be set to
0, while to verify a slave DUT, this parameter must
be set to 1.
This parameter only works in formal to define the
constraint.

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AMBA 3 Advanced Peripheral Bus (APB)


Monitor Checks

Table 4-2. AMBA 3 APB Monitor Parameter (cont.)


Order Parameter

Default Description

5.

SLAVE_COUNT

Width of PSELx bus. This parameter represents the


number of slave.

6.

RECOMMENDED_CHECKS_OFF

Disable the recommended checks in APB3. These


recommended checks are AMBA3_APB_13,
AMBA3_APB_12_paddr, and
AMBA3_APB_12_pwrite.

Note that the parameters must be specified in the above order.

AMBA 3 APB Monitor Instantiation Example


Example 4-1 instantiates an AMBA 3 APB monitor with an address width of 24 and a data
width of 16.
Example 4-1. AMBA 3 APB Monitor Instantiation
qvl_amba3_apb_monitor
#( /* Constraints_Mode */
0,
/* ADD_BUS_WIDTH */
24,
/* DATA_BUS_WIDTH */
16,
/* INTERFACE_TYPE */
0,
/* SLAVE_COUNT */
1,
/* RECOMMENDED_CHECKS_OFF */ 0
)
AMBA3_APB_MONITOR
(.pclk(pclk),
.presetn(presetn),
.paddr(paddr),
.pselx(pselx),
.penable(penable),
.pwrite(pwrite),
.pwdata(pwdata),
.prdata(prdata),
.pready(pready),
.pslverr(pslverr)
);

Monitor Checks
Table 4-3 shows the checks performed by the AMBA 3 APB monitor.
Table 4-3. AMBA 3 APB Monitor Checks
Check ID

Violation

AMBA3_APB_01

The bus should advance to SETUP When the bus is in the IDLE state, it can
state or remain in IDLE state, but advance to the SETUP state or remain in the
went to ACCESS state.
IDLE state. Advancing to ACCESS state
causes this check to fire.

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Description

69

AMBA 3 Advanced Peripheral Bus (APB)


Monitor Checks

Table 4-3. AMBA 3 APB Monitor Checks (cont.)

70

Check ID

Violation

Description

AMBA3_APB_02

The bus did not advance to


ACCESS or WAIT state in one
clock cycle from SETUP state,
instead went to an unknown state.

When the bus is in the SETUP state, it should


advance to the ACCESS or WAIT state in
one clock cycle. Any other behavior causes
this check to fire.

AMBA3_APB_03

The bus should advance to IDLE


or SETUP state, but went to an
unknown state.

When the bus is in the ACCESS state, it


should advance either to the IDLE state or to
the SETUP state (to perform back-to-back
cycles) in one clock cycle. Any other
behavior causes this check to fire.

AMBA3_APB_04

The bus should advance to


ACCESS or stay in WAIT state,
but went to an unknown state.

After staying in the WAIT state for some


time, the bus should either move to the
ACCESS state or keep waiting in the WAIT
until the pready signal is seen on the bus. Any
other behaviour cases this check to fire.

AMBA3_APB_UNKN

The bus should advance to IDLE


state, but remained in an unknown
state.

When the bus encounters an error condition,


it is required to return to the IDLE state
before attempting subsequent operations.
This is enforced to track accurately any
further operation on the bus. The check fires
until the bus transitions from an UNKNOWN
state to the IDLE state.

AMBA3_APB_06

The PADDR address should be


The PADDR signal should be stable when the
stable from SETUP until ACCESS bus transitions from SETUP to the ACCESS
state, but has changed.
state.

AMBA3_APB_07

The PWRITE signal should be


The PWRITE signal should be stable when
stable from SETUP until ACCESS the bus transitions from SETUP to the
state, but has changed.
ACCESS state.

AMBA3_APB_08

The PWDATA should be stable


from SETUP until ACCESS state
during write cycles, but has
changed.

The PWDATA signal should be stable when


the bus transitions from SETUP to the
ACCESS state.

AMBA3_APB_09_pselx
AMBA3_APB_09_penable
AMBA3_APB_09_pwrite
AMBA3_APB_09_pready
AMBA3_APB_09_pslverr

Control signals should not be X or


Z.

None of the control signals should have a X


or Z value at any time.

AMBA3_APB_10

Width of the APB Address bus is


at most 32.

The AMBA 3 APB standard requires that the


maximum width of the AMBA 3 APB
Address bus is 32.

AMBA3_APB_11

Width of the APB Data bus is at


most 32.

The AMBA 3 APB standard requires that the


maximum width of the AMBA 3 APB Data
bus is 32.

AMBA3_APB_12_paddr

To reduce power consumption,


PADDR must not change after a
transfer until the next access
occurs.

In order to reduce power consumption, the


address signal will not change after a transfer
until the next access occurs. This check is
disabled when
RECOMMENDED_CHECKS_OFF
parameter is set to 1.

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AMBA 3 Advanced Peripheral Bus (APB)


Monitor Corner Cases

Table 4-3. AMBA 3 APB Monitor Checks (cont.)


Check ID

Violation

Description

AMBA3_APB_12_pwrite

To reduce power consumption,


PWRITE must not change after a
transfer until the next access
occurs.

In order to reduce power consumption, the


write signal will not change after a transfer
until the next access occurs. This check is
disabled when
RECOMMENDED_CHECKS_OFF
parameter is set to 1.

AMBA3_APB_13

The protocol recommends


PSLVERR to be low when any of
PSEL, PENABLE, or PREADY is
low.

It is recommended that PSLVERR be driven


low when it is not being sampled. This check
is disabled when
RECOMMENDED_CHECKS_OFF
parameter is set to 1.

AMBA3_APB_14

PSELx must not have more than


one bit high.

At one time only one slave is selected. This


check fires if more than one bit in PSELx is
asserted.

AMBA3_APB_15

The PSELx should be stable from


SETUP until ACCESS state, but
has changed.

The PSELx signal should be stable when the


bus transitions from SETUP to the ACCESS
state.

Monitor Corner Cases


Table 4-4 shows the corner cases maintained by the AMBA 3 APB monitor.
Table 4-4. AMBA 3 APB Corner Cases
Corner Case

Description

Read Transfers

Number of read transfer operations.

Write Transfers

Number of write transfer operations.

Back to Back Transfers

Number of consecutive read or write transfer operations.

Monitor Statistics
Table 4-5 shows the statistics maintained by the AMBA 3 APB monitor.
Table 4-5. AMBA 3 APB Protocol Statistics
Statistic

Description

Total Transfers

Total number of transfer operations.

Idle State Count

Number of cycles in the IDLE state.

Setup State Count

Number of cycles in the SETUP state.

Access State Count

Number of cycles in the ACCESS state.

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71

AMBA 3 Advanced Peripheral Bus (APB)


Monitor Statistics

Table 4-5. AMBA 3 APB Protocol Statistics (cont.)

72

Statistic

Description

Transfer Failures

Number of transactions that got pslverr asserted during the access phase.

Questa Verification Library Monitors Data Book, v2010.2

Chapter 5
AMBA AXI
Introduction
The AXI is the latest generation AMBA interface, targeted at high-performance, high-frequency
system designs and includes a number of features that make it suitable for a high-speed
submicron interconnect. The QVL AMBA AXI monitor is designed for checking the AXI
interface.

Reference Documentation
This version of the AMBA AXI monitor is modeled from the requirements provided in the
following document:

AMBA AXI protocol specification, IHI 0022B, v1.0, 19 March 2004

Supported Features
Channel Handshake

Channel handshake.

Channel dependencies.

Addressing options

Burst lengths of 2, 4, 8, 16 transfers for wrapping bursts.

Burst lengths of 1 to 16 transfers for sequential incrementing bursts.

Data widths from 1 to 128 bytes.

Wrapping, incrementing, and fixed types of bursts.

Atomic Accesses

Exclusive accesses.

Locked transactions.

Response Signaling

All types of responses.

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73

AMBA AXI
Monitor Placement and Instantiation

Completions

Out of order completions.

Read and write data interleaving.

Data buses

Write strobes.

Narrow transfers and byte lane switching.

Unaligned transfers.

Low Power interface

Peripheral initiated clock control and handshake-based clock control.

Unsupported Features

The monitor will assume the data as-is and will not perform endianness conversion.

Monitor Placement and Instantiation


The QVL AMBA AXI monitor can be placed on the master or slave side to provide interface
checks. The checks in the AMBA AXI monitor can also be used as search targets and check
constraints while running formal analysis on the AXI master or slave devices. The AMBA AXI
monitor can also be placed on the interconnect. A typical AXI setup is shown in Figure 5-1.
Figure 5-1. AMBA AXI Monitor Implementation

AXI Monitor
INTERFACE_TYPE=0

AXI Monitor for


Slave Interface of I/C
INTERFACE_TYPE=3

AXI Monitor for


Master Interface of I/C
INTERFACE_TYPE=2

AXI Monitor
INTERFACE_TYPE=1

AXI Master Device

AXI Interconnect

AXI Slave Device

Refer to Table 5-2 on page 77, the INTERFACE_TYPE parameter, for descriptions on
monitor instantiations A, B, C, and D.

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AMBA AXI
Monitor Connectivity

Monitor Connectivity
Connect the AMBA AXI monitor pins as specified in the pin out Table 5-1 and illustrated in
Figure 5-2.

bid[3:0]
bresp[1:0]
bvalid
bready

READ CHANNEL
WRITE RESP.

aclk
areset_n
reset_n

rvalid
rready

AMBA AXI
Monitor
csysreq
csysack
cactive

wid
wdata
wstrb
wlast
wvalid
wready

L.P. I.

WRITE ADDRESS CHANNEL

awid[3:0]
awaddr
awlen
awsize[2:0]
awburst[1:0]
awlock[1:0]
awcache[3:0]
awprot[2:0]
awvalid
awready

rid[3:0]
rdata
rresp[1:0]
rlast

WRITE CHANNEL

READ ADDRESS CHANNEL

arid[3:0]
araddr
arlen
arsize[2:0]
arburst[1:0]
arlock[1:0]
arcache[3:0]
arprot[2:0]
arvalid
arready

GLOBAL

Figure 5-2. AMBA AXI Monitor Pins Diagram

Table 5-1. AMBA AXI Monitor Pins


Port

Description

aclk

Global clock signal (all signals are sampled on the rising edge of global clock).

araddr

Read address bus (address of the first transfer of the burst).

arburst[1:0]

Read burst type (type of burst - incremental / wrapping / fixed).

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75

AMBA AXI
Monitor Connectivity

Table 5-1. AMBA AXI Monitor Pins (cont.)

76

Port

Description

arcache[3:0]

Read cache type (attributes - bufferable / cacheable / write through, etc.).

areset_n

Global reset signal (active low).

arid

Read address ID (tag of the read or write transaction).

arlen

Read burst length (number of transfers - 1, 2, 3 .... 32).

arlock[1:0]

Read lock type (type of transaction - normal / exclusive / locked).

arprot[2:0]

Read protection level (normal / privileged / secure protection level).

arready

Read address ready (slave ready to accept an address).

arsize[2:0]

Read burst size (data width of each transfer).

arvalid

Read address valid (valid address and control information available).

awaddr

Write address bus (address of the first transfer of the burst).

awburst[1:0]

Write burst type (type of burst - incremental / wrapping / fixed).

awcache[3:0]

Write cache type (attributes - bufferable / cacheable / write through, etc.).

awid

Write address ID (tag of the read or write transaction).

awlen

Write burst length (number of transfers - 1, 2, 3 .... 32).

awlock[1:0]

Write lock type (type of transaction - normal / exclusive / locked).

awprot[2:0]

Write protection level (normal / privileged / secure protection level).

awready

Write address ready (slave ready to accept an address).

awsize[2:0]

Write burst size (data width of each transfer).

awvalid

Write address valid (valid address and control information available).

bid

Response ID (identification tag of the write response).

bready

Response ready (master ready to accept a write response).

bresp[1:0]

Write response (status of the write transaction - OKAY / EXOKAY, etc.).

bvalid

Write response valid (valid write response available).

cactive

Clock active (peripheral device requires clock signal). Connect it to 1'b1 for normal
operation.

csysack

Low-power request acknowledgement (for a low-power entry request). Connect it to


1'b1 for normal operation.

csysreq

System low-power request (clock controller to peripheral device). Connect it to 1'b1


for normal operation.

rdata

Read data (read data bus - 8-bits to 1024-bits wide).

reset_n

Synchronous reset signal (This active low signal is not part of standard AXI I/F).

rid

Read ID (tag of the read data transfer).

rlast

Read last (last data transfer of the read burst).

rready

Read ready (master ready to accept read data and response).

Questa Verification Library Monitors Data Book, v2010.2

AMBA AXI
Monitor Connectivity

Table 5-1. AMBA AXI Monitor Pins (cont.)


Port

Description

rresp[1:0]

Read response (status of the read transfer - OKAY / SLVERR, etc.).

rvalid

Read valid (valid read data available).

wdata

Write data (write data bus - 8-, 16-, 32-, .... 1024-bits).

wid

Write ID (tag of the write data transaction).

wlast

Write last (last data transfer of the burst).

wready

Write ready (slave ready to accept write data).

wstrb

Write strobe (write data strobe - 1 bit for each 8-bits of write data bus).

wvalid

Write valid (valid write data available on the bus).

Note that the widths of data buses and transaction IDs are implementation specific. Refer to the
Monitor Parameters section below for the appropriate parameter that defines the widths of these
signals.

Monitor Parameters
The parameters shown in Table 5-2 configure the AMBA AXI monitor.
Table 5-2. AMBA AXI Monitor Parameter
Order Parameter

Default Description

1.

Constraints_Mode

This parameter configures the checks in the


monitor as constraints during formal analysis.

2.

INTERFACE_TYPE

Set this parameter depending on the interface on


which the monitor is instantiated:
0 => Master interface (A in the monitor
implementation diagram)
1 => Slave interface (B in the monitor
implementation diagram)
2=> Master interface of an interconnect (C
in the monitor implementation diagram)
3 => Slave interface of an interconnect (D
in the monitor implementation diagram)

3.

WRITE_DATA_BUS_WIDTH

32

Width of the data bus of the write channel.

4.

READ_DATA_BUS_WIDTH

32

Width of the data bus of the read channel.

5.

TRAN_ID_WIDTH

Width of the transaction IDs - AID, WID, RID,


and BID.

6.

READ_REORDER_DEPTH

This is the read reorder depth of the slave device.


Set this parameter to 1 to indicates that all the
read responses are to be generated in the order of
requests.

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77

AMBA AXI
Monitor Connectivity

Table 5-2. AMBA AXI Monitor Parameter (cont.)

78

Order Parameter

Default Description

7.

READ_INTERLEAVING_DEPTH

This is the read data interleaving depth of the


device. Set this parameter to 1 to indicate that
read data cannot be interleaved.

8.

WRITE_INTERLEAVING_DEPTH

This is the write data interleaving depth of the


device. Set this parameter to 1 to indicate that
write data cannot be interleaved.

9.

EXCLUSIVE_ACCESS_ENABLE

Set this parameter to 0 to disable exclusive access


tracking. By default, the exclusive access checks
are enabled.

10.

LPI_ENABLE

Set this parameter to 1 to enable LPI checks and


tracking.

11.

MAX_OUTSTANDING_READ_
ADDR

16

This is the maximum number of outstanding read


requests. This indicates the depth of the
outstanding read addresses queue in the monitor.

12.

MAX_OUTSTANDING_WRITE_
ADDR

16

This is the maximum number of outstanding write


requests. This indicates the depth of the
outstanding write addresses queue in the monitor.

13.

CHECK_WRITE_DATA_
FOLLOWS_ADDR_ENABLE

Set this parameter to 1 to enable checking against


write data coming before write address.

14.

ENABLE_RESERVED_VALUE_
CHECKING

Set this parameter to 0 to disable checking for


reserved values on the interface signals.

15.

ENABLE_RECOMMENDATION_
CHECKING

Set this parameter to 1 to enable checking of


compliance to the recommendations in the
specification, which are not mandatory rules to be
adhered to.

16.

LENGTH_WIDTH

This is the width of the ARLEN and AWLEN


signals and indicates the maximum length of read
and write bursts respectively. The default value of
4 indicates the maximum burst length of 16. The
maximum value allowed for this parameter is 5
(i.e., a burst length of 32).

17.

ADDR_WIDTH

32

This is the width of the ARADDR and


AWADDR signals and indicates the width of the
read address and write address, respectively. The
default value is 32.

18.

MAX_UNIQUE_EXCLUSIVE_
ACCESS

16

This is the maximum number of unique exclusive


accesses. The default value of
MAX_OUTSTANDING_READ_ADDR
indicates that the
MAX_OUTSTANDING_READ_ADDR number
of unique accesses can be tracked.

19.

EXCLUSIVE_READ_RESPONSE_
CHECKING_ENABLE

Set this parameter to 0 to disable checking for


expected exclusive read responses.

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AMBA AXI
Monitor Connectivity

Table 5-2. AMBA AXI Monitor Parameter (cont.)


Order Parameter

Default Description

20.

DATA_X_Z_CHECK_ENABLE

This parameter can be used to enable / disable


checking X / Z on read and/or write data bus. By
default these checks are enabled.
Set this parameter to 0 to disable both write and
read data checks.
Set this parameter to 3 to enable both write and
read data checks.
Set this parameter to 1 to enable only write data
checks.
Set this parameter to 2 to enable only read data
checks.

21.

ALLOW_SLAVE_ERROR_
RESPONSE_AGAINST_
EXCLUSIVE_ACCESS

Normally the monitor expects ok and ex_ok


response from slave against exclusive accesses,
but under certain application circumstances slave
error response may be issued by the slave against
exclusive access such as read only memory
access and so on. Set this parameter to 1 to allow
this.

22.

MAX_OUTSTANDING_WRITE_
DATA

This is the number of data bursts that may be


completed before address controls for any of
these data bursts are issued. This parameter is
applicable when the AXI device supports data
before address scenario.

23.

ENABLE_AWLEN_CHECK_
AGAINST_COMPLETED_DATA_
BEFORE_ADDRESS

Set this parameter to 1 if a delayed check is to be


performed for already finished data phases
against the just issued address phase. This is
relevant for data before scenario.

Note that the parameters must be specified in the above order.

AMBA AXI Monitor Instantiation Examples


Example 1
Example 5-1 instantiates an AMBA AXI monitor on an AMBA AXI master interface with both
read and write channels having the same width of 32 bits, width of all the IDs being 4, and a
maximum of 16 outstanding read and 16 outstanding write addresses. The read reorder depth is
taken as 8 and is therefore the write data interleaving depth. Exclusive access support is
disabled and low power interface support is enabled.
Example 5-1. AMBA AXI Monitor Instantiation for Example 1
qvl_amba_axi_monitor #(
1,
/* Constraints_Mode */
0,
/* INTERFACE_TYPE */
32,
/* WRITE_DATA_BUS_WIDTH */
32,
/* READ_DATA_BUS_WIDTH */
4,
/* TRAN_ID_WIDTH */
8,
/* READ_REORDER_DEPTH */
8,
/* READ_INTERLEAVING_DEPTH */
8,
/* WRITE_INTERLEAVING_DEPTH */

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79

AMBA AXI
Monitor Connectivity
0,
/* EXCLUSIVE_ACCESS_ENABLE */
1,
/* LPI_ENABLE */
16,
/* MAX_OUTSTANDING_READ_ADDR */
16,
/* MAX_OUTSTANDING_WRITE_ADDR */
1,
/* CHECK_WRITE_DATA_FOLLOWS_ADDR_ENABLE */
1,
/* ENABLE_RESERVED_VALUE_CHECKING */
1,
/* ENABLE_RECCOMENDATION_CHECKING */
4,
/* LENGTH_WIDTH */
32
/* ADDR_WIDTH */
)
AMBA_AXI_MONITOR
(.aclk(aclk),
.areset_n(areset_n),
.reset_n(!reset),
.arvalid(arvalid),
.araddr(araddr),
.arlen(arlen),
.arsize(arsize),
.arburst(arburst),
.arlock(arlock),
.arcache(arcache),
.arprot(arprot),
.arid(arid),
.arready(arready),
.awvalid(awvalid),
.awaddr(awaddr),
.awlen(awlen),
.awsize(awsize),
.awburst(awburst),
.awlock(awlock),
.awcache(awcache),
.awprot(awprot),
.awid(awid),
.awready(awready),
.wvalid(wvalid),
.wlast(wlast),
.wdata(wdata),
.wstrb(wstrb),
.wid(wid),
.wready(wready),
.rvalid(rvalid),
.rlast(rlast),
.rdata(rdata),
.rresp(rresp),
.rid(rid),
.rready(rready),
.bvalid(bvalid),
.bresp(bresp),
.bid(bid),
.bready(bready),
.cactive(cactive),
.csysreq(csysreq),
.csysack(csysack)
);

80

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AMBA AXI
Monitor Connectivity

Example 2
Example 5-2 instantiates an AMBA AXI monitor on an AMBA AXI slave interface with read
and write channels having different widths of 8-bits and 32-bits, respectively, and the width of
all the IDs is 4 and a maximum of 16 outstanding read and 16 outstanding write addresses. The
read reorder depth is taken as 8 and therefore, is the write data interleaving depth. Exclusive
access support and low power interface support are enabled. Checks pertaining to reserved
values and recommendations are disabled.
Example 5-2. AMBA AXI Monitor Instantiation for Example 2
qvl_amba_axi_monitor #(
1,
/* Constraints_Mode */
1,
/* INTERFACE_TYPE */
32,
/* WRITE_DATA_BUS_WIDTH */
8,
/* READ_DATA_BUS_WIDTH */
4,
/* TRAN_ID_WIDTH */
8,
/* READ_REORDER_DEPTH */
8,
/* READ_INTERLEAVING_DEPTH */
8,
/* WRITE_INTERLEAVING_DEPTH */
1,
/* EXCLUSIVE_ACCESS_ENABLE */
1,
/* LPI_ENABLE */
16,
/* MAX_OUTSTANDING_READ_ADDR */
16,
/* MAX_OUTSTANDING_WRITE_ADDR */
1,
/* CHECK_WRITE_DATA_FOLLOWS_ADDR_ENABLE */
0,
/* ENABLE_RESERVED_VALUE_CHECKING */
0,
/* ENABLE_RECCOMENDATION_CHECKING */
4,
/* LENGTH_WIDTH */
32
/* ADDR_WIDTH */
)
AMBA_AXI_MONITOR
(.aclk(aclk),
.areset_n(areset_n),
.reset_n(!reset),
.arvalid(arvalid),
.araddr(araddr),
.arlen(arlen),
.arsize(arsize),
.arburst(arburst),
.arlock(arlock),
.arcache(arcache),
.arprot(arprot),
.arid(arid),
.arready(arready),
.awvalid(awvalid),
.awaddr(awaddr),
.awlen(awlen),
.awsize(awsize),
.awburst(awburst),
.awlock(awlock),
.awcache(awcache),
.awprot(awprot),
.awid(awid),
.awready(awready),
.wvalid(wvalid),

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81

AMBA AXI
Monitor Checks
.wlast(wlast),
.wdata(wdata),
.wstrb(wstrb),
.wid(wid),
.wready(wready),
.rvalid(rvalid),
.rlast(rlast),
.rdata(rdata),
.rresp(rresp),
.rid(rid),
.rready(rready),
.bvalid(bvalid),
.bresp(bresp),
.bid(bid),
.bready(bready),
.cactive(cactive),
.csysreq(csysreq),
.csysack(csysack)
);

Monitor Checks
Table 5-3 shows the general checks performed by the AMBA AXI monitor.
Table 5-3. AMBA AXI Monitor Checks

82

Check ID

Violation

Description

AMBA_AXI_ADDR_ACROSS_
4K_WITHIN_LOCKED_READ_
SEQUENCE

Transactions within a locked


read sequence should be
within the same 4K
boundary.

Since the locked sequences can have an


impact on the interconnect performance, it
is recommended to keep the locked read
sequences within the same 4K address
region. Although this is strictly not a
violation, this check fires whenever a read
transaction within a locked window is
addressed to a different 4K byte region
compared to the previous transaction. This
check is active only when the parameter
ENABLE_
RECOMMENDATION_CHECKING is
set to 1.

AMBA_AXI_ADDR_ACROSS_
4K_WITHIN_LOCKED_WRITE_
SEQUENCE

Transactions within a locked


write sequence should be
within the same 4K
boundary.

Since the locked sequences can have an


impact on the interconnect performance, it
is recommended to keep locked write
sequences within the same 4K address
region. Although this is strictly not a
violation, this check fires whenever a write
transaction within a locked window is
addressed to a different 4K byte region
compared to the previous transaction. This
check is active only when the parameter
ENABLE_
RECOMMENDATION_CHECKING is
set to 1.

Questa Verification Library Monitors Data Book, v2010.2

AMBA AXI
Monitor Checks

Table 5-3. AMBA AXI Monitor Checks (cont.)


Check ID

Violation

Description

AMBA_AXI_ADDR_FOR_
READ_BURST_ACROSS_4K_
BOUNDARY

The read address/control


signals issued should not
result in data access across a
4K boundary.

To prevent incrementing type read bursts


from crossing boundaries between slaves
and to limit the size of the address
incrementer required within a slave, read
data bursts must not cross 4K boundaries.
This check fires if the starting address,
length, and size issued is such that the read
burst crosses the applicable 4K boundary.

AMBA_AXI_ADDR_FOR_
WRITE_BURST_ACROSS_4K_
BOUNDARY

The write address/control


signals issued should not
result in data access across a
4K boundary.

To prevent incrementing type write bursts


from crossing boundaries between slaves
and to limit the size of the address
incrementer required within a slave, write
data bursts must not cross 4K boundaries.
This check fires if the starting write
address, length, and size issued is such that
the burst crosses the applicable 4K
boundary.

AMBA_AXI_ARADDR_UNKN

ARADDR signal should not


be X or Z.

Checks that ARADDR is both known (not


X) and driven (not Z). This check is active
only when ARVALID is high.

AMBA_AXI_ARBURST_UNKN

ARBURST signal should


not be X or Z.

Checks that ARBURST is both known (not


X) and driven (not Z). This check is active
only when ARVALID is high.

AMBA_AXI_ARCACHE_UNKN

ARCACHE signal should


not be X or Z.

Checks that ARCACHE is both known


(not X) and driven (not Z). This check is
active only when ARVALID is high.

AMBA_AXI_ARID_CHANGED_
WITHIN_LOCKED_READ_
SEQUENCE

All transactions within a


locked read sequence should
have the same ARID.

The master must ensure that all


transactions within a locked read sequence
have the same ARID value. This check
fires whenever this requirement is violated.

AMBA_AXI_ARID_UNKN

ARID signal should not be X Checks that ARID is both known (not X)
or Z.
and driven (not Z). This check is active
only when ARVALID is high.

AMBA_AXI_ARLEN_UNKN

ARLEN signal should not be Checks that ARLEN is both known (not X)
X or Z.
and driven (not Z). This check is active
only when ARVALID is high.

AMBA_AXI_ARLOCK_UNKN

ARLOCK signal should not


be X or Z.

Checks that ARLOCK is both known (not


X) and driven (not Z). This check is active
only when ARVALID is high.

AMBA_AXI_ARPROT_
ARCACHE_CHANGED_
WITHIN_LOCKED_SEQUENCE

It is recommended that a
master should not change
ARPROT or ARCACHE
during a sequence of locked
accesses.

Locked accesses require that the


interconnect prevents other transactions
occurring while the locked sequence is in
progress and can therefore have an impact
on the interconnect performance. It is
recommended that the read cache
(ARCACHE) and read protection unit
(ARPROT) information be held steady
during a locked sequence. This check fires
when any of these change during a locked
sequence and ENABLE_
RECOMMENDATION_CHECKING is
set to 1.

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83

AMBA AXI
Monitor Checks

Table 5-3. AMBA AXI Monitor Checks (cont.)

84

Check ID

Violation

Description

AMBA_AXI_ARPROT_UNKN

ARPROT signal should not


be X or Z.

Checks that ARPROT is both known (not


X) and driven (not Z). This check is active
only when ARVALID is high.

AMBA_AXI_ARREADY_UNKN

ARREADY signal should


not be X or Z.

Checks that ARREADY is both known


(not X) and driven (not Z).

AMBA_AXI_ARSIZE_UNKN

ARSIZE signal should not


be X or Z.

Checks that ARSIZE is both known (not


X) and driven (not Z). This check is active
only when ARVALID is high.

AMBA_AXI_ARVALID_
DEASSERTED_BEFORE_
ARREADY

ARVALID should be held


asserted until the slave
asserts ARREADY.

The master can assert ARVALID only


when it drives valid read address and
control information on the bus. It must be
held asserted until the slave accepts the
address and control information and
indicates the same by asserting the
ARREADY signal. This check fires if
ARVALID is detected de-asserted (after
being sampled asserted) even before
ARREADY is asserted.

AMBA_AXI_ARVALID_UNKN

ARVALID signal should not Checks that ARVALID is both known (not
be X or Z.
X) and driven (not Z).

AMBA_AXI_AWADDR_UNKN

AWADDR signal should not Checks that AWADDR is both known (not
be X or Z.
X) and driven (not Z). This check is active
only when AWVALID is high.

AMBA_AXI_AWBURST_UNKN

AWBURST signal should


not be X or Z.

Checks that AWBURST is both known


(not X) and driven (not Z). This check is
active only when AWVALID is high.

AMBA_AXI_AWCACHE_UNKN

AWCACHE signal should


not be X or Z.

Checks that AWCACHE is both known


(not X) and driven (not Z). This check is
active only when AWVALID is high.

AMBA_AXI_AWID_CHANGED_
WITHIN_LOCKED_WRITE_
SEQUENCE

All transactions within a


locked write sequence
should have the same
AWID.

The master must ensure that all


transactions within a locked write
sequence have the same AWID value. This
check fires whenever this requirement is
violated.

AMBA_AXI_AWID_UNKN

AWID signal should not be


X or Z.

Checks that AWID is both known (not X)


and driven (not Z). This check is active
only when AWVALID is high.

AMBA_AXI_AWLEN_
MISMATCHED_WITH_
ACTUAL_LENGTH_OF_WRITE_
DATA_BURST

Address follows data


scenario: Awlen value in
address control for
outstanding data does not
match actual length of data
burst

This assertion verifies the awlen field


when address is issued later than data. This
check keeps track of data burst length
actually transferred when data completes
before address and matches the same when
address control (mainly awlen)
information is available. This check
applies only when the parameter
ENABLE_AWLEN_CHECK_
AGAINST_COMPLETED_DATA_
BEFORE_ADDRESS is set to 1.

Questa Verification Library Monitors Data Book, v2010.2

AMBA AXI
Monitor Checks

Table 5-3. AMBA AXI Monitor Checks (cont.)


Check ID

Violation

Description

AMBA_AXI_AWLEN_UNKN

AWLEN signal should not


be X or Z.

Checks that AWLEN is both known (not


X) and driven (not Z). This check is active
only when AWVALID is high.

AMBA_AXI_AWLOCK_UNKN

AWLOCK signal should not


be X or Z.

Checks that AWLOCK is both known (not


X) and driven (not Z). This check is active
only when AWVALID is high.

AMBA_AXI_AWPROT_
AWCACHE_CHANGED_
WITHIN_LOCKED_SEQUENCE

It is recommended that a
master should not change
AWPROT or AWCACHE
during a sequence of locked
accesses.

Locked accesses require that the


interconnect prevents other transactions
occurring while the locked sequence is in
progress and can therefore have an impact
on the interconnect performance. It is
recommended that the write cache
(AWCACHE) and protection unit
(AWPROT) information be held steady
during a locked sequence. This check fires
when any of these change during a locked
sequence and ENABLE_
RECOMMENDATION_CHECKING is
set to 1.

AMBA_AXI_AWPROT_UNKN

AWPROT signal should not


be X or Z.

Checks that AWPROT is both known (not


X) and driven (not Z). This check is active
only when AWVALID is high.

AMBA_AXI_AWREADY_UNKN

AWREADY signal should


not be X or Z.

Checks that AWREADY is both known


(not X) and driven (not Z).

AMBA_AXI_AWSIZE_UNKN

AWSIZE signal should not


be X or Z.

Checks that AWSIZE is both known (not


X) and driven (not Z). This check is active
only when AWVALID is high.

AMBA_AXI_AWVALID_
DEASSERTED_BEFORE_
AWREADY

AWVALID should be held


asserted until the slave
asserts AWREADY.

The master can assert AWVALID only


when it drives valid write address and
control information on the bus. It must be
held asserted until the slave accepts the
write address and control information, and
indicates the same by asserting the
AWREADY signal. This check fires if
AWVALID is detected de-asserted (after
being sampled asserted) even before
AWREADY is asserted.

AMBA_AXI_AWVALID_UNKN

AWVALID signal should


not be X or Z.

Checks that AWVALID is both known


(not X) and driven (not Z).

AMBA_AXI_BID_CHANGED_
BEFORE_BREADY

Once BVALID is asserted,


BID should not change until
BREADY is asserted.

Once the slave asserts BVALID indicating


availability of a valid write response on the
bus, it must hold the BID value stable until
the master accepts the same with
BREADY. This check fires if the BID
value changes even before the master
asserts BREADY.

AMBA_AXI_BID_UNKN

BID signal should not be X


or Z.

Checks that BID is both known (not X) and


driven (not Z). This check is active only
when BVALID is high.

AMBA_AXI_BREADY_UNKN

BREADY signal should not


be X or Z.

Checks that BREADY is both known (not


X) and driven (not Z).

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85

AMBA AXI
Monitor Checks

Table 5-3. AMBA AXI Monitor Checks (cont.)

86

Check ID

Violation

Description

AMBA_AXI_BRESP_UNKN

BRESP signal should not be


X or Z.

Checks that BRESP is both known (not X)


and driven (not Z). This check is active
only when BVALID is high.

AMBA_AXI_BVALID_
DEASSERTED_BEFORE_
BREADY

BVALID should be held


asserted until the master
asserts BREADY.

The slave can assert BVALID only when it


drives a valid write response on the bus. It
must be held asserted until the master
accepts the response and indicates the
same by asserting the BREADY signal.
This check fires if BVALID is detected deasserted (after being sampled asserted)
even before BREADY is asserted.

AMBA_AXI_BVALID_UNKN

BVALID signal should not


be X or Z.

Checks that BVALID is both known (not


X) and driven (not Z).

AMBA_AXI_CACTIVE_UNKN

CACTIVE signal should not


be X or Z.

Checks that CACTIVE is both known (not


X) and driven (not Z). This check is active
only when the parameter LPI_ENABLE is
set to 1.

AMBA_AXI_CSYSACK_
ASSERTION_VIOLATION

CSYSACK should not be


asserted before CSYSREQ
is asserted.

An exit from low-power state begins with


the clock controller asserting CSYSREQ.
The peripheral should then assert
CSYSACK acknowledging the exit. This
check fires if the peripheral indicates an
exit by asserting CSYSACK even before
being directed by the controller. This check
is active only when LPI_ENABLE is set to
1.

AMBA_AXI_CSYSACK_
DEASSERTION_VIOLATION

Once asserted, CSYSACK


should not be de-asserted
before CSYSREQ is deasserted.

To request that the peripheral enter a lowpower state, the system clock controller
drives the CSYSREQ signal low. Only
then the peripheral can drive the
CSYSACK signal low to acknowledge the
entry to low-power state. This check fires
if this relationship is violated. This check
is active only when LPI_ENABLE is set to
1.

AMBA_AXI_CSYSACK_UNKN

CSYSACK signal should


not be X or Z.

Checks that CSYSACK is both known (not


X) and driven (not Z). This check is active
only when the parameter LPI_ENABLE is
set to 1.

AMBA_AXI_CSYSREQ_
ASSERTION_VIOLATION

Once de-asserted,
CSYSREQ should not be
asserted before CSYSACK
acknowledged the request
for entry into the low-power
state.

The clock controller requests the


peripheral device to enter a low-power
state by de-asserting CSYSREQ. This is
then acknowledged by the peripheral by
de-asserting CSYSACK. This check fires
if the clock controller asserts CSYSREQ
(requests an exit from low-power state)
even before the peripheral acknowledges
entry to the low-power state. This check is
active only when LPI_ENABLE is set to 1.

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AMBA AXI
Monitor Checks

Table 5-3. AMBA AXI Monitor Checks (cont.)


Check ID

Violation

Description

AMBA_AXI_CSYSREQ_
DEASSERTION_VIOLATION

CSYSREQ should not be deasserted to indicate new


request for entry to lowpower state even before the
previous exit from lowpower state was
acknowledged.

Once the clock controller indicates an exit


from low-power state, it must wait until the
peripheral asserts CSYSACK to
acknowledge the exit and only then deassert CSYSREQ to indicate a new lowpower entry request. This check fires if this
requirement is violated. This check is
active only when LPI_ENABLE is set to 1.

AMBA_AXI_CSYSREQ_UNKN

CSYSREQ signal should not Checks that CSYSREQ is both known (not
be X or Z.
X) and driven (not Z). This check is active
only when the parameter LPI_ENABLE is
set to 1.

AMBA_AXI_DATA_ISSUED_
EXCEEDS_MAX_ALLOWED_
OUTSTANDING_DATA_
BEFORE_ADDRESS

Address follows data


scenario: New data burst
should not be initiated while
number of completed data
burst has reached allowed
maximum outstanding data.

This check fires when number of


completed data bursts without addresses
exceeds the allowed number of outstanding
completed data before address. The
allowed number of outstanding completed
data before address is set by the parameter
MAX_OUTSTANDING_WRITE_DATA.

AMBA_AXI_DECODE_ERROR_
RESPONSE_BY_SLAVE

A slave should not issue


DECERR response.

In a system without a fully decoded


address map, the interconnect must provide
a suitable decode error response for
addresses at which there are no slaves to
respond to a transactions. A slave cannot
respond with a decode error as it is unable
to identify the address in the first place.
This check fires if a decode error is
detected on the slave side. This check is
active only when INTERFACE_TYPE is
set to 1.

AMBA_AXI_EX_WRITE_
BEFORE_EX_READ_RESPONSE

An exclusive write access


should not be performed
until the previously issued
exclusive read has been
responded.

The exclusive access consists of two parts:


the exclusive read followed by the
exclusive write (typically done only if the
exclusive read returns an EXOKAY
response). This check fires if the master
attempts the exclusive write even before an
exclusive read. This check is active only
when the parameter EXCLUSIVE_
ACCESS_ENABLE is set to 1.
Note that this check activates after a valid
EXREAD waiting of a response.

AMBA_AXI_EXCLUSIVE_
ACCESS_ADDRESS_
VIOLATION

The address and control


signals of an exclusive write
should be identical to that of
the exclusive read.

Questa Verification Library Monitors Data Book, v2010.2

A requirement for an exclusive write


access to be successful is that all the
address and control signals, except for
AWRITE must be identical with the one
that is being monitored. This check fires
whenever an exclusive write access is
performed on a location other than the one
being monitored against that ID. This
check is active only when both
EXCLUSIVE_ACCESS_ENABLE and
INTERFACE_TYPE are set to 1.

87

AMBA AXI
Monitor Checks

Table 5-3. AMBA AXI Monitor Checks (cont.)


Check ID

Violation

Description

AMBA_AXI_EXCLUSIVE_
ACCESS_WHILE_EXCLUSIVE_
ACCESS_NOT_SUPPORTED

Exclusive access may not be This check fires if the exclusive access is
tried by a master as the
tried by a master as the exclusive access
exclusive access
functionality is set.
functionality is configured to
be not supported by setting
EXCLUSIVE_ACCESS_
ENABLE to 0

AMBA_AXI_EXCLUSIVE_
READ_ACCESS_CACHEABLE

An exclusive read access


should not have the
cacheable attribute set.

An exclusive read access being monitored


by a slave must not be cacheable, to ensure
that it sees this transaction. This check
fires if an exclusive read access has the
cacheable attribute set. This check is active
only when the parameter
EXCLUSIVE_ACCESS_ENABLE is set
to 1.

AMBA_AXI_EXCLUSIVE_
READ_RESPONSE_MISMATCH

The exclusive read response


detected should match the
expected response.

A master starts an exclusive operation by


performing an exclusive read, for which
the slave returns an EXOKAY (success) or
an OKAY (failure). The monitor tracks the
exclusive access and internally determines
the expected response for a particular
exclusive read access. This check fires if
the response from the slave does not match
the expected response.
In case of a SLVERR response from the
slave or interconnect during exclusive
access monitoring, this check fails as the
monitor expects only OKAY or EXOKAY
during exclusive access transactions.

88

AMBA_AXI_EXCLUSIVE_
READ_SIZE_EXCEEDS_128

The number of bytes


transferred in an exclusive
read burst should not exceed
128.

The maximum number of bytes that can be


transferred in an exclusive burst is 128.
This check fires when this requirement is
violated.

AMBA_AXI_EXCLUSIVE_
READ_SIZE_NON_POWER_
OF_2

The number of bytes


transferred in an exclusive
read access should be a
power of 2.

The total number of bytes to be transferred


in an exclusive read burst must be a power
of 2, that is, 1, 2, 4, 8, 16, 32, 64, or 128
bytes. This effectively puts the restriction
that the burst length of the exclusive read
access must be a power of 2, since burst
size is always a power of 2. This check
fires when this requirement is violated.

AMBA_AXI_EXCLUSIVE_
WRITE_ACCESS_CACHEABLE

An exclusive write access


should not have the
cacheable attribute set.

An exclusive write access being monitored


by a slave must not be cacheable, to ensure
that it sees this transaction. This check
fires if an exclusive write access has the
cacheable attribute set. This check is active
only when the parameter EXCLUSIVE_
ACCESS_ENABLE is set to 1.

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AMBA AXI
Monitor Checks

Table 5-3. AMBA AXI Monitor Checks (cont.)


Check ID

Violation

Description

The exclusive write response Once the master receives an EXOKAY


AMBA_AXI_EXCLUSIVE_
response for the exclusive read, it can
WRITE_RESPONSE_MISMATCH detected should match the
expected response.
perform an exclusive write to that location.
The monitor tracks the exclusive access
and internally determines the expected
response for a particular exclusive read
access. The slave returns an EXOKAY
indicating a success or an OKAY
indicating a failure. This check fires if the
response from the slave does not match the
expected response.
In case of a SLVERR response from the
slave or interconnect during exclusive
access monitoring, this check fails as the
monitor expects only OKAY or EXOKAY
during exclusive access transactions.
AMBA_AXI_EXCLUSIVE_
WRITE_SIZE_EXCEEDS_128

The number of bytes


transferred in an exclusive
write burst should not
exceed 128.

The maximum number of bytes that can be


transferred in an exclusive burst is 128.
This check fires when this requirement is
violated.

AMBA_AXI_EXCLUSIVE_
WRITE_SIZE_NON_POWER_
OF_2

The number of bytes


transferred in an exclusive
write access should be a
power of 2.

The number of bytes to be transferred in an


exclusive access burst must be a power of
2, that is, 1, 2, 4, 8, 16, 32, 64, or 128
bytes. This check fires when this
requirement is violated.

AMBA_AXI_ILLEGAL_
LENGTH_WRAPPING_READ_
BURST

Burst length for a wrapping


read burst should be 2, 4, 8,
or 16.

The legal values of burst length in case of


wrapping read bursts are 2, 4, 8, and 16.
This check fires whenever the length
specified for a wrapping type read burst
transaction violates this requirement.

AMBA_AXI_ILLEGAL_
LENGTH_WRAPPING_WRITE_
BURST

Burst length for a wrapping


write burst should be 2, 4, 8,
or 16.

The legal values of burst length in the case


of wrapping write bursts are 2, 4, 8, and 16.
This check fires whenever the length
specified for a wrapping type write burst
transaction violates this requirement.

AMBA_AXI_ILLEGAL_
RESPONSE_EXCLUSIVE_READ

Response for an exclusive


read should not be other than
OKAY or EXOKAY.

A slave that supports exclusive operations


must return either an OKAY (to indicate a
failure) or EXOKAY (to indicate a
success). This check fires when an
exclusive read returns a response other
than OKAY and EXOKAY.

AMBA_AXI_ILLEGAL_
RESPONSE_EXCLUSIVE_
WRITE

Response for an exclusive


write should not be other
than OKAY or EXOKAY.

A slave that supports exclusive write


operations must return either an OKAY (to
indicate a failure) or EXOKAY (to indicate
a success). This check fires when an
exclusive write returns a response other
than OKAY and EXOKAY.

AMBA_AXI_ILLEGAL_
RESPONSE_NORMAL_READ

An EXOKAY response
should not be returned for a
normal (nonexclusive) read
operation.

The EXOKAY is an invalid response for


normal (nonexclusive) operations. This
check fires if an EXOKAY response is
detected for a nonexclusive read access.

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AMBA AXI
Monitor Checks

Table 5-3. AMBA AXI Monitor Checks (cont.)

90

Check ID

Violation

Description

AMBA_AXI_ILLEGAL_
RESPONSE_NORMAL_WRITE

An EXOKAY response
should not be returned for a
normal (nonexclusive) write
operation.

The EXOKAY is an invalid response for


normal (nonexclusive) operations. This
check fires if an EXOKAY response is
detected for a nonexclusive write access.

AMBA_AXI_INCORRECT_
LOW_POWER_SIGNAL_LEVEL

Any of the low power signal For low power interface disabled, the three
is not tied HIGH for disabled low power interface signals must be tied to
low power configuration.
HIGH. This check fires when any of the
low power interface signals is not sampled
HIGH.

AMBA_AXI_LOCKED_READ_
BEFORE_COMPLETION_OF_
PREVIOUS_READS

A locked read sequence


should not commence before
completion of all previously
issued read addresses.

When a master starts a locked sequence of


read transactions, it must ensure that it has
no other outstanding transactions waiting
to complete. This check fires when a
locked sequence of read transactions is
started when one or more previously issued
read transactions are waiting for response
from the slave.

AMBA_AXI_LOCKED_READ_
BEFORE_COMPLETION_OF_
PREVIOUS_WRITES

A locked read sequence


should not commence before
completion of all previously
issued write addresses.

When a master starts a locked sequence of


read transactions, it must ensure that it has
no other outstanding transactions waiting
to complete. This check fires when a
locked sequence of read transactions is
started when one or more previously issued
write transactions are waiting for response
from the slave.

AMBA_AXI_LOCKED_WRITE_
BEFORE_COMPLETION_OF_
PREVIOUS_READS

A locked write sequence


should not commence before
completion of all previously
issued read addresses.

When a master starts a locked sequence of


write transactions, it must ensure that it has
no other outstanding transactions waiting
to complete. This check fires when a
locked sequence of write transactions is
started when one or more previously issued
read transactions are waiting for response
from the slave.

AMBA_AXI_LOCKED_WRITE_
BEFORE_COMPLETION_OF_
PREVIOUS_WRITES

A locked write sequence


should not commence before
completion of all previously
issued write addresses.

When a master starts a locked sequence of


write transactions, it must ensure that it has
no other outstanding transactions waiting
to complete. This check fires when a
locked sequence of write transactions is
started when one or more previously issued
read transactions were waiting for a
response from the slave.

AMBA_AXI_NUMBER_OF_
LOCKED_READ_ACCESSES_
EXCEEDS_2

Number of accesses within a


locked read sequence should
not be more than two.

To reduce the impact of long locked read


data sequences on interconnect
performance (since no other master can
access that slave region until the current
master performs an unlocked transaction),
it is recommended to limit locked read
sequences to two transactions. Although
strictly not a violation, this check fires to
indicate locked sequences exceeding two
transactions. This check is active only
when the parameter ENABLE_
RECOMMENDATION_CHECKING is
set to 1.

Questa Verification Library Monitors Data Book, v2010.2

AMBA AXI
Monitor Checks

Table 5-3. AMBA AXI Monitor Checks (cont.)


Check ID

Violation

AMBA_AXI_NUMBER_OF_
LOCKED_WRITE_ACCESSES_
EXCEEDS_2

Number of accesses within a To reduce the impact of long locked write


locked write sequence
data sequences on interconnect
should not be more than two. performance (since no other master can
access that slave region until the current
master performs an unlocked transaction),
it is recommended to limit locked
sequences to two transactions. Although
strictly not a violation, this check fires to
indicate locked write sequences exceeding
two transactions. This check is active only
when ENABLE_
RECOMMENDATION_CHECKING is
set to 1.

AMBA_AXI_PARAM_READ_
DATA_BUS_WIDTH

READ_DATA_BUS_
WIDTH parameter should
be one of 8, 16, 32, 64, 128,
256, 512, or 1024.

The AMBA AXI specification provides for


a configurable read data bus width. The
legal values of read data bus width are 8,
16, 32, 64, 128, 256, 512, and 1024 bits.
This check fires if this requirement is
violated.

AMBA_AXI_PARAM_WRITE_
DATA_BUS_WIDTH

WRITE_DATA_BUS_
WIDTH parameter should
be one of 8, 16, 32, 64, 128,
256, 512, or 1024.

The AMBA AXI specification provides for


a configurable write data bus width. The
legal values of write data bus width are 8,
16, 32, 64, 128, 256, 512, and 1024 bits.
This check fires if this requirement is
violated.

AMBA_AXI_READ_ADDR_
BEFORE_COMPLETION_OF_
UNLOCK_TRANSACTION

The unlocking transaction of


a locked read sequence
should be completed before
further transactions are
initiated.

The master must ensure that the final


unlocking read transaction has fully
completed before any further transactions
are initiated. This check fires when this
requirement is violated.

AMBA_AXI_READ_ADDR_
CNTRL_CHANGED_BEFORE_
ARREADY

Once ARVALID is asserted,


the read address/control
signals {araddr, arlen, arsize,
arburst, arlock, arcache,
arprot, arid} should not
change until ARREADY is
asserted.

Once the master asserts ARVALID


indicating the availability of the valid read
address and control information on the bus,
it must hold these values stable until the
slave accepts them with ARREADY. This
check fires if the address/control values
change even before the slave asserts
ARREADY.

AMBA_AXI_READ_
ALLOCATE_WHEN_NON_
CACHEABLE

Read allocate bit of a read


address should not be HIGH
when the cacheable bit is
LOW.

When the read allocate bit is HIGH, it


indicates that a read access that misses
cache hit can be allocated in the cache.
This cannot be done when the access is not
cacheable in the first place. This check
fires if the attributes specified violates this
requirement.

AMBA_AXI_READ_BURST_
LENGTH_VIOLATION

Length of the read burst


detected should match the
expected length.

The number of transfers in a read burst


should equal the requested length
(ALEN+1). This check fires if the actual
number of transfers detected in a read burst
differs from the requested length.

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Description

91

AMBA AXI
Monitor Checks

Table 5-3. AMBA AXI Monitor Checks (cont.)

92

Check ID

Violation

Description

AMBA_AXI_READ_BURST_
SIZE_VIOLATION

Read burst size should not


exceed the data bus width.

The burst size indicates the maximum


number of data bytes to transfer in each
read data transfer within a burst. This must
not exceed the read data bus width of the
components in the transaction. This check
fires when this requirement is violated.

AMBA_AXI_READ_DATA_
BEFORE_ADDRESS

Read data transfer should


not be performed before the
corresponding read address.

A read data/response from a slave should


always follow the address (request from
the master). This check fires when a read
response is detected for which an
outstanding read address with AID the
same as the RID does not exist.

AMBA_AXI_READ_DATA_
RESP_CHANGED_BEFORE_
RREADY

Once RVALID is asserted,


read data/response should
not change until RREADY
is asserted.

Once the slave asserts RVALID indicating


availability of valid read data/response on
the bus, it must hold these values stable
until the master accepts them with
RREADY. This check fires if the read
data/response values change even before
the master asserts RREADY.

AMBA_AXI_READ_DATA_
UNKN

Read data should not be


driven with X or Z.

This check fires when the AXI slave


device returns X or Z on the read data bus.
The parameter
DATA_X_Z_CHECK_ENABLE controls
enabling of the check. By default, this
check is OFF. Refer to parameter
DATA_X_Z_CHECK_ENABLE for
enabling the check. This check supports
narrow transfers on the read data bus;
checks only the byte lanes that matter.

AMBA_AXI_READ_
INTERLEAVE_DEPTH_
VIOLATION

Read interleaving depth has


exceeded the allowed read
interleaving depth.

This check fires when read interleaving


depth exceeds the allowed read
interleaving depth set by the parameter
READ_INTERLEAVING_DEPTH.

AMBA_AXI_READ_REORDER_
DEPTH_VIOLATION

Read data should not be


reordered beyond the read
data reordering depth.

The read data reordering depth is a static


value that indicates the maximum
reordering capability of the slave. This
check fires if a read data is detected for
which the corresponding address is beyond
the reordering depth. This depth is
configured using
READ_REORDER_DEPTH.

AMBA_AXI_RESERVED_
ARLOCK_ENCODING

The reserved encoding of


2'b11 should not be used for
ARLOCK.

To enable the implementation of atomic


access primitives, the ARLOCK or
AWLOCK signal provides exclusive
access and locked access. The ARLOCK
signal being 2-bit wide, it indicates
whether the access is a normal / locked /
exclusive access. The unused encoding of
2'b11 is reserved. This checks if this
encoding is used and the parameter
ENABLE_RESERVED_VALUE_
CHECKING is set to 1.

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AMBA AXI
Monitor Checks

Table 5-3. AMBA AXI Monitor Checks (cont.)


Check ID

Violation

Description

AMBA_AXI_RESERVED_
AWLOCK_ENCODING

The reserved encoding of


2'b11 should not be used for
AWLOCK.

To enable the implementation of atomic


access primitives, the ARLOCK or
AWLOCK signal provides exclusive
access and locked access. The AWLOCK
signal being 2-bit wide, it indicates
whether the access is a normal / locked /
exclusive access. The unused encoding of
2'b11 is reserved. This check if this
encoding is used and the parameter
ENABLE_RESERVED_VALUE_
CHECKING is set to 1.

AMBA_AXI_RESERVED_
READ_BURST_TYPE

Read burst type encoding


should not be a reserved
value of 2'b11.

The burst-type control signals define the


type of read burst. The AXI protocol
provides for three types of read bursts:
Fixed, Incrementing, and Wrapping. This
being a 2-bit field, the unused encoding of
2'b11 is reserved. This check fires if this
encoding is used and the parameter
ENABLE_RESERVED_VALUE_
CHECKING is set to 1.

AMBA_AXI_RESERVED_
WRITE_BURST_TYPE

Write burst type encoding


should not be a reserved
value of 2'b11.

The burst-type control signals define the


type of write burst. The AXI protocol
provides for three types of write bursts:
Fixed, Incrementing, and Wrapping. This
being a 2-bit field, the unused encoding of
2'b11 is reserved. This check fires if this
encoding is used and ENABLE_
RESERVED_VALUE_CHECKING is set
to 1.

AMBA_AXI_RID_CHANGED_
BEFORE_RREADY

Once RVALID is asserted,


RID should not change until
RREADY is asserted.

Once the slave asserts RVALID indicating


availability of a valid read data on the bus,
it must hold the RID value stable until the
master accepts them with RREADY. This
check fires if the RID value changes even
before the master asserts RREADY.

AMBA_AXI_RID_UNKN

RID signal should not be X


or Z.

Checks that RID is both known (not X) and


driven (not Z). This check is active only
when RVALID is high.

AMBA_AXI_RLAST_
CHANGED_BEFORE_RREADY

Once RVALID is asserted,


RLAST should not change
until RREADY is asserted.

The slave can assert RLAST only when it


drives RVALID. Once the slave asserts
RVALID indicating availability of a valid
read data on the bus, it must hold RLAST
stable until the master accepts them with
RREADY. This check fires if RLAST is
toggled even before RREADY is sampled
asserted.

AMBA_AXI_RLAST_UNKN

RLAST signal should not be


X or Z.

Checks that RLAST is both known (not X)


and driven (not Z). This check is active
only when RVALID is high.

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AMBA AXI
Monitor Checks

Table 5-3. AMBA AXI Monitor Checks (cont.)

94

Check ID

Violation

Description

AMBA_AXI_RLAST_
VIOLATION

RLAST signal should be


asserted along with the final
transfer of the read data
burst.

In case of read accesses, the slave must


drive a burst of data and response starting
from the address issued and indicate the
final data transfer by asserting the RLAST
signal. This check fires when the RLAST
signal is not sample asserted along with the
last transfer of the read burst.

AMBA_AXI_RREADY_UNKN

RREADY signal should not


be X or Z.

Checks that RREADY is both known (not


X) and driven (not Z).

AMBA_AXI_RRESP_UNKN

RRESP signal should not be


X or Z.

Checks that RRESP is both known (not X)


and driven (not Z). This check is active
only when RVALID is high.

AMBA_AXI_RVALID_
DEASSERTED_BEFORE_
RREADY

RVALID should be held


asserted until the master
asserts RREADY.

The slave can assert RVALID only when it


drives valid data on the bus. It must be held
asserted until the master accepts the data
and indicates the same by asserting the
RREADY signal. This check fires if
RVALID is detected de-asserted (after
being sampled asserted) even before
RREADY is asserted.

AMBA_AXI_RVALID_UNKN

RVALID signal should not


be X or Z.

Checks that RVALID is both known (not


X) and driven (not Z).

AMBA_AXI_SIMULTANEOUS_
LOCK_WRITE_AND_LOCK_
READ_ACCESS

A master must not execute


This check fires is the lock write and lock
both lock write and lock read read are executed at the same time.
access at the same time.

AMBA_AXI_UNALIGNED_
ADDR_FOR_WRAPPING_
READ_BURST

Starting address of a
wrapping read burst should
be aligned to the size of the
transfer.

Wrapping read data bursts have the


restriction that the starting address must be
aligned to the size of the data transfer. This
check fires if this requirement is violated
(starting address is unaligned).

AMBA_AXI_UNALIGNED_
ADDR_FOR_WRAPPING_
WRITE_BURST

Starting address of a
wrapping write burst should
be aligned to the size of the
transfer.

Wrapping write bursts have the restriction


that the starting write address must be
aligned to the size of the data transfer. This
check fires if this requirement is violated
(starting address is unaligned).

AMBA_AXI_UNALIGNED_
ADDRESS_FOR_EXCLUSIVE_
READ

The start address of an


exclusive read should be
aligned to the total number
of bytes in the transaction.

The address of an exclusive read access


must be aligned to the total number of
bytes in the transaction. This check fires
when this requirement is violated.

AMBA_AXI_UNALIGNED_
ADDRESS_FOR_EXCLUSIVE_
WRITE

The start address of an


exclusive write should be
aligned to the total number
of bytes in the transaction.

The address of an exclusive write access


must be aligned to the total number of
bytes in the transaction. This check fires
when this requirement is violated.

Questa Verification Library Monitors Data Book, v2010.2

AMBA AXI
Monitor Checks

Table 5-3. AMBA AXI Monitor Checks (cont.)


Check ID

Violation

Description

AMBA_AXI_UNLOCKED_
READ_WHILE_
OUTSTANDING_LOCKED_
READS

All previous locked read


transactions should be
completed before unlocking
a locked read sequence.

Any transaction with ARLOCK[1:0] set to


indicate a locked sequence forces the
interconnect to lock the read transaction
that follows. Therefore, a locked sequence
must always complete with a final
transaction that does not have
ARLOCK[1:0] set to indicate a locked
access. This final transaction removes the
lock. When completing a locked sequence,
a master must ensure that all previous
locked transactions are complete before
issuing the final unlocking transaction.
This check fires when this requirement is
violated.

AMBA_AXI_UNLOCKED_
READ_WHILE_
OUTSTANDING_LOCKED_
WRITES

Unlocking read transaction


is detected while current
locked write transaction is
not yet complete.

If the bus / interconnect is locked by a


write from a master already, then the same
can be unlocked by a read or write
unlocking transaction by the same master
only after completion of the current lock
write transaction. This check fires when an
unlocking read transaction issued by a
master is detected while there is an
incomplete lock write transaction exists
issued by the same master.

AMBA_AXI_UNLOCKED_
WRITE_WHILE_
OUTSTANDING_LOCKED_
READS

Unlocking write transaction


is detected while current
locked read transaction is
not yet complete.

If the bus / interconnect is locked by a read


from a master already, then the same can
be unlocked by a read or write unlocking
transaction by the same master only after
completion of the current lock read
transaction. This check fires when an
unlocking write transaction issued by a
master is detected while there is an
incomplete lock read transaction exists
issued by the same master.

AMBA_AXI_UNLOCKED_
WRITE_WHILE_
OUTSTANDING_LOCKED_
WRITES

All previous locked write


transactions should be
completed before unlocking
a locked write sequence.

Any transaction with AWLOCK[1:0] set to


indicate a locked write sequence forces the
interconnect to lock the following write
transaction. Therefore, a locked sequence
must always complete with a final
transaction that does not have
AWLOCK[1:0] set to indicate a locked
access. This final transaction removes the
lock. When completing a locked sequence,
a master must ensure that all previous
locked transactions are complete before
issuing the final unlocking transaction.
This check fires when this requirement is
violated.

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AMBA AXI
Monitor Checks

Table 5-3. AMBA AXI Monitor Checks (cont.)

96

Check ID

Violation

Description

AMBA_AXI_UNLOCKING_
TRANSACTION_WITH_AN_
EXCLUSIVE_ACCESS

Unlocking transaction can


not be an exclusive access
transaction.

If the bus / interconnect is locked by a


write or read from a master already, then
the same can be unlocked by non-exclusive
read or write unlocking transaction by the
same master after completion of the
current lock read or lock write transaction.
This check fires when an exclusive access
unlocking transaction is tried by the same
master that already did the existing lock
access on the bus/interconnect.

AMBA_AXI_VALID_HIGH_ON_
FIRST_CLOCK

A master interface should


not drive ARVALID,
AWVALID, or WVALID on
the first rising edge of
ACLK after ARESET_n.

The AXI protocol includes a single active


LOW reset signal, ARESETn. The reset
signal can be asserted asynchronously, but
de-assertion must be synchronous after the
rising edge of ACLK. A master interface
must begin driving ARVALID,
AWVALID, or WVALID HIGH only at a
rising ACLK edge after ARESETn is
HIGH. This check fires if any of the
ARVALID, AWVALID, or WVALID
signals are asserted on the first clock after
ARESETn is HIGH.

AMBA_AXI_WID_CHANGED_
BEFORE_WREADY

Once WVALID is asserted, Once the master asserts WVALID


WID should not change until indicating availability of a valid write data
WREADY is asserted.
on the bus, it must hold the WID value
stable until the slave accepts them with
WREADY. This check fires if the WID
value changes even before the slave asserts
WREADY.

AMBA_AXI_WID_UNKN

WID signal should not be X


or Z.

Checks that WID is both known (not X)


and driven (not Z). This check is active
only when WVALID is high.

AMBA_AXI_WLAST_
CHANGED_BEFORE_WREADY

Once WVALID is asserted,


WLAST should not change
until WREADY is asserted.

The master can assert WLAST only when


it drives WVALID. Once the master
asserts WVALID indicating availability of
a valid write data on the bus, it must hold
WLAST stable until the slave accepts them
with WREADY. This check fires if
WLAST is toggled even before WREADY
is sampled asserted.

AMBA_AXI_WLAST_
ASSERTED_DURING_DATA_
PHASE_OTHER_THAN_LAST

WLAST must only be


asserted during the last data
phase

In case of write transactions, the master


must drive a burst of data starting from the
address issued with the write request and
indicate the final data transfer by asserting
the WLAST signal. This check fires when
the WLAST signal is not sample asserted
along with the last transfer of the write
burst.

AMBA_AXI_WLAST_UNKN

WLAST signal should not


be X or Z.

Checks that WLAST is both known (not


X) and driven (not Z). This check is active
only when WVALID is high.

AMBA_AXI_WREADY_UNKN

WREADY signal should not


be X or Z.

Checks that WREADY is both known (not


X) and driven (not Z).

Questa Verification Library Monitors Data Book, v2010.2

AMBA AXI
Monitor Checks

Table 5-3. AMBA AXI Monitor Checks (cont.)


Check ID

Violation

Description

AMBA_AXI_WRITE_ADDR_
BEFORE_COMPLETION_OF_
UNLOCK_TRANSACTION

The unlocking transaction of


a locked write sequence
should be completed before
further transactions are
initiated.

The master must then ensure that the final


unlocking transaction has fully completed
before any further transactions are
commenced.

AMBA_AXI_WRITE_ADDR_
CNTRL_CHANGED_BEFORE_
AWREADY

Once AWVALID is
asserted, the write
address/control signals
{awaddr, awlen, awsize,
awburst, awlock, awcache,
awprot, awid} should not
change until AWREADY is
asserted.

Once the master asserts AWVALID


indicating availability of valid write
address and control information on the bus,
it must hold these values stable until the
slave accepts them with AWREADY. This
check fires if the write address/control
values change even before the slave asserts
AWREADY.

AMBA_AXI_WRITE_ADDRESS_
PHASE_WHILE_MAXIMUM_
OUTSTANDING_WRITES_
ALREADY_REACHED

Write address phase should


not occur while maximum
allowed outstanding write
transactions are already
waiting for response.

A write address transaction requested by


an AXI Master cannot be entertained by an
AXI Slave in an AXI system where the
current number of write address
transactions waiting for write response is
equal to the maximum allowed outstanding
write transactions. This check fires when
the current number of outstanding write
address transactions is equal to the
parameter value
MAX_OUTSTANDING_WRITE_ADDR,
and a new write address transaction occurs
on the write address channel.

AMBA_AXI_WRITE_
ALLOCATE_WHEN_
NON_CACHEABLE

Write allocate bit for a write


address should not be HIGH
when the cacheable bit is
LOW.

When the write allocate bit is HIGH, it


indicates that a write access that misses a
cache hit can be allocated in the cache.
This cannot be done when the access is not
cacheable in the first place. This check
fires if the attributes specified violates this
requirement.

AMBA_AXI_WRITE_BURST_
SIZE_VIOLATION

Write burst size should not


exceed the data bus width.

The burst size indicates the maximum


number of data bytes to be written in each
data transfer within a burst. This must not
exceed the data bus width of the
components in the transaction. This check
fires when this requirement is violated.

AMBA_AXI_WRITE_DATA_
BEFORE_ADDRESS

Write data should not be


transferred before the
corresponding address.

Although the relationship between the


address and write data channels is flexible
where data can come before the address, in
simple cases the write data would follow
the corresponding address. This check fires
if write data precedes the address. This
check is active only when the parameter
CHECK_WRITE_DATA_
FOLLOWS_ADDR_ENABLE is set to 1.

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AMBA AXI
Monitor Checks

Table 5-3. AMBA AXI Monitor Checks (cont.)

98

Check ID

Violation

Description

AMBA_AXI_WRITE_DATA_
PHASE_WHILE_MAXIMUM_
OUTSTANDING_WRITES_
ALREADY_REACHED

Write data phase should not


occur while maximum
allowed outstanding write
transactions are already
waiting for response.

A write data burst transaction requested by


an AXI Master cannot be entertained by an
AXI Slave in an AXI system where the
current number of completed write data
burst transactions waiting for write
response is equal to the maximum allowed
outstanding write transactions. This check
fires when the current number of
outstanding write data burst transactions is
equal to the parameter value
MAX_OUTSTANDING_WRITE_ADDR,
and a new write data burst transaction
occurs on the write data channel.

AMBA_AXI_WRITE_DATA_
REORDER_DEPTH_VIOLATION

Write data should not be


reordered beyond the write
data reordering depth.

This check fires if the write data reordering


depth is exceeded.

AMBA_AXI_WRITE_DATA_
STROBE_CHANGED_BEFORE_
WREADY

Once WVALID is asserted,


write data/strobe should not
change until WREADY is
asserted.

Once the master asserts WVALID


indicating availability of a valid write data
on the bus, it must hold these values stable
until the slave accepts them with
WREADY. This check fires if the write
data values change even before the slave
asserts WREADY.

AMBA_AXI_WRITE_DATA_
UNKN

Write data should not be


driven with X or Z for valid
byte-lanes.

This check fires when the AXI master


interface drives X or Z on the write data
bus. The parameter
DATA_X_Z_CHECK_ENABLE controls
disabling of the check. By default, this
check is ON.
This check honors the write strobe enable
only checking the valid byte-lanes for X
and Z.

AMBA_AXI_WRITE_
INTERLEAVE_DEPTH_
VIOLATION

Write data bursts should not


be interleaved beyond the
write interleaving depth.

The slave declares a write data interleaving


depth, which is a static value that indicates
the maximum data interleaving that it can
accept. This check fires if more than the
interleaving depth number of write data
bursts are interleaved. This depth can be
configured using
WRITE_INTERLEAVING_DEPTH.

AMBA_AXI_WRITE_RESP_
CHANGED_BEFORE_BREADY

Once BVALID is asserted,


write response should not
change until BREADY is
asserted.

Once the slave asserts BVALID indicating


availability of a valid write response on the
bus, it must hold these values stable until
the master accepts them with BREADY.
This check fires if the write response
values change even before the master
asserts BREADY.

AMBA_AXI_WRITE_
RESPONSE_VALID_
WITHOUT_DATA

Write response valid should


not be sent before the
corresponding write data
burst have completed.

This check fires whenever a write response


is detected for which data has not been
already received.

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AMBA AXI
Monitor Corner Cases

Table 5-3. AMBA AXI Monitor Checks (cont.)


Check ID

Violation

Description

AMBA_AXI_WRITE_
RESPONSE_WITHOUT_ADDR

Write response should not be This check fires whenever a write response
sent before the
is detected for which the corresponding
corresponding address is
address has not been already received.
completed.
This check is active only if the
CHECK_WRITE_DATA_FOLLOWS_
ADDR_ENABLE parameter is set to 1.

AMBA_AXI_WRITE_
RESPONSE_WITHOUT_DATA

Write response should not be


sent before the
corresponding write data
burst is completed.

In case of write accesses, the slave can


issue a write response only when it has
completely received the write data. This
check fires whenever a write response is
detected for which data has not been
already received.

AMBA_AXI_WRITE_STROBE_
ON_INVALID_BYTE_LANES

Write data strobes should


not be asserted for byte lanes
that do not contain valid
data.

There is one write strobe for each eight bits


of the write data bus. A master must ensure
that the write strobes are asserted only for
byte lanes that contain valid data. This
check fires if write strobe is asserted for
any of the lanes that contain invalid data.

AMBA_AXI_WSTRB_UNKN

WSTRB signal should not


be X or Z.

Checks that WSTRB is both known (not


X) and driven (not Z). This check is active
only when WVALID is high

AMBA_AXI_WVALID_
DEASSERTED_BEFORE_
WREADY

WVALID should be held


asserted until the slave
asserts WREADY.

The master can assert WVALID only when


it drives valid write data on the bus. It must
be held asserted until the slave accepts the
data and indicates the same by asserting
the WREADY signal. This check fires if
WVALID is detected de-asserted (after
being sampled asserted) even before
WREADY is asserted.

AMBA_AXI_WVALID_UNKN

WVALID signal should not


be X or Z.

Checks that WVALID is both known (not


X) and driven (not Z).

Monitor Corner Cases


Table 5-4 shows the general checks performed by the AMBA AXI monitor.
Table 5-4. AMBA AXI Corner Cases
Corner Case

Description

Bufferable only reads

Number of bufferable only read accesses.

Bufferable only writes

Number of bufferable only write accesses.

Cacheable and bufferable but nonallocatable reads

Number of cacheable, bufferable but non allocatable read


accesses.

Cacheable and bufferable but nonallocatable writes

Number of cacheable, bufferable but non allocatable write


accesses.

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AMBA AXI
Monitor Corner Cases

Table 5-4. AMBA AXI Corner Cases (cont.)


Corner Case

Description

Cacheable but non-allocatable reads

Number of cacheable but non-allocatable read accesses.

Cacheable but non-allocatable writes

Number of cacheable but non-allocatable write accesses.

Cacheable write-back read allocate


reads

Number of cacheable write-back read allocatable read accesses.

Cacheable write-back read and write


allocatable reads

Number of cacheable write-back both read and write


allocatable read accesses.

Cacheable write-back read and write


allocatable writes

Number of cacheable write-back both read and write


allocatable write accesses.

Cacheable write-back write allocate


writes

Number of cacheable write-back write allocatable write


accesses.

Cacheable write-through read allocate Number of cacheable write-through read allocatable read
reads
accesses.
Cacheable write-through read and
write allocatable reads

Number of cacheable write-through both read and write


allocatable read accesses.

Cacheable write-through read and


write allocatable writes

Number of cacheable write-through both read and write


allocatable write accesses.

Cacheable write-through write


allocate writes

Number of cacheable write-through write allocatable write


accesses.

Exclusive read accesses

Number of exclusive read accesses.

Exclusive write accesses

Number of exclusive write accesses.

Fixed read addresses

Number of addresses for fixed read bursts.

Fixed write addresses

Number of addresses for fixed write bursts.

Incrementing read addresses

Number of addresses for incrementing read bursts.

Incrementing write addresses

Number of addresses for incrementing write bursts.

Locked read accesses

Number of locked read accesses.

Locked write accesses

Number of locked write accesses.

Narrow read transfers

Number of narrow read transfers.

Narrow write transfers

Number of narrow write transfers.

Non-cacheable non-bufferable reads

Number of non-cacheable non-bufferable read accesses.

Non-cacheable non-bufferable writes

Number of non-cacheable non-bufferable write accesses.

Normal nonsecure data read accesses

Number of normal nonsecure read data accesses. This relates to


protection levels specified by ARPROT[2:0].

Normal nonsecure data write accesses Number of normal nonsecure data write accesses. This relates
to protection levels specified by AWPROT[2:0].

100

Normal nonsecure instruction read


access

Number of normal nonsecure instruction read accesses. This


relates to protection levels specified by ARPROT[2:0].

Normal nonsecure instruction write


access

Number of normal nonsecure instruction write accesses. This


relates to protection levels specified by AWPROT[2:0].

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AMBA AXI
Monitor Corner Cases

Table 5-4. AMBA AXI Corner Cases (cont.)


Corner Case

Description

Normal read accesses

Number of unlocked, nonexclusive read accesses. This relates


to atomic access specified by ARLOCK[1:0].

Normal secure data read accesses

Number of normal secure read data accesses. This relates to


protection levels specified by ARPROT[2:0].

Normal secure data write accesses

Number of normal secure data write accesses. This relates to


protection levels specified by AWPROT[2:0].

Normal secure instruction read


accesses

Number of normal secure instruction read accesses. This relates


to protection levels specified by ARPROT[2:0].

Normal secure instruction write


accesses

Number of normal secure instruction write accesses. This


relates to protection levels specified by AWPROT[2:0].

Normal write accesses

Number of unlocked, non-exclusive write accesses. This relates


to atomic access specified by AWLOCK[1:0].

Privileged nonsecure data read


accesses

Number of privileged nonsecure read data accesse.This relates


to protection levels specified by ARPROT[2:0].

Privileged nonsecure data write


accesses

Number of privileged nonsecure data write accesses.This


relates to protection levels specified by AWPROT[2:0].

Privileged nonsecure instruction read


access

Number of privileged secure instruction read accesses. This


relates to protection levels specified by ARPROT[2:0].

Privileged nonsecure instruction write Number of privileged secure instruction write accesses. This
access
relates to protection levels specified by AWPROT[2:0].
Privileged secure data read accesses

Number of privileged secure read data accesses. This relates to


protection levels specified by ARPROT[2:0].

Privileged secure data write accesses

Number of privileged secure data write accesses. This relates to


protection levels specified by AWPROT[2:0].

Privileged secure instruction read


accesses

Number of privileged secure instruction read accesses. This


relates to protection levels specified by ARPROT[2:0].

Privileged secure instruction write


accesses

Number of privileged secure instruction write accesses. This


relates to protection levels specified by AWPROT[2:0].

Read addresses

Total number of read addresses.

Read data bursts

Number of read data bursts.

Read responses with decode error

Number of read responses with decode error.

Read responses with slave error

Number of read responses with slave error.

Simultaneous read write accesses

Number of simultaneous read and write accesses in the same


clock, in the entire simulation.

Unaligned read accesses

Number of unaligned read accesses.

Unaligned write accesses

Number of unaligned write accesses.

Wrapping read addresses

Number of addresses for wrapping read bursts.

Wrapping write addresses

Number of addresses for wrapping write bursts.

Write addresses

Total number of write addresses.

Write bursts with all data masked

Number of write data bursts with all data masked.

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AMBA AXI
Monitor Statistics

Table 5-4. AMBA AXI Corner Cases (cont.)


Corner Case

Description

Write data bursts

Number of write data bursts.

Write responses with decode error

Number of write responses with decode error.

Write responses with slave error

Number of write responses with slave error.

Monitor Statistics
Table 5-5 shows the statistics maintained by the AMBA AXI monitor.
Table 5-5. AMBA AXI Protocol Statistics
Statistic

Description

Back to back read data bursts

Number of back to back read data bursts.

Back to back write data bursts

Number of back to back write data bursts.

Cacheable write-back read allocate writes

Number of cacheable write-back read allocatable write


accesses.

Cacheable write-back write allocate reads

Number of cacheable write-back write allocatable read


accesses.

Cacheable write-through read allocate writes

Number of cacheable write-through read allocatable write


accesses.

Cacheable write-through write allocate reads

Number of cacheable write-through write allocatable read


accesses.

Exclusive access failures

Number of exclusive access failures.

Exclusive access successes

Number of exclusive access successes.

Exclusive read accesses to unsupported slave

Number of exclusive read accesses to an unsupported


slave.

Exclusive write accesses to unsupported slave

Number of exclusive write accesses to an unsupported


slave.

Incomplete exclusive accesses

Number of incomplete exclusive accesses.

Locked read sequences across 4K boundary

Number of times the read transactions within a locked


read sequence crossed the 4K address boundary.

Locked read sequences exceeding two accesses

Number of times more than two read transactions were


performed within a locked read sequence.

Locked write sequences across 4K boundary

Number of times the write transactions within a locked


write sequence crossed the 4K address boundary.

Locked write sequences exceeding two accesses Number of times more than two write transactions were
performed within a locked write sequence.

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Chapter 6
Double Data Rate SDRAM (DDR SDRAM)
Introduction
The QVL Double Data Rate SDRAM (DDR SDRAM) monitor provides a method of debugging
DDR SDRAM system designs by checking that the operation of the design is compliant with
the JEDEC standard. This monitor can also be configured for custom requirements. The
monitor can be used to guarantee that your controller design cannot perform an illegal operation
to the memory subsystem.
The DDR SDRAM monitor tracks all operations to the DDR SDRAM subsystem for a single
row of DDR SDRAMs. To check multiple memory rows, the user can instantiate multiple
instances of the DDR SDRAM monitor. Each DDR SDRAM monitor instance checks
operations on a virtual four-bank DDR SDRAM by monitoring the states of each bank, and by
setting and relaxing cycle-based timing checks on all operations on the banks.
The DDR SDRAM monitor instance determines illegal command sequences by comparing
bank-state against command issues. Checks for illegal commands and cycle-based timing
problems can be used as search targets. Use formal analysis to find legal stimulus sequences
(that is, corner-case behavior) that direct your controller design to violate legal DDR SDRAM
memory subsystem operations.

V1.0 Monitor
Reference Documentation
This DDR SDRAM monitor is modeled from the requirements provided in the following
documents:

JEDEC Standard, Double Data Rate (DDR) SDRAM Specification, JESD79,


(Release 2) JEDEC Solid State Technology Association, May 2002.

Micron, DOUBLE DATA RATE (DDR) SDRAM, 64Mb: x32 DDR SDRAM,
2M32DDR-07.p65-Rev. 9/01.

Mode Register Programming


For mode register programming, the DDR SDRAM monitor supports the following:

Burst lengths 2, 4, 8, 16, 32, 64, 128 and Full Page Mode (FPM).

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Double Data Rate SDRAM (DDR SDRAM)


V1.0 Monitor

CAS latencies 0.5, 1, 1.5, 2, 2.5, 3, and 4.

Sequential and interleaved burst types.

DLL reset, if DLL is enabled.

Normal operating mode.

The DDR SDRAM monitor does not support the following:

Interleaved burst type in Full Page Mode (FPM) burst.

Any reserved states and vendor-specific test modes.

Full Page mode burst and CAS Latency of 4 in NON JEDEC mode.

Extended Mode Register Programming


For extended mode register programming, the DDR SDRAM monitor supports the following:

DLL enable/disable.

Normal operating mode.

The DDR SDRAM monitor does not support the following:

Any reserved states.

Initialization Sequence Bypass


The DDR monitor can be used in cases where the initialization sequence is bypassed to save
simulation cycles. The parameter BYPASS_INIT determines this mode of operation as follows:

Normal mode.
By default (i.e., BYPASS_INIT = 0), the monitor tracks the initialization sequence and
validates the requirements described in the specification during the initialization
sequence. For example, the monitor fires if it does not detect at least two auto refresh
commands between a reset and an active command. In this mode, the monitor tracks the
MRS and EMRS commands and configures itself accordingly. The monitor ports
mode_register and extended_mode_register can be left unconnected.

Initialization bypass mode.


In this mode (i.e., BYPASS_INIT = 1), the monitor does not validate the requirements
described in the specification during the initialization sequence and does not track the
MRS and EMRS commands. However, for proper operation, the monitor requires the
information regarding the mode register settings. This information is passed through the
monitor ports mode_register and extended_mode_register. The values passed to
these ports must reflect the actual mode register setting in the DDR SDRAM memory.

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Double Data Rate SDRAM (DDR SDRAM)


V1.0 Monitor

Monitor Placement and Instantiation


To use the DDR SDRAM monitor, place one instance of the monitor inside the part of the
design that is searchable (a block of synthesizable code for formal analysis). For example, in a
DDR SDRAM memory controller chip design that has a DDR SDRAM memory interface for
the DDR SDRAM memory chips and an application interface for connecting other controllers,
the monitor should be instantiated inside the DDR SDRAM memory controller design with the
port signals connected to the DDR SDRAM memory interface (see Figure 6-1). Instantiations of
the DDR SDRAM monitors in a checker control file can be included.
Figure 6-1. DDR SDRAM System Implementation

Address

address
pipe

Control
control
DDR SDRAM
Memory

Application
Interface
Controller

DDR SDRAM
Memory

data
in/out

Data

DDR SDRAM Memory Controller

Monitor Connectivity
Connect the DDR SDRAM monitor pins to internal signals of the target design as specified in
the pin-out Table 6-1 and illustrated in Figure 6-2. The clock, reset, and asynchronous reset
should be available inside the target design. The remaining signals can be attached to the
outbound control and address signals of the target design.

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Double Data Rate SDRAM (DDR SDRAM)


V1.0 Monitor

Figure 6-2. DDR SDRAM Monitor Pin-Out Diagram

clock
clock_n
reset
areset
CKE[CS_CKE_WIDTH - 1:0]
CS_n[CS_CKE_WIDTH - 1:0]
RAS_n
CAS_n
WE_n
BA[1:0]
A[ADDR_WIDTH - 1:0]
DM[DM_WIDTH - 1:0]
DQ[DATA_WIDTH - 1:0]
DQS
mode_register
extended_mode_register

DDR SDRAM
Monitor

Table 6-1. DDR SDRAM Monitor Pin-Out

106

Pin

Description

A[ADDR_WIDTH 1:0]

Address.

areset

Asynchronous reset (active high).

BA[1:0]

Bank address.

CAS_n

Column address strobe (active low).

CKE[CS_CKE_WIDTH - 1:0]

Clock enable (active high).

clock

Clock (positive edge is active).

clock_n

Complementary clock, 180 degree out of phase with


clock.

CS_n[CS_CKE_WIDTH - 1:0]

Chip select (active low).

DM[DM_WIDTH - 1:0]

Data mask lines (active high).

DQ[DATA_WIDTH - 1:0]

Data lines.

DQS

Data strobe.

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Double Data Rate SDRAM (DDR SDRAM)


V1.0 Monitor

Table 6-1. DDR SDRAM Monitor Pin-Out (cont.)


Pin

Description

extended_mode_register[ADDR_WIDTH 1:0]

Extended mode register input. Leave this port


unconnected if BYPASS_INIT = 0. The width of this
register is equal to ADDR_WIDTH + Bank Address
width (i.e., 2). This width reflects the actual width of the
mode register in DDR SDRAM memory.

mode_register[ADDR_WIDTH +1:0]

Mode register input. Leave this port unconnected if


BYPASS_INIT = 0. The width of this register is equal to
ADDR_WIDTH + Bank Address width (i.e., 2). This
width reflects the actual width of the mode register in
DDR SDRAM memory.

RAS_n

Row address strobe (active low).

reset

Reset (active high).

WE_n

Write enable (active low).

Note that the timing value between a WRITE command and the first DQS latching transition is
called the tdqss value. For formal analysis, the DDR SDRAM monitor only supports tdqss
values equal to the clock period. This means that the DQS signal edges should be in line with
the clock signal for formal analysis. The monitor supports tdqss values from 75% to 125% of
the total clock period.

DDR SDRAMs Stacking


If the memory controller supports n stacked DDR SDRAMs (with data widths width and
memory sizes mem), then connect the monitors as follows (see Figure 6-3 and Figure 6-4):

If the memory controller supports n DDR SDRAMs stacked by data width (for a total
data width of n x width and memory size mem), then connect only one instance of the
monitor to track the controller. Set the CS_CKE_WIDTH parameter to the width of the
CS_n and CKE pins.

If the memory controller supports n DDR SDRAMs stacked by address width (for a
total data width of width and memory size n x mem), then connect n instances of the
monitor to track the controller. The CS_n and CKE pins of each monitor are connected
to the appropriate bits of the controllers chip select and clock enable pins.

Use the above scheme also when stacking by both data width and address width.

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Double Data Rate SDRAM (DDR SDRAM)


V1.0 Monitor

Figure 6-3. Stacking DDR SDRAMs by Data Width


Data

DDR SDRAM
Memory Controller

DDR SDRAM
Monitor

Address

...

DDR SDRAM
Memory #1

DDR SDRAM
Memory #2

...

DDR SDRAM
Memory #n

Figure 6-4. Stacking DDR SDRAMs by Address Width


Data

DDR SDRAM
Memory Controller

DDR SDRAM
Memory #1

Address

DDR SDRAM
Memory #2

...

...

DDR SDRAM
Monitor

Address

...

DDR SDRAM
Monitor

DDR SDRAM
Monitor

Address

DDR SDRAM
Memory #n

Monitor Parameters
The parameters shown in Table 6-2 configure the corresponding DDR SDRAM monitor. The
override parameters set timing parameters for the monitor. Refer to Table 6-5 for the JEDEC
standard compliant values of the parameters, which are used as default values.
Table 6-2. DDR SDRAM Monitor Parameters
Order

Parameter

Default Description

1.

Constraints_Mode

108

Set to 1 if the checks in the monitor are to be used


as constraints for formal analysis.

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Double Data Rate SDRAM (DDR SDRAM)


V1.0 Monitor

Table 6-2. DDR SDRAM Monitor Parameters (cont.)


Order

Parameter

Default Description

2.

CONTROLLER_SIDE

Set this parameter to 1 if the monitor is


instantiated on the DDR SDRAM controller side.
This parameter and the Constraints_Mode
parameter turn all checks in the monitor to
constraints (checks those connected on the input
signals to the controller) or targets (checks those
connected on output signals from the controller),
and checks those connected on the bidirectional
signals during formal analysis.

3.

CS_CKE_WIDTH

Width of chip select and clock enable signals.


Only use a nondefault value if all devices in the
stack are accessed simultaneously.

4.

ADDR_WIDTH

12

Width of address bus signals. Minimum value for


this parameter is 12. If your designs ADDR
WIDTH is less than 12, then for the upper address
lines of the monitor that are not available in the
design, connect with 1'b0.

5.

DM_WIDTH

Width of data mask signal.

6.

DATA_WIDTH

Width of data bus signals. Minimum value for this


parameter is 4.

7.

DLL_TRACKING_ENABLE

Set this parameter to 1 to enable the


DDR_SDRAM_no_dll_reset and
DDR_SDRAM_violates_tDLL checks.

8.

TRC_OVERRIDE

RAS# cycle timeminimum time interval


between successive ACTIVE commands to the
same bank. Set this parameter to 0 if you want the
JEDEC default value to be used.

9.

TRAS_OVERRIDE

RAS# active timeminimum time to precharge a


bank after it was previously issued an ACTIVE
command without losing read/write data. Set this
parameter to 0 if you want the JEDEC default
value to be used.

10.

TRP_OVERRIDE

RAS# precharge timeminimum time to


precharge a bank. Set this parameter to 0 if you
want the JEDEC default value to be used.

11.

TRCD_OVERRIDE

RAS# to CAS# delayminimum time to legally


issue a READ or WRITE command to a row after
opening it by issuing an ACTIVE command. Set
this parameter to 0 if you want the JEDEC default
value to be used.

12.

TRRD_OVERRIDE

RAS# to RAS# bank activate delayminimum


time interval between successive ACTIVE
commands to different banks. Set this parameter to
0 if you want the JEDEC default value to be used.

13.

TMRD_OVERRIDE

MODE REGISTER SET command cycle time


minimum time interval for any new command
issue after the MODE REGISTER SET command
was previously issued. Set this parameter to 0 if
you want the JEDEC default value to be used.

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V1.0 Monitor

Table 6-2. DDR SDRAM Monitor Parameters (cont.)


Order

Parameter

Default Description

14.

TRFC_OVERRIDE

AUTO REFRESH to ACTIVE command time


minimum time between AUTO REFRESH
command and an ACTIVE command to any bank.
Set this parameter to 0 if you want the JEDEC
default value to be used.

15.

TXSNR_OVERRIDE

SELF REFRESH to non-READ command time


minimum time interval between SELF REFRESH
command to any non-READ command to any
bank. Set this parameter to 0 if you want the
JEDEC default value to be used.

16.

TXSRD_OVERRIDE

SELF REFRESH to READ command time


minimum time interval between SELF REFRESH
command to a READ command to any bank. Set
this parameter to 0 if you want the JEDEC default
value to be used.

17.

TWR_OVERRIDE

WRITE burst end to PRECHARGE time


(minimum time interval between WRITE burst
end to PRECHARGE command). Set this
parameter to 0 if you want the JEDEC default
value to be used.

18.

TWTR_OVERRIDE

WRITE burst end to READ command time.


Minimum time interval between a WRITE burst
end to the READ command issue. Set this
parameter to 0 if you want the JEDEC default
value to be used.

19.

AUTOPRECHARGE_ENABLE_
ADDRESS_BIT

10

Bit-index specifying the auto precharge address


line. The address bit, specified by this parameter,
is used to enable/disable the auto precharge
function during a Read or Write command. This is
also used to decode a Single bank precharge and
all banks precharge during a precharge command
issue.

20.

COL_ADDRESS_WIDTH

Number of Column address lines. This parameter


is used to decode the size of the full page for Full
Page Mode (FPM) burst.

21.

READ_BEFORE_WRITE_
CHECK_ENABLE

Enables the check that ensures no read is


performed to a location when there was no
previous write to the same location. Set this
parameter to 0 to disable this check. Check ID:
DDR_SDRAM_read_before_write.

22.

CON_AUTO_PRECHARGE

Set this parameter to 1 if the device in which the


monitor is instantiated supports Concurrent Auto
Precharge. By default, the monitor assumes that
the device in which it is instantiated does not
support Concurrent Auto Precharge.

23.

ENABLE_WHY_PRECHARGE_
AN_IDLE_BANK

Set this parameter to 1 to enable the check that


ensures a PRECHARGE command is not issued to
an idle bank. By default, this check (Check ID:
DDR_SDRAM_why_precharge_an_idle_bank) is
turned off.

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V1.0 Monitor

Table 6-2. DDR SDRAM Monitor Parameters (cont.)


Order

Parameter

Default Description

24.

BYPASS_INIT

Set this parameter to 1 to bypass the initialization


sequence. If this parameter is set to 1, then the
complete initialization sequence need not be
performed. Nevertheless, valid operational values
must be passed to the mode register and extended
mode register inputs (otherwise, the monitor
behavior is undefined. By default, the monitor
requires the proper initialization sequence to be
performed as stated in the specification.

25.

NON_JEDEC

Set this parameter to 1 to enable the usage of the


non JEDEC values for the configuration of Burst
length, CAS Latency, and timing parameters. By
default, use of JEDEC values are only allowed.

26.

DATA_CHECK_ENABLE

This parameter enables or disables the following


data integrity checks: DDR_SDRAM_bad_data
and DDR_SDRAM_read_before_write.
Set this parameter to 1 to enable the data integrity
checks.
Setting to 0 removes the checks by completely
removing the data-checker module,
qvl_ddr_sdram_data_checker.

The parameters must be specified in the above order.


Time is measured in terms of number of clock cycles.

Programming the DQS Delay


Note the following about the `define compiler directive:
Name: QVL_DQS_DELAY
Default: 2
Description:
This is used to delay the DQS signal during read cycles in order to align the DQS signal edges at
the center of the DQ signal to guarantee the proper latching of DQ.
By default, the DQS signal is delayed by 2 time units (i.e., #2) internally.
The user should override this with a larger value if the DQS signal that is driven by the DDR
Memory should be delayed more than #2 to guarantee proper DQ latching.

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Double Data Rate SDRAM (DDR SDRAM)


V1.0 Monitor

JEDEC Mode
Full Page mode burst can be configured only in JEDEC mode (that is, when NON_JEDEC = 0).
When NON_JEDEC =1, the Burst Length configuration is as shown in Table 6-3.
Table 6-3. JEDEC Mode Burst Length Configuration
A[2:0]

BURST LENGTH

000

RSVD

001

010

011

100

16

101

32

110

64

111

128

CAS latency of 4 can be configured only in JEDEC mode (that is, when NON_JEDEC = 0).
When NON_JEDEC =1, the CAS Latency configuration is as shown in Table 6-4.
Table 6-4. JEDEC Mode CAS Latency Configuration
A[6:4]

CAS LATENCY

000

RSVD

001

1.0

010

2.0

011

3.0

100

0.5

101

1.5

110

2.5

111

RSVD

When constraints mode is disabled, all checks are used as targets during formal analysis. To use
the checks as constraints for formal analysis, do the following:

112

Set the Constraints_Mode parameter to 1.

Set the CONTROLLER_SIDE parameter as follows:

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Double Data Rate SDRAM (DDR SDRAM)


V1.0 Monitor
o

If the monitor is instantiated in the DDR SDRAM controller, then set


CONTROLLER_SIDE to 1.

If the monitor is instantiated in the DDR SDRAM memory, then set


CONTROLLER_SIDE to 0.

Table 6-5. JEDEC Standard Compliant Timing


Timing Parameter

JEDEC Standard Timing Value

TRC_OVERRIDE

TRAS_OVERRIDE

TRP_OVERRIDE

TRCD_OVERRIDE

TRRD_OVERRIDE

TMRD_OVERRIDE

TRFC_OVERRIDE

10

TXSNR_OVERRIDE

10

TXSRD_OVERRIDE

200

TWR_OVERRIDE

TWTR_OVERRIDE

Time is measured by an integer number of clock cycles.

Instantiation Examples
Example 1
Example 6-1 instantiates a JEDEC standard compliant DDR SDRAM monitor on the DDR
SDRAM controller side for unconstraint search with CS_CKE_WIDTH of 1, ADDR_WIDTH of 12,
DM_WIDTH of 1, DATA_WIDTH of 8, 8th bit of Address line as Auto precharge enable, Lower 8
Column Address lines are to be used for Full Page Mode burst, and DLL_TRACKING_ENABLE set
to 1.
Note that all timing parameters are the default values specified by JEDEC. The monitor is in
normal mode of operation, which enables the monitor to track the initialization sequence.
Example 6-1. DDR SDRAM Monitor Instantiated in the Controller
qvl_ddr_sdram_monitor
#( /* Constraints_Mode */
/* CONTROLLER_SIDE */
/* CS_CKE_WIDTH */
/* ADDR_WIDTH */
/* DM_WIDTH */

0,
1,
1,
12,
1,

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Double Data Rate SDRAM (DDR SDRAM)


V1.0 Monitor
/* DATA_WIDTH */
8)
DDR_SDRAM_MONITOR0 (
.clock
(clock),
.clock_n
(clock_n),
.reset
(reset),
.areset
(areset),
.CKE
(clock_enable_1),
.CS_n
(chip_select_1_n),
.RAS_n
(row_address_strobe_n),
.CAS_n
(column_address_strobe_n),
.WE_n
(write_enable_n),
.BA
(bank_address),
.A
(address_bus_12),
.DM
(data_mask_1),
.DQ
(data_bus_8),
.DQS
(data_strobe)
.mode_register (),
.extended_mode_register ());

Example 2
Example 6-2 instantiates two DDR SDRAM monitors for a JEDEC standard DDR SDRAM
controller design. The example has the following characteristics:

The controller design interfaces two stacked DDR SDRAMs, each having 16 bits of
DATA_WIDTH to form a 32-bit data bus.

The other input signals widths are as follows:


of 4, two for each row of DDR SDRAMs. One monitor is required
for each row of DDR SDRAM.

CS_CKE_WIDTH

ADDR_WIDTH

DM_WIDTH

of 12.

of 4, one for each byte of data.

The DLL tracking is enabled. Hence the DLL_TRACKING_ENABLE parameter is set to 1.

The monitor is instantiated for unconstrained formal analysis. Therefore, the


Constraints_Mode parameter is set to 0.

Initialization sequence tracking is enabled (by default).


Example 6-2. Two DDR SDRAM Monitors

qvl_ddr_sdram_monitor
#( /* Constraints_Mode */
/* CONTROLLER_SIDE */
/* CS_CKE_WIDTH */
/* ADDR_WIDTH */
/* DM_WIDTH */
/* DATA_WIDTH */
DDR_SDRAM_MONITOR0 (
.clock
(clock),

114

0,
1,
2,
12,
2,
16)

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Double Data Rate SDRAM (DDR SDRAM)


V1.0 Monitor
.clock_n
(clock_n),
.reset
(reset),
.areset
(areset),
.CKE
(clock_enable_4[1:0]),
.CS_n
(chip_select_4_n[1:0]),
.RAS_n
(row_address_strobe_n),
.CAS_n
(column_address_strobe_n),
.WE_n
(write_enable_n),
.BA
(bank_address),
.A
(address_bus_12),
.DM
(data_mask_4[1:0]),
.DQ
(data_bus_32[15:0]),
.DQS
(data_strobe),
.mode_register (),
.extended_mode_register () ;
qvl_ddr_sdram_monitor
#( /* Constraints_Mode */ 0,
/* CONTROLLER_SIDE */
1,
/* CS_CKE_WIDTH */
2,
/* ADDR_WIDTH */
12,
/* DM_WIDTH */
2,
/* DATA_WIDTH */
16)
DDR_SDRAM_MONITOR1 (
.clock
(clock),
.clock_n
(clock_n),
.reset
(reset),
.areset
(areset),
.CKE
(clock_enable_4[3:2]),
.CS_n
(chip_select_4_n[3:2]),
.RAS_n
(row_address_strobe_n),
.CAS_n
(column_address_strobe_n),
.WE_n
(write_enable_n),
.BA
(bank_address),
.A
(address_bus_12),
.DM
(data_mask_4[3:2]),
.DQ
(data_bus_32[31:16]),
.DQS
(data_strobe),
.mode_register (),
.extended_mode_register () ;

Example 3
Example 6-3 instantiates a DDR SDRAM monitor for a Micron 64 Mb compatible controller
design. The example has the following characteristics:

The controller design interfaces a DDR SDRAM having 32-bit DATA_WIDTH and 11-bit
ADDR_WIDTH.

The other input signals widths are as follows:


o

1-bit CS_CKE_WIDTH.

DM_WIDTH

of 4, one for each byte of data.

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V1.0 Monitor

DLL tracking is enabled. Therefore, the DLL_TRACKING_ENABLE parameter is set to 1.

The timing parameter values are as follows:


TRC
10
TRFC
11

TRAS
7
TXSNR
10

TRP
3
TXSRD
200

TRCD
3
TWR
2

TRRD
2
TWTR
1

TMRD
2

Autoprecharge is enabled through address bit 8; therefore, the


AUTOPRECHARGE_ENABLE_ADDRESS_BIT parameter is 8.

FPM mode is supported. FPM size is 256 and the number of address lines required to
burst up to 256 is 8. Therefore, the COL_ADDRESS_WIDTH is set to 8.

The DLL tracking is enabled. Therefore, the DLL_TRACKING_ENABLE parameter is set to


1.

The monitor is instantiated for unconstrained search. Therefore, the Constraints_Mode


parameter is set to 0.
Example 6-3. DDR SDRAM Monitor Instantiated in the Controller

qvl_ddr_sdram_monitor
#( /* Constraints_Mode */
0,
/* CONTROLLER_SIDE */
1,
/* CS_CKE_WIDTH */
1,
/* ADDR_WIDTH */
12,
/* DM_WIDTH */
1,
/* DATA_WIDTH */
8,
/* DLL_TRACKING_ENABLE */
1,
/* TRC_OVERRIDE */
10,
/* TRAS_OVERRIDE */
7,
/* TRP_OVERRIDE */
3,
/* TRCD_OVERRIDE */
3,
/* TRRD_OVERRIDE */
2,
/* TMRD_OVERRIDE */
2,
/* TRFC_OVERRIDE */
11,
/* TXSNR_OVERRIDE */
10,
/* TXSRD_OVERRIDE */
200,
/* TWR_OVERRIDE */
2,
/* TWTR_OVERRIDE */
1,
/* AUTOPRECHARGE_ENABLE_ADDRESS_BIT */ 8,
/* COL_ADDRESS_WIDTH */
8,
/* READ_BEFORE_WRITE_CHECK_ENABLE */
1,
/* CON_AUTO_PRECHARGE */
0,
/* ENABLE_WHY_PRECHARGE_AN_IDLE_BANK */0,
/* BYPASS_INIT*/
1)
DDR_SDRAM_MONITOR0 (
.clock
(clock),
.clock_n
(clock_n),
.reset
(reset),
.areset
(areset),
.CKE
(clock_enable),
.CS_n
(chip_select_n),

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V1.0 Monitor
.RAS_n
(row_address_strobe_n),
.CAS_n
(column_address_strobe_n),
.WE_n
(write_enable_n),
.BA
(bank_address),
.A
(address_bus_11),
.DM
(data_mask_4),
.DQ
(data_bus_32),
.DQS
(data_strobe),
.mode_register
(internal_mode_register),
.extended_mode_register (internal_mode_register) );

The monitor is instantiated with BYPASS_INIT = 1 and the internal signals are connected to
the monitor ports mode_register and extended_mode_register.

Example 4
Example 6-4 on page 117 instantiates a DDR SDRAM monitor to check a controller with NON
JEDEC timing parameter values. The example has the following characteristics:

The controller design interfaces a DDR SDRAM having 32-bit DATA_WIDTH and 11-bit
ADDR_WIDTH.

The other input signals widths are as follows:


o

1-bit CS_CKE_WIDTH.

DM_WIDTH

of 4, one for each byte of data.

DLL tracking is enabled. Therefore, the DLL_TRACKING_ENABLE parameter is set to 1.

The timing parameters are set to NON JEDEC values. Therefore, the NON_JEDEC
parameter is 1. The NON JEDEC timing parameter values are as follows
TRC
12
TRFC
16

TRAS
9
TXSNR
14

TRP
4
TXSRD
300

TRCD
4
TWR
3

TRRD
5
TWTR
1

TMRD
3

Autoprecharge is enabled through address bit 8. Therefore, the


AUTOPRECHARGE_ENABLE_ADDRESS_BIT parameter is 8.

The DLL tracking is enabled. Therefore, the DLL_TRACKING_ENABLE parameter is set to


1.

The monitor is instantiated for unconstrained search. Therefore, the Constraints_Mode


parameter is set to 0.

Example 6-4. DDR SDRAM Monitor Instantiated with NON JEDEC Timing
Parameter Values
qvl_ddr_sdram_monitor
#( /* Constraints_Mode */
/* CONTROLLER_SIDE */

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0,
1,

117

Double Data Rate SDRAM (DDR SDRAM)


V1.0 Monitor
/* CS_CKE_WIDTH */
1,
/* ADDR_WIDTH */
12,
/* DM_WIDTH */
1,
/* DATA_WIDTH */
8,
/* DLL_TRACKING_ENABLE */
1,
/* TRC_OVERRIDE */
12,
/* TRAS_OVERRIDE */
9,
/* TRP_OVERRIDE */
4,
/* TRCD_OVERRIDE */
4,
/* TRRD_OVERRIDE */
5,
/* TMRD_OVERRIDE */
3,
/* TRFC_OVERRIDE */
16,
/* TXSNR_OVERRIDE */
14,
/* TXSRD_OVERRIDE */
300,
/* TWR_OVERRIDE */
3,
/* TWTR_OVERRIDE */
1,
/* AUTOPRECHARGE_ENABLE_ADDRESS_BIT */ 8,
/* COL_ADDRESS_WIDTH */
8,
/* READ_BEFORE_WRITE_CHECK_ENABLE */
1,
/* CON_AUTO_PRECHARGE */
0,
/* ENABLE_WHY_PRECHARGE_AN_IDLE_BANK */0,
/* BYPASS_INIT*/
1,
/* NON_JEDEC*/
1)
DDR_SDRAM_MONITOR0 (
.clock
(clock),
.clock_n
(clock_n),
.reset
(reset),
.areset
(areset),
.CKE
(clock_enable),
.CS_n
(chip_select_n),
.RAS_n
(row_address_strobe_n),
.CAS_n
(column_address_strobe_n),
.WE_n
(write_enable_n),
.BA
(bank_address),
.A
(address_bus_11),
.DM
(data_mask_4),
.DQ
(data_bus_32),
.DQS
(data_strobe),
.mode_register (internal_mode_register),
.extended_mode_register (internal_mode_register) );

The monitor is instantiated with BYPASS_INIT = 1 and internal signals are connected to the
monitor ports mode_register and extended_mode_register.

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V1.0 Monitor

Monitor Checks
Table 6-6 shows the checks performed by a DDR SDRAM monitor.
Table 6-6. DDR SDRAM Monitor Checks
Check ID

Violation

Description

DDR_SDRAM_ADDRESS

Address bus, A, has a X or Z


value.

Address bus, A, should have a valid


value when mode register
set/extended mode register
set/read/write/read with auto
precharge/write with auto
precharge/bank activation command is
issued.

DDR_SDRAM_BA

Bank address bus, BA, has a X Bank address bus, BA, should have a
or Z value.
valid value when read/write/read with
auto precharge/write with auto
precharge/bank activation/single bank
precharge command is issued.

DDR_SDRAM_BYPASS_INIT

BYPASS_INIT should be
either 1 or 0.

The value of the BYPASS_INIT


parameter should be either 1 or 0.

DDR_SDRAM_CAS_n

Column address strobe,


CAS_n, has a X or Z value.

Column address strobe, CAS_n, must


always have a valid value. This check
is active only if CKE is high and CS_n
is low.

DDR_SDRAM_CKE

Clock enable, CKE, has a X or


Z value.

Clock enable, CKE, must always have


a valid value.

DDR_SDRAM_Constraint_Mode

Constraints_Mode should be
either 1 or 0.

The value of the Constraints_Mode


parameter should be either 1 or 0.

DDR_SDRAM_CONTROLLER_
SIDE

CONTROLLER_SIDE should The value of the


be either 1 or 0.
CONTROLLER_SIDE parameter
should be either 1 or 0.

DDR_SDRAM_CS_CKE_WIDTH

Chip select (cs_n) and clock


The value of CS_CKE_WIDTH
enable (cke) widths should not parameter should not be specified to
be less than the minimum
be less than 1.
limit of 1.

DDR_SDRAM_CS_n

Chip select, CS_n, has a X or


Z value.

Chip select, CS_n, must always have a


valid value. This check is active only
if CKE is high.

DDR_SDRAM_DATA_WIDTH

Data bus width should not be


less than the minimum limit of
4.

The value of the DATA_WIDTH


parameter should not be specified to
be less than 4.

DDR_SDRAM_DLL_TRACKING_
ENABLE

DLL_TRACKING_ENABLE
should be either 1 or 0.

The value of the


DLL_TRACKING_ENABLE
parameter should be either 1 or 0.

DDR_SDRAM_DM

Data mask, DM, has a X or Z


value.

Data mask, DM, must always have a


valid value. This check is active only
if CKE is high and a valid write data
phase is in progress.

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V1.0 Monitor

Table 6-6. DDR SDRAM Monitor Checks (cont.)


Check ID

Violation

Description

DDR_SDRAM_DM_WIDTH

Data mask width should not


be less than the minimum
limit of 1.

The value of the DM_WIDTH


parameter should not be less than 1.

DDR_SDRAM_incorrect_
command_before_mode_reg_set

A command that should not be


issued before the mode
register set command is
issued.

This check is applicable only if


BYPASS_INIT is set to 0 (i.e., a
proper MRS cycle is performed).
NOP, precharge, and refresh are the
only commands that are valid before
the MODE REGISTER SET. You
should check the designs reset
sequencing.

DDR_SDRAM_invalid_burst_
length

The burst length field of the


input mode register is invalid.

This check is applicable only if


BYPASS_INIT is set and
NON_JEDEC is 0. As per the JEDEC
specification, the valid burst length
values are 2 (3'b001), 4 (3'b010), 8
(3'b011), and Full Page Mode (FPM)
(3'b111). This check fires if a burst
length value other than the ones listed
above is passed through the
mode_register input.

DDR_SDRAM_invalid_burst_
length_value_in_mode_reg_set

Invalid burst length value


during mode register set
command.

This check is applicable only when the


NON_JEDEC parameter is set to 0. As
per the JEDEC specification, the valid
burst length values are 2 (3'b001), 4
(3'b010), 8 (3'b011), and Full Page
Mode (FPM) (3'b111). This check
fires if a burst length value other than
the ones listed above is programmed.

DDR_SDRAM_invalid_cas_latency

The CAS latency field of the


input mode register is invalid.

This check is applicable only if


BYPASS_INIT is set and
NON_JEDEC is 0. As per the JEDEC
specification, the valid CAS latency
values are 1.5 (3'b101), 2 (3'b010), 2.5
(3'b110), 3 (3'b011) and 4 (3'b100).
This check fires if a CAS latency
value other than the ones listed above
is passed through the mode_register
input.

DDR_SDRAM_invalid_cas_
latency_value_in_mode_reg_set

Invalid CAS latency value


during mode register set
command.

This check is applicable only when the


NON_JEDEC parameter is set to 0. As
per the JEDEC specification, the valid
CAS latency values are 1.5 (3'b101), 2
(3'b010), 2.5 (3'b110), 3 (3'b011), and
4 (3'b100). This check fires if a CAS
latency value other than the ones listed
above is programmed.

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V1.0 Monitor

Table 6-6. DDR SDRAM Monitor Checks (cont.)


Check ID

Violation

Description

DDR_SDRAM_invalid_operating_
mode

The operating mode field in


the mode register or extended
mode register input is invalid.

This check is applicable only if


BYPASS_INIT is set and an incorrect
value is passed to the mode_register
input. As per the JEDEC specification,
for normal operation, A[11:7] should
be either 5'b00000 or 5'b00010 in the
mode register and A[11:3] should be
9'b000000000 in the extended mode
register. EXTENDED MODE
REGISTER SET command. This
check fires if values other than the
above are passed to the corresponding
inputs.

DDR_SDRAM_invalid_operating_
mode_bits_mrs_or_emrs

Invalid operating mode bits


are programmed during the
mode register set or extended
mode register set command.

As per the JEDEC specification, for


normal operation, A[11:7] should be
either 5'b00000 or 5'b00010 during
MODE REGISTER SET command,
and A[11:3] should be 9'b000000000
during EXTENDED MODE
REGISTER SET command. This
check fires if a value other than the
ones listed above is driven on address
bus (A) during MODE REGISTER
SET or EXTENDED MODE
REGISTER SET command is issued.

DDR_SDRAM_RAS_n

Row address strobe, RAS_n,


has a X or Z value.

Row address strobe, RAS_n, must


always have a valid value. This check
is active only if CKE is high and CS_n
is low.

DDR_SDRAM_TMRD

TMRD value should not be


less than the minimum limit of
2.

This check is applicable only when the


NON_JEDEC parameter is set to 0.
The value of the TMRD timing
parameter should not be specified to
be less than 2.

DDR_SDRAM_TRAS

TRAS value should not be less This check is applicable only when the
than the minimum limit of 6.
NON_JEDEC parameter is set to 0.
The value of the TRAS timing
parameter should not be specified to
be less than 6.

DDR_SDRAM_TRC

TRC value should not be less


than the minimum limit of 9.

This check is applicable only when the


NON_JEDEC parameter is set to 0.
The value of the TRC timing
parameter should not be specified to
be less than 9.

DDR_SDRAM_TRCD

TRCD value should not be


less than the minimum limit of
3.

This check is applicable only when the


NON_JEDEC parameter is set to 0.
The value of the TRCD timing
parameter should not be specified to
be less than 3.

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V1.0 Monitor

Table 6-6. DDR SDRAM Monitor Checks (cont.)


Check ID

Violation

Description

DDR_SDRAM_TRFC

TRFC value should not be less


than the minimum limit of 10.

This check is applicable only when the


NON_JEDEC parameter is set to 0.
The value of the TRFC timing
parameter should not be specified to
be less than 10.

DDR_SDRAM_TRP

TRP value should not be less


than the minimum limit of 3.

This check is applicable only when the


NON_JEDEC parameter is set to 0.
The value of the TRP timing
parameter should not be specified to
be less than 3.

DDR_SDRAM_TRRD

TRRD value should not be


less than the minimum limit of
2.

This check is applicable only when the


NON_JEDEC parameter is set to 0.
The value of the TRRD timing
parameter should not be specified to
be less than 2.

DDR_SDRAM_TWR

TWR value should not be less


than the minimum limit of 2.

This check is applicable only when the


NON_JEDEC parameter is set to 0.
The value of the TWR timing
parameter should not be specified to
be less than 2.

DDR_SDRAM_TXSNR

TXSNR value should not be


less than the minimum limit of
10.

This check is applicable only when the


NON_JEDEC parameter is set to 0.
The value of the TXSNR timing
parameter should not be specified to
be less than 10.

DDR_SDRAM_TXSRD

TXSRD value should not be


less than the minimum limit of
200.

This check is applicable only when the


NON_JEDEC parameter is set to 0.
The value of the TXSRD timing
parameter should not be specified to
be less than 200.

DDR_SDRAM_violates_tRRD

An activate command is
issued too quickly after the
prior activate command.

The command just issued violates


tRRD (RAS to RAS delay timing).
This is an ACTIVATE command
issued too quickly after the
ACTIVATE command for another
bank. You should determine why the
commands are too close together.

DDR_SDRAM_WE_n

Write enable, WE_n, has a X


or Z value.

Write enable, WE_n, must always


have a valid value. This check is
active only if CKE is high and CS_n is
low.

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V1.0 Monitor

Table 6-7 shows the checks for each bank performed by a DDR SDRAM monitor.
Table 6-7. DDR SDRAM Monitor Checks for Each Bank
Check ID

Violation

Description

DDR_SDRAM_ADDRESS

Address bus, A, has a X or Z


value.

Address bus, A, should have a valid


value when mode register
set/extended mode register
set/read/write/read with auto
precharge/write with auto
precharge/bank activation
command is issued.

DDR_SDRAM_BA

Bank address bus, BA, has a X or


Z value.

Bank address bus, BA, should have


a valid value when read/write/read
with auto precharge/write with auto
precharge/bank activation/single
bank precharge command is issued.

DDR_SDRAM_bad_data

One or more bytes of data read


from the addressed DDR
SDRAM location did not match
the data byte(s) written to the
corresponding address.

Data read from the DDR SDRAM


did not match the data written to the
corresponding address. The data
check is performed only on reads to
locations that were previously
written at least once. Data checking
is done on a byte basis and the
bitmap indicates the data
inconsistency between the
corresponding bytes. This check
fires when at least one byte of read
data does not match the
corresponding valid data byte that
was written to that location.

DDR_SDRAM_CAS_n

Column address strobe, CAS_n,


has a X or Z value.

Column address strobe, CAS_n,


must always have a valid value.
This check is active only if CKE is
high.

DDR_SDRAM_CKE

Clock enable, CKE, has a X or Z


value.

Clock enable, CKE, must always


have a valid value.

DDR_SDRAM_con_auto_
precharge_min_delay_violation

Concurrent Auto Precharge


minimum delay violation.

Some devices support the


Concurrent Auto Precharge feature
such that when a read with auto
precharge or write with auto
precharge is enabled to one bank,
then any command to other banks
can be issued as long as this
command does not interrupt the
earlier command. The minimum
delay between the read/write
command with auto precharge to a
command to a different bank has to
be met in this case. This check fires
when the minimum delay in terms
of a clock cycle is violated. This
check is enabled only if the
CON_AUTO_PRECHARGE
parameter is set to 1.

Questa Verification Library Monitors Data Book, v2010.2

123

Double Data Rate SDRAM (DDR SDRAM)


V1.0 Monitor

Table 6-7. DDR SDRAM Monitor Checks for Each Bank (cont.)

124

Check ID

Violation

Description

DDR_SDRAM_Constraints_Mode

Constraints_Mode should be
either 1 or 0.

The value of Constraints_Mode


parameter value should be either 1
or 0.

DDR_SDRAM_CONTROLLER_
SIDE

CONTROLLER_SIDE should be
either 1 or 0.

The value of
CONTROLLER_SIDE parameter
value should be either 1 or 0.

DDR_SDRAM_CS_CKE_WIDTH

Chip select (cs_n) and clock


enable (cke) widths should not be
less than the minimum limit of 1.

The value of CS_CKE_WIDTH


parameter should not be specified to
be less than 1.

DDR_SDRAM_CS_n

Chip select, CS_n, has a X or Z


value.

Chip select, CS_n, must always


have a valid value. This check is
active only if CKE is high.

DDR_SDRAM_DATA_WIDTH

Data bus width should not be less


than the minimum limit of 4.

The value of the DATA_WIDTH


parameter should not be specified
as less than 4.

DDR_SDRAM_DLL_
TRACKING_ENABLE

DLL_TRACKING_ENABLE
should be either 1 or 0.

The value of the


DLL_TRACKING_ENABLE
parameter should be either 1 or 0.

DDR_SDRAM_DM

Data mask, DM, has a X or Z


value.

Data mask, DM, must always have


a valid value. This check is active
only if CKE is high.

DDR_SDRAM_DM_WIDTH

Data mask width should not be


less than the minimum limit of 1.

The value of DM_WIDTH


parameter should not be specified to
be less than 1.

DDR_SDRAM_illegal_command_
active

Illegal command is issued when


the bank is in ACTIVE state.

The command just issued is not


legal when the bank is in ACTIVE
state. All the valid commands for
ACTIVE state are listed in the
JEDEC specification under TRUTH
TABLE 2, 3, and 4. Any command
other than these are treated as
illegal commands by the monitor.
When this check fires, the current
state of the bank is encoded in the
state_string signal of the module
qvl_ddr_sdram_bank_monitor.

DDR_SDRAM_illegal_command_
aref

Illegal command is issued when


all the banks are in AUTO
REFRESH state.

The command just issued is not


legal when the bank is in AUTO
REFRESH state. All the valid
commands for AUTO REFRESH
state are listed in the JEDEC
specification under TRUTH
TABLE 2, 3 and 4. Any command
other than these are treated as
illegal commands by the monitor.
When this check fires, the current
state of the bank is encoded in the
state_string signal of the module
qvl_ddr_sdram_bank_monitor.

Questa Verification Library Monitors Data Book, v2010.2

Double Data Rate SDRAM (DDR SDRAM)


V1.0 Monitor

Table 6-7. DDR SDRAM Monitor Checks for Each Bank (cont.)
Check ID

Violation

Description

DDR_SDRAM_illegal_command_
emrs

Illegal command is issued when


all the banks are in
EXTENDENDED MODE
REGISTER SET state.

The command just issued is not


legal when the bank is in
EXTENDENDED MODE
REGISTER SET state. All the valid
commands for EXTENDENDED
MODE REGISTER SET state are
listed in the JEDEC specification
under TRUTH TABLE 2, 3, and 4.
Any command other than these are
treated as illegal commands by the
monitor. When this check fires, the
current state of the bank is encoded
in the state_string signal of the
module
qvl_ddr_sdram_bank_monitor.

DDR_SDRAM_illegal_command_
idle

Illegal command is issued when


the bank is in IDLE state.

The command just issued is not


legal when the bank is in IDLE
state. All the valid commands for
IDLE state are listed in the JEDEC
specification under TRUTH
TABLE 2, 3, and 4. Any command
other than these are treated as
illegal commands by the monitor.
When this check fires, the current
state of the bank is encoded in the
state_string signal of the module
qvl_ddr_sdram_bank_monitor.

DDR_SDRAM_illegal_command_
mrs

Illegal command is issued when


all the banks are in MODE
REGISTER SET state.

The command just issued is not


legal when the bank is in MODE
REGISTER SET state. All the valid
commands for MODE REGISTER
SET state are listed in the JEDEC
specification under TRUTH
TABLE 2, 3, and 4. Any command
other than these are treated as
illegal commands by the monitor.
When this check fires, the current
state of the bank is encoded in the
state_string signal of the module
qvl_ddr_sdram_bank_monitor.

DDR_SDRAM_illegal_command_
pall

Illegal command is issued when


all the banks are in
PRECHARGE state.

The command just issued is not


legal when the bank is in
PRECHARGE ALL state. All the
valid commands for PRECHARGE
ALL state are listed in the JEDEC
specification under TRUTH
TABLE 2, 3, and 4. Any command
other than these are treated as
illegal commands by the monitor.
When this check fires, the current
state of the bank is encoded in the
state_string signal of the module
qvl_ddr_sdram_bank_monitor.

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125

Double Data Rate SDRAM (DDR SDRAM)


V1.0 Monitor

Table 6-7. DDR SDRAM Monitor Checks for Each Bank (cont.)

126

Check ID

Violation

Description

DDR_SDRAM_illegal_command_
pre

Illegal command is issued when


the bank is in PRECHARGE
state.

The command just issued is not


legal when the bank is in
PRECHARGE state. All the valid
commands for PRECHARGE state
are listed in the JEDEC
specification under TRUTH
TABLE 2, 3, and 4. Any command
other than these are treated as
illegal commands by the monitor.
When this check fires, the current
state of the bank is encoded in the
state_string signal of the module
qvl_ddr_sdram_bank_monitor.

DDR_SDRAM_illegal_command_
read

Illegal command is issued when


the bank is in READ state.

The command just issued is not


legal when the bank is in READ
state. All the valid commands for
READ state are listed in the JEDEC
specification under TRUTH
TABLE 2, 3, and 4. Any command
other than these are treated as
illegal commands by the monitor.
When this check fires, the current
state of the bank is encoded in the
state_string signal of the module
qvl_ddr_sdram_bank_monitor.

DDR_SDRAM_illegal_command_
reada

Illegal command is issued when


the bank is in READ WITH
AUTO PRECHARGE state.

The command just issued is not


legal when the bank is in READ
WITH AUTO PRECHARGE state.
All the valid commands for READ
WITH AUTO PRECHARGE state
are listed in the JEDEC
specification under TRUTH
TABLE 2, 3, and 4. Any command
other than these are treated as
illegal commands by the monitor.
When this check fires, the current
state of the bank is encoded in the
state_string signal of the module
qvl_ddr_sdram_bank_monitor.

DDR_SDRAM_illegal_command_
write

Illegal command is issued when


the bank is in WRITE state.

The command just issued is not


legal when the bank is in WRITE
state. All the valid commands for
WRITE state are listed in the
JEDEC specification under TRUTH
TABLE 2, 3, and 4. Any command
other than these are treated as
illegal commands by the monitor.
When this check fires, the current
state of the bank is encoded in the
state_string signal of the module
qvl_ddr_sdram_bank_monitor.

Questa Verification Library Monitors Data Book, v2010.2

Double Data Rate SDRAM (DDR SDRAM)


V1.0 Monitor

Table 6-7. DDR SDRAM Monitor Checks for Each Bank (cont.)
Check ID

Violation

Description

DDR_SDRAM_illegal_command_
writea

Illegal command is issued when


the bank is in WRITE WITH
AUTOPRECHARGE state.

The command just issued is not


legal when the bank is in WRITE
WITH AUTOPRECHARGE state.
All the valid commands for WRITE
WITH AUTOPRECHARGE state
are listed in the JEDEC
specification under TRUTH
TABLE 2, 3, and 4. Any command
other than these are treated as
illegal commands by the monitor.
When this check fires, the current
state of the bank is encoded in the
state_string signal of the module
qvl_ddr_sdram_bank_monitor.

DDR_SDRAM_incorrect_
command_before_mode_reg_set

A command that should not be


issued before the mode register
set command is issued.

NOP, precharge, and refresh are the


only commands that are valid
before the MODE REGISTER SET.
You should check the designs reset
sequencing.

DDR_SDRAM_invalid_burst_
length_value_in_mode_reg_set

Invalid burst length value during


the mode register set command.

As per the JEDEC specification, the


valid burst length values are 2
(3'b001), 4 (3'b010), and 8 (3'b011).
This check fires if a burst length
value other than the ones listed
above is programmed.

DDR_SDRAM_invalid_cas_
latency_value_in_mode_reg_set

Invalid CAS latency value during


the mode register set command.

As per the JEDEC specification, the


valid CAS latency values are 1.5
(3'b101), 2 (3'b010), 2.5 (3'b110),
and 3 (3'b011). This check fires if a
CAS latency value other than the
ones listed above is programmed.

DDR_SDRAM_invalid_operating_
mode_bits_mrs_or_emrs

Invalid operating mode bits are


programmed during the mode
register set or the extended mode
register set command.

As per the JEDEC specification, for


normal operation, A[11:7] should
be 5'b00000 or 5'b00010 during the
MODE REGISTER SET command,
and A[11:3] should be
9'b000000000 during EXTENDED
MODE REGISTER SET command.
This check fires if a value other
than the ones listed above is driven
on address bus (A) during MODE
REGISTER SET or EXTENDED
MODE REGISTER SET command
is issued.

DDR_SDRAM_invalid_self_ref
_or_power_down_exit

Only NOP or DSEL command


should be issued during SELF
REFRESH or POWER DOWN
exit.

When DDR SDRAM is exited from


SELF REFRESH or POWER
DOWN mode, only the NOP or
DESELECT command should be
issued along with the SELF
REFRESH EXIT or POWER
DOWN EXIT command. This
check fires if a NOP or DESELECT
command is not issued during
SELF REFRESH or POWER
DOWN exit.

Questa Verification Library Monitors Data Book, v2010.2

127

Double Data Rate SDRAM (DDR SDRAM)


V1.0 Monitor

Table 6-7. DDR SDRAM Monitor Checks for Each Bank (cont.)

128

Check ID

Violation

Description

DDR_SDRAM_no_auto_ refresh

At least two auto refresh


commands should be issued after
reset and before first active
command.

Minimum two auto refresh


commands should be issued after
reset and before the first activate
command is issued. This check fires
if there is no auto refresh command
or only one auto refresh command
is issued before the first active
command issue.

DDR_SDRAM_no_dll_ reset

DLL is not reset after it was


enabled.

If DLL is enabled through


EXTENDED MODE REG SET
command, then there should be a
DLL reset command issued before
an activate command is issued.

DDR_SDRAM_RAS_n

Row address strobe, RAS_n, has


a X or Z value.

Row address strobe, RAS_n, must


always have a valid value. This
check is active only if CKE is high.

DDR_SDRAM_read_before_write

A read operation was performed Data was read from a DDR


on the DDR SDRAM that was not SDRAM address that was not
previously written into.
previously written into. This check
fires whenever a location being read
was previously not written into.

DDR_SDRAM_TMRD

TMRD value should not be less


than the minimum limit of 2.

The value of the TMRD timing


parameter should not be specified
as less than 2.

DDR_SDRAM_TRAS

TRAS value should not be less


than the minimum limit of 6.

The value of the TRAS timing


parameter should not be specified
as less than 6.

DDR_SDRAM_TRC

TRC value should not be less than The value of the TRC timing
the minimum limit of 9.
parameter should not be specified
as less than 9.

DDR_SDRAM_TRCD

TRCD value should not be less


than the minimum limit of 3.

The value of the TRCD timing


parameter should not be specified
as less than 3.

DDR_SDRAM_TRFC

TRFC value should not be less


than the minimum limit of 10.

The value of the TRFC timing


parameter should not be specified
as less than 10.

DDR_SDRAM_TRP

TRP value should not be less than


the minimum limit of 3.

The value of the TRP timing


parameter should not be specified
as less than 3.

DDR_SDRAM_TRRD

TRRD value should not be less


than the minimum limit of 2.

The value of the TRRD timing


parameter should not be specified
as less than 2.

DDR_SDRAM_TWR

TWR value should not be less


than the minimum limit of 2.

The value of the TWR timing


parameter should not be specified
as less than 2.

DDR_SDRAM_TXSNR

TXSNR value should not be less


than the minimum limit of 10.

The value of the TXSNR timing


parameter should not be specified
as less than 10.

Questa Verification Library Monitors Data Book, v2010.2

Double Data Rate SDRAM (DDR SDRAM)


V1.0 Monitor

Table 6-7. DDR SDRAM Monitor Checks for Each Bank (cont.)
Check ID

Violation

Description

DDR_SDRAM_TXSRD

TXSRD value should not be less


than the minimum limit of 200.

The value of the TXSRD timing


parameter should not be specified
as less than 200.

DDR_SDRAM_violates_CKE_
signal_P

CKE is low when control signals


and/or the monitor state machine
are not pointing to SELF
REFRESH or POWER DOWN
mode.

CKE should not go low when the


DDR SDRAM is performing a
READ or WRITE burst. The user
should determine why CKE goes
low when the DDR SDRAM is
performing a READ or WRITE
burst.

DDR_SDRAM_violates_CKE_
signal_N * (see the note at the end
of this table)

CKE is low when control signals


and/or the state machine are not
computing to SELF REFRESH or
POWER DOWN mode.

CKE should not go low when the


DDR SDRAM is performing a
READ or WRITE burst. The user
should determine why CKE goes
low when the DDR SDRAM is
performing a READ or WRITE
burst.

DDR_SDRAM_violates_tDLL

At least 200 clocks delay should


be given between the DLL enable
and a read/read with auto
precharge command.

If DLL is enabled, then there should


be a minimum of 200 clocks delay
before a read command or read with
autoprecharge command is issued.

DDR_SDRAM_violates_tMRD

A command that violates tMRD


timing is issued.

The command just issued violates


tMRD (minimum time delay
between MODE REGISTER SET
command and any other command)
timing. The new command is issued
too quickly after the MODE
REGISTER SET command. The
user should determine why the
commands are too close together.

DDR_SDRAM_violates_tRAS

A command that violates RAS


timing is issued.

The command just issued violates


tRAS (RAS to precharge timing).
This is a PRECHARGE command
issued too quickly after the
ACTIVATE command for this
bank. The user should determine
why the commands are too close
together.

DDR_SDRAM_violates_tRC

TRC timing violation: Bank


Activate / Refresh is issued
sooner than tRC cycles from the
last bank activate command.

The command just issued violates


tRC (RAS cycle timing). This is an
ACTIVATE/REFRESH command
issued too quickly after the last
ACTIVATE command for this
bank. The user should determine
why the commands are too close
together.

DDR_SDRAM_violates_CKE_
signal_N

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129

Double Data Rate SDRAM (DDR SDRAM)


V1.0 Monitor

Table 6-7. DDR SDRAM Monitor Checks for Each Bank (cont.)

130

Check ID

Violation

Description

DDR_SDRAM_violates_tRCD

A command that violates RAS to


CAS delay timing is issued.

The command just issued violates


tRCD (RAS to CAS delay timing).
This is a READ/WRITE command
issued too quickly after the
ACTIVATE command for this
bank. The user should determine
why the commands are too close
together.

DDR_SDRAM_violates_tRFC

A command that violates tRFC


timing is issued.

The command just issued violates


tRFC (minimum time delay
between AUTO REFRESH
command and any other command).
The new command is issued too
quickly after the AUTO REFRESH
command. The user should
determine why the commands are
too close together.

DDR_SDRAM_violates_tRP

A command that violates RAS


precharge timing is issued.

The command just issued violates


tRP (RAS precharge timing). This
is an ACTIVATE/REFRESH
command issued too quickly after
the last precharge command for this
bank. The user should determine
why the commands are too close
together.

DDR_SDRAM_violates_tRRD

An activate command is issued


too quickly after the prior activate
command.

The command just issued violates


tRRD (RAS to RAS delay timing).
This is an ACTIVATE command
issued too quickly after the
ACTIVATE command for another
bank. The user should determine
why the commands are too close
together.

DDR_SDRAM_violates_tXSNR

A command that violates tXSNR


timing is issued.

The command just issued violates


tXSNR (minimum time delay
between SELF REFRESH EXIT
command and any other non-READ
command) timing. A non-READ
command is issued too quickly after
the SELF REFRESH EXIT
command. The user should
determine why the commands are
too close together.

DDR_SDRAM_violates_tXSRD

A read/read with auto precharge


command that violates tXSRD
timing is issued.

The READ command just issued


violates tXSRD (minimum time
delay between SELF REFRESH
EXIT command and a READ
command) timing. A READ
command is issued too quickly after
the SELF REFRESH EXIT
command. The user should
determine why the commands are
too close together.

Questa Verification Library Monitors Data Book, v2010.2

Double Data Rate SDRAM (DDR SDRAM)


V1.0 Monitor

Table 6-7. DDR SDRAM Monitor Checks for Each Bank (cont.)
Check ID

Violation

Description

DDR_SDRAM_WE_n

Write enable, WE_n, has a X or Z


value.

Write enable, WE_n, must always


have a valid value. This check is
active only if CKE is high.

DDR_SDRAM_why_precharge_
an_idle_bank

A PRECHARGE command is
issued while the bank is already
in a precharged state.

The design is precharging (not an


all-bank PRECHARGE) a bank that
has already been precharged.
Although not illegal, this is
inefficient. You should examine
why the extra PRECHARGE
command is issued. This check is
enabled only when ENABLE_
WHY_PRECHARGE_AN_IDLE_
BANK parameter is set to 1.

* The DDR_SDRAM_violates_CKE_signal_N check is active on the positive edge of the clock_n


(complementary clock) signal. All other checks are active on the positive edge of the clock signal.

The minimum delay from a read/write with auto precharge command to any command to a
different bank is calculated as shown in Table 6-8.
Table 6-8. Calculate Minimum Delay From a Read/Write
From Command

To Command

Minimum Delay in Cycles

Write with AP

Read or Read AP

(BL/2) + tWR +1

Write or Write AP

BL/2

Precharge or Active

Read or Read AP

BL/2

Write or Write AP

CL + (BL/2)

Precharge or Active

Read with AP

BL = burst length
CL = CAS latency rounded up to next integer

Questa Verification Library Monitors Data Book, v2010.2

131

Double Data Rate SDRAM (DDR SDRAM)


V1.0 Monitor

Monitor Corner Cases


Table 6-9 shows the corner cases captured by the DDR SDRAM monitor for the protocol.
Table 6-9. DDR SDRAM Monitor Corner Cases
Corner Case

Description

Read Commands

Number of read operations from any bank in the DDR SDRAM.

Write Commands

Number of write operations to any bank in the DDR SDRAM.

Precharge Commands

Number of Precharge commands issued to the DDR SDRAM.

Burst Stop Commands

Number of times a Burst Stop command is issued to the DDR


SDRAM.

Mode Register Set Commands

Number of times a Mode Register Set command is issued to the DDR


SDRAM.

CBR (auto) Refresh Commands

Number of times a CBR (auto) Refresh is issued to the DDR


SDRAM.

Self Refresh Commands

Number of times a Self Refresh command is issued to the DDR


SDRAM.

Power Down Commands

Number of times a Power Down command is issued to the DDR


SDRAM.

Extended Mode Register Set


Commands

Number of times EXTENDED MODE REGISTER SET is issued to


DDR SDRAM.

Precharge all Commands

Number of times PRECHARGE ALL command is issued to DDR


SDRAM.

NOP Commands

Number of times a NOP command is issued to the DDR SDRAM.

Deselect Commands

Number of times the chip select signal (CS_n) of the DDR SDRAM
is de-asserted.

Table 6-10 shows the corner cases captured by the DDR SDRAM monitor for each DDR
SDRAM bank.
Table 6-10. DDR SDRAM Monitor Corner Cases Maintained for Each Bank

132

Corner Case

Description

Read Commands

Number of read operations from the bank in the DDR SDRAM.

Write Commands

Number of write operations to the bank in the DDR SDRAM.

Read without auto precharge


Commands

Number of read (without auto-precharge) operations from the bank in the


DDR SDRAM.

Read with auto precharge


Commands

Number of read (with auto-precharge) operations from the bank in the


DDR SDRAM.

Write without auto precharge


Commands

Number of write (without auto-precharge) operations from the bank in the


DDR SDRAM.

Questa Verification Library Monitors Data Book, v2010.2

Double Data Rate SDRAM (DDR SDRAM)


V1.0 Monitor

Table 6-10. DDR SDRAM Monitor Corner Cases Maintained for Each Bank
Corner Case

Description

Write with auto precharge


Commands

Number of write (with auto-precharge) operations from the bank in the


DDR SDRAM.

Read after Read in Page

Number of times a read operation was issued to a page that was already
opened for read in the bank.

Read after Write in Page

Number of times a read operation was issued to a page that was already
opened for write in the bank.

Write after Read in Page

Number of times a write operation was issued to a page that was already
opened for read in the bank.

Write after Write in Page

Number of times a write operation was issued to a page that was already
opened for write in the bank.

Precharge Commands

Number of precharge commands issued to the bank.

Burst Operations Terminated

Number of times a burst operation to the bank was terminated before it


was completed. This could be due to a Burst Stop command or if another
read or write command to the bank was issued before a current burst
operation was completed.

Monitor Statistics
Table 6-11 shows the corner cases captured by the DDR SDRAM monitor for the protocol.
Table 6-11. DDR SDRAM Monitor Statistics
Statistic

Description

Active Commands

Number of times any bank in the DDR SDRAM is selected.

Table 6-12 shows the corner cases captured by the DDR SDRAM monitor for each DDR
SDRAM bank.
Table 6-12. DDR SDRAM Monitor Statistics Maintained for Each Bank
Statistic

Description

Active Commands

Number times the bank in the DDR SDRAM is selected.

Questa Verification Library Monitors Data Book, v2010.2

133

Double Data Rate SDRAM (DDR SDRAM)


V2.0 Monitor

V2.0 Monitor
Reference Documentation
This DDR SDRAM 2.0 monitor is modeled from the requirements provided in the following
document:

JEDEC Standard, Double Data Rate (DDR) SDRAM Specification, JESD79C, (Revision
of JESD79B) JEDEC Solid State Technology Association, March 2003.

JEDEC Standard, Double Data Rate (DDR) SDRAM Specification, JESD79, (Release
2) JEDEC Solid State Technology Association, May 2002.

Micron, DOUBLE DATA RATE (DDR) SDRAM, 64Mb: x32 DDR SDRAM, 2M32DDR07.p65-Rev. 9/01.

JEDEC Standard, Double Data Rate (DDR) Specification, JESD79E, JEDEC Solid
State Technology Association, May 2005.

Mode Register Programming


For mode register programming, the DDR SDRAM 2.0 monitor supports the following:

Burst lengths 2, 4, 8, 16, 32, 64, 128, and Full Page Mode (FPM).

CAS latencies 0.5, 1, 1.5, 2, 2.5, 3, and 4.

Sequential and interleaved burst types.

DLL reset, if DLL is enabled.

Normal operating mode.

Clock frequency change

The DDR SDRAM 2.0 monitor does not support the following:

Interleaved burst type in Full Page Mode (FPM) burst.

Any reserved states and vendor-specific test modes.

Full Page Mode burst and CAS latency of 4 in NON JEDEC mode.

Extended Mode Register Programming


For extended mode register programming, the DDR SDRAM 2.0 monitor supports the
following:

134

DLL enable/disable.

Questa Verification Library Monitors Data Book, v2010.2

Double Data Rate SDRAM (DDR SDRAM)


V2.0 Monitor

Normal operating mode.

The DDR SDRAM 2.0 monitor does not support the following:

Any reserved states.

Data interface and Configurations

Data width configurations of x4, x8, and x16.

Data strobe DQS for x4 and x8 configurations.

Data strobes (LDQS, UDQS) for lower and upper data bytes in x16 configuration.

Write data masks LDM and UDM for lower and upper data bytes in x16 mode.

Initialization Sequence Bypass


The DDR monitor can be used in cases where the initialization sequence is bypassed to save
simulation cycles. The parameter BYPASS_INIT determines this mode of operation as follows:

Normal mode.
By default (i.e., BYPASS_INIT = 0), the monitor tracks the initialization sequence and
validates the requirements described in the specification during the initialization
sequence. For example, the monitor fires if it does not detect at least two auto refresh
commands between a reset and an active command. In this mode, the monitor tracks the
MRS and EMRS commands and configures itself accordingly. The monitor ports
mode_register and extended_mode_register can be left unconnected.

Initialization bypass mode.


In this mode (i.e., BYPASS_INIT = 1), the monitor does not validate the requirements
described in the specification during the initialization sequence and does not track the
MRS and EMRS commands. However, for proper operation, the monitor requires the
information regarding the mode register settings. This information is passed through the
monitor ports mode_register and extended_mode_register. The values passed to
these ports must reflect the actual mode register setting in the DDR SDRAM memory.

Monitor Placement and Instantiation


To use the DDR SDRAM 2.0 monitor, place one instance of the monitor inside the part of the
design that is searchable (a block of synthesizable code for formal analysis). For example, in a
DDR SDRAM memory controller chip design that has a DDR SDRAM memory interface for
the DDR SDRAM memory chips and an application interface for connecting other controllers,
the monitor should be instantiated inside the DDR SDRAM memory controller design with the
port signals connected to the DDR SDRAM memory interface (see Figure 6-5). Instantiations of
the DDR SDRAM 2.0 monitor in a checker control file can be included.
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Figure 6-5. DDR SDRAM System Implementation

Address

address
pipe

Control
control
DDR SDRAM
Memory

Application
Interface
Controller

DDR SDRAM
Monitor
Data

data
in/out
DDR SDRAM Memory Controller

Monitor Connectivity
Connect the DDR SDRAM 2.0 monitor pins to internal signals of the target design as specified
in the pin-out Table 6-13 and illustrated in Figure 6-6. The clock, reset, and asynchronous reset
should be available inside the target design. The remaining signals can be attached to the
outbound control and address signals of the target design.

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Figure 6-6. DDR SDRAM 2.0 Monitor Pin-Out Diagram


clock
clock_n
reset
areset
CKE
CS_n
RAS_n
CAS_n
WE_n
BA[1:0]
A[ADDR_WIDTH - 1:0]
DM
DQ[DATA_WIDTH - 1:0]
DQS
mode_register
extended_mode_register
LDQS
LDM
UDQS
UDM
TMRD

DDR SDRAM
Monitor

TRAS
TRC
TRCD
TRFC
TRP
TRRD
TWR
TWRT
TXSNR
TXSRD

Table 6-13. DDR SDRAM 2.0 Monitor Pin-Out


Pin

Description

A[ADDR_WIDTH 1:0]

Address.

areset

Asynchronous reset (active high).

BA[1:0]

Bank address.

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Table 6-13. DDR SDRAM 2.0 Monitor Pin-Out (cont.)

138

Pin

Description

CAS_n

Column address strobe (active low).

CKE

Clock enable signal(s).

clock

Clock (positive edge is active).

clock_n

Complementary clock, 180 degree out of phase with clock.

CS_n

Chip select (active low signal(s)).

DM

Data mask lines (active high).

DQ[DATA_WIDTH - 1:0]

Data lines.

DQS

Data strobe.

extended_mode_register
[ADDR_WIDTH 1:0]

Extended mode register input. Leave this port unconnected if


BYPASS_INIT = 0. The width of this register is equal to
ADDR_WIDTH + Bank Address width (i.e., 2). This width reflects
the actual width of the mode register in DDR SDRAM memory.

LDM

Data mask for port {DQ7:DQ0}.

LDQS

Data strobe for {DQ7:DQ0}.

mode_register[ADDR_WIDTH +1:0]

Mode register input. Leave this port unconnected if BYPASS_INIT


= 0. The width of this register is equal to ADDR_WIDTH + Bank
Address width (i.e., 2). This width reflects the actual width of the
mode register in DDR SDRAM memory.

RAS_n

Row address strobe (active low).

reset

Reset (active high).

TCLK

Represents minimum cycles to be lapsed before the clock frequency


can change in precharge power down mode after the clock enable
signal (CKE) is sampled LOW. This input is valid when both
CLOCK_CHANGE_TRACKING_ENABLE and
USE_PORTS_TO_CONFIGURE are set to 1.

TMRD

SELF REFRESH to non-READ command time parameter input


minimum time interval between SELF REFRESH command to any
non-READ command to any bank. This input is valid only when the
USE_PORTS_TO_CONFIGURE parameter is set to 1.

TRAS

RAS# active time parameter inputminimum time to precharge a


bank after it was previously issued an ACTIVE command without
losing read/write data.This input is valid only when the
USE_PORTS_TO_CONFIGURE parameter is set to 1.

TRC

RAS# cycle time parameter inputminimum time interval between


successive ACTIVE commands to the same bank. This input is valid
only when the USE_PORTS_TO_CONFIGURE parameter is set to
1.

TRCD

RAS# to CAS# delay parameter inputminimum time to legally


issue a READ or WRITE command to a row after opening it by
issuing an ACTIVE command. This input is valid only when the
USE_PORTS_TO_CONFIGURE parameter is set to 1.

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Table 6-13. DDR SDRAM 2.0 Monitor Pin-Out (cont.)


Pin

Description

TRFC

SELF REFRESH to READ command time parameter input


minimum time interval between SELF REFRESH command to a
READ command to any bank.This input is valid only when the
USE_PORTS_TO_CONFIGURE parameter is set to 1.

TRP

RAS# precharge time parameter inputminimum time to precharge


a bank. This input is valid only when the
USE_PORTS_TO_CONFIGURE parameter is set to 1.

TRRD

RAS# to RAS# bank activate delay parameter inputminimum time


interval between successive ACTIVE commands to different banks.
This input is valid only when the USE_PORTS_TO_CONFIGURE
parameter is set to 1.

TWR

MODE REGISTER SET command cycle time parameter input


minimum time interval for any new command issue after the MODE
REGISTER SET command was previously issued. This input is
valid only when the USE_PORTS_TO_CONFIGURE parameter is
set to 1.

TWRT

AUTO REFRESH to ACTIVE command time parameter input


minimum time between AUTO REFRESH command and an
ACTIVE command to any bank. This input is valid only when the
USE_PORTS_TO_CONFIGURE parameter is set to 1.

TXSNR

WRITE burst end to PRECHARGE time parameter input


minimum time interval between WRITE burst end to PRECHARGE
command. This input is valid only when the
USE_PORTS_TO_CONFIGURE parameter is set to 1.

TXSRD

WRITE burst end to READ command time parameter input.


Minimum time interval between a WRITE burst end to the READ
command issue. This input is valid only when the
USE_PORTS_TO_CONFIGURE parameter is set to 1.

UDM

Data mask for port {DQ15:DQ8}.

UDQS

Data strobe for port {DQ15:DQ8}.

WE_n

Write enable (active low).

Note that the timing value between a WRITE command and the first DQS latching transition is
called the tdqss value. For formal analysis, the DDR SDRAM 2.0 monitor only supports
tdqss values equal to the clock period. This means that the DQS signal edges should be in line
with the clock signal for formal analysis. The monitor supports tdqss values from 75% to
125% of the total clock period.

Monitor Parameters
The parameters shown in Table 6-14 configure the corresponding DDR SDRAM 2.0 monitor.
The override parameters set timing parameters for the monitor.

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Refer to Table 6-17 on page 145 for the JEDEC standard compliant values of the parameters
that are used as default values.
Table 6-14. DDR SDRAM 2.0 Monitor Parameters
Order Parameter

Default Description

1.

Constraints_Mode

Set to 1 if the checks in the monitor are to be used


as constraints for formal analysis.

2.

CONTROLLER_SIDE

Set this parameter to 1 if the monitor is instantiated


on the DDR SDRAM controller side. This
parameter and the Constraints_Mode parameter
turn all checks in the monitor to constraints (checks
those connected on the input signals to controller)
or targets (checks those connected on output signals
from controller), and checks those connected on the
bidirectional signals during formal analysis.

3.

ADDR_WIDTH

12

Width of address bus signals. Minimum value for


this parameter is 12. If your designs ADDR
WIDTH is less than 12, then for the upper address
lines of the monitor that are not available in the
design, connect with 1'b0.

4.

DATA_WIDTH

Width of data bus signals. Minimum value for this


parameter is 4.

5.

DLL_TRACKING_ENABLE

Set this parameter to 1 to enable the


DDR_SDRAM_no_dll_reset and
DDR_SDRAM_violates_tDLL checks.

6.

TRC_OVERRIDE

RAS# cycle timeminimum time interval between


successive ACTIVE commands to the same bank.
Set this parameter to 0 if you want the JEDEC
default value or the timing parameter from the port
to be used. This parameter is applicable only when
the USE_PORTS_TO_CONFIGURE is 0.

7.

TRAS_OVERRIDE

RAS# active timeminimum time to precharge a


bank after it was previously issued an ACTIVE
command without losing read/write data. Set this
parameter to 0 if you want the JEDEC default value
or the timing parameter from the port to be used.
This parameter is applicable only when the
USE_PORTS_TO_CONFIGURE is 0.

8.

TRP_OVERRIDE

RAS# precharge timeminimum time to precharge


a bank. Set this parameter to 0 if you want the
JEDEC default value or the timing parameter from
the port to be used. This parameter is applicable
only when the USE_PORTS_TO_CONFIGURE is
0.

9.

TRCD_OVERRIDE

RAS# to CAS# delayminimum time to legally


issue a READ or WRITE command to a row after
opening it by issuing an ACTIVE command. Set
this parameter to 0 if you want the JEDEC default
value or the timing parameter from the port to be
used. This parameter is applicable only when the
USE_PORTS_TO_CONFIGURE is 0.

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Table 6-14. DDR SDRAM 2.0 Monitor Parameters (cont.)


Order Parameter

Default Description

10.

TRRD_OVERRIDE

RAS# to RAS# bank activate delayminimum


time interval between successive ACTIVE
commands to different banks. Set this parameter to
0 if you want the JEDEC default value or the timing
parameter from the port to be used. This parameter
is applicable only when the
USE_PORTS_TO_CONFIGURE is 0.

11.

TMRD_OVERRIDE

MODE REGISTER SET command cycle time


minimum time interval for any new command issue
after the MODE REGISTER SET command was
previously issued. Set this parameter to 0 if you
want the JEDEC default value or the timing
parameter from the port to be used. This parameter
is applicable only when the
USE_PORTS_TO_CONFIGURE is 0.

12.

TRFC_OVERRIDE

AUTO REFRESH to ACTIVE command time


minimum time between AUTO REFRESH
command and an ACTIVE command to any bank.
Set this parameter to 0 if you want the JEDEC
default value or the timing parameter from the port
to be used. This parameter is applicable only when
the USE_PORTS_TO_CONFIGURE is 0.

13.

TXSNR_OVERRIDE

SELF REFRESH to non-READ command time


minimum time interval between SELF REFRESH
command to any non-READ command to any bank.
Set this parameter to 0 if you want the JEDEC
default value or the timing parameter from the port
to be used. This parameter is applicable only when
the USE_PORTS_TO_CONFIGURE is 0.

14.

TXSRD_OVERRIDE

SELF REFRESH to READ command time


minimum time interval between SELF REFRESH
command to a READ command to any bank. Set
this parameter to 0 if you want the JEDEC default
value or the timing parameter from the port to be
used. This parameter is applicable only when the
USE_PORTS_TO_CONFIGURE is 0.

15.

TWR_OVERRIDE

WRITE burst end to PRECHARGE time (minimum


time interval between WRITE burst end to
PRECHARGE command). Set this parameter to 0 if
you want the JEDEC default value or the timing
parameter from the port to be used. This parameter
is applicable only when the
USE_PORTS_TO_CONFIGURE is 0.

16.

TWTR_OVERRIDE

WRITE burst end to READ command time.


Minimum time interval between a WRITE burst
end to the READ command issue. Set this
parameter to 0 if you want the JEDEC default value
or the timing parameter from the port to be used.
This parameter is applicable only when the
USE_PORTS_TO_CONFIGURE is 0.

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Table 6-14. DDR SDRAM 2.0 Monitor Parameters (cont.)


Order Parameter

Default Description

17.

AUTOPRECHARGE_ENABLE_
ADDRESS_BIT

10

Bit-index specifying the auto precharge address


line. The address bit, specified by this parameter is
used to enable/disable the auto precharge function
during a Read or Write command. This is also used
to decode a Single bank precharge and all banks
precharge during a precharge command issue.

18.

COL_ADDRESS_WIDTH

Number of Column address lines. This parameter is


used to decode the size of the full page for Full
Page Mode (FPM) burst.

19.

READ_BEFORE_WRITE_
CHECK_ENABLE

Enables the check that ensures no read is performed


to a location when there is no previous write to the
same location. Set this parameter to 0 to disable this
check. Check ID:
DDR_SDRAM_read_before_write

20.

CON_AUTO_PRECHARGE

Set this parameter to 1 if the device in which the


monitor is instantiated supports the Concurrent
Auto Precharge. By default, the monitor assumes
that the device in which it is instantiated does not
support Concurrent Auto Precharge.

21.

ENABLE_WHY_PRECHARGE_
AN_IDLE_BANK

Set this parameter to 1 to enable the check that


ensures a PRECHARGE command is not issued to
an idle bank. By default, this check (Check ID:
DDR_SDRAM_why_precharge_an_idle_bank) is
turned off.

22.

BYPASS_INIT

Set this parameter to 1 to bypass the initialization


sequence. If this parameter is set to 1, then the
complete initialization sequence need not be
performed. Nevertheless, valid operational values
must be passed to the mode register and extended
mode register inputs (otherwise, the monitor
behavior is undefined). By default, the monitor
requires the proper initialization sequence to be
performed as stated in the specification.

23.

NON_JEDEC

Set this parameter to 1 to enable the usage of NON


JEDEC values for the configuration of Burst length,
CAS Latency, and timing parameters. By default,
the use of JEDEC values are only allowed.

24.

USE_PORTS_TO_CONFIGURE

Set this parameter to 1 to enable the usage of the


input ports to configure the various timing
parameter values. By default, the monitor uses the
defined JEDEC values.

25.

DATA_CHECK_ENABLE

This parameter enables or disables the following


data integrity checks: DDR_SDRAM_bad_data and
DDR_SDRAM_read_before_write.
Set this parameter to 1 to enable the data integrity
checks.
Setting to 0 removes the checks by completely
removing the data-checker module,
qvl_ddr_sdram_data_checker.

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Table 6-14. DDR SDRAM 2.0 Monitor Parameters (cont.)


Order Parameter

Default Description

26.

TCLK_OVERRIDE

27.

CLOCK_CHANGE_TRACKING_ 0
ENABLE

Set this parameter to 1 to enable support of the


change of input clock frequency on the fly as per
JESD79E May 2005 specification update.

28.

TCLK_CHECK_ENABLE

Set this parameter to 1 to enable checking for the


minimum clock cycles to be lapsed before the clock
frequency can change after CKE is sampled LOW.
This parameter is valid only when parameter
CLOCK_CHANGE_TRACKING_ENABLE is set
to 1.

29.

CLOCK_FREQUENCY_RANGE_ 0
CHECK_ENABLE

Set this parameter to 1 to enable checking for the


clock frequency if it is within the allowed ranges,
which is specified by another set of parameters
CLOCK_PERIOD_MAX and
CLOCK_PERIOD_MIN. This parameter is valid
only when the parameter
CLOCK_CHANGE_TRACKING_ENABLE is set
to 1.

30.

CLOCK_PERIOD_MAX

10

Set the highest allowed clock period specified in


nanoseconds (ns), which is a measure of the lowest
clock frequency supported by the DDR SDRAM.
The default value is set to 10 (ns). The default value
means a supported clock of 100 MHz, which is the
slowest clock supported for DDR SDRAM as per
JESD79E. The user can alter this value for nonJEDEC applications.

31.

CLOCK_PERIOD_MIN

Set the lowest allowed clock period specified in


nanoseconds (ns), which is a measure of the lowest
clock frequency supported by the DDR SDRAM.
The default value is set to 5 (ns). The default value
means a supported clock of 200 MHz, which is the
fastest clock supported for DDR SDRAM as per
JESD79E. The user can alter this value for nonJEDEC applications.

Represents the value for the minimum cycles to be


lapsed before the clock frequency can change in
precharge power down mode after the clock enable
signal (CKE) is sampled LOW. This parameter is
valid only when parameter
CLOCK_CHANGE_TRACKING_ENABLE is set
to 1 and parameter
USE_PORTS_TO_CONFIGURE is set to 0.

The parameters must be specified in the above order.


Time is measured in terms of number of clock cycles.

Programming the DQS Delay


Note the following about the `define compiler directive:
Name: QVL_DQS_DELAY
Default: 2

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Description:
This is used to delay the DQS signal during read cycles in order to align the DQS signal edges at
the center of the DQ signal to guarantee the proper latching of DQ.
By default, the DQS signal is delayed by 2 time units (i.e., #2) internally.
The user should override this with a larger value if the DQS signal that is driven by the DDR
Memory should be delayed more than #2 to guarantee proper DQ latching.

JEDEC Mode
Full Page mode burst can be configured only in JEDEC mode (that is, when NON_JEDEC = 0).
When NON_JEDEC =1, the Burst Length configuration is as shown in Table 6-15.
Table 6-15. JEDEC Mode Burst Length Configuration
A[2:0]

BURST LENGTH

000

RSVD

001

010

011

100

16

101

32

110

64

111

128

CAS latency of 4 can be configured only in JEDEC mode (that is, when NON_JEDEC = 0).
When NON_JEDEC =1, the CAS Latency configuration is as shown in Table 6-16.
Table 6-16. JEDEC Mode CAS Latency Configuration

144

A[6:4]

CAS LATENCY

000

RSVD

001

1.0

010

2.0

011

3.0

100

0.5

101

1.5

110

2.5

111

RSVD

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When constraints mode is disabled, all checks are used as targets during formal analysis. To use
the checks as constraints for formal analysis, do the following:

Set the Constraints_Mode parameter to 1.

Set the CONTROLLER_SIDE parameter as follows:


o

If the monitor is instantiated in the DDR SDRAM controller, then set


CONTROLLER_SIDE to 1.

If the monitor is instantiated in the DDR SDRAM memory, then set


CONTROLLER_SIDE to 0.

Table 6-17. JEDEC Compliant Min. Timing for DDR SDRAM Speed Grade 266
Timing Parameter

JEDEC Standard Timing Value

TRC

TRAS

TRP

TRCD

TRRD

TMRD

TRFC

TXSNR

TXSRD

200

TWR

TWTR

Time is measured by an integer number of clock cycles.

Instantiation Examples
Example 1
Example 6-5 instantiates a JEDEC standard compliant DDR SDRAM 2.0 monitor on the DDR
SDRAM controller side for unconstraint search with ADDR_WIDTH of 12, DATA_WIDTH of 8,
8th bit of Address line as Auto precharge enable, Lower 8 Column Address lines are to be used
for Full Page Mode burst, and DLL_TRACKING_ENABLE set to 1. Note that all timing parameters
are the default values specified by JEDEC. The monitor is in normal mode of operation, which
enables the monitor to track the initialization sequence.
Example 6-5. DDR SDRAM 2.0 Monitor Instantiated in the Controller
qvl_ddr_sdram_2_0_monitor

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#( /* Constraints_Mode */ 0,
/* CONTROLLER_SIDE */
1,
/* ADDR_WIDTH */
12,
/* DATA_WIDTH */
8)
DDR_SDRAM_MONITOR0 (
.clock
(clock),
.clock_n
(clock_n),
.reset
(reset),
.areset
(areset),
.CKE
(clock_enable_1),
.CS_n
(chip_select_1_n),
.RAS_n
(row_address_strobe_n),
.CAS_n
(column_address_strobe_n),
.WE_n
(write_enable_n),
.BA
(bank_address),
.A
(address_bus_12),
.DM
(data_mask_1),
.DQ
(data_bus_8),
.DQS
(data_strobe)
.mode_register (),
.extended_mode_register (),
.LDQS (1'b0),
.LDM (1'b0),
.UDQS (1'b0),
.UDM (1'b0)
.TRC(32'b0),
.TRAS(32'b0),
.TRP(32'b0),
.TRCD(32'b0),
.TRRD(32'b0),
.TWR(32'b0),
.TWTR(32'b0),
.TMRD(32'b0),
.TRFC(32'b0),
.TXSNR(32'b0),
.TXSRD(32'b0),
.TCLK(32'b0) );

Example 2
Example 6-6 instantiates two DDR SDRAM 2.0 monitors for a JEDEC standard DDR SDRAM
controller design. The example shows the following:

The controller design interfaces two DDR SDRAMs, each having 16 bits of
DATA_WIDTH to form a 32-bit data bus.

The other input signals widths are as follows:

146

ADDR_WIDTH

DM_WIDTH

of 12.

of 4, one for each byte of data.

The DLL tracking is enabled. Therefore, the DLL_TRACKING_ENABLE parameter is set to


1.

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The monitor is instantiated for unconstrained formal analysis. Therefore, the


Constraints_Mode parameter is set to 0.

Initialization sequence tracking is enabled (by default).


Example 6-6. Two DDR SDRAM 2.0 Monitors

qvl_ddr_sdram_2_0_monitor
#( /* Constraints_Mode */
0,
/* CONTROLLER_SIDE */
1,
/* ADDR_WIDTH */
12,
/* DATA_WIDTH */
16)
DDR_SDRAM_MONITOR0 (
.clock
(clock),
.clock_n
(clock_n),
.reset
(reset),
.areset
(areset),
.CKE
(clock_enable_4[1:0]),
.CS_n
(chip_select_4_n[1:0]),
.RAS_n
(row_address_strobe_n),
.CAS_n
(column_address_strobe_n),
.WE_n
(write_enable_n),
.BA
(bank_address),
.A
(address_bus_12),
.DM
(1'b0),
.DQ
(data_bus_32[15:0]),
.DQS
(1'b0),
.mode_register (),
.extended_mode_register (),
.LDQS (data_strobe),
.LDM (data_mask_4[0]),
.UDQS (data_strobe),
.UDM (data_mask_4[1]),
.TRC(32'b0),
.TRAS(32'b0),
.TRP(32'b0),
.TRCD(32'b0),
.TRRD(32'b0),
.TWR(32'b0),
.TWTR(32'b0),
.TMRD(32'b0),
.TRFC(32'b0),
.TXSNR(32'b0),
.TXSRD(32'b0),
.TCLK(32'b0) );
qvl_ddr_sdram_2_0_monitor
#( /* Constraints_Mode */ 0,
/* CONTROLLER_SIDE */
1,
/* ADDR_WIDTH */
12,
/* DATA_WIDTH */
16)
DDR_SDRAM_MONITOR1 (
.clock
(clock),
.clock_n
(clock_n),
.reset
(reset),
.areset
(areset),
.CKE
(clock_enable_4[3:2]),

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.CS_n
(chip_select_4_n[3:2]),
.RAS_n
(row_address_strobe_n),
.CAS_n
(column_address_strobe_n),
.WE_n
(write_enable_n),
.BA
(bank_address),
.A
(address_bus_12),
.DM
(1'b0),
.DQ
(data_bus_32[31:16]),
.DQS
(1'b0),
.mode_register (),
.extended_mode_register (),
.LDQS (data_strobe),
.LDM (data_mask_4[2]),
.UDQS (data_strobe),
.UDM (data_mask_4[3]),
.TRC(32'b0),
.TRAS(32'b0),
.TRP(32'b0),
.TRCD(32'b0),
.TRRD(32'b0),
.TWR(32'b0),
.TWTR(32'b0),
.TMRD(32'b0),
.TRFC(32'b0),
.TXSNR(32'b0),
.TXSRD(32'b0),
.TCLK(32'b0) );

Example 3
Example 6-7 instantiates a DDR SDRAM 2.0 monitor for a Micron 64 Mb compatible
controller design. The example has the following characteristics:

The controller design interfaces a DDR SDRAM having 8-bit DATA_WIDTH and 12-bit
ADDR_WIDTH.

The other input signal width is as follows:


o

DM_WIDTH

DLL tracking is enabled. Therefore, the DLL_TRACKING_ENABLE parameter is set to 1.

The timing parameter values are as follows:


TRC
10
TRFC
11

148

of 1.

TRAS
7
TXSNR
10

TRP
3
TXSRD
200

TRCD
3
TWR
2

TRRD
2
TWTR
1

TMRD
2

Autoprecharge is enabled through address bit 8. Therefore, the


AUTOPRECHARGE_ENABLE_ADDRESS_BIT parameter is 8.

FPM mode is supported. FPM size is 256 and the number of address lines required to
burst up to 256 is 8. Therefore, the COL_ADDRESS_WIDTH is set to 8.

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The DLL tracking is enabled. Therefore, the DLL_TRACKING_ENABLE parameter is set to


1.

The monitor is instantiated for unconstrained search. Therefore, the Constraints_Mode


parameter is set to 0.
Example 6-7. DDR SDRAM 2.0 Monitor Instantiated in the Controller

qvl_ddr_sdram__2_0_monitor
#( /* Constraints_Mode */
0,
/* CONTROLLER_SIDE */
1,
/* ADDR_WIDTH */
12,
/* DATA_WIDTH */
8,
/* DLL_TRACKING_ENABLE */
1,
/* TRC_OVERRIDE */
10,
/* TRAS_OVERRIDE */
7,
/* TRP_OVERRIDE */
3,
/* TRCD_OVERRIDE */
3,
/* TRRD_OVERRIDE */
2,
/* TMRD_OVERRIDE */
2,
/* TRFC_OVERRIDE */
11,
/* TXSNR_OVERRIDE */
10,
/* TXSRD_OVERRIDE */
200,
/* TWR_OVERRIDE */
2,
/* TWTR_OVERRIDE */
1,
/* AUTOPRECHARGE_ENABLE_ADDRESS_BIT */ 8,
/* COL_ADDRESS_WIDTH */
8,
/* READ_BEFORE_WRITE_CHECK_ENABLE */
1,
/* CON_AUTO_PRECHARGE */
0,
/* ENABLE_WHY_PRECHARGE_AN_IDLE_BANK */0,
/* BYPASS_INIT*/
1)
DDR_SDRAM_MONITOR0 (
.clock
(clock),
.clock_n
clock_n),
.reset
(reset),
.areset
(areset),
.CKE
(clock_enable),
.CS_n
(chip_select_n),
.RAS_n
(row_address_strobe_n),
.CAS_n
(column_address_strobe_n),
.WE_n
(write_enable_n),
.BA
(bank_address),
.A
(address_bus_12),
.DM
(data_mask_1),
.DQ
(data_bus_8),
.DQS
(data_strobe),
.mode_register (internal_mode_register),
.extended_mode_register (internal_mode_register),
.LDQS (1'b0),
.LDM (1'b0),
.UDQS (1'b0),
.UDM (1'b0),
.TRC(32'b0),
.TRAS(32'b0),
.TRP(32'b0),
.TRCD(32'b0),

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V2.0 Monitor
.TRRD(32'b0),
.TWR(32'b0),
.TWTR(32'b0),
.TMRD(32'b0),
.TRFC(32'b0),
.TXSNR(32'b0),
.TXSRD(32'b0),
.TCLK(32'b0) );

The monitor is instantiated with BYPASS_INIT = 1 and internal signals are connected to the
monitor ports mode_register and extended_mode_register.

Example 4
Example 6-8 on page 150 instantiates a DDR SDRAM 2.0 monitor to check the controller with
NON JEDEC timing values configured through parameters. The example has the following
characteristics:

The controller design interfaces a DDR SDRAM having 8-bit DATA_WIDTH and 12-bit
ADDR_WIDTH.

The other input signal width is as follows:


o

DM_WIDTH of 1

DLL tracking is enabled. Therefore, the DLL_TRACKING_ENABLE parameter is set to 1.

The timing parameters are set to NON JEDEC values through the parameters. Therefore, the
NON_JEDEC parameter is 1 and USE_PORTS_TO_CONFIGURE parameter is 0. The NON JEDEC
timing parameter values are as follows:
TRC
12
TRFC
15

TRAS
8
TXSNR
13

TRP
4
TXSRD
250

TRCD
4
TWR
3

TRRD
4
TWTR
2

TMRD
4

Autoprecharge is enabled through address bit 8. Therefore, the


AUTOPRECHARGE_ENABLE_ADDRESS_BIT parameter is 8.

The DLL tracking is enabled. Therefore, the DLL_TRACKING_ENABLE parameter is set to


1.

The monitor is instantiated for unconstrained search. Therefore, the Constraints_Mode


parameter is set to 0.

Example 6-8. DDR SDRAM 2.0 Monitor Instantiated with NON JEDEC Timing
Values Configured Through Parameters
qvl_ddr_sdram_2_0_monitor
#( /* Constraints_Mode */
/* CONTROLLER_SIDE */
/* ADDR_WIDTH */
/* DATA_WIDTH */

150

0,
1,
12,
8,

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Double Data Rate SDRAM (DDR SDRAM)


V2.0 Monitor
/* DLL_TRACKING_ENABLE */
1,
/* TRC_OVERRIDE */
12,
/* TRAS_OVERRIDE */
8,
/* TRP_OVERRIDE */
4,
/* TRCD_OVERRIDE */
4,
/* TRRD_OVERRIDE */
4,
/* TMRD_OVERRIDE */
4,
/* TRFC_OVERRIDE */
15,
/* TXSNR_OVERRIDE */
13,
/* TXSRD_OVERRIDE */
250,
/* TWR_OVERRIDE */
3,
/* TWTR_OVERRIDE */
2,
/* AUTOPRECHARGE_ENABLE_ADDRESS_BIT */ 8,
/* COL_ADDRESS_WIDTH */
8,
/* READ_BEFORE_WRITE_CHECK_ENABLE */
1,
/* CON_AUTO_PRECHARGE */
0,
/* ENABLE_WHY_PRECHARGE_AN_IDLE_BANK */0,
/* BYPASS_INIT*/
1,
/* NON_JEDEC*/
1,
/* USE_PORTS_TO_CONFIGURE*/
0,
/* DATA_CHECK_ENABLE */
0,
/* ZI_DDR_SDRAM_2_0 */
1,
/* DM_WIDTH */
1,
/* CLOCK_CHANGE_TRACKING_ENABLE */
1,
/* TCLK_CHECK_ENABLE */
1,
/* TCLK_OVERRIDE */
3,
/* CLOCK_FREQUENCY_RANGE_CHECK_ENABLE*/1,
/* CLOCK_PERIOD_MAX */
10,
/* CLOCK_PERIOD_MIN */
5,
/* NO_SET_CAS_LATENCY_CHECK_ENABLE */ 1)
DDR_SDRAM_MONITOR0 (
.clock
(clock),
.clock_n
(clock_n),
.reset
(reset),
.areset
(areset),
.CKE
(clock_enable),
.CS_n
(chip_select_n),
.RAS_n
(row_address_strobe_n),
.CAS_n
(column_address_strobe_n),
.WE_n
(write_enable_n),
.BA
(bank_address),
.A
(address_bus_12),
.DM
(data_mask_1),
.DQ
(data_bus_8),
.DQS
(data_strobe),
.mode_register (internal_mode_register),
.extended_mode_register (internal_mode_register),
.LDQS (1'b0),
.LDM (1'b0),
.UDQS (1'b0),
.UDM (1'b0),
.TRC(32'b0),
.TRAS(32'b0),
.TRP(32'b0),
.TRCD(32'b0),
.TRRD(32'b0),
.TWR(32'b0),
.TWTR(32'b0),

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V2.0 Monitor
.TMRD(32'b0),
.TRFC(32'b0),
.TXSNR(32'b0),
.TXSRD(32'b0),
.TCLK(32'b0) );

The monitor is instantiated with BYPASS_INIT = 1 and internal signals are connected to the
monitor ports mode_register and extended_mode_register.
Note that this example also shows parameter configuration for enabling clock frequency change
support model of the monitor.

Example 5
Example 6-9 on page 152 instantiates a DDR SDRAM 2.0 monitor to check the controller with
NON JEDEC timing values configured through input ports. The example has the following
characteristics:

The controller design interfaces a DDR SDRAM having 8-bit DATA_WIDTH and 12-bit
ADDR_WIDTH.

The other input signal width is as follows:


o

DM_WIDTH

of 1.

DLL tracking is enabled. Therefore, the DLL_TRACKING_ENABLE parameter is set to 1.

The timing parameters are set to NON JEDEC values through the input ports. Therefore,
the NON_JEDEC parameter is 1 and the USE_PORTS_TO_CONFIGURE parameter is 1. The
NON JEDEC timing parameter values are as follow:
TRC
12
TRFC
15

TRAS
8
TXSNR
13

TRP
4
TXSRD
250

TRCD
4
TWR
3

TRRD
4
TWTR
2

TMRD
4

Autoprecharge is enabled through address bit 8. Therefore, the


AUTOPRECHARGE_ENABLE_ADDRESS_BIT parameter is 8.

The DLL tracking is enabled. Therefore, the DLL_TRACKING_ENABLE parameter is set to


1.

The monitor is instantiated for unconstrained search. Therefore, the Constraints_Mode


parameter is set to 0.

Example 6-9. DDR SDRAM 2.0 Monitor Instantiated with NON JEDEC Timing
Values Configured Through Input Ports
qvl_ddr_sdram_2_0_monitor
#( /* Constraints_Mode */
/* CONTROLLER_SIDE */
/* ADDR_WIDTH */

152

0,
1,
12,

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Double Data Rate SDRAM (DDR SDRAM)


V2.0 Monitor
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*

DATA_WIDTH */
8,
DLL_TRACKING_ENABLE */
1,
TRC_OVERRIDE */
12,
TRAS_OVERRIDE */
8,
TRP_OVERRIDE */
4,
TRCD_OVERRIDE */
4,
TRRD_OVERRIDE */
4,
TMRD_OVERRIDE */
4,
TRFC_OVERRIDE */
15,
TXSNR_OVERRIDE */
13,
TXSRD_OVERRIDE */
250,
TWR_OVERRIDE */
3,
TWTR_OVERRIDE */
2,
AUTOPRECHARGE_ENABLE_ADDRESS_BIT */ 8,
COL_ADDRESS_WIDTH */
8,
READ_BEFORE_WRITE_CHECK_ENABLE */
1,
CON_AUTO_PRECHARGE */
0,
ENABLE_WHY_PRECHARGE_AN_IDLE_BANK */0,
BYPASS_INIT*/
1,
NON_JEDEC*/
1,
USE_PORTS_TO_CONFIGURE*/
1,
DATA_CHECK_ENABLE */
0,
ZI_DDR_SDRAM_2_0 */
1,
DM_WIDTH */
1,
CLOCK_CHANGE_TRACKING_ENABLE */
1,
TCLK_CHECK_ENABLE */
1,
TCLK_OVERRIDE */
2, // This parameter will
// not be effective as the
// port TCLK will be used
// to configure
// this timing parameter.
/* CLOCK_FREQUENCY_RANGE_CHECK_ENABLE*/1,
/* CLOCK_PERIOD_MAX */
10, // Specified in
// nanoseconds for a
// 100 MHz clock.
/* CLOCK_PERIOD_MIN */
5) // Specified in
// nanoseconds for a
// 200 MHz clock.
DDR_SDRAM_MONITOR0 (
.clock
(clock),
.clock_n
(clock_n),
.reset
(reset),
.areset
(areset),
.CKE
(clock_enable),
.CS_n
(chip_select_n),
.RAS_n
(row_address_strobe_n),
.CAS_n
(column_address_strobe_n),
.WE_n
(write_enable_n),
.BA
(bank_address),
.A
(address_bus_12),
.DM
(data_mask_1),
.DQ
(data_bus_8),
.DQS
(data_strobe),
.mode_register (internal_mode_register),
.extended_mode_register (internal_mode_register),
.LDQS (1'b0),
.LDM (1'b0),
.UDQS (1'b0),

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.UDM (1'b0),
.TRC(32'd11),
.TRAS(32'd7),
.TRP(32'd3),
.TRCD(32'd3),
.TRRD(32'd3),
.TWR(32'd2),
.TWTR(32'd1),
.TMRD(32'd3),
.TRFC(32'd14),
.TXSNR(32'd12),
.TXSRD(32'd249),
.TCLK(32'd3) );

The monitor is instantiated with BYPASS_INIT = 1 and internal signals are connected to the
monitor ports mode_register and extended_mode_register.
Note that this example also shows parameter configuration for enabling clock frequency change
support model of the monitor.

Monitor Checks
Table 6-18 shows the checks performed by a DDR SDRAM 2.0 monitor.
Table 6-18. DDR SDRAM 2.0 Monitor Checks
Check ID

Violation

Description

DDR_SDRAM_ADDRESS

Address bus, A, has a X or Z


value.

Address bus, A, should have a valid


value when mode register set/extended
mode register set/read/write/read with
auto precharge/write with auto
precharge/bank activation command is
issued.

DDR_SDRAM_BA

Bank address bus, BA, has a X


or Z value.

Bank address bus, BA, should have a


valid value when read/write/read with
auto precharge/write with auto
precharge/bank activation/single bank
precharge command is issued.

DDR_SDRAM_BYPASS_INIT

BYPASS_INIT should be
either 1 or 0.

The value of the BYPASS_INIT


parameter should be either 1 or 0.

DDR_SDRAM_CAS_n

Column address strobe,


CAS_n, has a X or Z value.

Column address strobe, CAS_n, must


always have a valid value. This check
is active only if CKE is high and CS_n
is low.

DDR_SDRAM_CKE

Clock enable, CKE, has a X or


Z value.

Clock enable, CKE, must always have


a valid value.

DDR_SDRAM_Constraint_Mode

Constraints_Mode should be
either 1 or 0.

The value of Constraints_Mode


parameter value should be either 1 or 0.

DDR_SDRAM_CONTROLLER_
SIDE

CONTROLLER_SIDE should The value of CONTROLLER_SIDE


be either 1 or 0.
parameter value should be either 1 or 0.

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V2.0 Monitor

Table 6-18. DDR SDRAM 2.0 Monitor Checks (cont.)


Check ID

Violation

Description

DDR_SDRAM_CS_n

Chip select, CS_n, has a X or


Z value.

Chip select, CS_n, must always have a


valid value. This check is active only if
CKE is high.

DDR_SDRAM_DATA_CONFIG

Data bus width should be


either 4, 8, or 16.

The value of the DATA_WIDTH


parameter should not be specified to be
other than 4, 8, or 16 since this
indicates the configuration of the data
bus and the allowed configurations are
x4, x8, or x16.

DDR_SDRAM_DLL_TRACKING_
ENABLE

DLL_TRACKING_ENABLE
should be either 1 or 0.

The value of the


DLL_TRACKING_ENABLE
parameter should be either 1 or 0.

DDR_SDRAM_DM

Data mask, DM, has a X or Z


value.

Data mask, DM, must always have a


valid value. This check is active only if
CKE is high and a valid write data
phase is in progress.

DDR_SDRAM_DM_WIDTH

Data mask width should not be


less than the minimum limit of
1.

The value of the DM_WIDTH


parameter should not be less than 1.

DDR_SDRAM_incorrect_
command_before_mode_reg_set

A command that should not be This check is applicable only if


issued before the mode
BYPASS_INIT is set to 0 (that is, a
register set command is issued. proper MRS cycle is performed). NOP,
precharge, and refresh are the only
commands that are valid before the
MODE REGISTER SET. The user
should check the designs reset
sequencing.

DDR_SDRAM_invalid_burst_
length

The burst length field of the


input mode register is invalid.

This check is applicable only if


BYPASS_INIT is set and
NON_JEDEC is 0. As per the JEDEC
specification, the valid burst length
values are 2 (3b001), 4 (3'b010), 8
(3'b011), and Full Page Mode (FPM)
(3'b111). This check fires if a burst
length value other than the ones listed
above is passed through the
mode_register input.

DDR_SDRAM_invalid_burst_
length_value_in_mode_reg_set

Invalid burst length value


during the mode register set
command.

This check is applicable only when the


NON_JEDEC parameter is set to 0. As
per the JEDEC specification, the valid
burst length values are 2 (3'b001), 4
(3'b010), 8 (3'b011), and Full Page
Mode (FPM) (3'b111). This check fires
if a burst length value other than the
ones listed above is programmed.

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Table 6-18. DDR SDRAM 2.0 Monitor Checks (cont.)


Check ID

Violation

Description

DDR_SDRAM_invalid_cas_latency

The CAS latency field of the


input mode register is invalid.

This check is applicable only if


BYPASS_INIT is set and
NON_JEDEC is 0. As per the JEDEC
specification, the valid CAS latency
values are 1.5 (3'b101), 2 (3'b010), 2.5
(3'b110), 3 (3'b011), and 4 (3'b100).
This check fires if a CAS latency value
other than the ones listed above is
passed through the mode_register
input.

DDR_SDRAM_invalid_cas_
latency_value_in_mode_reg_set

Invalid CAS latency value


during the mode register set
command.

This check is applicable only when the


NON_JEDEC parameter is set to 0. As
per the JEDEC specification, the valid
CAS latency values are 1.5 (3'b101), 2
(3'b010), 2.5 (3'b110), 3 (3'b011), and 4
(3'b100). This check fires if a CAS
latency value other than the ones listed
above is programmed.

DDR_SDRAM_invalid_operating_
mode

The operating mode field in


the mode register or extended
mode register input is invalid.

This check is applicable only if


BYPASS_INIT is set and an incorrect
value is passed to the mode_register
input. As per the JEDEC specification,
for normal operation, A[11:7] should
be either 5'b00000 or 5'b00010 in the
mode register and A[11:3] should be
9'b000000000 in the extended mode
register. EXTENDED MODE
REGISTER SET command. This check
fires if values other than the above are
passed to the corresponding inputs.

DDR_SDRAM_invalid_operating_
mode_bits_mrs_or_emrs

Invalid operating mode bits


are programmed during mode
register set or extended mode
register set command.

As per the JEDEC specification, for


normal operation, A[11:7] should be
either 5'b00000 or 5'b00010 during
MODE REGISTER SET command,
and A[11:3] should be 9'b000000000
during EXTENDED MODE
REGISTER SET command. This check
fires if a value other than the ones listed
above is driven on address bus (A)
during MODE REGISTER SET or
EXTENDED MODE REGISTER SET
command is issued.

DDR_SDRAM_RAS_n

Row address strobe, RAS_n,


has a X or Z value.

Row address strobe, RAS_n, must


always have a valid value. This check
is active only if CKE is high and CS_n
is low.

DDR_SDRAM_TMRD

TMRD value should not be


less than the minimum limit of
2.

This check is applicable only when the


NON_JEDEC parameter is set to 0.
The value of the TMRD timing
parameter should not be specified to be
less than 2.

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V2.0 Monitor

Table 6-18. DDR SDRAM 2.0 Monitor Checks (cont.)


Check ID

Violation

Description

DDR_SDRAM_TRAS

TRAS value should not be less


than the minimum limit of 4.

This check is applicable only when the


NON_JEDEC parameter is set to 0.
The value of the TRAS timing
parameter should not be specified to be
less than 4.

DDR_SDRAM_TRC

TRC value should not be less


than the minimum limit of 5.

This check is applicable only when the


NON_JEDEC parameter is set to 0.
The value of the TRC timing parameter
should not be specified to be less than
5.

DDR_SDRAM_TRCD

TRCD value should not be less This check is applicable only when the
than the minimum limit of 2.
NON_JEDEC parameter is set to 0.
The value of the TRCD timing
parameter should not be specified to be
less than 2.

DDR_SDRAM_TRFC

TRFC value should not be less


than the minimum limit of 6.

This check is applicable only when the


NON_JEDEC parameter is set to 0.
The value of the TRFC timing
parameter should not be specified to be
less than 6.

DDR_SDRAM_TRP

TRP value should not be less


than the minimum limit of 2.

This check is applicable only when the


NON_JEDEC parameter is set to 0.
The value of the TRP timing parameter
should not be specified to be less than
2.

DDR_SDRAM_TRRD

TRRD value should not be less This check is applicable only when the
than the minimum limit of 1.
NON_JEDEC parameter is set to 0.
The value of the TRRD timing
parameter should not be specified to be
less than 1.

DDR_SDRAM_TWR

TWR value should not be less


than the minimum limit of 1.

This check is applicable only when the


NON_JEDEC parameter is set to 0.
The value of the TWR timing
parameter should not be specified to be
less than 1.

DDR_SDRAM_TXSNR

TXSNR value should not be


less than the minimum limit of
6.

This check is applicable only when the


NON_JEDEC parameter is set to 0.
The value of the TXSNR timing
parameter should not be specified to be
less than 6.

DDR_SDRAM_TXSRD

TXSRD value should not be


less than the minimum limit of
200.

This check is applicable only when the


NON_JEDEC parameter is set to 0.
The value of the TXSRD timing
parameter should not be specified to be
less than 200.

DDR_SDRAM_violates_tRRD

An activate command is issued The command just issued violates


too quickly after the prior
tRRD (RAS to RAS delay timing). This
activate command.
is an ACTIVATE command issued too
quickly after the ACTIVATE
command for another bank. The user
should determine why the commands
are too close together.

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V2.0 Monitor

Table 6-18. DDR SDRAM 2.0 Monitor Checks (cont.)


Check ID

Violation

Description

DDR_SDRAM_WE_n

Write enable, WE_n, has a X


or Z value.

Write enable, WE_n, must always have


a valid value. This check is active only
if CKE is high and CS_n is low.

Table 6-19 shows the checks for each bank performed by a DDR SDRAM 2.0 monitor.
Table 6-19. DDR SDRAM 2.0 Monitor Checks for Each Bank
Check ID

Violation

Description

A_DDR_SDRAM_clock_change_
during_non_ppd_mode

Clock frequency has changed


while the DDR SDRAM is not
in precharge power down
mode.

The input clock frequency can change


only in precharge power down mode
while the clock enable signal CKE is
LOW. This check fires when the DDR
SDRAM clock changes while the DDR
SDRAM is not operating in idle or
precharge power down mode. This
check is functional only when the
parameter CLOCK_CHANGE_
TRACKING_ENABLE is set to 1.

A_DDR_SDRAM_clock_change_
during_illegal_cke

Clock frequency has changed


while CKE is not LOW.

The input clock frequency can change


only in precharge power down mode
while the clock enable signal CKE is
LOW. This check fires when the DDR
SDRAM clock changes while CKE is
not LOW. This check is functional only
when the parameter CLOCK_
CHANGE_TRACKING_ENABLE is
set to 1.

A_DDR_SDRAM_violates_tCLK

A command that violates


TCLK cycle timing is issued.

The input clock frequency can change


only in precharge power down mode
while the clock enable signal CKE is
LOW. This check fires when the DDR
SDRAM clock changes before elapse of
a minimum of clock cycles specified by
port TCLK (subject to the setting of
USE_PORTS_CONFIGURE = 1) or
parameter TCLK_OVERRRIDE after
CKE is LOW. This check is functional
only when both the parameter
CLOCK_CHANGE_TRACKING_
ENABLE and
TCLK_CHECK_ENABLE are set to 1.

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V2.0 Monitor

Table 6-19. DDR SDRAM 2.0 Monitor Checks for Each Bank (cont.)
Check ID

Violation

Description

A_DDR_SDRAM_clock_
frequency_out_of_range

The clock frequency is out of


the allowed range in the
current speed grade of DDR
SDRAM.

The input clock frequency can change


only within the allowed range in a speed
grade. This check fires when the DDR
SDRAM clock changes beyond the
allowed clock frequency range specified
by the parameters
CLOCK_PERIOD_MAX and
CLOCK_PERIOD_MIN. By default,
the monitor verifies a range of 100Mhz
to 200 MHz. This check is functional
only when both the parameters
CLOCK_CHANGE_TRACKING_
ENABLE and
CLOCK_FREQUENCY_RANGE_
CHECK_ENABLE are set to 1.

A_DDR_SDRAM_CKE_changed_
during_unstable_clock

CKE changed state while the


clock is not yet stable.

The input clock frequency can change


only in precharge power down mode
while the clock enable signal CKE is
LOW. This check fires when after a
clock frequency change, CKE changes
its state before a stable clock is
available. This check is functional only
when the parameter
CLOCK_CHANGE_TRACKING_
ENABLE is set to 1.

A_DDR_SDRAM_ppd_exit_
during_unstable_clock

Precharge power down mode


exited during an unstable
clock.

The input clock frequency can change


only in precharge power down mode
while the clock enable signal CKE is
LOW. This check fires when after a
clock frequency change, precharge
power down mode is exited before a
stable clock is available. This check is
functional only when the parameter
CLOCK_CHANGE_TRACKING_
ENABLE is set to 1.

A_DDR_SDRAM_dll_not_reset_
after_ppd_exit_after_clock_change

DLL is not reset after


precharge power down exit
after clock change.

This check fires when a DLL reset


command is not executed after a clock
frequency change. This check is
functional only when both the
parameters CLOCK_CHANGE_
TRACKING_ENABLE and
DLL_TRACKING_ENABLE are set to
1.

DDR_SDRAM_bad_data

One or more bytes of data


read from the addressed DDR
SDRAM location did not
match the data byte(s) written
to the corresponding address.

Data read from the DDR SDRAM did


not match the data written to the
corresponding address. The data check
is performed only on reads to locations
that were previously written at least
once. Data checking is done on a byte
basis and the bitmap indicates the data
inconsistency between the
corresponding bytes. This check fires
when at least one byte of read data does
not match the corresponding valid data
byte that is written to that location.

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Table 6-19. DDR SDRAM 2.0 Monitor Checks for Each Bank (cont.)
Check ID

Violation

Description

DDR_SDRAM_con_auto_
precharge_min_delay_violation

Concurrent Auto Precharge


minimum delay violation.

Some devices support Concurrent Auto


Precharge feature such that when a read
with auto precharge or write with auto
precharge is enabled to one bank, any
command to other bank can be issued as
long as this command does not interrupt
the earlier command. The minimum
delay between the read/write command
with auto precharge to a command to a
different bank has to be met in this case.
This check fires when the minimum
delay in terms of clock cycle is violated.
This check is enabled only if the
CON_AUTO_PRECHARGE parameter
is set to 1.

DDR_SDRAM_illegal_command_
active

Illegal command is issued


when the bank is in ACTIVE
state.

The command just issued is not legal


when the bank is in ACTIVE state. All
the valid commands for ACTIVE state
are listed in the JEDEC specification
under TRUTH TABLE 2, 3, and 4. Any
command other than these are treated as
illegal commands by the monitor. When
this check fires, the current state of the
bank is encoded in the state_string
signal of the module
qvl_ddr_sdram_bank_monitor.

DDR_SDRAM_illegal_command_
aref

Illegal command is issued


when all the banks are in
AUTO REFRESH state.

The command just issued is not legal


when the bank is in AUTO REFRESH
state. All the valid commands for
AUTO REFRESH state are listed in the
JEDEC specification under TRUTH
TABLE 2, 3, and 4. Any command
other than these are treated as illegal
commands by the monitor. When this
check fires, the current state of the bank
is encoded in the state_string signal of
the module
qvl_ddr_sdram_bank_monitor.

DDR_SDRAM_illegal_command_
emrs

Illegal command is issued


when all the banks are in
EXTENDENDED MODE
REGISTER SET state.

The command just issued is not legal


when the bank is in EXTENDENDED
MODE REGISTER SET state. All the
valid commands for EXTENDENDED
MODE REGISTER SET state are listed
in the JEDEC specification under
TRUTH TABLE 2, 3, and 4. Any
command other than these are treated as
illegal commands by the monitor. When
this check fires, the current state of the
bank is encoded in the state_string
signal of the module
qvl_ddr_sdram_bank_monitor.

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V2.0 Monitor

Table 6-19. DDR SDRAM 2.0 Monitor Checks for Each Bank (cont.)
Check ID

Violation

Description

DDR_SDRAM_illegal_command_
idle

Illegal command is issued


when the bank is in IDLE
state.

The command just issued is not legal


when the bank is in IDLE state. All the
valid commands for IDLE state are
listed in the JEDEC specification under
TRUTH TABLE 2, 3, and 4. Any
command other than these are treated as
illegal commands by the monitor. When
this check fires, the current state of the
bank is encoded in the state_string
signal of the module
qvl_ddr_sdram_bank_monitor.

DDR_SDRAM_illegal_command_
mrs

Illegal command is issued


when all the banks are in
MODE REGISTER SET
state.

The command just issued is not legal


when the bank is in MODE REGISTER
SET state. All the valid commands for
MODE REGISTER SET state are listed
in the JEDEC specification under
TRUTH TABLE 2, 3, and 4. Any
command other than these are treated as
illegal commands by the monitor. When
this check fires, the current state of the
bank is encoded in the state_string
signal of the module
qvl_ddr_sdram_bank_monitor.

DDR_SDRAM_illegal_command_
pall

Illegal command is issued


when all the banks are in
PRECHARGE state.

The command just issued is not legal


when the bank is in PRECHARGE ALL
state. All the valid commands for
PRECHARGE ALL state are listed in
the JEDEC specification under TRUTH
TABLE 2, 3, and 4. Any command
other than these are treated as illegal
commands by the monitor. When this
check fires, the current state of the bank
is encoded in the state_string signal of
the module
qvl_ddr_sdram_bank_monitor.

DDR_SDRAM_illegal_command_
pre

Illegal command is issued


when the bank is in
PRECHARGE state.

The command just issued is not legal


when the bank is in PRECHARGE
state. All the valid commands for
PRECHARGE state are listed in the
JEDEC specification under TRUTH
TABLE 2, 3, and 4. Any command
other than these are treated as illegal
commands by the monitor. When this
check fires, the current state of the bank
is encoded in the state_string signal of
the module
qvl_ddr_sdram_bank_monitor.

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Table 6-19. DDR SDRAM 2.0 Monitor Checks for Each Bank (cont.)
Check ID

Violation

Description

DDR_SDRAM_illegal_command_
read

Illegal command is issued


when the bank is in READ
state.

The command just issued is not legal


when the bank is in READ state. All the
valid commands for READ state are
listed in the JEDEC specification under
TRUTH TABLE 2, 3, and 4. Any
command other than these are treated as
illegal commands by the monitor. When
this check fires, the current state of the
bank is encoded in the state_string
signal of the module
qvl_ddr_sdram_bank_monitor.

DDR_SDRAM_illegal_command_
reada

Illegal command is issued


when the bank is in READ
WITH AUTO PRECHARGE
state.

The command just issued is not legal


when the bank is in READ WITH
AUTO PRECHARGE state. All the
valid commands for READ WITH
AUTO PRECHARGE state are listed in
the JEDEC specification under TRUTH
TABLE 2, 3, and 4. Any command
other than these are treated as illegal
commands by the monitor. When this
check fires, the current state of the bank
is encoded in the state_string signal of
the module
qvl_ddr_sdram_bank_monitor.

DDR_SDRAM_illegal_command_
write

Illegal command is issued


when the bank is in WRITE
state.

The command just issued is not legal


when the bank is in WRITE state. All
the valid commands for WRITE state
are listed in the JEDEC specification
under TRUTH TABLE 2, 3, and 4. Any
command other than these are treated as
illegal commands by the monitor. When
this check fires, the current state of the
bank is encoded in the state_string
signal of the module
qvl_ddr_sdram_bank_monitor.

DDR_SDRAM_illegal_command_
writea

Illegal command is issued


when the bank is in WRITE
WITH AUTOPRECHARGE
state.

The command just issued is not legal


when the bank is in WRITE WITH
AUTOPRECHARGE state. All the
valid commands for WRITE WITH
AUTOPRECHARGE state are listed in
the JEDEC specification under TRUTH
TABLE 2, 3, and 4. Any command
other than these are treated as illegal
commands by the monitor. When this
check fires, the current state of the bank
is encoded in the state_string signal of
the module
qvl_ddr_sdram_bank_monitor.

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Table 6-19. DDR SDRAM 2.0 Monitor Checks for Each Bank (cont.)
Check ID

Violation

Description

DDR_SDRAM_invalid_self_ref_or_ Only NOP or DSEL command


power_down_exit
should be issued during SELF
REFRESH or POWER
DOWN exit.

When DDR SDRAM is exited from the


SELF REFRESH or POWER DOWN
mode, only NOP or DESELECT
command should be issued along with
the SELF REFRESH EXIT or POWER
DOWN EXIT command. This check
fires if a NOP or DESELECT command
is not issued during SELF REFRESH or
POWER DOWN exit.

DDR_SDRAM_no_auto_ refresh

At least two auto refresh


commands should be issued
after reset and before first
active command.

Minimum two auto refresh commands


should be issued after reset and before
the first activate command is issued.
This check fires if there is no auto
refresh command or only one auto
refresh command is issued before the
first active command issue.

DDR_SDRAM_no_dll_ reset

DLL is not reset after it is


enabled.

If DLL is enabled through EXTENDED


MODE REG SET command, then there
should be a DLL reset command issued
before an activate command is issued.

DDR_SDRAM_read_before_write

A read operation was


performed on the DDR
SDRAM address that was not
previously written into.

Data is read from a DDR SDRAM


address that was not previously written
into. This check fires whenever a
location being read was previously not
written into.

DDR_SDRAM_violates_tDLL

At least 200 clocks delay


should be given between the
DLL enable and a read/read
with auto precharge
command.

If DLL is enabled, then there should be


a minimum of 200 clocks delay before a
read command or read with
autoprecharge command is issued.

DDR_SDRAM_violates_CKE_
signal_P

CKE is low when the control


signals and/or the monitor
state machine are not pointing
to SELF REFRESH or
POWER DOWN mode.

CKE should not go low when the DDR


SDRAM is performing a READ or
WRITE burst. The user should
determine why CKE goes low when the
DDR SDRAM is performing a READ
or WRITE burst.

DDR_SDRAM_violates_CKE_
signal_N * (see the note at the end of
this table)

CKE is low when the control


signals and/or the state
machine are not computing to
SELF REFRESH or POWER
DOWN mode.

CKE should not go low when the DDR


SDRAM is performing a READ or
WRITE burst. You should determine
why CKE goes low when the DDR
SDRAM is performing a READ or
WRITE burst.

DDR_SDRAM_violates_tMRD

A command that violates


tMRD timing is issued.

The command just issued violates


tMRD (minimum time delay between
MODE REGISTER SET command and
any other command) timing. The new
command is issued too quickly after the
MODE REGISTER SET command.
The user should determine why the
commands are too close together.

DDR_SDRAM_violates_CKE_
signal_N

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Table 6-19. DDR SDRAM 2.0 Monitor Checks for Each Bank (cont.)
Check ID

Violation

DDR_SDRAM_violates_tRAS

A command that violates RAS The command just issued violates tRAS
timing is issued.
(RAS to precharge timing). This is a
PRECHARGE command issued too
quickly after the ACTIVATE command
for this bank. The user should determine
why the commands are too close
together.

DDR_SDRAM_violates_tRC

A command that violates RAS The command just issued violates tRC
cycle timing is issued.
(RAS cycle timing). This is an
ACTIVATE/REFRESH command
issued too quickly after the last
ACTIVATE command for this bank.
The user should determine why the
commands are too close together.

DDR_SDRAM_violates_tRCD

A command that violates RAS The command just issued violates tRCD
to CAS delay timing is issued. (RAS to CAS delay timing). This is a
READ/WRITE command issued too
quickly after the ACTIVATE command
for this bank. The user should determine
why the commands are too close
together.

DDR_SDRAM_violates_tRFC

A command that violates


tRFC timing is issued.

DDR_SDRAM_violates_tRP

A command that violates RAS The command just issued violates tRP
precharge timing is issued.
(RAS precharge timing). This is an
ACTIVATE/REFRESH command
issued too quickly after the last
precharge command for this bank. The
user should determine why the
commands are too close together.

DDR_SDRAM_violates_tXSNR

A command that violates


tXSNR timing is issued.

The command just issued violates


tXSNR (minimum time delay between
SELF REFRESH EXIT command and
any other non-READ command)
timing. A non-READ command is
issued too quickly after the SELF
REFRESH EXIT command. The user
should determine why the commands
are too close together.

DDR_SDRAM_violates_tXSRD

A read/read with auto


precharge command that
violates tXSRD timing is
issued.

The READ command just issued


violates tXSRD (minimum time delay
between SELF REFRESH EXIT
command and a READ command)
timing. A READ command is issued too
quickly after the SELF REFRESH
EXIT command. The user should
determine why the commands are too
close together.

164

Description

The command just issued violates tRFC


(minimum time delay between AUTO
REFRESH command and any other
command). The new command is issued
too quickly after the AUTO REFRESH
command. The user should determine
why the commands are too close
together.

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V2.0 Monitor

Table 6-19. DDR SDRAM 2.0 Monitor Checks for Each Bank (cont.)
Check ID

Violation

Description

DDR_SDRAM_why_precharge_
an_idle_bank

A PRECHARGE command is
issued while the bank is
already in a precharged state.

The design is precharging (not an allbank PRECHARGE) a bank that has


already been precharged. Although not
illegal, this is inefficient. The user
should examine why the extra
PRECHARGE command is issued. This
check is enabled only when ENABLE_
WHY_PRECHARGE_AN_IDLE_
BANK parameter is set to 1.

* The DDR_SDRAM_violates_CKE_signal_N check is active on the positive edge of the clock_n


(complementary clock) signal. All other checks are active on the positive edge of the clock signal.

The minimum delay from a read/write with auto precharge command to any command to a
different bank is calculated as shown in Table 6-20.
Table 6-20. Calculate Minimum Delay From a read/Write
From Command

To Command

Minimum Delay in Cycles

Write with AP

Read or Read AP

(BL/2) + tWR +1

Write or Write AP

BL/2

Precharge or Active

Read or Read AP

BL/2

Write or Write AP

CL + (BL/2)

Precharge or Active

Read with AP

BL = burst length
CL = CAS latency rounded up to next integer

Monitor Corner Cases


Table 6-21 shows the corner cases captured by the DDR SDRAM 2.0 monitor for the protocol.
Table 6-21. DDR SDRAM 2.0 Monitor Corner Cases
Corner Case

Description

Read Commands

Number of read operations from any bank in the DDR SDRAM.

Write Commands

Number of write operations to any bank in the DDR SDRAM.

Precharge Commands

Number of Precharge commands issued to the DDR SDRAM.

Burst Stop Commands

Number of times a Burst Stop command is issued to the DDR SDRAM.

Mode Register Set Commands

Number of times a Mode Register Set command is issued to the DDR


SDRAM.

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Table 6-21. DDR SDRAM 2.0 Monitor Corner Cases (cont.)


Corner Case

Description

CBR (auto) Refresh Commands

Number of times a CBR (auto) Refresh is issued to the DDR SDRAM.

Self Refresh Commands

Number of times a Self Refresh command is issued to the DDR


SDRAM.

Power Down Commands

Number of times a Power Down command is issued to the DDR


SDRAM.

Extended Mode Register Set


Commands

Number of times EXTENDED MODE REGISTER SET is issued to


DDR SDRAM.

Precharge all Commands

Number of times PRECHARGE ALL command is issued to DDR


SDRAM.

NOP Commands

Number of times a NOP command is issued to the DDR SDRAM.

Deselect Commands

Number of times the chip select signal (CS_n) of the DDR SDRAM is
de-asserted.

Table 6-22 shows the corner cases captured by the DDR SDRAM 2.0 monitor for each DDR
SDRAM bank.
Table 6-22. DDR SDRAM 2.0 Monitor Corner Cases Maintained for Each Bank

166

Corner Case

Description

Read Commands

Number of read operations from the bank in the DDR SDRAM.

Write Commands

Number of write operations to the bank in the DDR SDRAM.

Read without auto precharge


Commands

Number of read (without auto-precharge) operations from the bank in


the DDR SDRAM.

Read with auto precharge


Commands

Number of read (with auto-precharge) operations from the bank in


the DDR SDRAM.

Write without auto precharge


Commands

Number of write (without auto-precharge) operations from the bank


in the DDR SDRAM.

Write with auto precharge


Commands

Number of write (with auto-precharge) operations from the bank in


the DDR SDRAM.

Read after Read in Page

Number of times a read operation is issued to a page that is already


opened for read in the bank.

Read after Write in Page

Number of times a read operation is issued to a page that is already


opened for write in the bank.

Write after Read in Page

Number of times a write operation is issued to a page that is already


opened for read in the bank.

Write after Write in Page

Number of times a write operation is issued to a page that is already


opened for write in the bank.

Precharge Commands

Number of precharge commands issued to the bank.

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Double Data Rate SDRAM (DDR SDRAM)


V2.0 Monitor

Table 6-22. DDR SDRAM 2.0 Monitor Corner Cases Maintained for Each Bank
Corner Case

Description

Burst Operations Terminated

Number times a burst operation to the bank is terminated before it is


completed. This could be due to a Burst Stop command or if another
read or write command to the bank is issued before a current burst
operation is completed.

Monitor Statistics
Table 6-23 shows the corner cases captured by the DDR SDRAM 2.0 monitor for the protocol.
Table 6-23. DDR SDRAM 2.0 Monitor Statistics
Statistic

Description

Active Commands

Number of times any bank in the DDR SDRAM is selected.

Table 6-24 shows the corner cases captured by the DDR SDRAM 2.0 monitor for each DDR
SDRAM bank.
Table 6-24. DDR SDRAM 2.0 Monitor Statistics Maintained for Each Bank
Statistic

Description

Active Commands

Number times the bank in the DDR SDRAM is selected.

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Chapter 7
Double Data Rate-II SDRAM (DDR-II SDRAM)
Introduction
The QVL Double Data Rate-II SDRAM (DDR-II SDRAM) monitor provides a method of
debugging DDR-II SDRAM system designs by checking that the operation of the design is
compliant with the JEDEC standard.
The DDR-II SDRAM monitor tracks all operations to the DDR-II SDRAM subsystem for a
single row of DDR-II SDRAMs. To check multiple memory rows, the user can instantiate
multiple instances of the DDR-II SDRAM monitor. Each DDR-II SDRAM monitor instance
checks operations on a virtual four-bank DDR-II SDRAM by monitoring the states of each bank
and by setting and relaxing cycle-based timing checks on all operations on the banks.
The DDR-II SDRAM monitor instance determines illegal command sequences by comparing
the bank-state against command issue. Checks for illegal commands and cycle-based timing
problems can be used as formal targets. The user can use formal analysis to find legal stimulus
sequences (that is, corner case behavior) that direct your controller design to violate legal DDRII SDRAM memory subsystem operations.

V1.0 Monitor
Reference Documentation
This DDR-II SDRAM 1.0 monitor is modeled on the requirements provided in the following
document:

JEDEC Double Data Rate - II (DDR-II) SDRAM Specification, JC 42.3, JEDEC Solid
State Technology Association, December 2000.

Mode Register Programming


For mode register programming, the DDR-II SDRAM 1.0 monitor supports the following:

Burst length 4.

CAS latencies 2, 3, 4, and 5.

Sequential and interleaved burst types.

DLL reset, if DLL is enabled.

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Normal operating mode.

The DDR SDRAM 1.0 monitor does not support the following:

Any reserved states and vendor-specific test modes.

Extended Mode Register Programming


For extended mode register programming, the DDR-II SDRAM 1.0 monitor supports the
following:

DLL enable/disable.

Normal operating mode.

The DDR SDRAM 1.0 monitor does not support the following:

Any reserved states.

Monitor Placement and Instantiation


To use the DDR-II SDRAM 1.0 monitor, place one instance of the monitor inside the part of the
design (that is, a block of synthesizable code) that can be analyzed by the formal tools. For
example, in a DDR-II SDRAM memory controller chip design that has a DDR-II SDRAM
memory interface for the DDR-II SDRAM memory chips and an application interface for
connecting other controllers, then the monitor should be instantiated inside the DDR-II
SDRAM memory controller design with the port signals connected to the DDR-II SDRAM
memory interface (see Figure 7-1). The user can include instantiations of the DDR-II SDRAM
1.0 monitors in a checker control file.

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Figure 7-1. DDR-II SDRAM 1.0 Block Diagram

Address

address
pipe

Control
control
DDR-II SDRAM
Memory

Application
Interface
Controller

DDR-II SDRAM
1.0 Monitor

data
in/out

Data

DDR-II SDRAM Memory Controller

Monitor Connectivity
Connect the DDR-II SDRAM 1.0 monitor pins to internal signals of the target design as
specified in the pin-out Table 7-1 and illustrated in Figure 7-2. The clock, reset, and
asynchronous reset signals should be available inside the target design. The remaining signals
can be attached to the outbound control and address signals of the target design.
Figure 7-2. DDR-II SDRAM 1.0 Monitor Pin-Out Diagram
ck
ck_n
reset
areset
cke
cs_n
ras_n
cas_n
we_n
ba[1:0]
a[ROW_ADDR_WIDTH - 1:0]
dm[DM_WIDTH - 1:0]
dq[DATA_BUS_WIDTH - 1:0]
dqs

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Table 7-1. DDR-II SDRAM 1.0 Monitor Pin-Out


Pin

Description

a[ROW_ADDR_WIDTH 1:0]

Address.

areset

Asynchronous reset (active high).

ba[1:0]

Bank address.

cas_n

Column address strobe (active low).

ck

Clock, active edge is the rising edge.

ck_n

Complementary clock, 180 degree out of phase with the clock.

cke

Clock enable (active high).

cs_n

Chip select (active low).

dm[DM_WIDTH -1:0]

Data mask line (active high).

dq[DATA_BUS_WIDTH - 1:0]

Data lines.

dqs

Data strobe.

ras_n

Row address strobe (active low).

reset

Reset (active high).

we_n

Write enable (active low).

Note that the timing value between a WRITE command and the first dqs latching transition is
called the tdqss value.
In simulation, the monitor uses the dqs signal to latch the dq bus, and it supports tdqss
values from 75% to 125% of the total clock period.
For formal analysis, the DDR-II SDRAM 1.0 monitor does not use the dqs signal to latch data
from the dq bus; instead, the monitor uses the ck/ck_n signals to latch the dq bus. Note that
the monitor assumes the tdqss value to be 100%, which is equal to one clock cycle width.
This indirectly means that during write operation, the designs should drive the dq and dqs
signals such that the dqs transitions are in-line with ck/ck_n transitions.
Also note that in simulation the monitor uses only the dqs signal to latch both odd and even
data from the dq bus, and it does not need the dqs_n in the monitor. That is, the monitor uses
the posedge of dqs to latch odd data from the dq bus, and it uses the negedge of the dqs
signal to latch even data, instead of using the posedge of dqs_n. Similarly, the monitor does not
use ldqs_n, udqs_n, and rdqs_n signals; instead, it uses both edges of ldqs, udqs, and
rdqs, respectively.

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DDR-II SDRAMs Stacking


If the memory controller supports n stacked DDR-II SDRAMs (with data widths width and
memory sizes mem), then connect the monitors as follows (see Figure 7-3 and Figure 7-4):

If the memory controller supports n DDR-II SDRAMs stacked by data width (for a
total data width of n x width and memory size mem), then connect only one instance
of the monitor to track the controller.

If the memory controller supports n DDR-II SDRAMs stacked by address width (for a
total data width of width and memory size n x mem), then connect n instances of the
monitor to track the controller.

Use the above scheme also when stacking by both data width and address width.
Figure 7-3. Stacking DDR-II SDRAMs by Data Width
Data

DDR-II SDRAM
Memory Controller

DDR-II SDRAM
Monitor

Address

...

DDR-II SDRAM
Memory #1

DDR-II SDRAM . . .
Memory #2

DDR-II SDRAM
Memory #n

Figure 7-4. Stacking DDR-II SDRAMs by Address Width


Data

DDR-II SDRAM
Memory Controller

DDR-II SDRAM
Monitor

Questa Verification Library Monitors Data Book, v2010.2

DDR-II SDRAM
Memory #1

Address

DDR-II SDRAM
Memory #2

Address

...

...

DDR-II SDRAM
Monitor

Address

...

DDR-II SDRAM
Monitor

DDR-II SDRAM
Memory #n

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Monitor Parameters
The parameters shown in Table 7-2 configures the DDR-II SDRAM 1.0 monitor. Refer to
Table 7-3 on page 176 for the JEDEC standard compliant values of the timing parameters,
which are used as default values.
Table 7-2. DDR-II SDRAM 1.0 Monitor Parameters

174

Order Parameter

Default Description

1.

Constraints_Mode

Set this parameter to 1 if the checks in the monitor are


to be used as constraints for formal analysis.

2.

CONTROLLER_SIDE

Set this parameter to 1 if the monitor is instantiated on


the DDR-II SDRAM controller side. This parameter
and Constraints_Mode parameter configure checks
that are connected to inputs as constraints.

3.

ROW_ADDR_WIDTH

13

Width of the address bus.

4.

DATA_BUS_WIDTH

Width of data bus. Minimum value for this parameter


is 4.

5.

DM_WIDTH

Width of data mask lines. Minimum value for this


parameter is 1.

6.

DLL_TRACKING_ENABLE

Set this parameter to 1 to enable the DLL


enable/disable tracking by the monitor.

7.

TRAS

RAS# active time. Minimum time between an


ACTIVATE and a PRECHARGE command.

8.

TRCD

RAS# to CAS# delay. Minimum time between an


ACTIVATE command and a READ/WRITE
command to that row.

9.

TRP

RAS# precharge command period. Minimum time to


precharge a bank.

10.

TRRD

RAS# to RAS# bank activate delay. Minimum time


between successive ACTIVATE commands to
different banks.

11.

TCCD

CAS# to CAS# delay. Minimum time between


READ/WRITE commands to different banks.

12.

TRTW

Read to Write turn-around-time. Minimum time


required between a READ and WRITE command to
the same bank.

13.

TWTR

Write to Read turn-around-time. The minimum time


between a WRITE and READ command is TWTR +
1+ cas_latency.

14.

TWR

Write recovery time. This is the minimum spacing


between completion of write burst and precharge.

15.

TRFC

10

AUTO REFRESH to ACTIVE / AUTO REFRESH


command time. Minimum time between the AUTO
REFRESH command and an ACTIVE or AUTO
REFRESH command to any bank.

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V1.0 Monitor

Table 7-2. DDR-II SDRAM 1.0 Monitor Parameters (cont.)


Order Parameter

Default Description

16.

TXSNR

10

SELF REFRESH to non-READ command time.


Minimum time between the SELF REFRESH
command and any non-READ command to any bank.

17.

TXSRD

200

SELF REFRESH to READ command time. Minimum


time between the SELF REFRESH command and a
READ command to any bank.

18.

TMRD

MODE REGISTER SET command cycle time.


Minimum time for any new command to be issued
after the MODE REGISTER SET command.

19.

AUTOPRECHARGE_
ENABLE_ADDRESS_BIT

10

Selects the address line to use as the auto precharge


enable for READ or WRITE commands and to
distinguish between PRECHARGE and
PRECHARGE ALL commands. By default, A10 is
used.

20.

READ_BEFORE_WRITE_
CHECK_ENABLE

Set this parameter to 0 to disable the READ BEFORE


WRITE check. By default, this check is enabled.

21.

DATA_CHECK_ENABLE

This parameter enables or disables the following data


integrity checks: DDR_SDRAM_bad_data and
DDR_SDRAM_read_before_write.
Set this parameter to 1 to enable the data integrity
checks.
Setting to 0 removes the checks by completely
removing the data-checker module,
qvl_ddr_sdram_data_checker.

The parameters must be specified in the above order.


Time is measured in terms of the number of clock cycles.

When constraints mode is not enabled, all checks are used as targets during formal verification.
To use the checks as constraints for formal analysis, do both of the following:

Set the Constraints_Mode parameter to 1.

Set the CONTROLLER_SIDE parameter as follows:


o

If the monitor is instantiated in the DDR-II SDRAM controller, then set


CONTROLLER_SIDE to 1.

If the monitor is instantiated in the DDR-II SDRAM memory, then set


CONTROLLER_SIDE to 0.

Programming the DQS Delay


Note the following about the `define compiler directive:
Name: QVL_DQS_DELAY

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Default: 2
Description:
This is used to delay the DQS signal during read cycles in order to align the DQS signal edges at
the center of the DQ signal to guarantee the proper latching of DQ.
By default, the DQS signal is delayed by 2 time units (i.e., #2) internally.
The user should override this with a larger value if the DQS signal that is driven by the DDR
Memory should be delayed more than #2 to guarantee proper DQ latching.

JEDEC Standard Compliant Values of the Timing Parameters


Table 7-3. JEDEC Standard Compliant Timing
Timing Parameter

JEDEC Standard Timing Value

TRAS

TRCD

TRP

TRRD

TCCD

TRTW

TWTR

TWR

TRFC

10

TXSNR

10

TXSRD

200

TMRD

Time is measured by an integer number of clock cycles.

Instantiation Examples
Example 1
Example 7-1 instantiates a DDR-II SDRAM 1.0 monitor on the DDR-II SDRAM controller
side with ROW_ADDR_WIDTH of 13, DATA_BUS_WIDTH of 8, and DLL_TRACKING_ENABLE set to
1.

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Example 7-1. DDR-II SDRAM 1.0 Monitor Instantiation


qvl_ddr2_sdram_monitor
#( 0,
/* Constraints_Mode */
1,
/* CONTROLLER_SIDE */
13,
/* ROW_ADDR_WIDTH */
8,
/* DATA_BUS_WITH */
1,
/* DM_WIDTH */
1)
/* DLL_TRACKING_ENABLE */
DDR2_SDRAM_MONITOR0 (
.ck
(clock),
.ck_n
(clock_n),
.reset
(reset),
.areset (areset),
.cke
(clock_enable_1),
.cs_n
(chip_select_n_1)
.ras_n, (row_address_strobe_n)
.cas_n, (column_address_strobe_n)
.we_n,
(write_enable_n),
.ba
(bank_address),
.a
(address_bus_13),
.dm
(data_mask_1),
.dq
(data_bus_8),
.dqs
(data_strobe) );

Example 2
Example 7-2 instantiates two instances of the DDR-II SDRAM 1.0 monitor for a DDR-II
SDRAM memory. The example has the following characteristics:

The controller design interfaces two stacked DDR-II SDRAMs, each having 12-bits of
ROW_ADDR_WIDTH (4K address space) and 32-bits of DATA_BUS_WIDTH.

The cs_n, cke, ras_n, cas_n, and we_n signals of width 2-bits each, one for each
DDR-II SDRAM.

Two bank addresses of width 2-bits each, one for each DDR-II SDRAM memory.

The DM_WIDTH of 4, one for each byte of data.

The DLL tracking is enabled. Therefore, the DLL_TRACKING_ENABLE parameter is set to


1.

The monitor is instantiated for constrained formal verification. Therefore, the


parameter is set to 1.

Constraints_Mode

Example 7-2. DDR-II SDRAM 1.0 Monitor Instantiation


qvl_ddr2_sdram_monitor
#( 1,
/* Constraints_Mode */
0,
/* CONTROLLER_SIDE */
12,
/* ROW_ADDR_WIDTH */
32,
/* DATA_BUS_WITH */
4,
/* DM_WIDTH */

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1)
/* DLL_TRACKING_ENABLE */
DDR2_SDRAM_MONITOR0 (
.ck
(clock),
.ck_n
(clock_n),
.reset
(reset),
.areset (areset),
.cke
(clock_enable_0),
.cs_n
(chip_select_n_0),
.ras_n
(row_address_strobe_n_0),
.cas_n
(column_address_strobe_n_0),
.we_n
(write_enable_n_0),
.ba
(bank_address_0),
.a
(address_bus_12_0),
.dm
(data_mask_4),
.dq
(data_bus_32),
.dqs
(data_strobe) );
qvl_ddr2_sdram_monitor
#( 1,
/* Constraints_Mode */
0,
/* CONTROLLER_SIDE */
12,
/* ROW_ADDR_WIDTH */
32,
/* DATA_BUS_WITH */
4,
/* DM_WIDTH */
1)
/* DLL_TRACKING_ENABLE */
DDR2_SDRAM_MONITOR1 (
.ck
(clock),
.ck_n
(clock_n),
.reset
(reset),
.areset (areset),
.cke
(clock_enable_1),
.cs_n
(chip_select_n_1),
.ras_n
(row_address_strobe_n_1),
.cas_n
(column_address_strobe_n_1),
.we_n
(write_enable_n_1),
.ba
(bank_address_1),
.a
(address_bus_12_1),
.dm
(data_mask_4),
.dq
(data_bus_32),
.dqs
(data_strobe) );

Monitor Checks
Table 7-4 shows the checks performed by a DDR-II SDRAM 1.0 monitor.
Table 7-4. Checks Performed by a DDR-II SDRAM 1.0 Monitor
Check ID

Violation

Description

DDR2_SDRAM_ADDITIVE_
LATENCY_INVALID

Invalid Additive latency value


is programmed in the extended
mode register during EMRS
command.

Additive latency values supported are


0, 1, and 2. Any other value is invalid.
Check the additive_latency value
programmed during the last EMRS
command.

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Table 7-4. Checks Performed by a DDR-II SDRAM 1.0 Monitor (cont.)


Check ID

Violation

Description

DDR2_SDRAM_ADDRESS_
LEVEL

Address lines are not driven to


valid levels.

Checks that address lines are both


known (not X) and driven (not Z). This
check is active only during MRS,
EMRS, Activate and memory Read
and Write commands.

DDR2_SDRAM_AUTO_
REFRESH_PRECHARGE

An auto refresh command is


issued when one or more banks
are not in precharge state.

An auto refresh command can be


issued only when all banks are in
precharged condition.

DDR2_SDRAM_BANK_LEVEL

Bank Address lines are not


driven to valid levels.

Checks that bank address lines are both


known (not X) and driven (not Z). This
check is active only during Precharge,
Activate and memory Read and Write
commands.

DDR2_SDRAM_CAS_LATENCY_
INVALID

Invalid CAS latency value is


CAS latency can be 2, 3, 4, or 5. Any
programmed in the mode
other value is invalid or reserved.
register during MRS command. Check the cas_latency value
programmed during the last MRS
command.

DDR2_SDRAM_CAS_LEVEL

cas_n is not driven to a valid


level.

Checks that CAS_n is both known (not


X) and driven (not Z). This check is
active only if CKE is high.

DDR2_SDRAM_CKE_LEVEL

cke is not driven to a valid


level.

Checks that CKE is both known (not


X) and driven (not Z). This check is
active after the first active edge of the
clock.

DDR2_SDRAM_CONSTRAINTS_
MODE

Constraints_Mode parameter
should be either 1 or 0.

The value of the CONSTRAINTS_


MODE parameter should be either 1 or
0. It is to be made 1 to make checks as
constraints and 0 to have them as
targets for formal analysis.

DDR2_SDRAM_CONTROLLER_
SIDE

CONTROLLER_SIDE
parameter should be either 1 or
0.

The value of the CONTROLLER_


SIDE parameter should be either 1 or
0.

DDR2_SDRAM_CS_LEVEL

cs_n is not driven to a valid


level.

Checks that CS_n is both known (not


X) and driven (not Z). Active only if
CKE is high.

DDR2_SDRAM_DATA_WIDTH

DATA_BUS_WIDTH
parameter should not be less
than the minimum limit of 4.

The value of the DATA_BUS_


WIDTH parameter should not be
specified to be less than 4.

DDR2_SDRAM_DLL_NOT_RESET

DLL not reset prior to the first


activation command.

If DLL is enabled during the


initialization sequence, then it must be
reset before issuing an activation
command to any bank. This check is
active only if
DLL_TRACKING_ENABLE is 1.

DDR2_SDRAM_DLL_TRACKING

DLL_TRACKING_ENABLE
parameter should be either 1 or
0.

The value of the


DLL_TRACKING_ENABLE
parameter should be either 1 or 0.

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Table 7-4. Checks Performed by a DDR-II SDRAM 1.0 Monitor (cont.)


Check ID

Violation

Description

DDR2_SDRAM_DM_LEVEL

dm is not driven to a valid


level.

Checks that DM is both known (not X)


and driven (not Z). Active only during
write bursts if CKE is high.

DDR2_SDRAM_DM_WIDTH

DM_WIDTH parameter should The value of the DM_WIDTH, which


not be less than the minimum
specifies the data_mask width, should
limit of 1.
not be specified less than 1.

DDR2_SDRAM_INCORRECT_
COMMAND_BEFORE_MRS

An invalid command is issued


before programming the mode
register (only NOP,
DESELECT and
PRECHARGE are valid at this
point).

NOP, precharge, and refresh are the


only commands that are valid before
the Mode register is set. The user
should check the designs reset
sequencing.

DDR2_SDRAM_INSUFFICIENT_
AUTO_REFRESH_ACTIVATE

Sufficient number (2) of auto


refresh commands are not
issued prior to the first
activation command.

During the initialization sequence, a


minimum of 2 auto refresh commands
should be issued before the first
activation command.

DDR2_SDRAM_MODE_
REGISTER_NOT_SET

Mode register was not


programmed prior to the first
activation command.

Mode register must be configured for


burst type, CAS latency, etc. during
initialization sequence, before the first
activation.

DDR2_SDRAM_MRS_
PRECHARGE

A mode register set command


is issued when one or more
banks are not in precharge
state.

A mode register set command can be


issued only when all banks are in
precharged condition.

DDR2_SDRAM_RAS_LEVEL

ras_n is not driven to a valid


level.

Checks that RAS_n is both known (not


X) and driven (not Z). This check is
active only if CKE is high.

DDR2_SDRAM_ROW_ADDRESS

ROW_ADDRESS_WIDTH
parameter should not be less
than the minimum limit of 12.

The value of the ROW_ADDRESS_


WIDTH parameter should not be
specified to be less than 12.

DDR2_SDRAM_SELF_REFRESH_
PRECHARGE

A self refresh command is


issued when one or more banks
are not in precharge state.

A self refresh command can be issued


only when all banks are in precharged
condition.

DDR2_SDRAM_TCCD

TCCD timing parameter should The value of the TCCD timing


not be less than the minimum
parameter should not be specified to be
limit of 2.
less than 2.

DDR2_SDRAM_TDLL_
VIOLATION_AFTER_DLL_RESET

A Read or Read with


Autoprecharge command is
issued before 200 clock cycles
after DLL reset.

A Mode Register Set command must


be issued for the Mode Register to
reset the DLL and to program the
operating parameters. Once the DLL
reset command is issued, a minimum
of 200 clock cycles are required before
any read command is issued.

DDR2_SDRAM_TMRD

TMRD timing parameter


should not be less than the
minimum limit of 2.

The value of the TMRD timing


parameter should not be specified to be
less than 2.

DDR2_SDRAM_TRAS

TRAS timing parameter should


not be less than the minimum
limit of 6.

The value of the TRAS timing


parameter should not be specified to be
less than 6.

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Table 7-4. Checks Performed by a DDR-II SDRAM 1.0 Monitor (cont.)


Check ID

Violation

Description

DDR2_SDRAM_TRCD

TRCD timing parameter should The value of the TRCD timing


not be less than the minimum
parameter should not be specified to be
limit of 3.
less than 3.

DDR2_SDRAM_TRFC

TRFC timing parameter should


not be less than the minimum
limit of 10.

The value of the TRFC timing


parameter should not be specified to be
less than 10.

DDR2_SDRAM_TRP

TRP timing parameter should


not be less than the minimum
limit of 3.

The value of the TRP timing parameter


should not be specified to be less than
3.

DDR2_SDRAM_TRRD

TRRD timing parameter should The value of the TRRD timing


not be less than the minimum
parameter should not be specified to be
limit of 2.
less than 2.

DDR2_SDRAM_TRRD_
VIOLATION

The command issued violates


the tRRD timing between
activation commands to
different banks.

The command just issued violates


tRRD (RAS to RAS delay timing).
This is an ACTIVATE command
issued too quickly after the
ACTIVATE command for another
bank. The user should determine why
the commands are too close together.

DDR2_SDRAM_TRTW

TRTW timing parameter


should not be less than the
minimum limit of 4.

The value of the TRTW timing


parameter should not be specified to be
less than 4.

DDR2_SDRAM_TWR

TWR timing parameter should


not be less than the minimum
limit of 3.

The value of the TWR timing


parameter should not be specified to be
less than 3.

DDR2_SDRAM_TWTR

TWTR timing parameter


should not be less than the
minimum limit of 2.

The value of the TWTR timing


parameter should not be specified to be
less than 2.

DDR2_SDRAM_TXSNR

TXSNR timing parameter


should not be less than the
minimum limit of 10.

The value of the TXSNR timing


parameter should not be specified to be
less than 10.

DDR2_SDRAM_TXSRD

TXSRD timing parameter


should not be less than the
minimum limit of 200.

The value of the TXSRD timing


parameter should not be specified to be
less than 200.

DDR2_SDRAM_WE_LEVEL

we_n is not driven to a valid


level.

Checks that WE_n is both known (not


X) and driven (not Z). This check is
active only if CKE is high.

Table 7-5 shows the checks for each bank performed by a DDR-II SDRAM 1.0 monitor.
Table 7-5. DDR-II SDRAM 1.0 Monitor Bank Checks
Check ID

Violation

Description

DDR2_SDRAM_ACTIVATE

An ACTIVATE command is
issued to an already open
bank without an intervening
PRECHARGE.

An open bank must be closed before


issuing another activation command to
that bank.

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Table 7-5. DDR-II SDRAM 1.0 Monitor Bank Checks (cont.)


Check ID

Violation

Description

DDR2_SDRAM_BAD_DATA

One or more bytes of data


read from the addressed
DDR2 SDRAM location did
not match the data bytes
written to the corresponding
address.

Data read from the DDR2 SDRAM did


not match the data written to the
corresponding address. The data check
is performed only on the reads to
locations that were previously written
at least once. Data checking is done on
a byte basis and the bitmap indicates
the data inconsistency between the
corresponding bytes. The check fires
when at least one byte of read data
does not match the corresponding valid
data byte that was written to that
location.

DDR2_SDRAM_BURST_
ABORTED_P

A read or write is aborted.

In DDR2 SDRAMs, burst interruption


is prohibited. Once a 4-n burst has
started, then it has to be completed
before the start of a new burst.

DDR2_SDRAM_CKE_LOW

CKE is driven low during a


cycle other than self refresh
or power down.

Clock Enable can be driven low only


during self refresh and power down
commands, and it has to be maintained
high during all other cycles.

DDR2_SDRAM_ILLEGAL_
COMMAND_ACT_PWR_DN

An illegal command is issued


when the bank is in Active
Power Down state.

The command just issued is not a legal


command when the bank is in the
Active Power Down state. All the valid
commands from this state are outlined
in the state diagram in the reference
material. The user should trace why an
illegal command is issued.

DDR2_SDRAM_ILLEGAL_
COMMAND_ACTIVE

An illegal command is issued


when the bank is in
ACTIVATE state.

The command just issued is not a legal


command when the bank is in the
ACTIVATE state. All the valid
commands from this state are outlined
in the state diagram in the reference
material. The user should trace why an
illegal command is issued.

DDR2_SDRAM_ILLEGAL_
COMMAND_CBR

An illegal command is issued


when the memory is in
AUTO REFRESH state.

The command just issued is not a legal


command when the bank is in the
AUTO_REFRESH state. All the valid
commands from this state are outlined
in the state diagram in the reference
material. The user should trace why an
illegal command is issued.

DDR2_SDRAM_ILLEGAL_
COMMAND_EMRS

An illegal command is issued The command just issued is not a legal


when the memory is in
command when the bank is in
EX_MODE_REG_SET state. EX_MODE_REG_SET state. All the
valid commands from this state are
outlined in the state diagram in the
reference material. The user should
trace why an illegal command is
issued.

DDR2_SDRAM_BURST_
ABORTED_N

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Table 7-5. DDR-II SDRAM 1.0 Monitor Bank Checks (cont.)


Check ID

Violation

Description

DDR2_SDRAM_ILLEGAL_
COMMAND_IDLE

An illegal command is issued


when the bank is in IDLE
state.

The command just issued is not a legal


command when the bank is in IDLE
state. All the valid commands from this
state are outlined in the state diagram
in the reference material. The user
should trace why an illegal command
is issued.

DDR2_SDRAM_ILLEGAL_
COMMAND_IDLE_PWR_DN

An illegal command is issued


when the bank is in Idle
Power Down state.

The command just issued is not a legal


command when the bank is in the
IDLE Power Down state. All the valid
commands from this state are outlined
in the state diagram in the reference
material. The user should trace why an
illegal command is issued.

DDR2_SDRAM_ILLEGAL_
COMMAND_MRS

An illegal command is issued


when the memory is in
MODE_REG_SET
state.

The command just issued is not a legal


command when the bank is in
MODE_REG_SET state. All the valid
commands from this state are outlined
in the state diagram in the reference
material. The user should trace why an
illegal command is issued.

DDR2_SDRAM_ILLEGAL_
COMMAND_NOP

An illegal command is issued


when the bank is in NOP
state.

The command just issued is not a legal


command when the bank is in the
SELF_REFRESH state. All the valid
commands from this state are outlined
in the state diagram in the reference
material. The user should trace why an
illegal command is issued. For this, the
user can also look at
r_from_state_string.

DDR2_SDRAM_ILLEGAL_
COMMAND_PRE

An illegal command is issued


when the bank is in
PRECHARGE state.

The command just issued is not a legal


command when the bank is in
PRECHARGE state. All the valid
commands from this state are outlined
in the state diagram in the reference
material. The user should trace why an
illegal command is issued.

DDR2_SDRAM_ILLEGAL_
COMMAND_PRE_ALL

An illegal command is issued


when all banks are in
PRECHARGE state.

The command just issued is not a legal


command when the bank is in
PRECHARGE_ALL state. All the
valid commands from this state are
outlined in the state diagram in the
reference material. The user should
trace why an illegal command is
issued.

DDR2_SDRAM_ILLEGAL_
COMMAND_READ

An illegal command is issued


when the bank is in READ
state.

The command just issued is not a legal


command when the bank is in the
READ state. All the valid commands
from this state are outlined in the state
diagram in the reference material. The
user should trace why an illegal
command is issued.

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Table 7-5. DDR-II SDRAM 1.0 Monitor Bank Checks (cont.)


Check ID

Violation

Description

DDR2_SDRAM_ILLEGAL_
COMMAND_READ_AP

An illegal command is issued


when the bank is in the
READ_AUTO_
PRECHARGE state.

The command just issued is not a legal


command when the bank is in the
READ_AUTO_PRECHARGE state.
All the valid commands from this state
are outlined in the state diagram in the
reference material. The user should
trace why an illegal command is
issued.

DDR2_SDRAM_ILLEGAL_
COMMAND_SFR

An illegal command is issued


when the memory is in
SELF_REFRESH
state.

The command just issued is not a legal


command when the bank is in the
SELF_REFRESH state. All the valid
commands from this state are outlined
in the state diagram in the reference
material. The user should trace why an
illegal command is issued.

DDR2_SDRAM_ILLEGAL_
COMMAND_WRITE

An illegal command is issued


when the bank is in WRITE
state.

The command just issued is not a legal


command when the bank is in the
WRITE state. All the valid commands
from this state are outlined in the state
diagram in the reference material. The
user should trace why an illegal
command is issued.

DDR2_SDRAM_ILLEGAL_
COMMAND_WRITE_AP

An illegal command is issued


when the bank is in the
WRITE_AUTO_
PRECHARGE state.

The command just issued is not a legal


command when the bank is in the
WRITE_AUTO_PRECHARGE state.
All the valid commands from this state
are outlined in the state diagram in the
reference material. The user should
trace why an illegal command is
issued.

DDR2_SDRAM_PRECHARGE_
TO_IDLE_BANK

A Precharge command is
issued to an idle bank.

A PRECHARGE command was just


issued to an already idle bank.
Although this is not an illegal
operation, it is redundant. The user can
check why redundant commands are
issued.

DDR2_SDRAM_READ_AP_
VIOLATION

The command issued violates


the timing between read with
auto precharge and the
activation command issued to
the same bank.

The DDR2 SDRAM starts an auto


precharge operation on the rising edge
that is (AL + BL/2) cycles later than
the read with AP command if tRAS
and tRTP are satisfied. A new bank
activate command may be issued to the
same bank if tRP has been satisfied
from the clock at which auto precharge
begins, and tRC from the previous
bank activation has been satisfied.

DDR2_SDRAM_READ_BEFORE_
WRITE

Data was read from the


address, Bank bank, Row
row, and Column column of
the DDR-II SDRAM that was
not previously written into.

Data was read from the DDR-II


SDRAM from an address that was not
previously written into.

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Table 7-5. DDR-II SDRAM 1.0 Monitor Bank Checks (cont.)


Check ID

Violation

Description

DDR2_SDRAM_READ_TO_IDLE_
BANK

A read command is issued to


an idle bank.

The bank to which the READ


command was just issued is in
precharged idle condition. The user
should determine why a READ
command is issued to an idle bank
without issuing an ACTIVATE
command.

DDR2_SDRAM_TCCD_VIOLATION The command issued violates


the tCCD timing between two
Read/Write commands.

The command just issued violates


tCCD (CAS to CAS delay timing).
This is a READ/WRITE command
issued too quickly after a
READ/WRITE command for another
bank. The user should determine why
the commands are too close together.

DDR2_SDRAM_TCKE_VIOLATION CKE signal should be held at


a valid input level for at least
tCKE clock cycles.

The DDR2 standard specifies that the


CKE signal should be held at valid
input level (either 1 or 0) for a
minimum of three clock cycles. This
check fires if CKE changes its value
within three clock cycles.

DDR2_SDRAM_TMRD_
VIOLATION

The command issued violates


the tMRD timing after a
MRS/EMRS command was
issued.

Once a Mode Register Set, or


Extended Mode Register Set command
is issued, there cannot be any
command issued, including another
MRS or EMRS command until TMRD
number of clock cycles expire.

DDR2_SDRAM_TRAS_VIOLATION The command issued violates


the tRAS timing between an
activation and precharge
command.

The command just issued violates


tRAS (RAS to precharge timing). This
is a PRECHARGE command issued
too quickly after the ACTIVATE
command for this bank. The user
should determine why the commands
are too close together.

DDR2_SDRAM_TRC_VIOLATION

Once an activation command is issued


to the bank, another activation
command cannot be issued to the same
bank until tRC cycles.

The command issued violates


the tRC timing between an
activation command and
another activation command
issued to the same bank.

DDR2_SDRAM_TRCD_VIOLATION The command issued violates


the tRCD timing between an
activation and Read/Write
command.

The command just issued violates


tRCD (RAS to CAS delay timing).
This is a READ/WRITE command
issued too quickly after the
ACTIVATE command for this bank.
The user should determine why the
commands are too close together.

DDR2_SDRAM_TRFC_VIOLATION

The command just issued violates


tRFC (minimum time delay between
AUTO REFRESH command and any
other command). The new command is
issued too quickly after the AUTO
REFRESH command. The user should
determine why the commands are too
close together.

The command issued violates


the tRFC timing between
Auto Refresh and Auto
Refresh/Activate command.

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Table 7-5. DDR-II SDRAM 1.0 Monitor Bank Checks (cont.)


Check ID

Violation

Description

DDR2_SDRAM_TRP_VIOLATION

The command issued violates


the precharge command
period (tRP).

The command just issued violates tRP


(RAS precharge timing). This is an
ACTIVATE/REFRESH command
issued too quickly after the last
precharge command for this bank. The
user should determine why the
commands are too close together.

DDR2_SDRAM_TRTP_VIOLATION

The command issued violates


the tRTP timing between a
Read and Precharge
command.

The command just issued violates


Read to Precharge delay timing. This is
a PRECHARGE command issued too
quickly after a previous READ
command to the same bank. The
minimum delay should be additive
latency + 2. The user should determine
why the commands are too close
together.

DDR2_SDRAM_TRTR_VIOLATION The command issued violates


the tRTR timing between two
Read commands.

The command just issued violates


Read to Read delay timing. This is a
READ command issued too quickly
after a previous READ command to
the same bank. The minimum delay
should be 2 clocks since the 4-n bursts
cannot be interrupted. The user should
determine why the commands are too
close together.

DDR2_SDRAM_TRTW_
VIOLATION

The command issued violates


the tRTW timing between a
READ and WRITE
command.

The command just issued violates


tRTW (Read to Write delay timing).
This is a WRITE command issued too
quickly after a previous READ
command to the same bank. The user
should determine why the commands
are too close together.

DDR2_SDRAM_TWTP_VIOLATION The command issued violates


the tWTP timing between a
Write and Precharge
command.

The command just issued violates


Write to Precharge delay timing. This
is a PRECHARGE command issued
too quickly after a previous WRITE
command to the same bank. The
minimum delay should be WL (write
latency) + TWR (write recovery time)
+ 2. The user should determine why
the commands are too close together.

DDR2_SDRAM_TWTR_
VIOLATION

The command just issued violates


Write to Read delay timing. This is a
READ command issued too quickly
after a previous WRITE command to
the same bank. The minimum delay
should be tWTR (write to read turnaround-time) + CAS latency + 1. The
user should determine why the
commands are too close together.

186

The command issued violates


the tWTR timing between a
Write and Read command.

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V1.0 Monitor

Table 7-5. DDR-II SDRAM 1.0 Monitor Bank Checks (cont.)


Check ID

Violation

Description

DDR2_SDRAM_TWTW_
VIOLATION

The command issued violates


the tWTW timing between
two Write commands.

The command just issued violates


Write to Write delay timing. This is a
WRITE command issued too quickly
after a previous WRITE command to
the same bank. The minimum delay
should be 2 clocks since the 4-n bursts
cannot be interrupted. The user should
determine why the commands are too
close together.

DDR2_SDRAM_TXSNR_
VIOLATION

The command issued violates


the tXSNR timing required
between a Self Refresh Exit
and a Non-Read command.

The command just issued violates


tXSNR (minimum time delay between
SELF REFRESH EXIT command and
any other non-READ command)
timing. A non-READ command is
issued too quickly after the SELF
REFRESH EXIT command. The user
should determine why the commands
are too close together.

DDR2_SDRAM_TXSRD_
VIOLATION

The command issued violates


the tXSRD timing between a
Self Refresh Exit and a Read
command.

The READ command just issued


violates tXSRD (minimum time delay
between SELF REFRESH EXIT
command and a READ command)
timing. A READ command is issued
too quickly after the SELF REFRESH
EXIT command. The user should
determine why the commands are too
close together.

DDR2_SDRAM_UNKNOWN_
STATE

The bank state machine went


to UNKNOWN_STATE.

The command just issued has caused


the monitor state machine to go to an
UNKNOWN state. This can be due to
an illegal command. The user should
look at the state machine transitions
and check as to why it entered this
state.

DDR2_SDRAM_WRITE_TO_IDLE_
BANK

A write command is issued to


an idle bank.

The bank to which the WRITE


command was just issued is in
precharged idle condition. The user
should determine why a WRITE
command is issued to an idle bank
without issuing an ACTIVATE
command.

Monitor Corner Cases


Table 7-6 shows the corner cases captured by the DDR-II SDRAM 1.0 monitor for the protocol.
Table 7-6. DDR-II SDRAM 1.0 Monitor Corner Cases
Corner Case

Description

Multiple Banks Activation

Number of times more than one bank is in the activated state.

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Table 7-6. DDR-II SDRAM 1.0 Monitor Corner Cases (cont.)


Corner Case

Description

Precharge All Banks

Number of Precharge All commands issued to the DDR-II SDRAM.

CBR Refresh Commands

Number of times CBR Auto Refresh commands are issued.

Interleaved Bursts

Number of times Mode Register is programmed for Interleaved burst.

Sequential Bursts

Number of times Mode Register is programmed for Sequential burst.

Self Refresh Commands

Number of times Self Refresh command is issued.

Power Down Commands

Number of times Power Down command is issued.

NOP Commands

Number of times NOP command is issued.

Deselect Commands

Number of times Deselect command is issued.

Table 7-7 shows the corner cases captured by the DDR-II SDRAM 1.0 monitor for the DDR-II
SDRAM banks.
Table 7-7. DDR-II SDRAM 1.0 Bank Corner Cases
Corner Case

Description

Reads Without Precharge

Number of read without precharge commands issued to a bank.

Writes Without Precharge

Number of write without precharge commands issued to a bank.

Single Bank Precharges

Number of single bank Precharge commands issued to a bank.

Seamless Reads

Number of times a Read is immediately followed by another Read from the


same bank.

Seamless Writes

Number of times a Write is immediately followed by another Write to the


same bank.

Reads with Precharge

Number of times Read with Auto Precharge operation is performed to a


bank.

Writes with Precharge

Number of times Write with Auto Precharge operation is performed to a


bank.

Posted Reads

Number of times Posted Read cycles are exercised.

Posted Writes

Number of times Posted Write cycles are exercised.

Read after Read in Page

Number of times a read operation is issued to a page that is already opened


for read in the bank.

Read after Write in Page

Number of times a read operation is issued to a page that is already opened


for write in the bank.

Write after Read in Page

Number of times a write operation is issued to a page that is already opened


for read in the bank.

Write after Write in Page

Number of times a write operation is issued to a page that is already opened


for write in the bank.

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Monitor Statistics
Table 7-8 lists the statistics collected for the protocol.
Table 7-8. DDR-II SDRAM 1.0 Monitor Statistics
Statistic

Description

Total Number of Memory Accesses

Total number of data accesses to the DDR-II SDRAM for all banks.

Table 7-9 lists the statistics collected for each bank.


Table 7-9. DDR-II SDRAM 1.0 Bank Statistics
Statistic

Description

Total Number of Bank Accesses

Total number of times a bank is activated and data accesses performed on the
bank.

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V2.0 Monitor

V2.0 Monitor
Reference Documentation
This DDR-II SDRAM 2.0 monitor is modeled on the requirements provided in the following
document:

JESD79-2 DDR2 SDRAM Specification, JEDEC Solid State Technology Association,


September 2003.

JEDEC Double Data Rate - II (DDR-II) SDRAM Specification, JC 42.3, JEDEC Solid
State Technology Association, December 2000.

JEDEC Standard, Double Data Rate-II (DDR) Specification, JESD79-2C, JEDEC Solid
State Technology Association, May 2006.

Mode Register Programming


For mode register programming, the DDR-II SDRAM 2.0 monitor supports the following:

Burst length 4 and 8.

CAS latencies 2, 3, 4, 5, and 6.

Sequential and interleaved burst types.

DLL reset, if DLL is enabled.

Normal operating mode.

Write recovery for auto precharge.

Active power down exit time.

EMRS2 and EMR3 programming (Extended Mode Register Set commands).

On-die-termination (ODT) 50 Ohm restriction.

Off-chip driver (OCD) calibration cycles.

Clock frequency change.

The DDR-II SDRAM 2.0 monitor does not support the following:

Any reserved states and vendor-specific test modes.

Extended Mode Register Programming


For extended mode register programming, the DDR-II SDRAM 2.0 monitor supports the
following:

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DLL enable/disable.

Normal operating mode.

Additive latencies of 0, 1, 2, 3, and 4.

RDQS using the DM pin as read data strobe for x8 configuration.

Strobe function matrix.

The DDR-II SDRAM 2.0 monitor does not support the following:

Any reserved states.

Initialization Sequence Bypass


The DDR-II SDRAM 2.0 monitor can be used in cases when you want to bypass the
initialization sequence. The BYPASS_INIT parameter sets this mode of operation as follows:

Normal mode.
By default (BYPASS_INIT=0), the monitor tracks the initialization sequence. In this
mode, the monitor validates the requirements described in the JEDEC specification
during the initialization sequence. For example, in the normal mode of operation, the
monitor fires if it does not detect an EMRS(2) command followed by an EMRS(3)
command.
In the normal mode of operation, the monitor tracks the MRS and EMRS commands and
configures itself accordingly. The monitor ports mode_register_in and
ex_mode_register_in can be left unconnected.

Initialization bypass mode.


The user can configure the monitor into the initialization bypass mode by setting the
BYPASS_INIT parameter to 1. In this mode, the monitor does not validate the
requirements described in the JEDEC specification during the initialization sequence
and does not track the MRS and EMRS commands. However, for proper operation, the
monitor requires the information regarding the mode register settings. The mode-related
information must be passed through the monitor ports mode_register_in and
ex_mode_register_in. Be sure that the values passed to these ports reflect the actual
mode register setting in the DDR-II SDRAM memory.

Monitor Placement and Instantiation


To use the DDR-II SDRAM 2.0 monitor, place one instance of the monitor inside the part of the
design (that is, a block of synthesizable code) that can be analyzed by the formal tools. For
example, in a DDR-II SDRAM memory controller chip design that has a DDR-II SDRAM
memory interface for the DDR-II SDRAM memory chips and an application interface for
connecting other controllers, then the monitor should be instantiated inside the DDR-II
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SDRAM memory controller design with the port signals connected to the DDR-II SDRAM
memory interface (see Figure 7-5). The user can include instantiations of the DDR-II SDRAM
2.0 monitors in a checker control file.
Figure 7-5. DDR-II SDRAM 2.0 Block Diagram

Address

address
pipe

Control
control
DDR-II SDRAM
Memory

Application
Interface
Controller

DDR-II SDRAM
2.0 Monitor
Data

data
in/out
DDR-II SDRAM Memory Controller

Monitor Connectivity
Connect the DDR-II SDRAM 2.0 monitor pins to internal signals of the target design as
specified in the pin-out Table 7-10 and illustrated in Figure 7-6. The clock, reset, and
asynchronous reset signals should be available inside the target design. The remaining signals
can be attached to the outbound control and address signals of the target design.

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Figure 7-6. DDR-II SDRAM 2.0 Monitor Pin-Out Diagram


ck
ck_n
reset
areset
cke
cs_n
ras_n
cas_n
we_n
ba[1:0]
ba[BANK_ADDR_WIDTH - 1:0]
a[ROW_ADDR_WIDTH - 1:0]
dm_rdqs
dq
dqs
ldqs
ldm
udqs
udm
mode_register_in
ex_mode_register_in
odt
tras_inp
trcd_inp
trp_inp
trrd_inp
tccd_inp
trtw_inp
twtr_inp
twr_inp
trfc_inp
txsnr_inp
txsrd_inp
tmrd_inp
txp_inp
txard_inp

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Table 7-10. DDR-II SDRAM 2.0 Monitor Pin-Out

194

Pin

Description

a[ROW_ADDR_WIDTH 1:0]

Address.

areset

Asynchronous reset (active high).

ba[BANK_ADDR_WIDTH-1:0]

Bank address.

cas_n

Column address strobe (active low).

ck

Clock, active edge is the rising edge.

ck_n

Complementary clock, 180 degree out of phase with the clock.

cke

Clock enable (active high).

cs_n

Chip select (active low).

dm_rdqs

Data mask for port dq / Read data strobe (only in x8 mode).

dq

Data bus.

dqs

Data strobe for port dq.

ex_mode_register_in

Extended mode register input. Leave this port unconnected if


BYPASS_INIT=0. The width of this register is equal to
ADDR_WIDTH + BANK_ADDR_WIDTH. This width reflects the
actual width of the mode register in the DDR-II SDRAM memory.

ldm

Data mask for port {dq7:dq0}.

ldqs

Data strobe for {dq7:dq0}.

mode_register_in

Mode register input. Leave this port unconnected if BYPASS_INIT=0.


The width of this register is equal to ADDR_WIDTH +
BANK_ADDR_WIDTH. This width reflects the actual width of the
mode register in the DDR-II SDRAM memory.

odt

On-die-termination.

ras_n

Row address strobe (active low).

reset

Reset (active high).

tccd_inp[31:0]

Port for tCCD timing input. This input is valid only when
USE_PORTS_TO_CONFIGURE parameter is set to 1.

tmrd_inp[31:0]

Port for tMRD timing input. This input is valid only when
USE_PORTS_TO_CONFIGURE parameter is set to 1.

tras_inp[31:0]

Port for tRAS timing input. This input is valid only when
USE_PORTS_TO_CONFIGURE parameter is set to 1.

trcd_inp[31:0]

Port for tRCD timing input. This input is valid only when
USE_PORTS_TO_CONFIGURE parameter is set to 1.

trfc_inp[31:0]

Port for tRFC timing input. This input is valid only when
USE_PORTS_TO_CONFIGURE parameter is set to 1.

trp_inp[31:0]

Port for tRP timing input. This input is valid only when
USE_PORTS_TO_CONFIGURE parameter is set to 1.

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V2.0 Monitor

Table 7-10. DDR-II SDRAM 2.0 Monitor Pin-Out (cont.)


Pin

Description

trrd_inp[31:0]

Port for tRRD timing input. This input is valid only when
USE_PORTS_TO_CONFIGURE parameter is set to 1.

trtw_inp[31:0]

Port for tRTW timing input. This input is valid only when
USE_PORTS_TO_CONFIGURE parameter is set to 1.

twr_inp[31:0]

Port for tWR timing input. This input is valid only when
USE_PORTS_TO_CONFIGURE parameter is set to 1.

twtr_inp[31:0]

Port for tWTR timing input. This input is valid only when
USE_PORTS_TO_CONFIGURE parameter is set to 1.

txard_inp[31:0]

Port for tXARD timing input. This input is valid only when
USE_PORTS_TO_CONFIGURE parameter is set to 1.

txp_inp[31:0]

Port for tXP timing input. This input is valid only when
USE_PORTS_TO_CONFIGURE parameter is set to 1.

txsnr_inp[31:0]

Port for tXSNR timing input. This input is valid only when
USE_PORTS_TO_CONFIGURE parameter is set to 1.

txsrd_inp[31:0]

Port for tXSRD timing input. This input is valid only when
USE_PORTS_TO_CONFIGURE parameter is set to 1.

udm

Data mask for port {dq15:dq8}.

udqs

Data strobe for port {dq15:dq8}.

we_n

Write enable (active low).

The timing value between a WRITE command and the first dqs latching transition is called the
tdqss value.
In simulation, the monitor uses the dqs signal to latch the dq bus, and it supports tdqss
values from 75% to 125% of the total clock period.
For formal analysis, the DDR-II SDRAM 2.0 monitor does not use the dqs signal to latch data
from the dq bus; instead, the monitor uses the ck/ck_n signals to latch the dq bus. Note that
the monitor assumes the tdqss value to be 100%, which is equal to one clock cycle width.
This indirectly means that during write operation, the designs should drive the dq and dqs
signals such that the dqs transitions are in-line with the ck/ck_n transitions.
Also note that in simulation the monitor uses only the dqs signal to latch both odd and even
data from the dq bus, and it does not need the dqs_n in the monitor. That is, the monitor uses
the posedge of dqs to latch odd data from the dq bus, and it uses the negedge of the dqs
signal to latch even data, instead of using the posedge of dqs_n. Similarly, the monitor does not
use ldqs_n, udqs_n, and rdqs_n signals; instead, it uses both edges of ldqs, udqs, and
rdqs, respectively.
In x8 mode, if RDQS is enabled, then the DM pin can be used as the read data strobe, RDQS. In
this case, the DM function is disabled for x8 writes. Therefore, if operating in x8 configuration
and RDQS is enabled, connect DQS to DM. For writes, DQS is the data strobe and for reads RDQS
(using the DM pin) is the data strobe. DQ is the data bus for both operations.
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The x4 and x16 configurations are not affected by the RDQS function of the DM pin. In x16
mode, LDQS corresponds to the data on DQ0-DQ7 and UDQS corresponds to the data on
DQ8-DQ15. The corresponding data masks are LDM and UDM.

Monitor Parameters
The parameters shown in Table 7-11 configure the DDR-II SDRAM 2.0 monitor. Refer to
Table 7-12 for the JEDEC standard compliant values of the timing parameters, which are used
as default values.
Table 7-11. DDR-II SDRAM 2.0 Monitor Parameters
Order Parameter

Default Description

1.

Constraints_Mode

Set this parameter to 1 if the checks in the monitor are to


be used as constraints for formal analysis.

2.

CONTROLLER_SIDE

Set this parameter to 1 if the monitor is instantiated on


the DDR-II SDRAM controller side. This parameter and
Constraints_Mode parameter configure checks that are
connected to inputs as constraints.

3.

ROW_ADDR_WIDTH

16

Width of the address bus.

4.

DATA_BUS_WIDTH

Width of data bus. Use this parameter to set the data bus
configuration to x4, x8, or x16. These are the only valid
values of this parameter.

5.

DLL_TRACKING_ENABLE

Set this parameter to 1 to enable the DLL enable and


disable tracking by the monitor.

6.

TRAS

RAS# active time (minimum time between an


ACTIVATE and a PRECHARGE command).
This parameter is valid only when the
USE_PORTS_TO_CONFIGURE parameter is set to 0,
which is the default value of the parameter
USE_PORTS_TO_CONFIGURE.

7.

TRCD

RAS# to CAS# delay (minimum time between an


ACTIVATE command and a READ/WRITE command
to that row). This parameter is valid only when the
USE_PORTS_TO_CONFIGURE parameter is set to 0,
which is the default value of the parameter
USE_PORTS_TO_CONFIGURE.

8.

TRP

RAS# precharge command period (minimum time to


precharge a bank). This parameter is valid only when the
USE_PORTS_TO_CONFIGURE parameter is set to 0,
which is the default value of the parameter
USE_PORTS_TO_CONFIGURE.

9.

TRRD

RAS# to RAS# bank activate delay (minimum time


between successive ACTIVATE commands to different
banks). This parameter is valid only when the
USE_PORTS_TO_CONFIGURE parameter is set to 0,
which is the default value of the parameter
USE_PORTS_TO_CONFIGURE.

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Table 7-11. DDR-II SDRAM 2.0 Monitor Parameters (cont.)


Order Parameter

Default Description

10.

TCCD

CAS# to CAS# delay (minimum time between


READ/WRITE commands to different banks).
This parameter is valid only when the
USE_PORTS_TO_CONFIGURE parameter is set to 0,
which is the default value of the parameter
USE_PORTS_TO_CONFIGURE.

11.

TRTW

Read to Write turn-around-time (minimum time required


between a READ and WRITE command to the same
bank). This parameter is valid only when the
USE_PORTS_TO_CONFIGURE parameter is set to 0,
which is the default value of the parameter
USE_PORTS_TO_CONFIGURE.

12.

TWTR

Write to Read turn-around-time. The minimum time


between a WRITE and READ command is TWTR + 1 +
cas_latency. This parameter is valid only when the
USE_PORTS_TO_CONFIGURE parameter is set to 0,
which is the default value of the parameter
USE_PORTS_TO_CONFIGURE.

13.

TWR

Write recovery time. This is the minimum spacing


between completion of write burst and precharge.
This parameter is valid only when the
USE_PORTS_TO_CONFIGURE parameter is set to 0,
which is the default value of the parameter
USE_PORTS_TO_CONFIGURE.

14.

TRFC

AUTO REFRESH to ACTIVE / AUTO REFRESH


command time (minimum time between AUTO
REFRESH command and an ACTIVE or AUTO
REFRESH command to any bank). This parameter is
valid only when the USE_PORTS_TO_CONFIGURE
parameter is set to 0, which is the default value of the
parameter USE_PORTS_TO_CONFIGURE.

15.

TXSNR

10

SELF REFRESH to non-READ command time


(minimum time between SELF REFRESH command and
any non-READ command to any bank). This parameter
is valid only when the USE_PORTS_TO_CONFIGURE
parameter is set to 0, which is the default value of the
parameter USE_PORTS_TO_CONFIGURE.

16.

TXSRD

200

SELF REFRESH to READ command time (minimum


time between SELF REFRESH command and a READ
command to any bank). This parameter is valid only
when the USE_PORTS_TO_CONFIGURE parameter is
set to 0, which is the default value of the parameter
USE_PORTS_TO_CONFIGURE.

17.

TMRD

MODE REGISTER SET command cycle time (minimum


time for any new command to be issued after the MODE
REGISTER SET command). This parameter is valid only
when the USE_PORTS_TO_CONFIGURE parameter is
set to 0, which is the default value of the parameter
USE_PORTS_TO_CONFIGURE.

18.

AUTOPRECHARGE_
ENABLE_ADDRESS_BIT

10

Selects the address line to use as the auto precharge


enable for READ or WRITE commands and to
distinguish between PRECHARGE and PRECHARGE
ALL commands. By default, A10 is used.

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Table 7-11. DDR-II SDRAM 2.0 Monitor Parameters (cont.)


Order Parameter

Default Description

19.

READ_BEFORE_WRITE_
CHECK_ENABLE

Set this parameter to 0 to disable the READ BEFORE


WRITE check. By default, this check is enabled.

20.

TXP

Precharge power down exit to nonread latency, in


number of clocks. This parameter is valid only when the
USE_PORTS_TO_CONFIGURE parameter is set to 0,
which is the default value of the parameter
USE_PORTS_TO_CONFIGURE.

21.

TXARD

Active power down exit, with fast exit to a read


command latency, in number of clocks. This parameter is
valid only when the USE_PORTS_TO_CONFIGURE
parameter is set to 0, which is the default value of the
parameter USE_PORTS_TO_CONFIGURE.

22.

BANK_ADDR_WIDTH

Configures the Bank Address line width. Configure this


parameter with the value 2 to track designs with 4 banks.
Configure with the value 3 to track designs with 8 banks.
The maximum allowed value is 3.

23.

ENABLE_PRECHARGE_
TO_IDLE_BANK

Set this parameter to include the check to fire on multiple


precharge commands to a bank that is already in idle
condition. By default, this check is turned off.

24.

BYPASS_INIT

Set this parameter to 1 to bypass the initialization


sequence. If this parameter is set to 1, then the complete
initialization sequence need not be performed.
Nevertheless, valid operational values must be passed to
the mode register/extended mode register inputs, failing
which the monitor behavior is undefined. By default, the
monitor requires the proper initialization sequence to be
performed as described in the JEDEC specification.

25.

DATA_CHECK_ENABLE

This parameter enables or disables the following data


integrity checks: DDR_SDRAM_bad_data and
DDR_SDRAM_read_before_write.
Set this parameter to 1 to enable the data integrity checks.
Setting to 0 removes the checks by completely removing
the data-checker module, qvl_ddr_sdram_data_checker.

26.

OPTIONAL_ADDITIVE_
LATENCY_ENABLE

If optional additive latency is supported to enable


verification of setting of the same while programming
EMR(1), then set this parameter to 1.

27.

IMPEDANCE_
CALIBRATION_CHECKS_
ENABLE

Set this parameter to 1 if OCD impedance calibration is


supported.

28.

PARTIAL_SELF_
REFRESH_ENABLE

Set this parameter to 1 if partial Self Refresh related


values need to be verified in EMR programming while
initializing DDR2 SDRAM.

29.

DUTY_CYCLE_
CONTROL_ENABLE

Set this parameter to if clock duty cycle control is


supported and related initialization values need to be
verified during EMR programming.

30.

DDR2_SPEED_GRADE

400

This parameter is used to enable any speed grade specific


checks. For example, ODT value of 50 ohms for speed
grade 800 setting while EMRS1 is programming.

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Table 7-11. DDR-II SDRAM 2.0 Monitor Parameters (cont.)


Order Parameter

Default Description

31.

HIGH_TEMP_SELF_
REFRESH_RATE_ENABLE

Set this parameter to 1 to switch on checking of the high


temperature Self Refresh bit setting during EMR(2)
programming.

32.

CLOCK_CHANGE_
TRACKING_ENABLE

Set this parameter to 1 to enable support of the change of


input clock frequency on the fly as per JESD79-2C May
2005 specification update.

33.

TCLK_CHECK_ENABLE

Set this parameter to 1 to enable checking for minimum


clock cycles to be lapsed before the clock frequency can
change after CKE is sampled LOW. This parameter is
valid only when the parameter
CLOCK_CHANGE_TRACKING_ENABLE is set to 1.

34.

TCLK

Represents the value for minimum cycles to be lapsed


before the clock frequency can change in precharge
power down mode after clock enable signal (CKE) is
sampled LOW. This parameter is valid only when the
parameter CLOCK_CHANGE_TRACKING_ENABLE
is set to 1.

35.

CLOCK_FREQUENCY_
RANGE_CHECK_ENABLE

Set this parameter to 1 to enable checking for the clock


frequency if it is within allowed ranges, which is
specified by the other set of parameters
CLOCK_PERIOD_MAX and CLOCK_PERIOD_MIN.
This parameter is valid only when the parameter
CLOCK_CHANGE_TRACKING_ENABLE is set to 1.

36.

CLOCK_PERIOD_MAX

2500

Set the highest allowed clock period specified in


picoseconds (ps), which is a measure of the lowest clock
frequency supported by the DDR2 SDRAM. The default
value is set to 2500 (ps). The default value means a
supported clock of 400 MHz, which is the slowest clock
supported for DDR2 SDRAM as per JESD79-2C. The
user can alter this value for non-JEDEC applications.

37.

CLOCK_PERIOD_MIN

1250

Set the lowest allowed clock period specified in


picoseconds (ps), which is a measure of the lowest clock
frequency supported by the DDR2 SDRAM. The default
value is set to 1250 (ps). The default value means a
supported clock of 800 MHz, which is the fastest clock
supported for DDR2 SDRAM as per JESD79-2C. The
user can alter this value for non-JEDEC applications.

38.

USE_PORTS_TO_
CONFIGURE

Set this parameter to 1 to enable the usage of the input


ports to configure the various timing parameter values.
By default, the monitor uses the defined JEDEC values.

The parameters must be specified in the above order.


Time is measured in terms of number of clock cycles.

When constraints mode is disabled, all checks are used as targets during formal analysis. To use
the checks as constraints for formal analysis, do both of the following:

Set the Constraints_Mode parameter to 1.

Set the CONTROLLER_SIDE parameter as follows:

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o

If the monitor is instantiated in the DDR-II SDRAM controller, then set


CONTROLLER_SIDE to 1.

If the monitor is instantiated in the DDR-II SDRAM memory, then set


CONTROLLER_SIDE to 0.

Programming the DQS Delay


Note the following about the `define compiler directive:
Name: QVL_DQS_DELAY
Default: 2
Description:
This is used to delay the DQS signal during read cycles in order to align the DQS signal edges at
the center of the DQ signal to guarantee the proper latching of DQ.
By default, the DQS signal is delayed by 2 time units (i.e., #2) internally.
The user should override this with a larger value if the DQS signal that is driven by the DDR
Memory should be delayed more than #2 to guarantee proper DQ latching.

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JEDEC Standard Compliant Values of the Timing Parameters


Table 7-12. JEDEC Standard Compliant Timing for DDR2 400 Speed Grade
Timing Parameter

JEDEC Standard Timing Value

TRAS

TRCD

TRP

TRRD

TCCD

TRTW

TWTR

TWR

TRFC

TXSNR

10

TXSRD

200

TMRD

TXP

TXARD

TCLK

Time is measured by an integer number of clock cycles obtained by dividing the absolute
AC timing parameter by tCK (clock period) and rounding off to the nearest integer.

Instantiation Examples
Example 1
Example 7-3 instantiates a DDR-II SDRAM 2.0 monitor on the DDR-II SDRAM controller
side with ROW_ADDR_WIDTH of 16, DATA_BUS_WIDTH of 8, and DLL_TRACKING_ENABLE set to
1. The timing parameters are the default values specified by JEDEC. The monitor is instantiated
with BYPASS_INIT = 1. Internal signals are connected to the monitor ports
mode_register_in and ex_mode_register_in.
Example 7-3. DDR-II SDRAM 2.0 Monitor Instantiation
qvl_ddr2_sdram_2_0_monitor
#( 1,
/* Constraints_Mode */
1,
/* CONTROLLER_SIDE */
16,
/* ROW_ADDR_WIDTH */
8,
/* DATA_BUS_WITH */
1,
/* DLL_TRACKING_ENABLE */
6,
/* TRAS */

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2,
2,
1,
2,
4,
1,
2,
9,
10,
200,
2,
10,
1,
2,
2,
3,
0,
1,
1,
1,
0,
1,

/* TRCD */
/* TRP */
/* TRRD */
/* TCCD */
/* TRTW */
/* TWTR */
/* TWR */
/* TRFC */
/* TXSNR */
/* TXSRD */
/* TMRD */
/* AUTOPRECHARGE_ENABLE_ADDRESS_BIT*/
/* READ_BEFORE_WRITE_CHECK_ENABLE */
/* TXP */
/* TXARD */
/* BANK_ADDR_WIDTH */
/* ENABLE_PRECHARGE_TO_IDLE_BANK */
/* BYPASS_INIT */
/* ZI_DDR2_SDRAM_2_0 */
/* ZI_DM_WIDTH */
/*OPTIONAL_ADDITIVE_LATENCY_ENABLE*/
/*IMPEDANCE_CALIBRATION_CHECKS_ENABLE*/ // OCD Calibration
// enabled
0,
/* PARTIAL_SELF_REFRESH_ENABLE*/
0,
/*DUTY_CYCLE_CONTROL_ENABLE*/
800,
/*DDR2_SPEED_GRADE*/
0,
/*HIGH_TEMP_SELF_REFRESH_RATE_ENABLE*/
0,
/* CLOCK_CHANGE_TRACKING_ENABLE */
0,
/* TCLK_CHECK_ENABLE */
2,
/* TCLK*/
0,
/* CLOCK_FREQUENCY_RANGE_CHECK_ENABLE*/
2500,
/* CLOCK_PERIOD_MAX */
1250)
/* CLOCK_PERIOD_MIN */
DDR2_SDRAM_MONITOR0 (
.ck
(clock),
.ck_n
(clock_n),
.reset
(reset),
.areset
(areset),
.cke
(clock_enable_1),
.cs_n
(chip_select_n_1),
.ras_n
(row_address_strobe_n),
.cas_n
(column_address_strobe_n),
.we_n
(write_enable_n),
.ba
(bank_address),
.a
(address_bus_16),
.dm
(data_mask_1),
.dq
(data_bus_8),
.dqs
(data_strobe)
.ldqs
(1'b0),
.ldm
(1'b0)
.udqs
(1'b0),
.udm
(1'b0),
.mode_register_in
(internal_mode_register),
.ex_mode_register_in (internal_ex_mode_register), // If any
.odt(odt) ); // On-die-termination

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Example 2
Example 7-4 instantiates two instances of the DDR-II SDRAM 2.0 monitor for a DDR-II
SDRAM memory. The example has the following characteristics:

The controller design interfaces two stacked DDR-II SDRAMs, each having 12-bits of
ROW_ADDR_WIDTH (4K address space) and 16-bits of DATA_BUS_WIDTH.

The cs_n, cke, ras_n, cas_n, and we_n signals of width 2-bits each, one for each
DDR-II SDRAM.

Two bank addresses of width 2-bits each, one for each DDR-II SDRAM memory.

The DLL tracking is enabled. Therefore, the DLL_TRACKING_ENABLE parameter is set to


1.

The monitor is instantiated for constrained formal verification. Therefore, the


Constraints_Mode parameter is set to 1.

Initialization sequence tracking is enabled (by default).

Mode register and extended mode register ports are left unconnected.
Example 7-4. DDR-II SDRAM 2.0 Monitor Instantiation

qvl_ddr2_sdram_2_0_monitor
#( 1,
/* Constraints_Mode */
0,
/* CONTROLLER_SIDE */
12,
/* ROW_ADDR_WIDTH */
16)
/* DATA_BUS_WITH */
DDR2_SDRAM_MONITOR0 (
.ck
(clock),
.ck_n
(clock_n),
.reset
(reset),
.areset
(areset),
.cke
(clock_enable_0),
.cs_n
(chip_select_n_0),
.ras_n
(row_address_strobe_n_0),
.cas_n
(column_address_strobe_n_0),
.we_n
(write_enable_n_0),
.ba
(bank_address_0),
.a
(address_bus_12_0),
.dm_rdqs
(1'b0),
.dq
(upper_data_byte_0,lower_data_byte_0),
.dqs
(1'b0)
.ldqs
(lower_data_strobe_0),
.ldm
(lower_data_mask_0),
.udqs
(upper_data_strobe_0),
.udm
(upper_data_mask_0),
.mode_register_in
(),
.ex_mode_register_in
(),
.odt(odt) ); // On-die-termination
qvl_ddr2_sdram_2_0_monitor
#( 1,

/* Constraints_Mode */

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0,
/* CONTROLLER_SIDE */
12,
/* ROW_ADDR_WIDTH */
16)
/* DATA_BUS_WITH */
DDR2_SDRAM_MONITOR1 (
.ck
(clock),
.ck_n
(clock_n),
.reset
(reset),
.areset
(areset),
.cke
(clock_enable_1)
.cs_n
(chip_select_n_1),
.ras_n
(row_address_strobe_n_1),
.cas_n
(column_address_strobe_n_1),
.we_n
(write_enable_n_1),
.ba
(bank_address_1),
.a
(address_bus_12_1),
.dm_rdqs
(1'b0),
.dq
(upper_data_byte_1,lower_data_byte_1),
.dqs
(1'b0)
.ldqs
(lower_data_strobe_1),
.ldm
(lower_data_mask_1),
.udqs
(upper_data_strobe_1),
.udm
(upper_data_mask_1),
.mode_register_in
(),
.ex_mode_register_in
(),
.odt(odt) ); // On-die-termination

Monitor Checks
Table 7-13 shows the checks performed by a DDR-II SDRAM 2.0 monitor.
Table 7-13. DDR-II SDRAM 2.0 Monitor Checks
Check ID

Violation

Description

A_DDR2_SDRAM_ILLEGAL_
RESERVED_STATES_IN_EMR1

Bits BA2 and A13-A15 are


reserved for future use, and
they must be set to 0 when
programming EMR1.

Reserved bit fields in the extended


mode register 1 must be set to 0 during
initialization. This check fires if the
reserved bits are not set to 0 during
EMR1 programming.

A_DDR2_SDRAM_ILLEGAL_
OCD_VALUE_FOR_DDR2_800_
EMR1

Incorrect programming for bits


A2 and A6 in the EMR1 for
DDR2 SDRAM speed grade
800.

For DDR2 SDRAM with speed grade


800 Mhz, it is a mandatory
requirement that during initialization
extended mode register 1 must be
programmed to reflect a 50 ohm
impedance against the setting of bits
A2 and A6. The requirement is that
both of these bits are set HIGH for
this. If any of these two bit settings
violates this requirement for such an
DDR2 SDRAM, then this check fires.
This check is functional only when the
parameter DDR2_SPEED_GRADE is
set to 800.

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Table 7-13. DDR-II SDRAM 2.0 Monitor Checks (cont.)


Check ID

Violation

Description

A_DDR2_SDRAM_ILLEGAL_
RESERVED_STATES_IN_EMR2

Bits BA2, A4-A6, and A8A15 are reserved for future use,
and they must be set to 0 when
programming EMR2.

Reserved bit fields in the extended


mode register 2 must be set to 0 during
initialization. This check fires if the
reserved bits are not set to 0 during
EMR2 programming.

A_DDR2_SDRAM_ILLEGAL_
HTSRR_BIT_STATE_IN_EMR2

When high temperature Self


Refresh is not supported, the
respective bit in EMR2
programming should be set to
0.

The parameter HIGH_TEMP_SELF_


REFRESH_RATE_ENABLE enables
or disables high temperature Self
Refresh support. This check fires
when this parameter is set to 0
reflecting a non-supported model for
this feature, but EMR2 is programmed
incorrectly with a nonzero value in the
respective bit A7. This check is
functional only when the parameter
HIGH_TEMP_SELF_REFRESH_
RATE_ENABLE is set to 0.

A_DDR2_SDRAM_ILLEGAL_
PASR_BIT_STATES_IN_EMR2

When partial Self Refresh is


not supported, the pasr bits
should always be set to 0s to
represent full page access
during EMR2 programming.

The parameter PARTIAL_SELF_


REFRESH_ENABLE enables or
disables partial array Self Refresh
support. This check fires when this
parameter is set to 0 reflecting a nonsupported model for this feature, but
EMR2 is programmed incorrectly
with a nonzero value in the respective
bits A2-A0. This check is functional
only when the parameter
PARTIAL_SELF_REFRESH_
ENABLE is set to 0.

A_DDR2_SDRAM_ILLEGAL_
DCC_BIT_STATE_IN_EMR2

When duty cycle control is not


supported, the relevant bit
should always be set to 0
during EMR2 programming.

The parameter DUTY_CYCLE_


CONTROL_ENABLE enables or
disables duty cycle control of the
clock. This check fires when this
parameter is set to 0 reflecting a nonsupported model for this feature, but
EMR2 is programmed incorrectly
with a nonzero value in the respective
bit A3. This check is functional only
when the parameter DUTY_CYCLE_
CONTROL_ENABLE is set to 0.

A_DDR2_SDRAM_ILLEGAL_
RESERVED_STATES_IN_EMR3

Bits BA2 and A0-A15 are


reserved for future use, and
they must be set to 0 when
programming EMR3.

Except for bits BA0 and BA1, all


other bits in extended mode register 3
are reserved for future use. Reserved
bit fields in EMR3 must be set to 0
during initialization. This check fires
if the reserved bits are not set to 0
during EMR3 programming.

A_DDR2_SDRAM_ODT_
VIOLATION_DURING_DLL_
STABILIZATION

ODT should be LOW while


DLL is within its lock period.

The on-die-termination signal input


ODT should be driven LOW while
DLL is within its lock period. This
check fires when ODT is sampled
with a value other than 0 during the
DLL lock period.

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Table 7-13. DDR-II SDRAM 2.0 Monitor Checks (cont.)


Check ID

Violation

Description

A_DDR2_SDRAM_FIRST_
EMRS_NOT_ISSUED_WITH_
OCD_EXIT

First EMR command during


initialization should be issued
with OCD exit mode.

During initialization sequence, when


the very first EMR set command is
issued, it should have OCD mode
settings as exit mode. This check
monitors this requirement.

A_DDR2_SDRAM_EMRS2_IS_
NOT_ISSUED_AFTER_FIRST_
PRECHARGE_ALL

EMR2 set command is not


issued after the first precharge
all.

During initialization sequence, the


first precharge all command must be
followed by an EMR2 set command.
This check monitors this requirement.

A_DDR2_SDRAM_OCD_
DEFAULT_CALIBRATION_NOT_
SET_AFTER_SECOND_MRS

OCD default calibration mode


is not set after the second MRS
during initialization.

During initialization sequence, after


the second MRS command, there
should follow a OCD default
calibration mode entry. This check
monitors this requirement.

A_DDR2_SDRAM_INVALID_BL_
BEFORE_ENTERING_OCD_
ADJUST_MODE

The burst length is not set to 4


before OCD adjust mode entry
during initialization.

During initialization, before off-chip


driver (OCD) impedance adjustment,
the burst length must be set to 4 by an
MSR command. Failing to set this
accordingly will trigger this check.
This check is functional only when the
parameter IMPEDANCE_
CALIBRATION_CHECKS_
ENABLE is set to 1.

A_DDR2_SDRAM_OCD_
DRIVE0_MODE_NOT_
FOLLOWED_BY_OCD_CALI_
EXIT_MODE

OCD drive0 mode is not


followed by OCD calibration
exit during initialization.

Every OCD mode must be followed


by an OCD calibration mode exit. This
check fires if OCD drive0 mode is not
followed by OCD calibration mode
exit. This check is functional only
when the parameter
IMPEDANCE_CALIBRATION_
CHECKS_ENABLE is set to 1.

A_DDR2_SDRAM_OCD_
DRIVE1_MODE_NOT_
FOLLOWED_BY_OCD_CALI_
EXIT_MODE

OCD drive1 mode is not


followed by OCD calibration
exit during initialization.

Every OCD mode must be followed


by an OCD calibration mode exit. This
check fires if OCD drive1 mode is not
followed by OCD calibration mode
exit. This check is functional only
when the parameter
IMPEDANCE_CALIBRATION_
CHECKS_ENABLE is set to 1.

A_DDR2_SDRAM_OCD_
ADJUST_MODE_NOT_
FOLLOWED_BY_OCD_CALI_
EXIT_MODE

OCD adjust mode is not


followed by OCD calibration
exit during initialization.

Every OCD mode must be followed


by an OCD calibration mode exit. This
check fires if OCD adjust mode is not
followed by OCD calibration mode
exit. This check is functional only
when the parameter
IMPEDANCE_CALIBRATION_
CHECKS_ENABLE is set to 1.

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Table 7-13. DDR-II SDRAM 2.0 Monitor Checks (cont.)


Check ID

Violation

Description

A_DDR2_SDRAM_ILLEGAL_
DQ_DQS_IN_OCD_DRIVE0_
MODE

The data and data strobe


signals are not driven LOW
while in OCD drive0 mode
during initialization.

The input clock frequency can change


only in precharge power down mode
while the clock enable signal CKE is
LOW. This check fires when the
DDR2 SDRAM clock changes while
the DDR2 SDRAM is not operating in
idle or precharge power down mode.
This check is functional only when the
parameter CLOCK_CHANGE_
TRACKING_ENABLE is set to 1.

A_DDR2_SDRAM_ILLEGAL_
DQ_DQS_IN_OCD_DRIVE1_
MODE

The data and data strobe


signals are not driven HIGH in
OCD drive1 mode during
initialization.

The input clock frequency can change


only in precharge power down mode
while the clock enable signal CKE is
LOW. This check fires when the
DDR2 SDRAM clock changes while
CKE is not LOW. This check is
functional only when the parameter
CLOCK_CHANGE_TRACKING_
ENABLE is set to 1.

DDR2_SDRAM_ADDITIVE_
LATENCY_INVALID

Invalid Additive latency value


is programmed in the extended
mode register during the
EMRS command.

This check is applicable only if


BYPASS_INIT is 0 (i.e., normal
initialization sequence). Supported
additive latency values are 0, 1, 2, 3,
and 4. Any other value is invalid.
Check the additive_latency value
programmed during the last EMRS
command.

DDR2_SDRAM_ADDITIVE_
LATENCY_INVALID_BYPASS

The additive latency field of


the input extended mode
register is invalid.

This check is applicable only if


BYPASS_INIT is set and an incorrect
value is passed to the
ex_mode_register_in input. Supported
additive latency values are 0, 1, 2, 3,
and 4. Any other value is invalid. This
check fires if an additive latency value
other than the ones listed above is
passed through the
ex_mode_register_in input.

DDR2_SDRAM_ADDRESS_
LEVEL

Address lines are not driven to


valid levels.

Checks that address lines are both


known (not X) and driven (not Z).
This check is active only during MRS,
EMRS, Activate and memory Read ad
Write commands.

DDR2_SDRAM_AUTO_
REFRESH_PRECHARGE

An auto refresh command is


issued when one or more banks
are not in precharge state.

An auto refresh command can be


issued only when all banks are in
precharged condition.

DDR2_SDRAM_BANK_LEVEL

Bank Address lines are not


driven to valid levels.

Checks that bank address lines are


both known (not X) and driven (not
Z). This check is active only during
Precharge, Activate and memory Read
and Write commands.

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Table 7-13. DDR-II SDRAM 2.0 Monitor Checks (cont.)


Check ID

Violation

Description

DDR2_SDRAM_CAS_LATENCY_
INVALID

Invalid CAS latency value is


programmed in the mode
register during the MRS
command.

This check is applicable only if


BYPASS_INIT is 0 (i.e., normal
initialization sequence). CAS latency
can be either 2, 3, 4, or 5. Any other
value is invalid or reserved. Check the
cas_latency value programmed during
the last MRS command.

DDR2_SDRAM_CAS_LATENCY_
INVALID_BYPASS

The CAS latency field of the


input mode register is invalid.

This check is applicable only if


BYPASS_INIT is set and an incorrect
value is passed to the
mode_register_in input. As per
JEDEC specification, the valid CAS
latency values are 2, 3, 4, and 5. This
check fires if a CAS latency value
other than the ones listed above is
passed through the mode_register_in
input.

DDR2_SDRAM_CAS_LEVEL

cas_n is not driven to a valid


level.

Checks that CAS_n is both known


(not X) and driven (not Z). This check
is active only if CKE is high.

DDR2_SDRAM_CKE_LEVEL

cke is not driven to a valid


level.

Checks that CKE is both known (not


X) and driven (not Z). This check is
active after the first active edge of the
clock.

DDR2_SDRAM_CONSTRAINTS_
MODE

Constraints_Mode parameter
should be either 1 or 0.

The value of the


CONSTRAINTS_MODE parameter
should be either 1 or 0. It is to be made
1 to make checks as constraints and 0
to have them as targets during formal
analysis.

DDR2_SDRAM_CONTROLLER_
SIDE

CONTROLLER_SIDE
parameter should be either 1 or
0.

The value of CONTROLLER_SIDE


parameter should be either 1 or 0.

DDR2_SDRAM_CS_LEVEL

cs_n is not driven to a valid


level.

Checks that CS_n is both known (not


X) and driven (not Z). Active only if
CKE is high.

DDR2_SDRAM_DATA_CONFIG

DATA_BUS_WIDTH
parameter should be either 4, 8,
or 16.

The value of the


DATA_BUS_WIDTH parameter
should not be specified to be other
than 4, 8, or 16 since this indicates the
configuration of the data bus and the
allowed configurations are x4, x8, or
x16.

DDR2_SDRAM_DLL_NOT_RESET

DLL not reset prior to the first


activation command.

This check is applicable only if


BYPASS_INIT is 0 (i.e, normal
initialization sequence). If DLL is
enabled during the initialization
sequence, then it must be reset before
issuing an activation command to any
bank. This check is active only if
DLL_TRACKING_ENABLE is 1.

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Table 7-13. DDR-II SDRAM 2.0 Monitor Checks (cont.)


Check ID

Violation

Description

DDR2_SDRAM_DLL_TRACKING

DLL_TRACKING_ENABLE
parameter should be either 1 or
0

The value of the


DLL_TRACKING_ENABLE
parameter should be either 1 or 0.

DDR2_SDRAM_DM_RDQS_
LEVEL

dm_rdqs is not driven to a valid Checks that DM_RDQS is both


level.
known (not X) and driven (not Z).
Active only during write bursts in x4
and x16 configurations and 8x
configuration when RDQS is disabled,
if CKE is high.

DDR2_SDRAM_EMRS_3_
BEFORE_EMRS_2

An EMRS(3) command is
issued prior to an EMRS(2)
command during initialization
sequence.

This check is applicable only if


BYPASS_INIT is 0 (i.e., normal
initialization sequence). During the
initialization sequence, an EMRS(2)
command followed by an EMRS(3)
command should be issued even
before the DLL is enabled using the
EMRS command.

DDR2_SDRAM_EMRS_BEFORE_
EMRS_3

An EMRS command to enable


DLL is issued prior to an
EMRS(3) during initialization
sequence.

This check is applicable only if


BYPASS_INIT is 0 (i.e., normal
initialization sequence). During the
initialization sequence, an EMRS(2)
command followed by an EMRS(3)
command should be issued even
before the DLL is enabled using the
EMRS command.

DDR2_SDRAM_EMRS_
PRECHARGE

An extended mode register set


command is issued when one
or more banks are not in
precharge state.

An extended mode register set


command can be issued only when all
banks are in a precharged condition.

DDR2_SDRAM_INCORRECT_
COMMAND_BEFORE_MRS

An invalid command is issued


before programming the mode
register (only NOP,
DESELECT, and
PRECHARGE are valid at this
point).

This check is applicable only if


BYPASS_INIT is 0 (i.e., normal
initialization sequence). NOP,
precharge, and refresh are the only
commands that are valid before the
Mode register is set. Check the
designs reset sequencing.

DDR2_SDRAM_INSUFFICIENT_
AUTO_REFRESH_ACTIVATE

Sufficient number (2) of auto


refresh commands are not
issued prior to the first
activation command.

This check is applicable only if


BYPASS_INIT is 0 (i.e., normal
initialization sequence). During the
initialization sequence, at least 2 auto
refresh commands must be issued
before the first activation command.

DDR2_SDRAM_LDM_LEVEL

ldm is not driven to a valid


level.

Checks that LDM is both known (not


X) and driven (not Z). Active only
during write bursts if CKE is high.

DDR2_SDRAM_MODE_
REGISTER_NOT_SET

Mode register is not


programmed prior to the first
activation command.

This check is applicable only if


BYPASS_INIT is 0 (i.e., normal
initialization sequence). The mode
register must be configured for burst
type, CAS latency, etc. during the
initialization sequence, before the first
activation.

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209

Double Data Rate-II SDRAM (DDR-II SDRAM)


V2.0 Monitor

Table 7-13. DDR-II SDRAM 2.0 Monitor Checks (cont.)


Check ID

Violation

Description

DDR2_SDRAM_MRS_
PRECHARGE

A mode register set command


is issued when one or more
banks are not in precharge
state.

A mode register set command can be


issued only when all banks are in
precharged condition.

DDR2_SDRAM_RAS_LEVEL

ras_n is not driven to a valid


level.

Checks that RAS_n is both known


(not X) and driven (not Z). This check
is active only if CKE is high.

DDR2_SDRAM_ROW_ADDRESS

ROW_ADDRESS_WIDTH
parameter should not be less
than the minimum limit of 12.

The value of the


ROW_ADDRESS_WIDTH parameter
should not be specified to be less than
12.

DDR2_SDRAM_SELF_REFRESH_
PRECHARGE

A self refresh command is


issued when one or more banks
are not in precharge state.

A self refresh command can be issued


only when all banks are in precharged
condition.

DDR2_SDRAM_SEQUENTIAL_
ACTIVATION_VIOLATION

The number of activation


commands in a rolling window
of (4*tRRD + 2tCK) exceeded
4.

In order to ensure that 8 bank devices


do not exceed the instantaneous
current supplying capability of 4 bank
devices, the following restriction must
be observed: no more than 4 banks can
be activated in a rolling (4 * tRRD + 2
* tCK) window, and a rolling window
is often also called a sliding window.

DDR2_SDRAM_TCCD

TCCD timing parameter should The value of the TCCD timing


not be less than the minimum
parameter should not be specified to
limit of 2.
be less than 2.

DDR2_SDRAM_TDLL_
VIOLATION_AFTER_DLL_RESET

A Read or Read with


Autoprecharge command is
issued before 200 clock cycles
after DLL reset.

This check is applicable only if


BYPASS_INIT is 0 (i.e., normal
initialization sequence). A Mode
Register Set command must be issued
for the Mode Register to reset the
DLL and to program the operating
parameters. Once the DLL reset
command is issued, a minimum of 200
clock cycles are required before any
read command is issued.

DDR2_SDRAM_TMRD

TMRD timing parameter


should not be less than the
minimum limit of 2.

The value of the TMRD timing


parameter should not be specified to
be less than 2.

DDR2_SDRAM_TRAS

TRAS timing parameter should The value of the TRAS timing


not be less than the minimum
parameter should not be specified to
limit of 6.
be less than 6.

DDR2_SDRAM_TRCD

TRCD timing parameter should The value of the TRCD timing


not be less than the minimum
parameter should not be specified to
limit of 2.
be less than 2.

DDR2_SDRAM_TRFC

TRFC timing parameter should


not be less than the minimum
limit of 9.

The value of the TRFC timing


parameter should not be specified to
be less than 9.

DDR2_SDRAM_TRP

TRP timing parameter should


not be less than the minimum
limit of 2.

The value of the TRP timing


parameter should not be specified to
be less than 2.

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Double Data Rate-II SDRAM (DDR-II SDRAM)


V2.0 Monitor

Table 7-13. DDR-II SDRAM 2.0 Monitor Checks (cont.)


Check ID

Violation

DDR2_SDRAM_TRRD

TRRD timing parameter should The value of the TRRD timing


not be less than the minimum
parameter should not be specified to
limit of 1.
be less than 1.

DDR2_SDRAM_TRRD_
VIOLATION

The command issued violates


the tRRD timing between
activation commands to
different banks.

The command just issued violates


tRRD (RAS to RAS delay timing).
This is an ACTIVATE command
issued too quickly after the
ACTIVATE command for another
bank. The user should determine why
the commands are too close together.

DDR2_SDRAM_TRTW

TRTW timing parameter


should not be less than the
minimum limit of 4.

The value of the TRTW timing


parameter should not be specified to
be less than 4.

DDR2_SDRAM_TWR

TWR timing parameter should


not be less than the minimum
limit of 2.

The value of the TWR timing


parameter should not be specified to
be less than 2.

DDR2_SDRAM_TWTR

TWTR timing parameter


should not be less than the
minimum limit of 1.

The value of the TWTR timing


parameter should not be specified to
be less than 1.

DDR2_SDRAM_TXARD

TXARD timing parameter


should not be less than the
minimum limit of 2.

The value of the TXARD timing


parameter should not be specified to
be less than 2.

DDR2_SDRAM_TXP

TXP timing parameter should


not be less than the minimum
limit of 2.

The value of the TXP timing


parameter should not be specified to
be less than 2.

DDR2_SDRAM_TXSNR

TXSNR timing parameter


should not be less than the
minimum limit of 10.

The value of the TXSNR timing


parameter should not be specified to
be less than 10.

DDR2_SDRAM_TXSRD

TXSRD timing parameter


should not be less than the
minimum limit of 200.

The value of the TXSRD timing


parameter should not be specified to
be less than 200.

DDR2_SDRAM_UDM_LEVEL

udm is not driven to a valid


level.

Checks that UDM is both known (not


X) and driven (not Z). Active only
during write bursts if CKE is high.

DDR2_SDRAM_WE_LEVEL

we_n is not driven to a valid


level.

Checks that WE_n is both known (not


X) and driven (not Z). This check is
active only if CKE is high.

Questa Verification Library Monitors Data Book, v2010.2

Description

211

Double Data Rate-II SDRAM (DDR-II SDRAM)


V2.0 Monitor

Table 7-14 shows the checks for each bank performed by a DDR-II SDRAM 2.0 monitor.
Table 7-14. DDR-II SDRAM 2.0 Monitor Bank Checks
Check ID

Violation

Description

A_DDR2_SDRAM_CLOCK_
CHANGE_DURING_NON_PPD_
MODE

Clock frequency has changed


while the DDR2 SDRAM is not
in precharge power down
mode.

The input clock frequency can


change only in precharge power
down mode while the clock enable
signal CKE is LOW. This check
fires when the DDR2 SDRAM
clock changes while the DDR2
SDRAM is not operating in idle or
precharge power down mode. This
check is functional only when the
parameter CLOCK_CHANGE_
TRACKING_ENABLE is set to 1.

A_DDR2_SDRAM_CLOCK_
CHANGE_DURING_ILLEGAL_CKE

Clock frequency has changed


while CKE is not LOW.

The input clock frequency can


change only in precharge power
down mode while the clock enable
signal CKE is LOW. This check
fires when the DDR2 SDRAM
clock changes while CKE is not
LOW. This check is functional
only when the parameter
CLOCK_CHANGE_
TRACKING_ENABLE is set to 1.

A_DDR2_SDRAM_CLOCK_
FREQUENCY_OUT_OF_RANGE

The clock frequency is out of


The input clock frequency can
the allowed range in current
change only within the allowed
speed grade of DDR2 SDRAM. range in a speed grade. This check
fires when the DDR2 SDRAM
clock changes beyond the allowed
clock frequency range specified by
the parameters
CLOCK_PERIOD_MAX and
CLOCK_PERIOD_MIN. By
default, the monitor verifies a range
of 400 Mhz - 800 MHz. This check
is functional only when both the
parameters CLOCK_CHANGE_
TRACKING_ENABLE and
CLOCK_FREQUENCY_
RANGE_CHECK_ENABLE are
set to 1.

A_DDR2_SDRAM_CKE_
CHANGED_DURING_UNSTABLE_
CLOCK

CKE changed state while the


clock is not yet stable.

212

The input clock frequency can


change only in precharge power
down mode while the clock enable
signal CKE is LOW. This check
fires when after a clock frequency
change, CKE changes its state
before a stable clock is available.
This check is functional only when
the parameter CLOCK_CHANGE_
TRACKING_ENABLE is set to 1.

Questa Verification Library Monitors Data Book, v2010.2

Double Data Rate-II SDRAM (DDR-II SDRAM)


V2.0 Monitor

Table 7-14. DDR-II SDRAM 2.0 Monitor Bank Checks (cont.)


Check ID

Violation

A_DDR2_SDRAM_PPD_EXIT_
DURING_UNSTABLE_CLOCK

Precharge power down mode


The input clock frequency can
exited during an unstable clock. change only in precharge power
down mode while the clock enable
signal CKE is LOW. This check
fires when after a clock frequency
change, precharge power down
mode is exited before a stable clock
is available. This check is
functional only when the parameter
CLOCK_CHANGE_TRACKING_
ENABLE is set to 1.

A_DDR2_SDRAM_DLL_NOT_
RESET_AFTER_PPD_EXIT_
AFTER_CLOCK_CHANGE

DLL is not reset after precharge


power down exit after clock
change.

This check fires when a DLL reset


command is not executed after a
clock frequency change. This
check is functional only when both
the parameters
CLOCK_CHANGE_TRACKING_
ENABLE and
DLL_TRACKING_ENABLE are
set to 1.

DDR2_SDRAM_ACTIVATE

An ACTIVATE command is
issued to an already open bank
without an intervening
PRECHARGE.

An open bank must be closed


before issuing another activation
command to that bank.

DDR2_SDRAM_BAD_DATA

One or more bytes of data read


from the addressed DDR2
SDRAM location did not match
the data bytes written to the
corresponding address.

Data read from the DDR2 SDRAM


did not match the data written to
the corresponding address. The
data check is performed only on the
reads to locations that were
previously written at least once.
Data checking is done on a byte
basis and the bitmap indicates the
data inconsistency between the
corresponding bytes. The check
fires when at least one byte of read
data does not match the
corresponding valid data byte that
was written to that location.

DDR2_SDRAM_BURST_
ABORTED_P

A read or write is aborted.

In DDR2 SDRAMs, burst


interruption is prohibited. Once a
4-n burst has started, then it has to
be completed before the start of a
new burst.

CKE de-asserted while an


operation is in progress.

CKE is not allowed while mode


register or extended mode register
command time, or read or write
operation is in progress. The
behavior of the system for an
asynchronous low on CKE is
undefined.

DDR2_SDRAM_BURST_
ABORTED_N
DDR2_SDRAM_CKE_DRIVEN_
LOW

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Description

213

Double Data Rate-II SDRAM (DDR-II SDRAM)


V2.0 Monitor

Table 7-14. DDR-II SDRAM 2.0 Monitor Bank Checks (cont.)


Check ID

Violation

Description

DDR2_SDRAM_CKE_LOW

CKE is driven low during a


cycle other than self refresh or
power down.

Clock Enable can be driven low


only during self refresh and power
down commands and has to be
maintained high during all other
cycles.

DDR2_SDRAM_ILLEGAL_
COMMAND_ACT_PWR_DN

An illegal command is issued


when the bank is in the Active
Power Down state.

The command just issued is not a


legal command when the bank is in
the Active Power Down state. All
the valid commands from this state
are outlined in the state diagram in
the reference material. The user
should trace why an illegal
command is issued.

DDR2_SDRAM_ILLEGAL_
COMMAND_ACTIVE

An illegal command is issued


when the bank is in the
ACTIVATE state.

The command just issued is not a


legal command when the bank is in
the ACTIVATE state. All the valid
commands from this state are
outlined in the state diagram in the
reference material. The user should
trace why an illegal command is
issued.

DDR2_SDRAM_ILLEGAL_
COMMAND_CBR

An illegal command is issued


when the memory is in the
AUTO REFRESH state.

The command just issued is not a


legal command when the bank is in
the AUTO_REFRESH state. All
the valid commands from this state
are outlined in the state diagram in
the reference material. The user
should trace why an illegal
command is issued.

DDR2_SDRAM_ILLEGAL_
COMMAND_EMRS

An illegal command is issued


when the memory is in the
EX_MODE_REG_SET state.

The command just issued is not a


legal command when the bank is in
the EX_MODE_REG_SET state.
All the valid commands from this
state are outlined in the state
diagram in the reference material.
The user should trace why an
illegal command is issued.

DDR2_SDRAM_ILLEGAL_
COMMAND_IDLE

An illegal command is issued


when the bank is in the IDLE
state.

The command just issued is not a


legal command when the bank is in
IDLE state. All the valid
commands from this state are
outlined in the state diagram in the
reference material. The user should
trace why an illegal command is
issued.

DDR2_SDRAM_ILLEGAL_
COMMAND_IDLE_PWR_DN

An illegal command is issued


when the bank is in the Idle
Power Down state.

The command just issued is not a


legal command when the bank is in
the IDLE Power Down state. All
the valid commands from this state
are outlined in the state diagram in
the reference material. The user
should trace why an illegal
command is issued.

214

Questa Verification Library Monitors Data Book, v2010.2

Double Data Rate-II SDRAM (DDR-II SDRAM)


V2.0 Monitor

Table 7-14. DDR-II SDRAM 2.0 Monitor Bank Checks (cont.)


Check ID

Violation

Description

DDR2_SDRAM_ILLEGAL_
COMMAND_MRS

An illegal command is issued


when the memory is in the
MODE_REG_SET state.

The command just issued is not a


legal command when the bank is in
the MODE_REG_SET state. All
the valid commands from this state
are outlined in the state diagram in
the reference material. The user
should trace why an illegal
command is issued.

DDR2_SDRAM_ILLEGAL_
COMMAND_NOP

An illegal command is issued


when the bank is in the NOP
state.

The command just issued is not a


legal command when the bank is in
the SELF_REFRESH state. All the
valid commands from this state are
outlined in the state diagram in the
reference material. The user should
trace why an illegal command is
issued. For this, you can also look
at r_from_state_string.

DDR2_SDRAM_ILLEGAL_
COMMAND_PRE

An illegal command is issued


when the bank is in the
PRECHARGE state.

The command just issued is not a


legal command when the bank is in
the PRECHARGE state. All the
valid commands from this state are
outlined in the state diagram in the
reference material. The user should
trace why an illegal command is
issued.

DDR2_SDRAM_ILLEGAL_
COMMAND_PRE_ALL

An illegal command is issued


when all banks are in the
PRECHARGE state.

The command just issued is not a


legal command when the bank is in
the PRECHARGE_ALL state. All
the valid commands from this state
are outlined in the state diagram in
the reference material. The user
should trace why an illegal
command is issued.

DDR2_SDRAM_ILLEGAL_
COMMAND_READ

An illegal command is issued


when the bank is in the READ
state.

The command just issued is not a


legal command when the bank is in
the READ state. All the valid
commands from this state are
outlined in the state diagram in the
reference material. The user should
trace why an illegal command was
issued.

DDR2_SDRAM_ILLEGAL_
COMMAND_READ_AP

An illegal command is issued


when the bank is in the
READ_AUTO_PRECHARGE
state.

The command just issued is not a


legal command when the bank is in
the READ_AUTO_PRECHARGE
state. All the valid commands from
this state are outlined in the state
diagram in the reference material.
The user should trace why an
illegal command is issued.

Questa Verification Library Monitors Data Book, v2010.2

215

Double Data Rate-II SDRAM (DDR-II SDRAM)


V2.0 Monitor

Table 7-14. DDR-II SDRAM 2.0 Monitor Bank Checks (cont.)


Check ID

Violation

Description

DDR2_SDRAM_ILLEGAL_
COMMAND_SFR

An illegal command is issued


when the memory is in the
SELF_REFRESH
state.

The command just issued is not a


legal command when the bank is in
the SELF_REFRESH state. All the
valid commands from this state are
outlined in the state diagram in the
reference material. The user should
trace why an illegal command is
issued.

DDR2_SDRAM_ILLEGAL_
COMMAND_WRITE

An illegal command is issued


when the bank is in the WRITE
state.

The command just issued is not a


legal command when the bank is in
the WRITE state. All the valid
commands from this state are
outlined in the state diagram in the
reference material. The user should
trace why an illegal command is
issued.

DDR2_SDRAM_ILLEGAL_
COMMAND_WRITE_AP

An illegal command is issued


when the bank is in the
WRITE_AUTO_
PRECHARGE state.

The command just issued is not a


legal command when the bank is in
WRITE_AUTO_PRECHARGE
state. All the valid commands from
this state are outlined in the state
diagram in the reference material.
The user should trace why an
illegal command is issued.

DDR2_SDRAM_ILLEGAL_RD_
BURST_8B_INTERRUPTION

A read burst of length 8 from a


bank is interrupted at a 4-bit
boundary by a non-Read or
Read with the Autoprecharge
command.

A read burst of length 8 can only be


interrupted by another read, or read
with auto precharge enabled, at a 4bit burst boundary. This check fires
whenever a non-Read or Read with
Autoprecharge command interrupts
a read burst.

DDR2_SDRAM_ILLEGAL_WR_
BURST_8B_INTERRUPTION

A Write burst of length 8 from


a bank is interrupted at a 4-bit
boundary by a non-Write or
Write with the Autoprecharge
command.

A write burst of length 8 can only


be interrupted by another write, or
write with auto precharge enabled,
at a 4-bit burst boundary. This
check fires whenever a non-Write
or Write with Autoprecharge
command interrupts a write burst.

DDR2_SDRAM_PRECHARGE_
TO_IDLE_BANK

A Precharge command is issued A PRECHARGE command was


to an idle bank.
just issued to an already idle bank.
Although this is not an illegal
operation, it is redundant. The user
can check why such redundant
commands are issued.

DDR2_SDRAM_RD_BURST_8B_
INTERRUPTED_AT_6B

A read burst of length 8 from a


bank is interrupted at a 6-bit
boundary by a command.

216

A read burst can only be


interrupted by another read, or read
with auto precharge enabled, at a 4bit burst boundary. Any other form
of read interrupt is not allowed.
This check fires whenever a read
burst is interrupted at a 6-bit
boundary (typically the third clock
after the read command).

Questa Verification Library Monitors Data Book, v2010.2

Double Data Rate-II SDRAM (DDR-II SDRAM)


V2.0 Monitor

Table 7-14. DDR-II SDRAM 2.0 Monitor Bank Checks (cont.)


Check ID

Violation

Description

DDR2_SDRAM_READ_AP_
VIOLATION

The command issued violates


the timing between read with
auto precharge and activation
command issued to the same
bank.

The DDR2 SDRAM starts an auto


precharge operation on the rising
edge which is (AL + BL/2) cycles
later than the read with AP
command if tRAS(min) and
tRTP(min) are satisfied. A new
bank activate command may be
issued to the same bank if, tRP has
been satisfied from the clock at
which auto precharge begins and
tRC from the previous bank
activation has been satisfied.

DDR2_SDRAM_READ_BEFORE_
WRITE

A read operation is performed


on the DDR2 SDRAM address
at Row row and Column
column of Bank bank that was
not previously written into.

Data is read from the DDR-II


SDRAM from an address that was
not previously written into.

DDR2_SDRAM_READ_TO_IDLE_
BANK

A read command is issued to an


idle bank.

The bank to which the READ


command was just issued is in
precharged idle condition. The user
should determine why a READ
command is issued to an idle bank
without issuing an ACTIVATE
command.

DDR2_SDRAM_READA_BURST_
8B_INTERRUPTED

A read burst of length 8 from a


bank with autoprecharge
enabled is interrupted by a
command.

A read burst of length 8 with auto


precharge enabled must not be
interrupted and should be allowed
to go through the automatic
sequence to precharge.

DDR2_SDRAM_TCCD_VIOLATION

The command issued violates


the tCCD timing between two
Read/Write commands.

The command just issued violates


tCCD (CAS to CAS delay timing).
This is a READ/WRITE command
issued too quickly after a
READ/WRITE command for
another bank. The user should
determine why the commands are
too close together.

DDR2_SDRAM_TCKE_VIOLATION

CKE signal should be held at a


valid input level for at least
tCKE clock cycles.

The DDR2 standard specifies that


the CKE signal should be held at
valid input level (either 1 or 0)
for a minimum of three clock
cycles. This check fires if CKE
changes its value within three clock
cycles.

DDR2_SDRAM_TMRD_VIOLATION The command issued violates


the tMRD timing after a
MRS/EMRS command was
issued.

Questa Verification Library Monitors Data Book, v2010.2

Once a Mode Register Set, or


Extended Mode Register Set
command is issued, there cannot be
any command issued, including
another MRS or EMRS command
until TMRD number of clock
cycles expire.

217

Double Data Rate-II SDRAM (DDR-II SDRAM)


V2.0 Monitor

Table 7-14. DDR-II SDRAM 2.0 Monitor Bank Checks (cont.)


Check ID

Violation

Description

DDR2_SDRAM_TRAS_VIOLATION

The command issued violates


the tRAS timing between an
activation and precharge
command.

The command just issued violates


tRAS (RAS to precharge timing).
This is a PRECHARGE command
issued too quickly after the
ACTIVATE command for this
bank. The user should determine
why the commands are too close
together.

DDR2_SDRAM_TRC_VIOLATION

The command issued violates


the tRC timing between an
activation command and
another activation command
issued to the same bank.

Once an activation command is


issued to the bank, another
activation command can be issued
only after tRC cycles.

DDR2_SDRAM_TRCD_VIOLATION

The command issued violates


the tRCD timing between an
activation and Read/Write
command.

The command just issued violates


tRCD (RAS to CAS delay timing).
This is a READ/WRITE command
issued too quickly after the
ACTIVATE command for this
bank. The user should determine
why the commands are too close
together.

DDR2_SDRAM_TRFC_VIOLATION

The command issued violates


the tRFC timing between Auto
Refresh and Auto
Refresh/Activate command.

The command just issued violates


tRFC (minimum time delay
between AUTO REFRESH
command and any other
command). The new command is
issued too quickly after the AUTO
REFRESH command. The user
should determine why the
commands are too close together.

DDR2_SDRAM_TRP_VIOLATION

The command issued violates


the precharge command period
(tRP).

The command just issued violates


tRP (RAS precharge timing). This
is an ACTIVATE/REFRESH
command issued too quickly after
the last precharge command for
this bank. The tRP for a precharge
all command to an 8 bank device is
equal to tRP + 1. The user should
determine why the commands are
too close together.

DDR2_SDRAM_TRTP_VIOLATION

The command issued violates


the tRTP timing between a
Read and Precharge command.

The command just issued violates


Read to Precharge delay timing.
This is a PRECHARGE command
issued too quickly after a previous
READ command to the same bank.
The minimum delay should be
additive latency + BL/2 (burst
length / 2). You should determine
why the commands are too close
together.

218

Questa Verification Library Monitors Data Book, v2010.2

Double Data Rate-II SDRAM (DDR-II SDRAM)


V2.0 Monitor

Table 7-14. DDR-II SDRAM 2.0 Monitor Bank Checks (cont.)


Check ID

Violation

Description

DDR2_SDRAM_TRTR_VIOLATION

The command issued violates


the tRTR timing between two
Read commands.

The command just issued violates


Read to Read delay timing. This is
a READ command issued too
quickly after a previous READ
command to the same bank. The
minimum delay should be 2 clocks
since the 4-n bursts cannot be
interrupted. The user should
determine why the commands are
too close together.

DDR2_SDRAM_TRTW_VIOLATION The command issued violates


the tRTW timing between a
READ and WRITE command.

The command just issued violates


tRTW (Read to Write delay
timing). This is a WRITE
command issued too quickly after a
previous READ command to the
same bank. The user should
determine why the commands are
too close together.

DDR2_SDRAM_TWTP_VIOLATION

The command issued violates


The command just issued violates
the tWTP timing between a
Write to Precharge delay timing.
Write and Precharge command. This is a PRECHARGE command
issued too quickly after a previous
WRITE command to the same
bank. The minimum delay should
be WL (write latency) + TWR
(write recovery time) + BL/2 (burst
length / 2). The user should
determine why the commands are
too close together.

DDR2_SDRAM_TWTR_
VIOLATION

The command issued violates


the tWTR timing between a
Write and Read command.

The command just issued violates


Write to Read delay timing. This is
a READ command issued too
quickly after a previous WRITE
command to the same bank. The
minimum delay should be tWTR
(write to read turn-around-time) +
CAS latency + BL/2 (burst length /
2) 1. The user should determine
why the commands are too close
together.

DDR2_SDRAM_TWTW_
VIOLATION

The command issued violates


the tWTW timing between two
Write commands.

The command just issued violates


Write to Write delay timing. This is
a WRITE command issued too
quickly after a previous WRITE
command to the same bank. The
minimum delay should be 2 clocks
since the 4-n bursts cannot be
interrupted. The user should
determine why the commands are
too close together.

DDR2_SDRAM_TXARD_
VIOLATION

The command issued violates


the tXARD timing between
Exit ACTIVE POWER DOWN
with fast exit and a READ
command.

The fast exit latency from an


Active power down exit to a read
command is violated.

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Double Data Rate-II SDRAM (DDR-II SDRAM)


V2.0 Monitor

Table 7-14. DDR-II SDRAM 2.0 Monitor Bank Checks (cont.)


Check ID

Violation

Description

DDR2_SDRAM_TXARDS_
VIOLATION

The command issued violates


the tXARDS timing between
Exit ACTIVE POWER DOWN
with slow exit and a READ
command.

The slow exit latency from an


Active power down exit to a read
command is violated.

DDR2_SDRAM_TXP_VIOLATION

The command issued violates


the tXP timing between a
PRECHARGE POWER
DOWN exit and a NON-READ
command.

The latency from an Idle power


down exit to any nonread
command is violated.

DDR2_SDRAM_TXSNR_
VIOLATION

The command issued violates


the tXSNR timing required
between a Self Refresh Exit and
a No-Read command.

The command just issued violates


tXSNR (minimum time delay
between SELF REFRESH EXIT
command and any other nonREAD command) timing. A nonREAD command is issued too
quickly after the SELF REFRESH
EXIT command. The user should
determine why the commands are
too close together.

DDR2_SDRAM_TXSRD_
VIOLATION

The command issued violates


the tXSRD timing between a
Self Refresh Exit and a Read
command.

The READ command just issued


violates tXSRD (minimum time
delay between SELF REFRESH
EXIT command and a READ
command) timing. A READ
command is issued too quickly
after the SELF REFRESH EXIT
command. The user should
determine why the commands are
too close together.

DDR2_SDRAM_UNKNOWN_
STATE

The bank state machine went to


the UNKNOWN_STATE.

The command just issued has


caused the monitor state machine
to go to an UNKNOWN state. This
can be due to an illegal command.
You should look at the state
machine transitions and check why
it entered this state.

DDR2_SDRAM_WR_BURST_8B_
INTERRUPTED_AT_6B

A write burst of length 8 from a


bank is interrupted at a 6-bit
boundary by a command.

A write burst can only be


interrupted by another write, or
write with auto precharge enabled,
at a 4-bit burst boundary. Any other
form of write interrupt is not
allowed. This check fires whenever
a write burst is interrupted at a 6-bit
boundary (typically the third clock
after the write command).

DDR2_SDRAM_WRITE_TO_IDLE_
BANK

A write command is issued to


an idle bank.

The bank to which the WRITE


command was just issued is in
precharged idle condition. You
should determine why a WRITE
command was issued to an idle
bank without issuing an
ACTIVATE command.

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Double Data Rate-II SDRAM (DDR-II SDRAM)


V2.0 Monitor

Table 7-14. DDR-II SDRAM 2.0 Monitor Bank Checks (cont.)


Check ID

Violation

Description

DDR2_SDRAM_WRITEA_BURST_
8B_INTERRUPTED

A write burst of length 8 from a


bank with autoprecharge
enabled is interrupted by a
command.

A write burst of length 8 with auto


precharge enabled must not be
interrupted and should be allowed
to go through the automatic
sequence to precharge.

Monitor Corner Cases


Table 7-15 shows the corner cases captured by the DDR-II SDRAM 2.0 monitor for the
protocol.
Table 7-15. DDR-II SDRAM 2.0 Monitor Corner Cases
Corner Case

Description

Multiple Banks Activation

Number of times more than one bank is in activated state.

Precharge All Banks

Number of Precharge All commands issued to the DDR-II SDRAM.

CBR Refresh Commands

Number of times CBR Auto Refresh commands are issued.

Interleaved Bursts

Number of times Mode Register is programmed for Interleaved burst.

Sequential Bursts

Number of times Mode Register is programmed for Sequential burst.

Self Refresh Commands

Number of times Self Refresh command is issued.

Power Down Commands

Number of times Power Down command is issued.

NOP Commands

Number of times NOP command is issued.

Deselect Commands

Number of times Deselect command is issued.

Table 7-16 shows the corner cases captured by the DDR-II SDRAM 2.0 monitor for the DDR-II
SDRAM banks.
Table 7-16. DDR-II SDRAM 2.0 Bank Corner Cases
Corner Case

Description

Reads Without Precharge

Number of read without precharge commands issued to a bank.

Writes Without Precharge

Number of write without precharge commands issued to a bank.

Single Bank Precharges

Number of single bank Precharge commands issued to a bank.

Seamless Reads

Number of times a Read is immediately followed by another Read from the same
bank.

Seamless Writes

Number of times a Write is immediately followed by another Write to the same


bank.

Reads with Precharge

Number of times Read with Auto Precharge operation is performed to a bank.

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Double Data Rate-II SDRAM (DDR-II SDRAM)


V2.0 Monitor

Table 7-16. DDR-II SDRAM 2.0 Bank Corner Cases (cont.)


Corner Case

Description

Writes with Precharge

Number of times Write with Auto Precharge operation is performed to a bank.

Posted Reads

Number of times Posted Read cycles are exercised.

Posted Writes

Number of times Posted Write cycles are exercised.

Read after Read in Page

Number of times a read operation is issued to a page that is already opened for
read in the bank.

Read after Write in Page

Number of times a read operation is issued to a page that is already opened for
write in the bank.

Write after Read in Page

Number of times a write operation is issued to a page that is already opened for
read in the bank.

Write after Write in Page

Number of times a write operation is issued to a page that is already opened for
write in the bank.

Monitor Statistics
Table 7-17 lists the statistics collected for the protocol.
Table 7-17. DDR-II SDRAM 2.0 Monitor Statistics
Statistic

Description

Total Number of Memory


Accesses

Total number of data accesses to the DDR-II SDRAM for all banks.

Table 7-18 lists the statistics collected for each bank.


Table 7-18. DDR-II SDRAM 2.0 Bank Statistics

222

Statistic

Description

Total Number of Bank Accesses

Total number of times a bank is activated and data accesses


performed on the bank.

Questa Verification Library Monitors Data Book, v2010.2

Chapter 8
Gigabit Ethernet
Introduction
The Ethernet Standard ISO/IEC 8802-3 (CSMA/CD MAC) is a comprehensive International
Standard for Local Area Networks (LANs) employing CSMA/CD as the access method. This
International Standard encompasses several media types and techniques for signal rates from
1 Mb/s to 100 Mb/s.
Gigabit Ethernet couples an extended version of the ISO/IEC 8802-3 (CSMA/CD MAC) to a
family of 1000 Mb/s Physical Layers by extending the ISO/IEC 8802-3 MAC beyond 100 Mb/s
to 1000 Mb/s. The 10 Gigabit Ethernet further extends the IEEE 802.3 MAC beyond 1000 Mb/s
to 10 Gb/s. Similarly, 40G and 100G further extends the IEEE 802.3 MAC beyond 10Gb/s to
40Gb/s and 100Gb/s, respectively. The bit rate is faster and the bit times are shorter both in
proportion to the change in bandwidth. The minimum packet transmission time has been
reduced by a factor of ten. Achievable topologies for 10 Gb/s operation are comparable to those
found in 1000BASE-X Full Duplex mode and equivalent to those found in WAN applications.
The IEEE 802.3 and IEEE 802.3ae Standards define these interfaces as follows:

10/100M Ethernet Media Independent Interface (MII) between a MAC and PHY.

Gigabit Media Independent Interface (GMII) between a 1Gb/s MAC and PHY.

Ten Gigabit Media Independent Interface (XGMII) between a 10 Gb/s MAC and PHY.

40G or 100G Ethernet Media Independent Interface (XLGMII/CGMII) between a


40Gb/s or 100Gb/s MAC and PHY.

Gigabit Interface (TBI) between PCS and PMA (in the case of 1000BASE-X PHYs).

Ten Gigabit Attachment Unit Interface (XAUI) between two 10 Gigabit Extenders.

PCS to PMA interface (in case of 10GBASE-X PHYs).

Ten Gigabit Sixteen Bit Interface (XSBI) between PCS and PMA (in the case of
10GBASE-R PHYs).

Hundred Gigabit Interface (XLAUI) and Forty Gigabit interface (CAUI) (in the case of
100GBASE-R and 40GBASE-R PHYs).

Optional forward error correction (FEC) layer.

40G or 100G Auto negotiation Interface.

The QVL Gigabit Ethernet monitor is designed for checking these Gigabit Ethernet interfaces.
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Gigabit Ethernet
Reference Documentation

In addition to the above interfaces, QVL Gigabit Ethernet Monitor also checks Low pin count
Reduced Media Independent Interface (RMII) between a MAC and PHY and Reduced Gigabit
Media Independent Interface (RGMII) for 1G speed. Also, it supports Gigabit Serial Interface
(SGMII for 1G speed only) and Reduced Ten Bit Interface (RTBI) between PCS and PMA.

Reference Documentation
This version of the Gigabit Ethernet monitor is modeled from the requirements provided in the
following documents:

802.3 IEEE Standard for Information Technology, CSMA/CD access method and
physical layer specifications, 2002.

802.3ae Amendment: Media Access Control (MAC) Parameters and Physical Layers for
10 Gb/s Operation, 2002.

P802.3ba D2.1 draft Amendment: Media Access Control Parameters, Physical Layers
and Management Parameters for 40 Gb/s and 100 Gb/s Operation.

Reduced Gigabit Media Independence Interface (RGMII) version 2.0.

Supported Features
Gigabit Media Independent Interface (GMII)

Half Duplex and Full Duplex modes

Data frames Untagged, VLAN tagged, and Priority tagged frames

Control frames Pause and Reserved frames

Jumbo frames Untagged, VLAN tagged, and Priority tagged Jumbo frame

Inter-packet gap requirements

Data integrity (FCS)

Reduced Gigabit Media Independent Interface (RGMII)

224

Reduced pin count interface for 1G speed only.

Single clock reference sourced from MAC to PHY (or from an external source)

Half Duplex and Full Duplex modes

Data frames Untagged, VLAN tagged, and Priority tagged frames

Questa Verification Library Monitors Data Book, v2010.2

Gigabit Ethernet
Supported Features

Control frames Pause and Reserved frames

Jumbo frames Untagged, VLAN tagged, and Priority tagged Jumbo frame

Inter-packet gap requirements

Data integrity (FCS)

Media Independent Interface (MII)

Half Duplex and Full Duplex modes

Data frames Untagged, VLAN tagged, and Priority tagged frames

Control frames Pause and Reserved frames

Jumbo frames Untagged, VLAN tagged, and Priority tagged Jumbo frame

Inter-packet gap requirements

Data integrity (FCS)

Reduced Media Independent Interface (RMII)

Reduced pin count interface

Single clock reference sourced from MAC to PHY (or from an external source)

Half Duplex and Full Duplex modes

Data frames Untagged, VLAN tagged, and Priority tagged frames

Control frames Pause and Reserved frames

Jumbo frames Untagged, VLAN tagged, and Priority tagged Jumbo frame

Inter-packet gap requirements

Data integrity (FCS)

10 Gigabit Media Independent Interface (XGMII)

64-bit single data rate and 32-bit dual data rate modes

Data frames Untagged, VLAN tagged, and Priority tagged frames

Control frames Pause and Reserved frames

Jumbo frames Untagged, VLAN tagged, and Priority tagged Jumbo frame

Inter-packet gap requirements

Control character alignment requirements

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Gigabit Ethernet
Supported Features

Ordered sets Sequence and Idle

Data integrity (FCS)

40/100 Gigabit Media Independent Interface


(XLGMII/CGMII)

64-bit wide data path

Data frames Untagged, VLAN tagged, and Priority tagged frames

Control frames Pause and Reserved frames

Jumbo frames Untagged, VLAN tagged, and Priority tagged Jumbo frame

Inter-packet gap requirements

Control character alignment requirements

Ordered sets Sequence and Idle

Data integrity (FCS)

1000BASE-X Ten bit Interface (TBI) between PCS and


PMA

Support for 1000BASE-X technology

Half Duplex and Full Duplex modes

1-bit serial and 10-bit symbol modes

Data frames Untagged, VLAN tagged, and Priority tagged frames

Control frames Pause and Reserved frames

Jumbo frames Untagged, VLAN tagged, and Priority tagged Jumbo frame

Inter-packet gap requirements

Link synchronization

8b/10b decoding

Data integrity (FCS)

Reduced Ten bit Interface (RTBI) between PCS and PMA

226

Half Duplex and Full Duplex modes

Data frames Untagged, VLAN tagged, and Priority tagged frames

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Gigabit Ethernet
Supported Features

Control frames Pause and Reserved frames

Jumbo frames Untagged, VLAN tagged, and Priority tagged Jumbo frame

Inter-packet gap requirements

Link synchronization

8b/10b decoding

Data integrity (FCS)

10 Gigabit Attachment Unit Interface (XAUI)

4-bit serial (1-bit per lane) and 10-bit symbol (10-bits per lane) modes

Data frames Untagged, VLAN tagged, and Priority tagged frames

Control frames Pause and Reserved frames

Jumbo frames Untagged, VLAN tagged, and Priority tagged Jumbo frame

Inter-packet gap requirements

Lane synchronization

Lane-to-lane deskew, link alignment, and realignment

8b/10b decoding

Align, Sync, Skip, and Sequence ordered sets

Data integrity (FCS)

XAUI Limitation
The XAUI monitor is designed to support dual data rate (DDR) mode only. There is a
workaround if the user is using the single data rate (SDR) mode on the parallel interface. If your
serial interface uses a DDR mode, then use the monitors serial interface. To implement an SDR
workaround for the parallel interface, the user can hook-up a divide-by-2 clock to simulate the
DDR mode.

10 Gigabit Sixteen Bit Interface (XSBI)

Data blocks and Control blocks

Data frames Untagged, VLAN tagged, and Priority tagged frames

Control frames Pause and Reserved frames

Jumbo frames Untagged, VLAN tagged, and Priority tagged Jumbo frame

Inter-packet gap requirements

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Gigabit Ethernet
Supported Features

All defined block types

Descrambling

64b/66b decoding

Block synchronization

Data integrity (FCS)

40G/100G Attachment Unit Interface (XLAUI, CAUI)

1, 2, and 4 lanes for 40G and 1, 2, 4, 5, 10, and 20 lanes for 100G

Data frames Untagged, VLAN tagged, and Priority tagged frames

Control frames Pause and Reserved frames

Jumbo frames Untagged, VLAN tagged, and Priority tagged Jumbo frame

Inter-packet gap requirements

Lane lock state machine

Lane-to-lane bit level and symbol level automatic deskew

Link alignment state machine

Alignment marker support

All defined block types

Descrambling

64b/66b decoding

Data integrity (FCS)

40G or 100G Auto Negotiation Interface

228

Supports 1000BASE-KX, 10GBASE-KX4, 10GBASE-KR, 40GBASE-KR4,


40GBASE-CR4, and 100GBASE-CR10 technologies

Priority resolution function over above interfaces and FEC layer

Base page and next pages

DME timing

Arbitration state machine

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Gigabit Ethernet
Monitor Placement and Instantiation

Supported Control Characters

Start 8'hFB

Terminate 8'hFD

Error 8'hFE

Idle 8'h07

Sequence 8'h9C

Unsupported Features

10GBASE-W PHYs

MDIO Interface

Monitor Placement and Instantiation


The QVL Gigabit Ethernet monitor can be placed on either side of a GMII link to provide
interface checks. This can be on the Reconciliation Sublayer (MAC side) or the PHY side of the
link. The 10 Gigabit Ethernet monitor can be placed on the Reconciliation sublayer (RS) side or
the XGXS side of the XGMII interface to provide interface checks. Similarly, the monitor can
be placed on either of the two XGXSs of the XAUI interface. Likewise, the monitor can be
instantiated on the XSBI (10 Gigabit Sixteen Bit Interface) in case of the 10GBASE-R family of
PHYs. The 40/100 Gigabit Ethernet monitor can be placed on either side of a XLGMII/CGMII
link to provide interface checks.
In all of the above interfaces, the MAC_SIDE parameter in the monitor can be used to configure
the monitor instance to be on the interface closer to the MAC or closer to the medium. The
checks in the Gigabit Ethernet monitor can also be used as search targets and check constraints
while running formal analysis on the 1 Gb/s, 10 Gb/s, and 40/100 Gb/s ethernet components.
A typical Gigabit Ethernet setup is illustrated in Figure 8-1.

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Gigabit Ethernet
Monitor Connectivity

Figure 8-1. Gigabit Ethernet Monitor Implementation


XGMII
XGMII
QVL
Monitor

MAC/ RS

XAUI
QVL
Monitor

XAUI

XGXS
GMII
XGMII
MII
RMII
XLGMII
CGMII
QVL
Monitor

XGMII

XGMII
QVL
Monitor

XGMII
QVL
Monitor

XAUI
QVL
Monitor
XGXS

XGMII
QVL
Monitor
TBI
SGMII
XAUI
XSBI
XLAUI
CAUI
QVL
Monitor
GMII
XGMII
MII
RMII
XLGMII
CGMII
QVL
Monitor

GMII / MII / RMII / XGMII / XLGMII / CGMII

MAC

XAUI /
XSBI

TBI
SGMII
XAUI
XSBI
XLAUI
CAUI
QVL
Monitor

PMA

PHY

The QVL 10/100M Ethernet monitor can be placed on either side of a MII link to provide
interface checks. This can be on the Reconciliation Sublayer (MAC side) or the PHY side of the
link.
In the above interface, the MAC_SIDE parameter in the monitor can be used to configure the
monitor instance to be on the interface closer to the MAC or closer to the medium. The checks
in the 10/100M Ethernet monitor can also be used as search targets and check constraints while
running formal analysis on the 10/100M Ethernet components.

Monitor Connectivity
Connect the Gigabit Ethernet monitor pins as shown in Figure 8-2. Refer to pin-out Table 8-1
on page 232 through Table 8-10 on page 236 for the pin descriptions.

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Gigabit Ethernet
Monitor Connectivity

tx_clk
txd[63:0]
txc[7:0]

40/100G GIGABIT
ETHERNET
(XLGMII/CGMII)
Monitor

rx_clk
rxd[63:0]
rxc[7:0]
areset
reset
an_clk
tx_clk
rx_clk
tx_data[19:0]
rx_data[19:0]

Auto-Negotiation
Monitor

SOURCE

sl_clk
sl0_p
sl1_p
sl2_p
sl3_p

10 GIGABIT
ETHERNET
(XAUI) Monitor

dl_clk
dl0_p
dl1_p
dl2_p
dl3_p

areset
reset
TBI
Monitor

tx_clk
txd
rx_clk
rxd

areset
reset
txc
td[3:0]
tx_ctl

RTBI
Monitor

rxc
rd[3:0]
rx_ctl

areset
reset
tx_clk
txd

DESTINATION

TRANSMIT
RECEIVE

areset
reset

areset
reset

10/100M
ETHERNET
(RMII) Monitor

10 GIGABIT
ETHERNET
(XSBI) Monitor

rx_clk
rxd
bypass_descramble

Questa Verification Library Monitors Data Book, v2010.2

TRANSMIT

rx_clk
rxd
rxc

TRANSMIT

10 GIGABIT
ETHERNET
(XGMII) Monitor

10/100M
ETHERNET
(MII) Monitor

areset
reset
ref_clk
txd[1:0]
tx_en
txd[1:0]
crs_dv
rx_er

RECEIVE

tx_clk
txd
txc

areset
reset
tx_clk
txd[3:0]
tx_en
tx_er
rx_clk
rxd[3:0]
rx_dv
rx_er
col
crs

RECEIVE TRANSMIT

areset
reset

TRANSMIT

1 GIGABIT
ETHERNET
(GMII) Monitor

RECEIVE

areset
reset
tx_clk
txd[7:0]
tx_en
tx_er
rx_clk
rxd[7:0]
rx_dv
rx_er
col
crs

RECEIVE

RECEIVE

TRANSMIT RECEIVE

TRANSMIT

RECEIVE

TRANSMIT

RECEIVE TRANSMIT

RECEIVE

TRANSMIT

Figure 8-2. Gigabit Ethernet Monitor Pin-Out Diagram

areset
reset
tx_clk
tx_lane[PHYSICAL_
LANE_COUNT-1:0]
rx_clk
rx_lane[PHYSICAL_
LANE_COUNT-1:0]
caui_interface
fec_enable

40/100M GIGABIT
ETHERNET
(XLAUI/CAUI)
Monitor

231

Gigabit Ethernet
Monitor Connectivity

Table 8-1. GMII Monitor Pin Descriptions


Port

Description

areset

Asynchronous reset signal (not part of standard I/F signals).

col

Collision detect.

crs

Carrier sense.

half_duplex

Dynamic configuration to switch between half_duplex and full_duplex mode.


Monitor considers a half duplex mode when the value on this pin is 1 and
consider a full duplex mode when the value is 0.

reset

Synchronous reset signal (not part of standard I/F signals).

rx_clk

Receive clock signal (used to sample all Rx interface signals).

rx_dv

Receive data valid.

rx_er

Receive error.

rxd[7:0]

Receive data (8-bits).

tx_clk

Transmit clock signal (used to sample all Tx interface signals).

tx_en

Transmit enable.

tx_er

Transmit error.

txd[7:0]

Transmit data (8-bits).

Table 8-2. RGMII Monitor Pin Descriptions

232

Port

Description

areset

Asynchronous reset signal (not part of standard I/F signals).

half_duplex

Dynamic configuration to switch between half_duplex and full_duplex mode.


Monitor considers a half duplex mode when the value on this pin is 1 and
consider a full duplex mode when the value is 0.

reset

Synchronous reset signal (not part of standard I/F signals).

rxc

Receive clock signal (used to sample all Rx interface signals).

rxd[3:0]

Receive data (4-bits).

rx_ctl

Receive Control.

txc

Transmit clock signal (used to sample all Tx interface signals).

tx_ctl

Transmit Control.

txd[3:0]

Transmit data (4-bits).

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Gigabit Ethernet
Monitor Connectivity

Table 8-3. MII Monitor Pin Descriptions


Port

Description

areset

Asynchronous reset signal (not part of standard I/F signals).

col

Collision detect.

crs

Carrier sense.

half_duplex

Dynamic configuration to switch between half_duplex and full_duplex mode.


Monitor considers a half duplex mode when the value on this pin is 1 and
consider a full duplex mode when the value is 0.

reset

Synchronous reset signal (not part of standard I/F signals).

rx_clk

Receive clock signal (used to sample all Rx interface signals).

rx_dv

Receive data valid.

rx_er

Receive error.

rxd[3:0]

Receive data (4-bits).

tx_clk

Transmit clock signal (used to sample all Tx interface signals).

tx_en

Transmit enable.

tx_er

Transmit error.

txd[3:0]

Transmit data (4-bits).

Table 8-4. RMII Monitor Pin Descriptions


Port

Description

areset

Asynchronous reset signal (not part of standard I/F signals).

crs_dv

Carrier Sense/Receive Data Valid.

half_duplex

Dynamic configuration to switch between half_duplex and full_duplex


mode. Monitor considers a half duplex mode when the value on this pin is 1
and consider a full duplex mode when the value is 0.

reset

Synchronous reset signal (not part of standard I/F signals).

ref_clk

Synchronous clock reference for receive and transmit interface.

rxd[1:0]

Receive data (2-bits).

rx_er

Receive Error.

txd[1:0]

Transmit data (2-bits).

tx_en

Transmit enable.

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Gigabit Ethernet
Monitor Connectivity

Table 8-5. XGMII Monitor Pin Descriptions


Port

Description

areset

Asynchronous reset signal (not part of standard I/F signals).

reset

Synchronous reset signal (not part of standard I/F signals).

rx_clk

Receive clock signal (used to sample all Rx interface signals).

rxc[3:0] / [7:0]

Receive control lines (1 line for each lane (byte) of RXD, 4 bits in case of
DDR mode and 8 bits in case of SDR mode).

rxd[31:0] / [63:0]

Receive data (4 lanes of 1 byte each in case of DDR 32-bit mode and 8 lanes
of 1 byte each in case of SDR 64-bit mode).

tx_clk

Transmit clock signal (used to sample all Tx interface signals).

txc[3:0] / [7:0]

Transmit control lines (1 line for each lane (byte) of TXD, 4 bits in case of
DDR mode and 8 bits in case of SDR mode).

txd[31:0] / [63:0]

Transmit data (4 lanes of 1 byte each in case of DDR 32-bit mode and 8 lanes
of 1 byte each in case of SDR 64-bit mode).

Table 8-6. XLGMII/CGMII Monitor Pin Descriptions


Port

Description

areset

Asynchronous reset signal (not part of standard I/F signals).

reset

Synchronous reset signal (not part of standard I/F signals).

tx_clk

Transmit clock signal (used to sample all Tx interface signals).

txd[63:0]

Transmit data (8 lanes of 1 byte each).

txc[7:0]

Transmit control lines (1 line for each lane (byte) of TXD).

rx_clk

Receive clock signal (used to sample all Rx interface signals).

rxd[63:0]

Receive data (8 lanes of 1 byte each).

rxc[7:0]

Receive control lines (1 line for each lane (byte) of RXD).

Table 8-7. 1000BASE-X Ten bit Interface Monitor Pin Descriptions

234

Port

Description

areset

Asynchronous reset signal (not part of standard I/F signals).

half_duplex

Dynamic configuration to switch between half_duplex and full_duplex mode.


Monitor considers a half duplex mode when the value on this pin is 1 and consider a
full duplex mode when the value is 0.

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Gigabit Ethernet
Monitor Connectivity

Table 8-7. 1000BASE-X Ten bit Interface Monitor Pin Descriptions (cont.)
Port

Description

reset

Synchronous reset signal (not part of standard I/F signals).

tx_clk

Transmit interface clock.

txd

Transmit data (10-bit or 1-bit).

rx_clk

Receive interface clock.

rxd

Receive data (10-bit or 1-bit).

Table 8-8. Reduced Ten bit Interface Monitor Pin Descriptions


Port

Description

areset

Asynchronous reset signal (not part of standard I/F signals).

half_duplex

Dynamic configuration to switch between half_duplex and full_duplex mode. Monitor


considers a half duplex mode when the value on this pin is 1 and consider a full duplex
mode when the value is 0.

reset

Synchronous reset signal (not part of standard I/F signals).

txc

Transmit interface clock.

td[3:0]

Transmit data (4-bit).

tx_ctl

Transmit control.

rxc

Receive interface clock.

rd[3:0]

Receive data (4-bit).

rx_ctl

Receive control,

Table 8-9. XAUI Monitor Pin Descriptions


Port

Description

areset

Asynchronous reset signal (not part of standard I/F signals).

dl0_p

Destination lane 0.

dl1_p

Destination lane 1.

dl2_p

Destination lane 2.

dl3_p

Destination lane 3.

dl_clk

Destination lanes clock (used to sample all destination lanes).

reset

Synchronous reset signal (not part of standard I/F signals).

sl0_p

Source lane 0.

sl1_p

Source lane 1.

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Table 8-9. XAUI Monitor Pin Descriptions (cont.)


Port

Description

sl2_p

Source lane 2.

sl3_p

Source lane 3.

sl_clk

Source lanes clock (used to sample all source lanes).

Note that if SYMBOL_MODE = 1, then sl0_p, sl1_p, sl2_p, sl3_p, dl0_p, dl1_p, dl2_p, and dl3_p are 10-bits
wide; otherwise 1-bit wide.

Table 8-10. XSBI Monitor Pin Descriptions


Port

Description

areset

Asynchronous reset signal (not part of standard I/F signals).

bypass_descramble

Enables bypass of descrambler.

reset

Synchronous reset signal (not part of standard I/F signals).

rx_clk

Receive clock (used to sample all Rx interface signals).

rxd

Receive data lines.

tx_clk

Transmit clock (used to sample all Tx interface signals).

txd

Transmit data lines.

Note that if SYMBOL_MODE = 1, then both rxd and txd are 16-bits wide; otherwise 1-bit wide.

Table 8-11. XLAUI/CAUI Monitor Pin Descriptions


Port

Description

areset

Asynchronous reset signal (not part of standard I/F signals).

reset

Synchronous reset signal (not part of standard I/F signals).

rx_clk

Receive clock (used to sample all Rx interface signals).

rx_lanes[PHYSICAL_LANE_COUNT-1:0]

Receive data lines.

tx_clk

Transmit clock (used to sample all Tx interface signals).

tx_lanes[PHYSICAL_LANE_COUNT-1:0]

Transmit data lines.

caui_interface

Enables 100G mode (not part of standard I/F signals).

fec_enable

Enables optional FEC layer (not part of standard I/F signals).

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Table 8-12. 40/100G Auto-Negotiation Monitor Pin Descriptions


Port

Description

areset

Asynchronous reset signal (not part of standard I/F signals).

reset

Synchronous reset signal (not part of standard I/F signals).

an_clk

Sampling clock (not part of standard I/F signals). It is used to sample DME
encoded data.

rx_clk

Receive clock (used to sample all Rx interface signals).

rx_data[19:0]

Receive data lines.

tx_clk

Transmit clock (used to sample all Tx interface signals).

tx_data[19:0]

Transmit data lines.

Notes:
1. In 64-bit SDR mode of operation of the XGMII monitor, one clock of data in the DDR
mode comprising of two columns are mapped to one column of twice the length. If say
the two columns of data in the 32-bit (DDR) mode are denoted as {d00, d01, d02,
d03} and {d10, d11, d12, d13} where d00 and d10 are the lane0 data
respectively, then the corresponding 64-bit (SDR) data is {d00, d01, d02, d03,
d10, d11, d12, d13}, where d00 is lane0 data.
2. In Full Duplex mode of operation, the CRS (carrier sense) and COL (collision detect)
signals have no meaning and can be left unconnected.
3. In TBI/RTBI/XAUI mode, the monitor only takes in the lane_p component of the
balanced differential pair {lane_p, lane_n}.
4. If {a,b,c,d,e,i,f,g,h,j} is the 10-bit encoded data, then the TBI/RTBI/XAUI
assumes the first bit received to be a and the last bit to be j in the serial mode of
operation, and the most significant bit as j and the least significant bit as a in the 10bit symbol mode of operation.
5. In XLAUI/CAUI mode, caui_interface and fec_enable are used when auto
negotiation mode is enabled to dynamically change the values. Otherwise, they are
ignored and can be tied to any value.

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Monitor Parameters
The parameters shown in the following tables configure the Gigabit Ethernet monitor.
Table 8-13. GMII Monitor Parameters
Order

Parameter

Default

Description

1.

Constraints_Mode

Set this parameter to 1 if the checks in the monitor are to


be used as constraints for formal analysis.

2.

MAC_SIDE

Set this parameter to 0 if the monitor is instantiated on the


PHY side of an interface. By default, the monitor is
instantiated on the MAC side or the Reconciliation
Sublayer side of the interface.

3.

JUMBO_FRAME_DATA_
LENGTH

9216

Set this parameter to the desired length of Jumbo frames.


The default length of Jumbo frames is taken to be 9K
bytes (9216 bytes). Note that the upper limit for the
Jumbo frame size is 12K bytes, since this is the maximum
possible payload for 32-bit CRC.

4.

RESERVED_VALUE_
CHECK_ENABLE

By default, the monitor checks for any reserved values.


Set this parameter to 0 to disable checking of reserved
fields.

5.

MAC_MIN_TAGGED_
FRAME_SIZE_68

Set this parameter to 1 if the minimum size of tagged


frame is 68. In this case, QTag Prefix is not included in
the MAC client data. Therefore, the minimum tagged
frame size is 68 after auto-padding.

6.

RESERVED_CONTROL_
FRAME_SUPPORTED

Set this parameter to 1 if Reserved Control Frame is


supported.

7.

SLOT_TIME

512

Set this parameter to value of the Slot Time for Half


Duplex mode.

8.

JAM_SIZE

32

Set this parameter to the value of JAM Size for HAlf


Duplex mode.

9.

BURST_LIMIT

65536

Set this parameter to the total burst limit. By default, it is


65536 for Half Duplex mode.

Notes:
1. The parameters must be specified in the above order.
2. The HALF_DUPLEX parameter is deprecated; instead a pin is added for dynamic switch between
half duplex and full duplex modes. See Table 8-1 on page 232 for a detailed description.

Table 8-14. RGMII Monitor Parameters


Order

Parameter

Default

Description

1.

Constraints_Mode

Set this parameter to 1 if the checks in the monitor are to


be used as constraints for formal analysis.

2.

MAC_SIDE

Set this parameter to 0 if the monitor is instantiated on the


PHY side of an interface. By default, the monitor is
instantiated on the MAC side or the Reconciliation
Sublayer side of the interface.

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Table 8-14. RGMII Monitor Parameters (cont.)


Order

Parameter

Default

Description

3.

JUMBO_FRAME_DATA_
LENGTH

9216

Set this parameter to the desired length of Jumbo frames.


The default length of Jumbo frames is taken to be 9K
bytes (9216 bytes). Note that the upper limit for the
Jumbo frame size is 12K bytes, since this is the maximum
possible payload for 32-bit CRC.

4.

RESERVED_VALUE_
CHECK_ENABLE

By default, the monitor checks for any reserved values.


Set this parameter to 0 to disable checking of reserved
fields.

5.

MAC_MIN_TAGGED_
FRAME_SIZE_68

Set this parameter to 1 if the minimum size of tagged


frame is 68. In this case, QTag Prefix is not included in
the MAC client data. Therefore, the minimum tagged
frame size is 68 after auto-padding.

6.

RESERVED_CONTROL_
FRAME_SUPPORTED

Set this parameter to 1 if Reserved Control Frame is


supported.

7.

SLOT_TIME

512

Set this parameter to value of the Slot Time for Half


Duplex mode.

8.

JAM_SIZE

32

Set this parameter to the value of JAM Size for HAlf


Duplex mode.

9.

BURST_LIMIT

65536

Set this parameter to the total burst limit. By default, it is


65536 for Half Duplex mode.

10.

DUPLEX_MODE_
INDICATION

Set this parameter to 1 if optional duplex mode indication


is enabled.

11.

CLK_SPEED_
INDICATION

Set this parameter to 1if optional Clock speed indication


is enabled.

Notes:
1. The parameters must be specified in the above order.
2. The HALF_DUPLEX parameter is deprecated; instead a pin is added for dynamic switch between
half duplex and full duplex modes. See Table 8-2 on page 232 for a detailed description.

Table 8-15. MII Monitor Parameters


Order

Parameter

Default

Description

1.

Constraints_Mode

Set this parameter to 1 if the checks in the monitor are to


be used as constraints for formal analysis.

2.

MAC_SIDE

Set this parameter to 0 if the monitor is instantiated on


the PHY side of an interface. By default, the monitor is
instantiated on the MAC side or the Reconciliation
Sublayer side of the interface.

3.

JUMBO_FRAME_DATA_
LENGTH

9216

Set this parameter to the desired length of Jumbo frames.


The default length of Jumbo frames is taken to be 9K
bytes (9216 bytes).
Note that the upper limit for the Jumbo frame size is 12K
bytes, since this is the maximum possible payload for
32-bit CRC.

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Table 8-15. MII Monitor Parameters (cont.)


Order

Parameter

Default

Description

4.

RESERVED_VALUE_
CHECK_ENABLE

By default, the monitor checks for any reserved values.


Set this parameter to 0 to disable checking of reserved
fields.

5.

MAC_MIN_TAGGED_
FRAME_SIZE_68

Set this parameter to 1 if the minimum size of tagged


frame is 68. In this case, QTag Prefix is not included in
the MAC client data. Therefore, the minimum tagged
frame size is 68 after auto-padding.

6.

RESERVED_CONTROL_
FRAME_SUPPORTED

Set this parameter to 1 if Reserved Control Frame is


supported.

7.

SLOT_TIME

64

Set this parameter to value of the Slot Time for Half


Duplex mode.

8.

JAM_SIZE

32

Set this parameter to the value of JAM Size for HAlf


Duplex mode.

Notes:
1. The parameters must be specified in the above order.
2. The HALF_DUPLEX parameter is deprecated; instead a pin is added for dynamic switch between
half duplex and full duplex modes. See Table 8-3 on page 233 for a detailed description.

Table 8-16. RMII Monitor Parameters


Order Parameter

Default

Description

1.

Constraints_Mode

Set this parameter to 1 if the checks in the monitor are to


be used as constraints for formal analysis.

2.

MAC_SIDE

Set this parameter to 0 if the monitor is instantiated on


the PHY side of an interface. By default, the monitor is
instantiated on the MAC side or the Reconciliation
Sublayer side of the interface.

3.

JUMBO_FRAME_DATA_
LENGTH

9216

Set this parameter to the desired length of Jumbo frames.


The default length of Jumbo frames is taken to be 9K
bytes (9216 bytes).
Note that the upper limit for the Jumbo frame size is 12K
bytes, since this is the maximum possible payload for
32-bit CRC.

4.

RESERVED_VALUE_
CHECK_ENABLE

By default, the monitor checks for any reserved values.


Set this parameter to 0 to disable checking of reserved
fields.

5.

MAC_MIN_TAGGED_
FRAME_SIZE_68

Set this parameter to 1 if the minimum size of tagged


frame is 68. In this case, QTag Prefix is not included in
the MAC client data. Therefore, the minimum tagged
frame size is 68 after auto-padding.

6.

RESERVED_CONTROL_
FRAME_SUPPORTED

Set this parameter to 1 if Reserved Control Frame is


supported.

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Table 8-16. RMII Monitor Parameters (cont.)


Order Parameter

Default

Description

Notes:
1. The parameters must be specified in the above order.
2. The HALF_DUPLEX parameter is deprecated; instead a pin is added for dynamic switch between
half duplex and full duplex modes. See Table 8-1 on page 232 for a detailed description.

Table 8-17. XGMII Monitor Parameters


Order

Parameter

Default

Description

1.

Constraints_Mode

Set this parameter to 1 if the checks in the monitor are


to be used as constraints for formal analysis.

2.

MAC_SIDE

Set this parameter to 0 if the monitor is instantiated on


the PHY side of an interface. By default, the monitor
is instantiated on the MAC side or the Reconciliation
Sublayer side of the interface.

3.

JUMBO_FRAME_DATA_
LENGTH

9216

Set this parameter to the desired length of Jumbo


frames. The default length of Jumbo frames is taken to
be 9K bytes (9216 bytes).
Note that the upper limit for Jumbo frame size is 12K
bytes, since this is the maximum possible payload for
32-bit CRC.

4.

RESERVED_VALUE_
CHECK_ENABLE

By default, the monitor checks for any reserved


values. Set this parameter to 0 to disable checking of
reserved fields.

5.

DDR

Set this parameter to 0 to indicate a single-edge


XGMII with a 64-bit data bus instead of the standard
dual-edge 32-bit data interface. The default value of 1
indicates a dual edge 32-bit data XGMII interface.

6.

DIC_SUPPORTED

Set this parameter to 1 if Deficient Idle Count (DIC) is


supported. In this case, the minimum interframe gap
requirement is 72-bits instead of 96-bits.

7.

MAC_MIN_TAGGED_
FRAME_SIZE_68

Set this parameter to 1 if the minimum size of tagged


frame is 68. In this case, QTag Prefix is not included
in the MAC client data. Therefore, the minimum
tagged frame size is 68 after auto-padding.

8.

RESERVED_CONTROL_
FRAME_SUPPORTED

Set this parameter to 1 if Reserved Control Frame is


supported.

The parameters must be specified in the above order.

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Table 8-18. XLGMII/CGMII Monitor Parameters


Order

Parameter

Default Description

1.

Constraints_Mode

Set this parameter to 1 if the checks in the monitor are


to be used as constraints for formal analysis.

2.

MAC_SIDE

Set this parameter to 0 if the monitor is instantiated on


the PHY side of an interface. By default, the monitor
is instantiated on the MAC side or the Reconciliation
Sublayer side of the interface.

3.

JUMBO_FRAME_DATA_
LENGTH

9216

Set this parameter to the desired length of Jumbo


frames. The default length of Jumbo frames is taken to
be 9K bytes (9216 bytes).
Note that the upper limit for Jumbo frame size is 12K
bytes, since this is the maximum possible payload for
32-bit CRC.

4.

RESERVED_VALUE_
CHECK_ENABLE

By default, the monitor checks for any reserved


values. Set this parameter to 0 to disable checking of
reserved fields.

5.

DIC_SUPPORTED

Set this parameter to 1 if Deficient Idle Count (DIC) is


supported. In this case, the minimum interframe gap
requirement is 40-bits instead of 96-bits.

6.

MAC_MIN_TAGGED_
FRAME_SIZE_68

Set this parameter to 1 if the minimum size of tagged


frame is 68. In this case, QTag Prefix is not included
in the MAC client data. Therefore, the minimum
tagged frame size is 68 after auto-padding.

7.

RESERVED_CONTROL_
FRAME_SUPPORTED

Set this parameter to 1 if Reserved Control Frame is


supported.

The parameters must be specified in the above order.

Table 8-19. TBI Monitor Parameters


Order

Parameter

Default

Description

1.

Constraints_Mode

Set this parameter to 1 if the checks in the monitor are to


be used as constraints for formal analysis.

2.

MAC_SIDE

Set this parameter to 0 if the monitor is instantiated on the


PHY side of an interface. By default, the monitor is
instantiated on the MAC side or the Reconciliation
Sublayer side of the interface.

3.

SYMBOL_MODE

Set this parameter to 1 if the monitor is instantiated on a


parallel 10-bit (symbol) interface. The default value of 0
indicates a serial interface.

4.

JUMBO_FRAME_DATA_
LENGTH

9216

Set this parameter to the desired length of Jumbo frames.


The default length of Jumbo frames is taken to be 9K
bytes (9216 bytes). Note that the upper limit for the
Jumbo frame size is 12K bytes, since this is the maximum
possible payload for 32-bit CRC.

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Table 8-19. TBI Monitor Parameters (cont.)


Order

Parameter

Default

Description

5.

RESERVED_VALUE_
CHECK_ENABLE

By default, the monitor checks for any reserved values.


Set this parameter to 0 to disable checking of reserved
fields.

6.

MAC_MIN_TAGGED_
FRAME_SIZE_68

Set this parameter to 1 if the minimum size of tagged


frame is 68. In this case, QTag Prefix is not included in
the MAC client data. Therefore, the minimum tagged
frame size is 68 after auto-padding.

7.

RESERVED_CONTROL_
FRAME_SUPPORTED

Set this parameter to 1 if Reserved Control Frame is


supported.

8.

SLOT_TIME

512

Set this parameter to value of the Slot Time for Half


Duplex mode.

9.

JAM_SIZE

32

Set this parameter to the value of JAM Size for HAlf


Duplex mode.

10.

BURST_LIMIT

65536

Set this parameter to the total burst limit. By default, it is


65536 for Half Duplex mode.

Notes:
1. The parameters must be specified in the above order.
2. The HALF_DUPLEX parameter is deprecated; instead a pin is added for dynamic switch between
half duplex and full duplex modes. See Table 8-7 on page 234 for a detailed description.

Table 8-20. RTBI Monitor Parameters


Order

Parameter

Default

Description

1.

Constraints_Mode

Set this parameter to 1 if the checks in the monitor are to


be used as constraints for formal analysis.

2.

MAC_SIDE

Set this parameter to 0 if the monitor is instantiated on the


PHY side of an interface. By default, the monitor is
instantiated on the MAC side or the Reconciliation
Sublayer side of the interface.

3.

JUMBO_FRAME_DATA_
LENGTH

9216

Set this parameter to the desired length of Jumbo frames.


The default length of Jumbo frames is taken to be 9K
bytes (9216 bytes). Note that the upper limit for the
Jumbo frame size is 12K bytes, since this is the maximum
possible payload for 32-bit CRC.

4.

RESERVED_VALUE_
CHECK_ENABLE

By default, the monitor checks for any reserved values.


Set this parameter to 0 to disable checking of reserved
fields.

5.

MAC_MIN_TAGGED_
FRAME_SIZE_68

Set this parameter to 1 if the minimum size of tagged


frame is 68. In this case, QTag Prefix is not included in
the MAC client data. Therefore, the minimum tagged
frame size is 68 after auto-padding.

6.

RESERVED_CONTROL_
FRAME_SUPPORTED

Set this parameter to 1 if Reserved Control Frame is


supported.

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Table 8-20. RTBI Monitor Parameters (cont.)


Order

Parameter

Default

Description

7.

SLOT_TIME

512

Set this parameter to value of the Slot Time for Half


Duplex mode.

8.

JAM_SIZE

32

Set this parameter to the value of JAM Size for HAlf


Duplex mode.

9.

BURST_LIMIT

65536

Set this parameter to the total burst limit. By default, it is


65536 for Half Duplex mode.

Notes:
1. The parameters must be specified in the above order.
2. The HALF_DUPLEX parameter is deprecated; instead a pin is added for dynamic switch between
half duplex and full duplex modes. See Table 8-8 on page 235 for a detailed description.

Table 8-21. XAUI Monitor Parameters

244

Order

Parameter

Default

Default

1.

Constraints_Mode

Set this parameter to 1 if the checks in the monitor are


to be used as constraints for formal analysis.

2.

MAC_SIDE

Set this parameter to 0 if the monitor is instantiated on


the PHY side of an interface. By default, the monitor
is instantiated on the MAC side or the Reconciliation
Sublayer side of the interface.

3.

JUMBO_FRAME_DATA_
LENGTH

9216

Set this parameter to the desired length of Jumbo


frames. The default length of Jumbo frames is taken to
be 9K bytes (9216 bytes).
Note that the upper limit for the Jumbo frame size is
12K bytes, since this is the maximum possible
payload for 32-bit CRC.

4.

RESERVED_VALUE_
CHECK_ENABLE

By default, the monitor checks for any reserved


values. Set this parameter to 0 to disable checking of
reserved fields.

5.

SYMBOL_MODE

Set this parameter to 1 if the monitor is instantiated on


a parallel 10-bit (symbol) interface. The default value
of 0 indicates a serial interface.

6.

BYPASS_DESKEW

Set this parameter to 1 to bypass the deskew logic.


This can be done when the input data stream is
guaranteed to be free of skew between lanes. The
default value of 1 attempts to deskew the lanes before
processing the data further.

7.

DIC_SUPPORTED

Set this parameter to 1 if Deficient Idle Count (DIC) is


supported. In this case, the minimum interframe gap
requirement is 72-bits instead of 96-bits.

8.

MAC_MIN_TAGGED_
FRAME_SIZE_68

Set this parameter to 1 if the minimum size of tagged


frame is 68. In this case, QTag Prefix is not included
in the MAC client data. Therefore, the minimum
tagged frame size is 68 after auto-padding.

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Table 8-21. XAUI Monitor Parameters (cont.)


Order

Parameter

Default

Default

9.

RESERVED_CONTROL_
FRAME_SUPPORTED

Set this parameter to 1 if Reserved Control Frame is


supported.

The parameters must be specified in the above order.

Table 8-22. XSBI Monitor Parameters


Order

Parameter

Default

Description

1.

Constraints_Mode

Set this parameter to 1 if the checks in the monitor


are to be used as constraints for formal analysis.

2.

MAC_SIDE

Set this parameter to 0 if the monitor is


instantiated on the PHY side of an interface. By
default, the monitor is instantiated on the MAC
side or the Reconciliation Sublayer side of the
interface.

3.

JUMBO_FRAME_DATA_LENGTH 9216

Set this parameter to the desired length of Jumbo


frames. The default length of Jumbo frames is
taken to be 9K bytes (9216 bytes).
Note that the upper limit for the Jumbo frame size
is 12K bytes, since this is the maximum possible
payload for 32-bit CRC.

4.

RESERVED_VALUE_CHECK_
ENABLE

By default, the monitor checks for any reserved


values. Set this parameter to 0 to disable checking
of reserved fields.

5.

BYPASS_BLOCK_SYNC

Set this parameter to 0 to enable the block


synchronization process that will determine block
boundaries and obtain synchronization. The
default value of 1 will bypass the block
synchronization process.

6.

DIC_SUPPORTED

Set this parameter to 1 if Deficient Idle Count


(DIC) is supported. In this case, the minimum
interframe gap requirement is 72-bits instead of
96-bits.

7.

MAC_MIN_TAGGED_FRAME_
SIZE_68

Set this parameter to 1 if the minimum size of


tagged frame is 68. In this case, QTag Prefix is not
included in the MAC client data. Therefore, the
minimum tagged frame size is 68 after autopadding.

8.

RESERVED_CONTROL_FRAME_
SUPPORTED

Set this parameter to 1 if Reserved Control Frame


is supported.

9.

SYMBOL_MODE

Parameter SYMBOL_MODE = 1 indicates a


parallel (symbol) 16-bit interface. The default of 1
implies a parallel interface. A value 0 configures
the serial interface.

The parameters must be specified in the above order.

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Table 8-23. XLAUI/CAUI Monitor Parameters


Order Parameter

Default Description

1.

Constraints_Mode

Set this parameter to 1 if the checks in the


monitor are to be used as constraints for formal
analysis.

2.

MAC_SIDE

Set this parameter to 0 if the monitor is


instantiated on the PHY side of an interface.
By default, the monitor is instantiated on the
MAC side or the Reconciliation Sublayer side
of the interface.

3.

JUMBO_FRAME_DATA_LENGTH

9216

Set this parameter to the desired length of


Jumbo frames. The default length of Jumbo
frames is taken to be 9K bytes (9216 bytes).
Note that the upper limit for the Jumbo frame
size is 12K bytes, since this is the maximum
possible payload for 32-bit CRC.

4.

RESERVED_VALUE_CHECK_ENABLE

By default, the monitor checks for any


reserved values. Set this parameter to 0 to
disable checking of reserved fields.

5.

CAUI_INTERFACE

Set this parameter to 1 for interface type to


40G (XLAUI) and 0 for 100G (CAUI). This
parameter is ignored if AUTONEG_MODE is
set to 1.

6.

FEC_ENABLE

Set this parameter to 1 for fec layer support.


This parameter is ignored if
AUTONEG_MODE is set to 1.

7.

AM_COUNTER_16383

800

This parameter defines the number of blocks


between two alignment marker.

8.

AM_LOCK_ON_FIRST_AM

Set this parameter to 1 to have AM lock


achieved on detection of first alignment
marker. Otherwise, lock is achieved based on
state machine.

9.

AUTONEG_MODE

Set this parameter to 1 to configure autoneg


mode. If this parameter is set to 1, then
CAUI_INTERFACE and FEC_ENABLE
parameters are ignored and caui_interface and
fec_enable wires will be used to determine
interface type.

10.

PHYSICAL_LANE_COUNT

Sets the physical lane count. Valid values are


XLAUI: 1, 2, and 4.
CAUI: 1, 2, 4, 5, 10, and 20

11.

DIC_SUPPORTED

Set this parameter to 1 if Deficient Idle Count


(DIC) is supported. In this case, the minimum
interframe gap requirement is 72-bits instead
of 96-bits.

12.

MAC_MIN_TAGGED_FRAME_SIZE_68

Set this parameter to 1 if the minimum size of


tagged frame is 68. In this case, QTag Prefix is
not included in the MAC client data.
Therefore, the minimum tagged frame size is
68 after auto-padding.

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Table 8-23. XLAUI/CAUI Monitor Parameters (cont.)


Order Parameter

Default Description

13.

RESERVED_CONTROL_FRAME_
SUPPORTED

Set this parameter to 1 if Reserved Control


Frame is supported.

The parameters must be specified in the above order.

Table 8-24. 40/100G Auto-Negotiation Monitor Parameters


Order Parameter

Default

Description

1.

Constraints_Mode

Set this parameter to 1 if the checks in the


monitor are to be used as constraints for
formal analysis.

2.

MAC_SIDE

Set this parameter to 0 if the monitor is


instantiated on the PHY side of an interface.
By default, the monitor is instantiated on the
MAC side or the Reconciliation Sublayer
side of the interface.

3.

CLK_TO_CLK_MIN_CYCLES

62

Holds the minimum number of an_clk


(sampling clock) posedge that must be
sampled for considering valid clock
transition to clock transition (and hence a
valid Data bit 0). A default value 62
corresponds to minimum T2 value 6.2 ns
assuming an_clk to be of period 0.1 ns.

4.

CLK_TO_CLK_MAX_CYCLES

66

Holds the maximum number of an_clk


posedge that can be sampled for considering
valid clock transition to clock transition
(and hence a valid Data bit 0). A default
value 66 corresponds to maximum T2 value
6.6 ns assuming an_clk to be of period 0.1
ns.

5.

CLK_TO_DATA_MIN_CYCLES

30

Holds the minimum number of an_clk


(sampling clock) posedge that must be
sampled for considering valid clock
transition to data transition (and hence a
valid Data bit 1). A default value 30
corresponds to minimum T3 value 3.0 ns
assuming an_clk to be of period 0.1 ns.

6.

CLK_TO_DATA_MAX_CYCLES

34

Holds the maximum number of an_clk


(sampling clock) posedge that can be
sampled for considering valid clock
transition to data transition (and hence a
valid Data bit 1). A default value 34
corresponds to maximum T3 value 3.4 ns
assuming an_clk to be of period 0.1 ns.

7.

MANCHESTER_DELIMITER_MIN_
CYCLES

126

Holds the minimum number of an_clk


(sampling clock) posedge that must be
sampled for considering valid Manchester
violation delimiter. The default value 126
corresponds to minimum T6 value 12.6 ns
assuming an_clk to be of period 0.1 ns.

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Table 8-24. 40/100G Auto-Negotiation Monitor Parameters (cont.)


Order Parameter

Default

Description

8.

MANCHESTER_DELIMITER_MAX_
CYCLES

130

Parameter MANCHESTER_
DELIMITER_MAX_CYCLES holds the
maximum number of an_clk (sampling
clock) posedge that must be sampled for
considering valid Manchester violation
delimiter. The default value 130
corresponds to maximum T6 value 13.0 ns
assuming an_clk to be of period 0.1 ns.

9.

REMAINING_ACK_COUNT_MIN

Specifies the minimum number of


additional link codewords with the
Acknowledge bit set to logical one that are
sent by local device to ensure that the link
partner receives the acknowledgement.

10.

REMAINING_ACK_COUNT_MAX

Specifies the maximum number of


additional link codewords with the
Acknowledge bit set to logical one that are
sent by local device to ensure that the link
partner receives the acknowledgement.

11.

BREAK_LINK_TIMER_CYCLES

100000

After the auto-negotiation completion, break


link timer is started. If a valid page is
detected with in
BREAK_LINK_TIMER_CYCLES number
of an_clk posedge samples, the monitor
fires.

12.

PHYSICAL_LANE_COUNT

Sets the physical lane count. Valid values


are
XLAUI: 1, 2, and 4.
CAUI: 1, 2, 4, 5, 10, and 20.

13.

JUMBO_FRAME_DATA_LENGTH

9216

Set this parameter to the desired length of


Jumbo frames. The default length of Jumbo
frames is taken to be 9K bytes (9216 bytes).
Note that the upper limit for the Jumbo
frame size is 12K bytes, since this is the
maximum possible payload for 32-bit CRC.

14.

RESERVED_VALUE_CHECK_ENABLE

By default, the monitor checks for any


reserved values. Set this parameter to 0 to
disable checking of reserved fields.

15.

BYPASS_BLOCK_SYNC

BYPASS_BLOCK_SYNC = 1 will bypass


the block synchronization process and
assume that the blocks are coming in
aligned from first data. To enable block
synchronization set this parameter to 0.

16.

DIC_SUPPORTED

Set this parameter to 1 if Deficient Idle


Count (DIC) is supported. In this case, the
minimum interframe gap requirement is 72bits instead of 96-bits.

17.

MAC_MIN_TAGGED_FRAME_
SIZE_68

Set this parameter to 1 if the minimum size


of tagged frame is 68. In this case, QTag
Prefix is not included in the MAC client
data. Therefore, the minimum tagged frame
size is 68 after auto-padding.

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Monitor Connectivity

Table 8-24. 40/100G Auto-Negotiation Monitor Parameters (cont.)


Order Parameter

Default

Description

18.

BYPASS_DESKEW

Set this parameter to 1 to bypass the deskew


logic. This can be done when the input data
stream is guaranteed to be free of skew
between lanes. The default value of 1
attempts to deskew the lanes before
processing the data further.

19.

AM_COUNTER_16383

800

This parameter defines the number of block


between two alignment marker.

20.

AM_LOCK_ON_FIRST_AM

Set this parameter to 1 to have AM lock


achieved on detection of first alignment
marker. Otherwise, lock is achieved based
on state machine.

The parameters must be specified in the above order.

NOTE:
One can use user type frame (Len/Type) by defining the following:

QVL_GBIT_USER_TYPES_COUNT as number of user type frames.

QVL_GBIT_USER_TYPES as Len/Type field specifying all the supported user types.

Example:
The user can configure QVL to support two types, say 16'h0800 and 16'h0900, by defining the
above defines as follows:
+define+QVL_GBIT_USER_TYPES_COUNT=2
+define+QVL_GBIT_USER_TYPES="32'h08000900"

Instantiation Examples
Example 1
Example 8-1 instantiates a 1 Gigabit Ethernet GMII monitor on the MAC side (on the
Reconciliation Sublayer) with the Jumbo frame size configured as 9216. The reserved value
checking is disabled and the monitor is instantiated in Half Duplex mode.
Example 8-1. 1 Gigabit Ethernet GMII Monitor Instantiation
qvl_gigabit_ethernet_gmii_monitor #(
.Constraints_Mode(0),
.MAC_SIDE(1),
.JUMBO_FRAME_DATA_LENGTH(9216),
.RESERVED_VALUE_CHECK_ENABLE(0),
.MAC_MIN_TAGGED_FRAME_SIZE_68(0),

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.RESERVED_CONTROL_FRAME_SUPPORTED(1),
.SLOT_TIME(512),
.JAM_SIZE(32),
.BURST_LIMIT(65536)
)
GMII_MONITOR
(.areset (areset),
.reset (reset),
.tx_clk (tx_clk),
.txd (txd),
.tx_en (tx_en),
.tx_er (tx_er),
.rx_clk (rx_clk),
.rxd (rxd),
.rx_dv (rx_dv),
.rx_er (rx_er),
.col (col),
.crs (crs),
.half_duplex(half_duplex));

Example 2
Example 8-2 instantiates a 1G RGMII monitor on the MAC side (on the Reconciliation
Sublayer) with the Jumbo frame size configured as 9216. The reserved value checking is
disabled and the monitor is instantiated in Half Duplex mode.
Example 8-2. Reduced Gigabit Ethernet RGMII Monitor Instantiation
qvl_gigabit_ethernet_rgmii_monitor #(
.Constraints_Mode(0),
.MAC_SIDE(1),
.JUMBO_FRAME_DATA_LENGTH(9216),
.RESERVED_VALUE_CHECK_ENABLE(0),
.MAC_MIN_TAGGED_FRAME_SIZE_68(0),
.RESERVED_CONTROL_FRAME_SUPPORTED(1),
.SLOT_TIME(512),
.JAM_SIZE(32),
.DUPLEX_MODE_INDICATION(0),
.CLK_SPEED_INDICATION(0)
)
RGMII_MONITOR
(.areset (areset),
.reset (reset),
.txc (txc),
.td (td),
.tx_ctl (tx_ctl),
.rxc (rxc),
.rd (rd),
.rx_ctl (rx_ctl),
.half_duplex(half_duplex));

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Example 3
Example 8-3 instantiates a 10/100M MII monitor on the MAC side (on the Reconciliation
Sublayer) with the Jumbo frame size configured as 9216. The reserved value checking is
disabled and the monitor is instantiated in Half Duplex mode.
Example 8-3. 10/100M Gigabit Ethernet MII Monitor Instantiation
qvl_gigabit_ethernet_mii_monitor #(
.Constraints_Mode(0),
.MAC_SIDE(1),
.JUMBO_FRAME_DATA_LENGTH(9216),
.RESERVED_VALUE_CHECK_ENABLE(0),
.MAC_MIN_TAGGED_FRAME_SIZE_68(0),
.RESERVED_CONTROL_FRAME_SUPPORTED(1),
.SLOT_TIME(64),
.JAM_SIZE(32)
)
MII_MONITOR
(.areset (areset),
.reset (reset),
.tx_clk (tx_clk),
.txd (txd),
.tx_en (tx_en),
.tx_er (tx_er),
.rx_clk (rx_clk),
.rxd (rxd),
.rx_dv (rx_dv),
.rx_er (rx_er),
.col (col),
.crs (crs),
.half_duplex(half_duplex));

Example 4
Example 8-4 instantiates a RMII monitor on the MAC side (on the Reconciliation Sublayer)
with the Jumbo frame size configured as 9216. The reserved value checking is disabled and the
monitor is instantiated in Half Duplex mode.
Example 8-4. 10/100M Gigabit Ethernet RMII Monitor Instantiation
qvl_gigabit_ethernet_rmii_monitor #(
.Constraints_Mode(0),
.MAC_SIDE(1),
.JUMBO_FRAME_DATA_LENGTH(9216),
.RESERVED_VALUE_CHECK_ENABLE(0),
.MAC_MIN_TAGGED_FRAME_SIZE_68(0),
.RESERVED_CONTROL_FRAME_SUPPORTED(1)
)
RMII_MONITOR
(.areset (areset),
.reset (reset),
.ref_clk (ref_clk),

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.txd (txd),
.tx_en (tx_en),
.rxd (rxd),
.crs_dv (crs_dv),
.rx_er (rx_er),
.half_duplex(half_duplex));

Example 5
Example 8-5 instantiates a 10 Gigabit Ethernet XGMII monitor on the PHY side (on the XGMII
interface of the first XGXS from MAC or XGMII interface of PCS) with the Jumbo frame size
configured as 4096. The reserved value checking is enabled and the monitor is instantiated in
the single edge 64-bit mode.
Example 8-5. 10 Gigabit Ethernet XGMII Monitor Instantiation
qvl_gigabit_ethernet_xgmii_monitor #(
.Constraints_Mode(0),
.MAC_SIDE(1),
.JUMBO_FRAME_DATA_LENGTH(9216),
.RESERVED_VALUE_CHECK_ENABLE(0),
.DIC_SUPPORTED(1),
.MAC_MIN_TAGGED_FRAME_SIZE_68(1),
.RESERVED_CONTROL_FRAME_SUPPORTED(1)
)
XGMII_MONITOR
(.areset (areset),
.reset (reset),
.tx_clk (tx_clk),
.txd (txd),
.txc (txc),
.rx_clk (rx_clk),
.rxd (rxd),
.rxc (rxc));

Example 6
Example 8-6 instantiates a 40/100 Gigabit Ethernet XLMGMII/CGMII monitor on the PHY
side (on the MAC side) with the Jumbo frame size configured as 9216. The reserved value
checking is enabled.
Example 8-6. 40/100 Gigabit Ethernet XLGMII/CGMII Monitor Instantiation
qvl_gigabit_ethernet_xlgmii_cgmii_monitor #(
.Constraints_Mode(0),
.MAC_SIDE(1),
.JUMBO_FRAME_DATA_LENGTH(9216),
.RESERVED_VALUE_CHECK_ENABLE(0),
.DIC_SUPPORTED(1),
.MAC_MIN_TAGGED_FRAME_SIZE_68(1),

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.RESERVED_CONTROL_FRAME_SUPPORTED(1)
)
XGMII_MONITOR
(.areset (areset),
.reset (reset),
.tx_clk (tx_clk),
.txd (txd),
.txc (txc),
.rx_clk (rx_clk),
.rxd (rxd),
.rxc (rxc));

Example 7
Example 8-7 instantiates a 1000BASE-X TBI monitor on the MAC side with symbol model set
to 1 with the Jumbo frame size configured as 9216. The reserved value checking is disabled and
the monitor is instantiated in Half Duplex mode.
Example 8-7. 1000BASE-X TBI Monitor
qvl_gigabit_ethernet_tbi_monitor #(
.Constraints_Mode(0),
.MAC_SIDE(1),
.SYMBOL_MODE(1),
.JUMBO_FRAME_DATA_LENGTH(9216),
.RESERVED_VALUE_CHECK_ENABLE(0),
.MAC_MIN_TAGGED_FRAME_SIZE_68(0),
.RESERVED_CONTROL_FRAME_SUPPORTED(1),
.SLOT_TIME(512),
.JAM_SIZE(32),
.BURST_LIMIT(65536))
TBI_MONITOR (
(.areset(1'b0),
.reset(reset),
.tx_clk(tx_clk),
.txd(txd_10b),
.rx_clk(rx_clk),
.rxd(rxd_10b),
.half_duplex(half_duplex));

Example 8
Example 8-8 instantiates a Reduced Ten bit interface monitor on the MAC side with the Jumbo
frame size configured as 9216. The reserved value checking is disabled and the monitor is
instantiated in Half Duplex mode.
Example 8-8. Reduced Ten bit Interface Monitor
qvl_gigabit_ethernet_rtbi_monitor #(
.Constraints_Mode(0),

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.MAC_SIDE(1),
.JUMBO_FRAME_DATA_LENGTH(9216),
.RESERVED_VALUE_CHECK_ENABLE(0),
.MAC_MIN_TAGGED_FRAME_SIZE_68(0),
.RESERVED_CONTROL_FRAME_SUPPORTED(1),
.SLOT_TIME(512),
.JAM_SIZE(32),
.BURST_LIMIT(65536))
RTBI_MONITOR (
(.areset(1'b0),
.reset(reset),
.txc(txc),
.td(td),
.tx_ctl(tx_ctl),
.rxc(rxc),
.rd(rd),
.rx_ctl(rx_ctl),
.half_duplex(half_duplex));

Example 9
Example 8-9 instantiates a 10 Gigabit Ethernet XAUI monitor on the MAC side (on the XAUI
interface of the first XGXS from MAC or XAUI interface of PCS) with the Jumbo frame size
configured as 9216. The reserved value checking is enabled and the monitor is instantiated in
symbol mode (ten-bit interface) with deskew enabled.
Example 8-9. 10 Gigabit Ethernet XAUI Monitor Instantiation
qvl_gigabit_ethernet_xaui_monitor #(
.Constraints_Mode(0),
.MAC_SIDE(1),
.JUMBO_FRAME_DATA_LENGTH(9216),
.RESERVED_VALUE_CHECK_ENABLE(0),
.BYPASS_DESKEW(0),
.DIC_SUPPORTED(1),
.MAC_MIN_TAGGED_FRAME_SIZE_68(1),
.RESERVED_CONTROL_FRAME_SUPPORTED(1)
)
XAUI_MONITOR
(.areset (areset),
.reset (reset),
.dl_clk (dl_clk),
.sl_clk (sl_clk),
.sl0_p (sl0_p),
.sl1_p (sl1_p),
.sl2_p (sl2_p),
.sl3_p (sl3_p),
.dl0_p (dl0_p),
.dl1_p (dl1_p),
.dl2_p (dl2_p),
.dl3_p (dl3_p));

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Example 10
Example 8-10 instantiates a 10 Gigabit Ethernet XSBI monitor on the PHY side (on the XSBI
interface of PMA) with the Jumbo frame size configured as 1024. The reserved value checking
is disabled and the monitor is instantiated with block synchronization disabled and
descrambling enabled.
Example 8-10. 10 Gigabit Ethernet XSBI Monitor Instantiation
qvl_gigabit_ethernet_xsbi_monitor #(
.Constraints_Mode(0),
.MAC_SIDE(1),
.JUMBO_FRAME_DATA_LENGTH(9216),
.RESERVED_VALUE_CHECK_ENABLE(0),
.BYPASS_BLOCK_SYNC(0),
.DIC_SUPPORTED(1),
.MAC_MIN_TAGGED_FRAME_SIZE_68(1),
.RESERVED_CONTROL_FRAME_SUPPORTED(1)
)
XSBI_MONITOR
(areset (areset),
.reset (reset),
.tx_clk (tx_clk),
.rx_clk (rx_clk),
.txd (txd),
.rxd (rxd),
.bypass_descramble (bypass_descramble));

Example 11
Example 8-11 instantiates a 100 Gigabit Ethernet XLAUI monitor on the PHY side (on the
CAUI interface of PMA) with the am counter value 1200 and physical lane count 5. The
reserved value checking is disabled.
Example 8-11. 100 Gigabit Ethernet CAUI Monitor Instantiation
qvl_gigabit_ethernet_xlaui_caui_monitor #
(.Constraints_Mode(0),
.MAC_SIDE(1),
.JUMBO_FRAME_DATA_LENGTH(9216),
.RESERVED_VALUE_CHECK_ENABLE(0),
.CAUI_INTERFACE(1),
.FEC_ENABLE(0),
.AM_COUNTER_16383(1200),
.AM_LOCK_ON_FIRST_AM(1),
.AUTONEG_MODE(0),
.PHYSICAL_LANE_COUNT(5),
.DIC_SUPPORTED(1),
.MAC_MIN_TAGGED_FRAME_SIZE_68(0),
.RESERVED_CONTROL_FRAME_SUPPORTED(0))
CAUI_MONITOR
.areset(areset),
.reset (reset ),

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.tx_clk(tx_clk),
.rx_clk(rx_clk),
.caui_interface(1'b0),
.fec_enable(1'b0),
.tx_lanes(tx_lanes),
.rx_lanes(rx_lanes));

Example 12
Example 8-12 instantiates a 40/100G Auto-Negotiation monitor on the PHY side. The reserved
value checking is disabled.
Example 8-12. 100 Gigabit Ethernet Auto-Negotiation Monitor Instantiation
qvl_gigabit_ethernet_an_monitor #
(.Constraints_Mode(0),
.MAC_SIDE(1),
.JUMBO_FRAME_DATA_LENGTH(9216),
.RESERVED_VALUE_CHECK_ENABLE(0),
.AM_COUNTER_16383(1200),
.AM_LOCK_ON_FIRST_AM(1),
.DIC_SUPPORTED(1),
.MAC_MIN_TAGGED_FRAME_SIZE_68(0),
.RESERVED_CONTROL_FRAME_SUPPORTED(0))
AN_MONITOR
.areset(areset),
.reset (reset ),
.an_clk(an_clk),
.tx_clk(tx_clk),
.rx_clk(rx_clk),
.tx_data(tx_data),
.rx_data(rx_data));

Monitor Checks
The checks performed by the Gigabit Ethernet monitor are classified as follows:

MAC checks
These validate frame formation with regards to the size, type, address, FCS, and
interframe gap requirements. These are listed in Table 8-25 on page 258.

GMII checks
These validate 1Gb/s specific requirements, mainly with regards to the Half Duplex
mode of operation. These are listed in Table 8-26 on page 261

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Monitor Checks

These validate RGMII specific requirements (for 1 Gbps speed), mainly with regards to
the Half Duplex mode of operation. These are listed in Table 8-27 on page 263.

MII checks
These validate 10/100M specific requirements, mainly with regards to the Half Duplex
mode of operation. These are listed in Table 8-28 on page 265.

RMII checks
These validate 10/100M specific requirements of RMII Interface, mainly with regards to
the Half Duplex mode of operation. These are listed in Table 8-29 on page 268.

XGMII checks
These validate lane alignment, frame encapsulation, and control character related
requirements in an XGMII interface. These are listed in Table 8-30 on page 269.

XLGMII/CGMII checks
These validate lane alignment, frame encapsulation, and control character related
requirements in an XLGMII/CGMII interface These are listed in Table 8-31 on
page 272.

TBI/RTBI checks
These validate 8B/10B encoding, link synchronization, ordered set location, and code
group requirements. These are listed in Table 8-32 on page 273.

XAUI checks
These validate 8B/10B encoding, link synchronization and alignment, ordered set
location, and spacing requirements. These are listed in Table 8-33 on page 275.

BASER checks for XSBI, XLAUI, and CAUI


These validate 64B/66B encoding, synchronization headers, block types, and null fields.
These are listed in Table 8-34 on page 280.

XLAUI/CAUI checks
These validate lane synchronization, alignment marker and deskew error. These are
listed in Table 8-35 on page 282.

40/100G Auto-Negotiation Checks


These validate DME timing, arbitration state machine, and valid priority resolution.
These are listed in Table 8-36 on page 283.

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Table 8-25. MAC Checks


Check ID

Violation

Description

GIGABIT_ETHERNET_
CONTROL_FRAME_
LENGTH_VIOLATION_P

The length of MAC control


frames should be 64 octets
(MinFrameSize - 32 bits +
FCS).

MAC Control frames are of fixed length,


containing MinFrameSize-32 bits. The
underlying MAC appends the FCS. This
maps to overall frame size of 64 octets (64
octets - 32 bits/8 + 4 octets). This check
fires when this requirement is violated. This
check is active only if the parameter
RESERVED_VALUE_CHECK_ENABLE
is set to 1.

The CRC computed by the


receiving station should be
the same as the one
appended to the frame.

The frame check sequence (FCS) field


contains a 4-octet (32-bit) cyclic
redundancy check (CRC) value. This check
fires when the CRC appended to a frame
does not match the CRC computed on the
frame.

The length of the frame


should be equal to the
expected length (2 x address
fields + len_type field +
length + fcs field).

In case of untagged data frames, the


LEN/TYPE field indicates the length of the
subsequent data in octets. The overall frame
size is the sum of the length of data field, 6
octets each of destination address, and
source address and 4 octets of FCS. This
check fires if the actual frame size does not
match the above sum.

The LEN/TYPE field should


be lesser than or equal to
16'd1500 or greater than
16'd1535.

If the value of LEN/TYPE field is less than


or equal to 1500 (decimal), then it indicates
the number of MAC client data octets
contained in the subsequent data.
If the value of this field is greater than or
equal to 1536 (decimal), then it indicates the
nature of the MAC client protocol. Values
between these bounds are invalid and not to
be used.
This check fires when a LEN/TYPE value
within this range is detected.

The size of an untagged


Ethernet MAC frame should
be lesser than the maximum
allowed size of 1518 octets.

The maximum number of octets of data that


can be transmitted on an untagged data
frame is 1500. This comes from the
LEN/TYPE field value restrictions. This
check fires whenever an untagged data
frame exceeds this upper limit.

GIGABIT_ETHERNET_
CONTROL_FRAME_
LENGTH_VIOLATION_N
GIGABIT_ETHERNET_
CRC_VIOLATION_P
GIGABIT_ETHERNET_
CRC_VIOLATION_N
GIGABIT_ETHERNET_
FRAME_LENGTH_
MISMATCH_VIOLATION_P
GIGABIT_ETHERNET_
FRAMELENGTH_
MISMATCH_VIOLATION_N
GIGABIT_ETHERNET_
LENGTH_TYPE_VIOLATION_P
GIGABIT_ETHERNET_
LENGTH_TYPE_VIOLATION_N

GIGABIT_ETHERNET_
MAX_FRAME_SIZE_
VIOLATION_P
GIGABIT_ETHERNET_
MAX_FRAME_SIZE_
VIOLATION_N

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Table 8-25. MAC Checks (cont.)


Check ID

Violation

Description

GIGABIT_ETHERNET_
MIN_FRAME_SIZE_
VIOLATION_P

The size of an ethernet MAC


frame should be equal to or
greater than the minimum
allowed size of 64 octets.

The data field contains a sequence of n


octets. A minimum frame size (of 64 octets)
is required for correct CSMA/CD protocol
operation. This check fires when this
minimum frame size requirement is
violated.

The destination address in a


PAUSE control frame on the
transmit interface should be
globally assigned multicast
address 01-80-C2-00-00-01.

The globally assigned 48-bit multicast


address 01-80-C2-00-00-01 has been
reserved for use in MAC Control PAUSE
frames for inhibiting transmission of data
frames from a DTE. A transmitting station
sending out a Pause frame must use this
global address. This check fires when this
requirement is violated.

The reserved field in a


PAUSE control frame
should have a value of 8'h00
in all the octets.

The Reserved field is used when the MAC


Control parameters do not fill the fixed
length MAC Control frame. The size of the
Reserved field is determined by the size of
the MAC Control Parameters. In the case of
Pause frames, only two octets of pause
quantum parameter is defined and all the
remaining reserved fields must be 0. This
check fires when this requirement is
violated. This check is active only if
RESERVED_VALUE_CHECK_ENABLE
is set to 1.

All octets of the preamble


field should have a value of
8'b10101010 (8'hAA).

The preamble field is a 7-octet field that is


used to allow the PLS circuitry to reach its
steady-state synchronization with the
received frames timing. The preamble
pattern is a continuous stream of 8 bit
sequences of 10101010. The nature of the
pattern is such that, for Manchester
encoding, it appears as a periodic waveform
on the medium that enables bit
synchronization. This check fires when this
preamble pattern is violated.

The control opcode should


not be reserved.

The Length/Type field of a MAC Control


frame contains the hexadecimal value of
88-08. The next two octets define the
control opcode. Currently, the only defined
opcode is 00_01 to denote Pause control
frames. This check fires whenever a
reserved opcode is detected.

GIGABIT_ETHERNET_
MIN_FRAME_SIZE_
VIOLATION_N
GIGABIT_ETHERNET_
PAUSE_DEST_ADDR_
VIOLATION_P
GIGABIT_ETHERNET_
PAUSE_DEST_ADDR_
VIOLATION_N
GIGABIT_ETHERNET_
PAUSE_RESERVED_
VIOLATION_P
GIGABIT_ETHERNET_
PAUSE_RESERVED_
VIOLATION_N

GIGABIT_ETHERNET_
PREAMBLE_VIOLATION_P
GIGABIT_ETHERNET_
PREAMBLE_VIOLATION_N

GIGABIT_ETHERNET_
RESERVED_CONTROL_
OPCODE_P
GIGABIT_ETHERNET_
RESERVED_CONTROL_
OPCODE_N

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Table 8-25. MAC Checks (cont.)


Check ID

Violation

Description

GIGABIT_ETHERNET_
RX_MIN_IFG_VIOLATION_P

The spacing between two


packets on the receive
interface should be greater
than the minimum of 8 BT,
40 BT and 64 BT in
100/40G, 10G, and 1G
implementations,
respectively.

In the case of 1 Gb/s implementations, the


spacing between two non-colliding packets,
from the last bit of the FCS field of the first
packet to the first bit of the preamble of the
second packet, should be a minimum of 64
BT (bit times), as measured at the GMII
receive signals at the DTE. For 10G/s
implementation, a minimum gap of 40 bit
times and for 100/40G/s implementation, a
minimum gap of 8 bit times must be
maintained. This check fires when the gap
between two frames violates this
requirement.
This check not valid for XLAUI and CAUI
interfaces.

The start frame delimiter


(SFD) should have a value
of 8'b10101011 (8'hAB).

The SFD field has the sequence 10101011.


It immediately follows the preamble pattern
and indicates the start of a frame. Upon
reception of this sequence, further bits are
sent to the MAC client for processing. This
check fires when this pattern is violated.

The source address should


be an individual address.

A multi-destination address associated with


one or more stations on a given network are
called multicast addresses. A source address
cannot be a group (multicast) address. This
check fires when a multicast source address
is detected.

The spacing between two


packets on the transmit
interface should be a
minimum of 96 BTs.

On the transmit interface, both 1G/s and


10G/s implementations must ensure a
minimum interframe spacing of 96 bit times.
This check fires when this requirement is
violated.
This check is not valid for XLAUI and
CAUI interfaces.

When the LEN/TYPE field


indicates a TYPE, this value
should indicate one of
CONTROL, TAGGED, or
JUMBO frames.

If the value of this field is greater than or


equal to 1536 (decimal), then this field
indicates the nature of the MAC client
protocol (Type interpretation). However, the
only defined types are Control frames,
Tagged frames, and Jumbo frames. This
check fires when the LEN/TYPE field
indicates a type other than these defined
values.

GIGABIT_ETHERNET_
RX_MIN_IFG_VIOLATION_N

GIGABIT_ETHERNET_
SFD_VIOLATION_P
GIGABIT_ETHERNET_
SFD_VIOLATION_N
GIGABIT_ETHERNET_
SOURCE_ADDR_VIOLATION_P
GIGABIT_ETHERNET_
SOURCE_ADDR_VIOLATION_N
GIGABIT_ETHERNET_
TX_MIN_IFG_VIOLATION_P
GIGABIT_ETHERNET_
TX_MIN_IFG_VIOLATION_N
GIGABIT_ETHERNET_
TYPE_VIOLATION_P
GIGABIT_ETHERNET_
TYPE_VIOLATION_N

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Table 8-26. GMII Checks


Check ID

Violation

Description

GIGABIT_ETHERNET_GMII_
CAR_EXTN_ON_RX_
WITHOUT_FRAME

Carrier extension detected


on receive interface without
a preceding frame.

Carrier extension is performed to maintain


the minimum carrier event. This can only
follow a frame. This check fires if a carrier
extension is detected on the receive
interface without a preceding frame.

GIGABIT_ETHERNET_GMII_
CAR_EXTN_ON_TX_
WITHOUT_FRAME

Carrier extension detected


Carrier extension is performed to maintain
on transmit interface without the minimum carrier event. This can only
a preceding frame.
follow a frame. This check fires if a carrier
extension is detected on the transmit
interface without a preceding frame.

GIGABIT_ETHERNET_GMII_
CAR_EXTN_FULL_DUPLEX_
VIOLATION

Carrier extension should not


be there in Full Duplex
mode.

Carrier extension is not a part of Full


Duplex mode. This assertion gets fired
when it detected carrier extension in Full
Duplex.

GIGABIT_ETHERNET_GMII_
COLLISION_DETECTED_
WITHOUT_CAR

In Half Duplex mode, a


collision is detected even
when there is no carrier
sense.

In Half Duplex mode, the collision detect


signal is driven by the PHY upon detection
of a collision on the medium. A collision
cannot be detected when there is no carrier
sensed in the medium. This check fires if
the CRS signal is low, indicating that both
transmit and receive interfaces are idle and
COL is asserted, indicating a collision.

GIGABIT_ETHERNET_GMII_
CRS_DEASSERTED_DURING_
COLLISION

In Half Duplex mode, carrier


sense should be held high
throughout the collision
period.

In the event of a collision, the COL is


asserted by the PHY and is held high until
the collision persists, after which it is deasserted. The carrier sense should also be
driven high until the collision persists. This
check fires when CRS is de-asserted while
COL is high.

GIGABIT_ETHERNET_GMII_
RESERVED_VALUES_ON_RX_
INTERFACE

Reserved values detected on


receive interface when the
RX_DV was not asserted
and RX_ER is asserted.

Reserved values should not be used on the


receive interface when RX_DV is deasserted and RX_ER is asserted. This check
fires when RX_DV is de-asserted and
RX_ER is asserted with a reserved value on
RXD. This check is active only if
RESERVED_VALUE_CHECK_ENABLE
is set to 1.

GIGABIT_ETHERNET_GMII_
RESERVED_VALUES_ON_TX_
INTERFACE

Reserved values detected on


the transmit interface when
TX_EN was not asserted and
TX_ER is asserted.

Reserved values should not be used on the


transmit interface when TX_EN is asserted
and TX_ER is asserted. This check fires
when TX_EN is de-asserted and TX_ER is
asserted with a reserved value on TXD.
This check is active only if
RESERVED_VALUE_CHECK_ENABLE
is set to 1.

GIGABIT_ETHERNET_GMII_
RX_INTERFACE_ACTIVE_
WHEN_TX_ACTIVE

In Half Duplex mode, the


receive interface is non-idle
when the transmit interface
is already active.

In Half Duplex mode, either the transmit or


the receive interface can be active at any
given time and the other interface should be
idle. This check fires when the receive
interface is detected active when the
transmit interface is already active.

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Table 8-26. GMII Checks (cont.)


Check ID

Violation

Description

GIGABIT_ETHERNET_GMII_
RX_START_WITH_
NON_PREAMBLE_OR_SFD

When RX_DV is asserted, it


indicates that a frame
reception has started. A
frame reception must always
begin with a preamble or
SFD.

When RX_DV is asserted, the value on the


RXD can only start with preamble or SFD.
This check fires when this is violated.

GIGABIT_ETHERNET_GMII_
TX_ASSERTED_WHEN_
CAR_SENSED

In Half Duplex mode,


TX_EN should not be
asserted when the carrier
sense is high.

In Half Duplex mode, the carrier sense


signal is driven by the PHY when either the
transmit or the receive interface is non-idle.
If the transmit interface is idle and the
carrier sense is asserted, then it means that
the receive interface is non-idle and the
TX_EN should not be asserted until CRS is
sampled low. This check fires if TX_EN is
asserted when CRS is high.

GIGABIT_ETHERNET_GMII_
TX_ASSERTED_WHEN_
COLLISION_DETECTED

In Half Duplex mode,


TX_EN should not be
asserted when a collision is
detected.

In Half Duplex mode, the collision detect


signal is driven by the PHY upon detection
of a collision on the medium, and shall
remain asserted while the collision
condition persists. The transmit interface
should not make an attempt to transmit a
frame (assert TX_EN) during a collision
period and must wait until COL is low. This
check fires if TX_EN is asserted when COL
is high.

GIGABIT_ETHERNET_GMII_
TX_INTERFACE_ACTIVE_
WHEN_RX_ACTIVE

In Half Duplex mode, the


transmit interface is non-idle
when the receive interface is
already active.

In Half Duplex mode, either the receive or


the transmit interface can be active at any
given time and the other interface should be
idle. This check fires when the transmit
interface is detected active when the receive
interface is already active.

GIGABIT_ETHERNET_GMII_
TX_START_WITH_
NON_PREAMBLE

When TX_EN is asserted, it This check fires whenever TX_EN is


indicates that a frame
asserted, indicating a new frame and the
transmission has started. The data is other than preamble (8'h55).
frame transmission should
always begin with a
preamble.

GIGABIT_ETHERNET_GMII_
TX_ER_ASSERTED_DURING_
FRAME_TRANSMISSION

TX_ER is asserted while


frame is being transmitted.

During the frame transmission, TX_EN is


asserted. Assertion of TX_ER at this
moment indicates a Transmit error
propagation.

GIGABIT_ETHERNET_GMII_
RX_ER_ASSERTED_DURING_
FRAME_TRANSMISSION

RX_ER is asserted while


frame is being transmitted.

During the frame transmission, RX_DV is


asserted. Assertion of RX_ER at this
moment indicates a Data Reception error.

GIGABIT_ETHERNET_GMII_
TX_EXTN_ERR

TX_ER is asserted with


This check is fired when an error is
TXD carrying 0x1F while
encountered within carrier extension
extension bits are being sent. indicated by 0x1F on TXD while keeping
TX_EN de-asserted.

GIGABIT_ETHERNET_GMII_
RX_EXTN_ERR

RX_ER is asserted with


This check is fired when an error is
RXD carrying 0x1F while
encountered within carrier extension
extension bits are being sent. indicated by 0x1F on RXD while keeping
RX_EN de-asserted.

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Table 8-26. GMII Checks (cont.)


Check ID

Violation

Description

GIGABIT_ETHERNET_FALSE_
CAR_INDICATION

RX_ER is asserted with


0x0E on RXD.

While RX_DV is de-asserted, the PHY may


provide a False carrier indication by
asserting the RX_ER signal while driving
0x0E on RXD.

GIGABIT_ETHERNET_GMII_
BURST_LIMIT_EXCEEDED

Burst limit is exceeded

The transmitting station is allowed to


initiate frame transmission until a specified
limit specified as burstLimit. This check is
fired when this limit is exceeded.

GIGABIT_ETHERNET_GMII_
INCORRECT_EXTN_LENGTH

Extension length is not


correct.

If frame (or first frame in a burst) has length


less than slot time, then it should be
extended with the extension length as
(slotTime-FrameSize).
This check is fired when the number of
extension bits are not correct.

GIGABIT_ETHERNET_PAUSE_
FRAME_DETECTED

In Half Duplex mode, pause


frame is detected.

Pause frames are sent by DTEs configured


for Full Duplex operation. This check fires
when pause frame is sent in Half Duplex
mode.

GIGABIT_ETHERNET_LATE_
COLLISION_DETECTED

Late collision is detected.

MAC treats any collision that occurs after


the first frame of a burst, or that occurs after
the slotTime has been reached in the first
frame of a burst, as a late collision. This
check is fired when late collision is
detected.

GIGABIT_ETHERNET_JAM_
SIZE_NOT_CORRECT

Jam size is not equal to the


specified JAM_SIZE
parameter bit times.

When a collision is detected during a frame


transmission, the transmission continues for
additional bits corresponding to jam
sequence. This check fires when jam size is
not correct.

Table 8-27. RGMII Checks


Check ID

Violation

Description

GIGABIT_ETHERNET_RGMII_
RESERVED_VALUES_ON_RX_
INTERFACE

Reserved values detected on


receive interface when the
RX_DV was not asserted
and RX_ER is asserted.

Reserved values should not be used on the


receive interface when RX_DV is deasserted and RX_ER is asserted. This check
fires when RX_DV is de-asserted and
RX_ER is asserted with a reserved value on
RXD. This check is active only if
RESERVED_VALUE_CHECK_ENABLE
is set to 1.

GIGABIT_ETHERNET_RGMII_
RESERVED_VALUES_ON_TX_
INTERFACE

Reserved values detected on


the transmit interface when
TX_EN was not asserted and
TX_ER is asserted.

Reserved values should not be used on the


transmit interface when TX_EN is asserted
and TX_ER is asserted. This check fires
when TX_EN is de-asserted and TX_ER is
asserted with a reserved value on TXD.
This check is active only if
RESERVED_VALUE_CHECK_ENABLE
is set to 1.

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Table 8-27. RGMII Checks (cont.)


Check ID

Violation

Description

GIGABIT_ETHERNET_RGMII_
RX_INTERFACE_ACTIVE_
WHEN_TX_ACTIVE

In Half Duplex mode, the


receive interface is non-idle
when the transmit interface
is already active.

In Half Duplex mode, either the transmit or


the receive interface can be active at any
given time and the other interface should be
idle. This check fires when the receive
interface is detected active when the
transmit interface is already active.

GIGABIT_ETHERNET_RGMII_
RX_START_WITH_
NON_PREAMBLE_OR_SFD

When RX_DV is asserted, it


indicates that a frame
reception has started. A
frame reception must always
begin with a preamble or
SFD.

When RX_DV is asserted, the value on the


RXD can only start with preamble or SFD.
This check fires when this is violated.

GIGABIT_ETHERNET_RGMII_
TX_INTERFACE_ACTIVE_
WHEN_RX_ACTIVE

In Half Duplex mode, the


transmit interface is non-idle
when the receive interface is
already active.

In Half Duplex mode, either the receive or


the transmit interface can be active at any
given time and the other interface should be
idle. This check fires when the transmit
interface is detected active when the receive
interface is already active.

GIGABIT_ETHERNET_RGMII_
TX_START_WITH_
NON_PREAMBLE

When TX_EN is asserted, it This check fires whenever TX_EN is


indicates that a frame
asserted, indicating a new frame and the
transmission has started. The data is other than preamble (8'h55).
frame transmission should
always begin with a
preamble.

GIGABIT_ETHERNET_RGMII_
TX_ER_ASSERTED_DURING_
FRAME_TRANSMISSION

TX_ER is asserted while


frame is being transmitted.

During the frame transmission, TX_EN is


asserted. Assertion of TX_ER at this
moment indicates a Transmit error
propagation.

GIGABIT_ETHERNET_RGMII_
RX_ER_ASSERTED_DURING_
FRAME_TRANSMISSION

RX_ER is asserted while


frame is being transmitted.

During the frame transmission, RX_DV is


asserted. Assertion of RX_ER at this
moment indicates a Data Reception error.

GIGABIT_ETHERNET_RGMII_
TX_EXTN_ERR

TX_ER is asserted with


This check is fired when an error is
TXD carrying 0x1F while
encountered within carrier extension
extension bits are being sent. indicated by 0x1F on TXD while keeping
TX_EN de-asserted.

GIGABIT_ETHERNET_RGMII_
RX_EXTN_ERR

RX_ER is asserted with


This check is fired when an error is
RXD carrying 0x1F while
encountered within carrier extension
extension bits are being sent. indicated by 0x1F on RXD while keeping
RX_EN de-asserted.

GIGABIT_ETHERNET_RGMII_
INVALID_DUPLEX_STATUS

RX_CTL 0, 0 then rxd


shows duplex indication.

This check is fired when normal interframe


RXD value does not show proper Duplex
indication configured.

GIGABIT_ETHERNET_RGMII_
INVALID_CLK_SPEED_STATUS

RX_CTL 0, 0 then rxd


should be x10x for 125
MHz.

This check is fired when normal interframe


RXD value is not equal to x10x for 125
MHz speed.

GIGABIT_ETHERNET_RGMII_
RESERVED_CLK_SPEED_
STATUS

RX_CTL 0, 0 then rxd


should not be x11x which
indicates reserved status
value.

This check is fired when normal interframe


RXD value is equal to x11x.

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Table 8-27. RGMII Checks (cont.)


Check ID

Violation

Description

GIGABIT_ETHERNET_RGMII_
INVALID_NIBBLES_ON_
NEGEDGE_INTERFRAME

During interframe if optional


status is enabled, then data
on negedge should be the
same as data on posedge.

This check is fired during normal


interframe if optional status indictions are
enabled and RXD on negedge is not the
same as RXD on posedge.

GIGABIT_ETHERNET_FALSE_
CAR_INDICATION

RX_ER is asserted with


0x0E on RXD.

While RX_DV is de-asserted, the PHY may


provide a False carrier indication by
asserting the RX_ER signal while driving
0x0E on RXD.

GIGABIT_ETHERNET_GMII_
BURST_LIMIT_EXCEEDED

Burst limit is exceeded

The transmitting station is allowed to


initiate frame transmission until a specified
limit specified as burstLimit. This check is
fired when this limit is exceeded.

GIGABIT_ETHERNET_GMII_
INCORRECT_EXTN_LENGTH

Extension length is not


correct.

If frame (or first frame in a burst) has length


less than slot time, then it should be
extended with the extension length as
(slotTime-FrameSize).
This check is fired when the number of
extension bits are not correct.

GIGABIT_ETHERNET_PAUSE_
FRAME_DETECTED

In Half Duplex mode, pause


frame is detected.

Pause frames are sent by DTEs configured


for Full Duplex operation. This check fires
when pause frame is sent in Half Duplex
mode.

GIGABIT_ETHERNET_LATE_
COLLISION_DETECTED

Late collision is detected.

MAC treats any collision that occurs after


the first frame of a burst, or that occurs after
the slotTime has been reached in the first
frame of a burst, as a late collision. This
check is fired when late collision is
detected.

GIGABIT_ETHERNET_JAM_
SIZE_NOT_CORRECT

Jam size is not equal to the


specified JAM_SIZE
parameter bit times.

When a collision is detected during a frame


transmission, the transmission continues for
additional bits corresponding to jam
sequence. This check fires when jam size is
not correct.

Table 8-28. MII Checks


Check ID

Violation

Description

ETHERNET_MII_COLLISION_
DETECTED_WITHOUT_CAR

In Half Duplex mode, a collision


is detected even when there is no
carrier sense.

In Half Duplex mode, the collision


detect signal is driven by the PHY
upon detection of a collision on the
medium. A collision cannot be
detected when there is no carrier
sensed in the medium. This check fires
if the CRS signal is low, indicating
that both transmit and receive
interfaces are idle and COL is asserted,
indicating a collision.

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Table 8-28. MII Checks (cont.)


Check ID

Violation

Description

ETHERNET_MII_CRS_
DEASSERTED_
DURING_COLLISION

In Half Duplex mode, carrier


sense should be held high
throughout the collision period.

In the event of a collision, the COL is


asserted by the PHY and is held high
until the collision persists, after which
it is de-asserted. The carrier sense
should also be driven high until the
collision persists. This check fires
when CRS is de-asserted while COL is
high.

ETHERNET_MII_RESERVED_
VALUES_ON_RX_
INTERFACE

Reserved values detected on the


receive interface when the
RX_DV is not asserted and
RX_ER is asserted.

Reserved values should not be used on


the receive interface when rx_dv is deasserted and rx_er is asserted. This
check fires when rx_dv is de-asserted
and rx_er is asserted with a reserved
value on rxd. This check is active only
if RESERVED_VALUE_CHECK_
ENABLE is set to 1.

ETHERNET_MII_RESERVED_
VALUES_ON_TX_
INTERFACE

Reserved values detected on the


transmit interface when TX_EN
was not asserted and TX_ER was
asserted.

Reserved values should not be used on


the transmit interface when TX_EN is
de-asserted and TX_ER is asserted.
This check fires when TX_EN is deasserted and TX_ER is asserted with a
reserved value on txd. This check is
active only if RESERVED_VALUE_
CHECK_ENABLE is set to 1.

ETHERNET_MII_RX_
EXTRA_NIBBLE_
DETECTED

An extra nibble is detected on the


RX interface.

When the frame ends, there should not


be any extra nibble, which cannot be
packed as 8-bit data. The frame should
always contain an even number of
nibbles so that the data is byte aligned.

ETHERNET_MII_RX_
INTERFACE_ACTIVE_
WHEN_TX_ACTIVE

In Half Duplex mode, the receive


interface is non-idle when the
transmit interface is already
active.

In Half Duplex mode, either the


transmit or the receive interface can be
active at any given time and the other
interface should be idle. This check
fires when transmit interface is
detected active when the receive
interface is already active.

ETHERNET_MII_RX_
START_WITH_NON_
PREAMBLE_OR_SFD

When RX_DV is asserted, it


indicates that a frame reception
has started. A frame reception
must always begin with a
preamble or SFD.

When rx_dv is asserted, the value on


the rxd can only start with preamble or
SFD. This check fires when this is
violated.

ETHERNET_MII_TX_EN_
ASSERTED_WHEN_
CAR_SENSED

In Half Duplex mode, TX_EN


should not be asserted when
carrier sense is high.

In Half Duplex mode, the carrier sense


signal is driven by the PHY when
either the transmit or the receive
interface is non-idle. If the transmit
interface is idle and the carrier sense is
asserted, then it means that the receive
interface is non-idle and the tx_en
should not be asserted until CRS is
sampled low. This check fires if tx_en
is asserted when CRS is high.

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Monitor Checks

Table 8-28. MII Checks (cont.)


Check ID

Violation

Description

ETHERNET_MII_TX_EN_
ASSERTED_WHEN_
COLLISION_DETECTED

In Half Duplex mode, TX_EN


should not be asserted when a
collision is detected.

In Half Duplex mode, the collision


detect signal is driven by the PHY
upon detection of a collision on the
medium, and shall remain asserted
while the collision condition persists.
The transmit interface should not make
an attempt to transmit a frame (assert
TX_EN) during a collision period and
must wait until COL is low. This
check fires if tx_en is asserted when
COL is high.

ETHERNET_MII_TX_
EXTRA_NIBBLE_
DETECTED

An extra nibble is detected on the


TX interface.

When the frame ends, there should not


be any extra nibble, which cannot be
packed as 8-bit data. The frame should
always contain an even number of
nibbles so that the data is byte aligned.

ETHERNET_MII_TX_
INTERFACE_ACTIVE_
WHEN_RX_ACTIVE

In Half Duplex mode, the


transmit interface is non-idle
when the receive interface is
already active.

In Half Duplex mode, either the


receive or the transmit interface can be
active at any given time and the other
interface should be idle. This check
fires when transmit interface is
detected active when the receive
interface is already active.

ETHERNET_MII_TX_
START_WITH_NON_
PREAMBLE

When TX_EN is asserted, it


indicates that a frame
transmission has started. The
frame transmission should always
begin with a preamble.

This check fires whenever tx_en is


asserted, indicating a new frame and
the data is other than preamble
(8'hAA).

ETHERNET_MII_
TX_ER_ASSERTED_DURING_
FRAME

TX_ER is asserted while frame is


being transmitted.

During the frame transmission,


TX_EN is asserted. Assertion of
TX_ER at this moment indicates a
Transmit error propagation.

ETHERNET_MII_
RX_ER_ASSERTED_DURING_
FRAME

RX_ER is asserted while frame is


being transmitted.

During the frame transmission,


RX_DV is asserted. Assertion of
RX_ER at this moment indicates a
Data Reception error.

GIGABIT_ETHERNET_FALSE_
CAR_INDICATION

RX_ER is asserted with 0x0E on


RXD.

While RX_DV is de-asserted, the PHY


may provide a False carrier indication
by asserting the RX_ER signal while
driving 0x0E on RXD.

GIGABIT_ETHERNET_PAUSE_
FRAME_DETECTED

In Half Duplex mode, pause


frame is detected.

Pause frames are sent by DTEs


configured for Full Duplex operation.
This check fires when pause frame is
sent in Half Duplex mode.

GIGABIT_ETHERNET_LATE_
COLLISION_DETECTED

Late collision is detected.

MAC treats any collision that occurs


after the first frame of a burst, or that
occurs after the slotTime has been
reached in the first frame of a burst, as
a late collision. This check is fired
when late collision is detected.

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Monitor Checks

Table 8-28. MII Checks (cont.)


Check ID

Violation

Description

GIGABIT_ETHERNET_JAM_
SIZE_NOT_CORRECT

Jam size is not equal to the


specified JAM_SIZE parameter
bit times.

When a collision is detected during a


frame transmission, the transmission
continues for additional bits
corresponding to jam sequence. This
check fires when jam size is not
correct.

Table 8-29. RMII Checks


Check ID

Violation

Description

ETHERNET_RMII_RESERVED_
VALUES_ON_RX_INTERFACE:

Reserved values detected on


the receive interface when the
CRS_DV is not asserted and
RX_ER is asserted.

Reserved values should not be used on


the receive interface when crs_dv is deasserted and rx_er is asserted. This
check fires when crs_dv is de-asserted
and rx_er is asserted with a reserved
value on rxd. This check is active only
if RESERVED_VALUE_CHECK_
ENABLE is set to 1.

ETHERNET_RMII_RESERVED_
VALUES_ON_TX_INTERFACE

Reserved values detected on


the transmit interface when
TX_EN was not asserted.

Reserved values should not be used on


the transmit interface when TX_EN is
not asserted. This check fires when
TX_EN is de-asserted with a reserved
value on txd. This check is active only
if RESERVED_VALUE_CHECK_
ENABLE is set to 1.

ETHERNET_RMII_RX_INTERFACE_
ACTIVE_WHEN_TX_ACTIVE

In Half Duplex mode, the


receive interface is non-idle
when the transmit interface is
already active.

In Half Duplex mode, either the


transmit or the receive interface can be
active at any given time and the other
interface should be idle. This check
fires when transmit interface is detected
active when the receive interface is
already active.

ETHERNET_RMII_RX_START_
WITH_NON_PREAMBLE_OR_SFD

When CRS_DV is asserted, it


indicates that a frame reception
has started. A frame reception
must always begin with a
preamble or SFD.

When crs_dv is asserted, the value on


the rxd can only start with preamble or
SFD. This check fires when this is
violated.

ETHERNET_RMII_TX_INTERFACE_
ACTIVE_WHEN_RX_ACTIVE

In Half Duplex mode, the


transmit interface is non-idle
when the receive interface is
already active.

In Half Duplex mode, either the receive


or the transmit interface can be active at
any given time and the other interface
should be idle. This check fires when
transmit interface is detected active
when the receive interface is already
active.

ETHERNET_RMII_TX_START_
WITH_NON_PREAMBLE

When TX_EN is asserted, it


indicates that a frame
transmission has started. The
frame transmission should
always begin with a preamble.

This check fires whenever tx_en is


asserted, indicating a new frame and
the data is other than preamble
(8'hAA).

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Gigabit Ethernet
Monitor Checks

Table 8-29. RMII Checks (cont.)


Check ID

Violation

Description

ETHERNET_RMII_RX_ER_
ASSERTED_DURING_FRAME

RX_ER is asserted while frame During the frame transmission,


is being transmitted.
CRS_DV is asserted. Assertion of
RX_ER at this moment indicates a Data
Reception error.

ETHERNET_RMII_FALSE_
CAR_INDICATION

RX_ER is asserted with 2'b10


on RXD.

PHY may provide a False carrier


indication at the beginning of a packet
where preamble is decoded (i.e.,
RXD[1:0]=01) while driving 2'b10 on
RXD.

GIGABIT_ETHERNET_PAUSE_
FRAME_DETECTED

In Half Duplex mode, pause


frame is detected.

Pause frames are sent by DTEs


configured for Full Duplex operation.
This check fires when pause frame is
sent in Half Duplex mode.

Table 8-30. XGMII Checks


Check ID

Violation

Description

GIGABIT_ETHERNET_XGMII_
IDLE_BEFORE_TERM_
VIOLATION_P

Idle is detected while the


frame is in progress.

Once a frame has started with a Start control


character, it must be terminated with a
Terminate character before sending Idle
characters. This check fires when Idle
characters are detected even before the
frame is terminated.

When the bus is idle, Idle


control characters should
be detected on all lanes.

Idle columns are transmitted in full columns,


except when a Terminate is detected,
wherein only the remaining lanes are Idles.
This check fires when an Idle column is
detected with a non-Idle character.

The column prior to the


column containing start
control character should
have all Idle characters or
a sequence ordered set.

In XGMII, a frame is considered valid only


when it begins with a start control character
aligned to lane 0 with the previous column
being all-idles or a sequence ordered set.
This check fires when a frame violates this
requirement.

GIGABIT_ETHERNET_XGMII_
IDLE_BEFORE_TERM_
VIOLATION_N
GIGABIT_ETHERNET_XGMII_
IDLE_COLUMN_VIOLATION_P
GIGABIT_ETHERNET_XGMII_
IDLE_COLUMN_VIOLATION_N
GIGABIT_ETHERNET_XGMII_
NON_IDLE_OR_SEQ_PRIOR_TO_
START_P
GIGABIT_ETHERNET_XGMII_
NON_IDLE_OR_SEQ_PRIOR_TO_
START_N

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269

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Monitor Checks

Table 8-30. XGMII Checks (cont.)


Check ID

Violation

Description

GIGABIT_ETHERNET_XGMII_
RSVD_CONTROL_CHAR_
VIOLATION_P

Reserved control
characters should not be
used.

TXC/RXC indicate whether data or control


characters are being transmitted/received.
The TXC signal for a lane is asserted when a
control character is being sent. In XGMII,
only 5 characters are defined: Idle, Start,
Terminate, Error, and Sequence. All other
encodings are reserved. This check fires
when a reserved encoding is detected.

When Error Control


character is detected on Rx
lanes.

An Error Control Character should not be


present on Rx lanes while a frame is in
progress. This check fires when this
requirement is violated.

The sequence control


character should be
aligned to lane 0.

Status is signaled through a four byte


Sequence ordered set, with the sequence
control character on lane 0 and data on the
remaining three lanes. The sequence control
character must be aligned to lane 0. This
check fires if this requirement is violated.

The sequence ordered set


should not contain
reserved values.

The PHY indicates Local Fault with a


Sequence control character in lane 0, data
characters of 0x00 in lanes 1 and 2, and a
data character of 0x01 in lane 3.
The RS indicates a Remote Fault with a
Sequence control character in lane 0, data
characters of 0x00 in lanes 1 and 2, and a
data character of 0x02 in lane 3.
All other values are reserved for future use
and are not to be used. This check fires when
a Sequence ordered set contains a reserved
value.

The start frame delimiter


should be aligned to lane
3.

The preamble and SFD are transmitted


through the XGMII as octets sequentially
ordered on the lanes of the XGMII. If a start
control character is detected on lane 0 in the
previous clock edge, then the start frame
delimiter should be detected on lane 3. This
check fires if SFD is detected on any lane
other than lane 3.

GIGABIT_ETHERNET_XGMII_
RSVD_CONTROL_CHAR_
VIOLATION_N
GIGABIT_ETHERNET_XGMII_
RX_ERROR_CONTROL_
CHARACTER_DETECTED_P
GIGABIT_ETHERNET_XGMII_
RX_ERROR_CONTROL_
CHARACTER_DETECTED_N
GIGABIT_ETHERNET_XGMII_
SEQUENCE_ALIGNMENT_
VIOLATION_P
GIGABIT_ETHERNET_XGMII_
SEQUENCE_ALIGNMENT_
VIOLATION_N
GIGABIT_ETHERNET_XGMII_
SEQUENCE_OS_
VIOLATION_P
GIGABIT_ETHERNET_XGMII_
SEQUENCE_OS_
VIOLATION_N

GIGABIT_ETHERNET_XGMII_
SFD_ALIGNMENT_
VIOLATION_P
GIGABIT_ETHERNET_XGMII_
SFD_ALIGNMENT_
VIOLATION_N

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Monitor Checks

Table 8-30. XGMII Checks (cont.)


Check ID

Violation

Description

GIGABIT_ETHERNET_XGMII_
START_ALIGNMENT_
VIOLATION_P

The start control character


should be aligned to lane
0.

The Start control character indicates the


beginning of MAC data on the XGMII. The
start control character must be aligned to
lane 0 of the XGMII by the RS on transmit
and by the PHY on receive. This check fires
if a Start control character is detected on any
lane other than lane 0.

A start control character


for a new frame should not
be issued before
terminating previous
frame.

A new frame can begin only after the end of


current frame. Since the end of frame is
indicated by a Terminate character, a start
character for a new frame should follow a
terminate for the current frame. This check
fires when successive starts are detected
without an intervening terminate.

The terminate control


character should follow a
start control character.

Terminate control character on any lane


constitutes an end of frame delimiter for the
data stream. A terminate should not be
issued before a frame and should always
follow a start control character. This check
fires when a terminate control character is
detected before the start control character.

When Terminate is
detected, all lanes
following the terminate
character should carry idle
control character.

A terminate should be followed by idle


characters. If terminate is not in lane 3, then
all the lanes following the terminate should
be idle characters. This check fires when this
requirement is violated.

When Error Control


character is detected on Tx
lanes.

An Error Control Character should not be


present on Tx lanes while a frame is in
progress. This check fires when this
requirement is violated.

GIGABIT_ETHERNET_XGMII_
START_ALIGNMENT_
VIOLATION_N
GIGABIT_ETHERNET_XGMII_
START_BEFORE_TERM_
VIOLATION_P
GIGABIT_ETHERNET_XGMII_
START_BEFORE_TERM_
VIOLATION_N
GIGABIT_ETHERNET_XGMII_
TERM_BEFORE_START_
VIOLATION_P
GIGABIT_ETHERNET_XGMII_
TERM_BEFORE_START_
VIOLATION_N
GIGABIT_ETHERNET_XGMII_
TERMINATE_COLUMN_
VIOLATION_P
GIGABIT_ETHERNET_XGMII_
TERMINATE_COLUMN_
VIOLATION_N
GIGABIT_ETHERNET_XGMII_
TX_ERROR_CONTROL_
CHARACTER_DETECTED_P
GIGABIT_ETHERNET_XGMII_
TX_ERROR_CONTROL_
CHARACTER_DETECTED_N

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Monitor Checks

Table 8-31. XLGMII/CGMII Checks


Check ID

Violation

Description

GIGABIT_ETHERNET_
XLGMII_CGMII_START_
ALIGNMENT_VIOLATION

The start control


character should be
aligned to lane 0.

The Start control character indicates the


beginning of MAC data on the
XLGMII/CGMII. The start control character
must be aligned to lane 0 of the
XLGMII/CGMII by the RS on transmit and by
the PHY on receive. This check fires if a Start
control character is detected on any lane other
than lane 0.

GIGABIT_ETHERNET_
XLGMII_CGMII_SFD_
ALIGNMENT_VIOLATION

The start frame delimiter


should be aligned to lane
7.

The preamble and SFD are transmitted through


the XLGMII/CGMII as octets sequentially
ordered on the lanes of the XLGMII/CGMII. If
a start control character is detected on lane 0,
then the start frame delimiter should be
detected on lane 7. This check fires if SFD is
detected on any lane other than lane 7 or no
SFD detected on lane 7.

GIGABIT_ETHERNET_
XLGMII_CGMII_SEQUENCE_
ALIGNMENT_VIOLATION

The sequence control


character should be
aligned to lane 0.

Status is signaled through an eight byte


Sequence ordered set, with the sequence
control character on lane 0 and data on the
remaining 7 lanes. The sequence control
character must be aligned to lane 0. This check
fires if this requirement is violated.

GIGABIT_ETHERNET_
XLGMII_CGMII_SEQUENCE_
OS_VIOLATION

The sequence ordered set The PHY indicates Local Fault with a
should not contain
Sequence control character in lane 0, data
reserved values.
characters of 0x00 in lanes 1 and 2, a data
character of 0x01 in lane 3, and a 0x00 on
lanes 4 to 7.
The RS indicates a Remote Fault with a
Sequence control character in lane 0, data
characters of 0x00 in lanes 1 and 2, a data
character of 0x02 in lane 3, and a 0x00 on
lanes 4 to 7.
All other values are reserved for future use and
are not to be used. This check fires when a
Sequence ordered set contains a reserved
value.

GIGABIT_ETHERNET_
XLGMII_CGMII_TERM_
BEFORE_START_VIOLATION

The terminate control


Terminate control character on any lane
character should follow a constitutes an end of frame delimiter for the
start control character.
data stream. A terminate should not be issued
before a frame and should always follow a start
control character. This check fires when a
terminate control character is detected before
the start control character.

GIGABIT_ETHERNET_
XLGMII_CGMII_START_
BEFORE_TERM_VIOLATION

A start control character


for a new frame should
not be issued before
terminating previous
frame.

272

A new frame can begin only after the end of


the current frame. Since the end of frame is
indicated by a Terminate character, a start
character for a new frame should follow a
terminate for the current frame. This check
fires when successive starts are detected
without an intervening terminate.

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Gigabit Ethernet
Monitor Checks

Table 8-31. XLGMII/CGMII Checks (cont.)


Check ID

Violation

Description

GIGABIT_ETHERNET_
XLGMII_CGMII_IDLE_
BEFORE_TERM_VIOLATION

Idle was detected while


the frame is in progress.

Once a frame has started with a Start control


character, it must be terminated with a
Terminate character before sending Idle
characters. This check fires when Idle
characters are detected even before the frame is
terminated.

GIGABIT_ETHERNET_
XLGMII_CGMII_RSVD_
CONTROL_CHAR_
VIOLATION

Reserved control
characters should not be
used.

TXC/RXC indicate whether data or control


characters are being transmitted/received. The
TXC signal for a lane is asserted when a
control character is being sent.
In XLGMII/CGMII, only 5 characters are
defined: Idle, Start, Terminate, Error, and
Sequence. All other encodings are reserved.
This check fires when a reserved encoding is
detected.

GIGABIT_ETHERNET_
XLGMII_CGMII_IDLE_
COLUMN_VIOLATION

When the bus is idle, Idle Idle columns are transmitted in full columns,
control characters should except when a Terminate is detected, wherein
be detected on all lanes. only the remaining lanes are Idles.
This check fires when an Idle column is
detected with a non-Idle character.

GIGABIT_ETHERNET_
XLGMII_CGMII_TERMINATE_
COLUMN_VIOLATION

When Terminate is
detected, all lanes
following the terminate
character should carry
idle control character.

GIGABIT_ETHERNET_
XLGMII_CGMII_TX_ERROR_
CONTROL_CHARACTER_
DETECTED

Error control character is An Error Control Character should not be


detected on Tx interface. present on Tx lanes while a frame is in
progress. This check fires when this
requirement is violated.

GIGABIT_ETHERNET_
XLGMII_CGMII_RX_ERROR_
CONTROL_CHARACTER_
DETECTED

Error control character is An Error Control Character should not be


detected on Rx interface. present on Rx lanes while a frame is in
progress. This check fires when this
requirement is violated.

A terminate should be followed by idle


characters. If terminate is not in lane 7, then all
the lanes following the terminate should be
idle characters. This check fires when this
requirement is violated.

Table 8-32. TBI Checks


Check ID

Violations

GIGABIT_ETHERNET_TBI_
INVALID_10B_CG

Detected an invalid 10B code- Invalid 10B code-group that cannot be


group.
decoded into 8b.

GIGABIT_ETHERNET_TBI_
DISPARITY_ERROR_IN_K_CG

Disparity error in /K/ codegroup detected.

/K/code detected has wrong disparity.

GIGABIT_ETHERNET_TBI_
DISPARITY_ERROR_IN_D_CG

Disparity error in /D/ codegroup detected.

/D/ code detected has wrong disparity.

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Descriptions

273

Gigabit Ethernet
Monitor Checks

Table 8-32. TBI Checks (cont.)


Check ID

Violations

Descriptions

GIGABIT_ETHERNET_TBI_
LOSS_OF_SYNC

Synchronization lost on lane.

After achieving synchronization, it has


been lost on bus.

GIGABIT_ETHERNET_TBI_
T_NOT_FOLLOWED_BY_R_
VIOLATION

The terminate code-group /T/


should be followed by /R/
code-group.

Terminate code group /T/ sequence /T/R/ is


not correct.

GIGABIT_ETHERNET_TBI_
MULTI_OS_FIRST_CG_
VIOLATION

First code-group of
multigroup ordered set should
be transmitted on even
position.

First Code group of multigroup ordered set


must be on even position.

GIGABIT_ETHERNET_TBI_
EPD_OS_VIOLATION

In End of Packet (EPD), /T/


EPD rule violation. It should be either
must be followed by /R/R/ if
/T/R/ or /T/R/R/ if first /R/ is on even
first /R/ ends on even position. position.

GIGABIT_ETHERNET_TBI_
R_CG_VIOLATION

Code-group /R/ should follow


either /R/ or /T/ code-group.

Code-group /R/ occurrence violation. It


should be present either in carrier extension
or EPD.

GIGABIT_ETHERNET_TBI_
INVALID_CG_AFTER_K28_5

Code-group other than /D5.6/,


/D16.2/, /D21.5/, and /D2.2/
detected after /K28.5/.

Invalid code-group i.e., non-idle nonconfiguration code-group.

FIRST /I/ followed the packet


GIGABIT_ETHERNET_TBI_
INVALID_IDLE_OS_AFTER_PKT should restore negative
running disparity.

/I1/ and /I2/ occurrence violation. /I1/


should be there if running disparity at end
is positive, else /I2/ to maintain running
disparity negative.

GIGABIT_ETHERNET_TBI_
INVALID_IDLE_OS_AFTER_
CONFIGURATION_OS

FIRST /I/ followed the


configuration ordered set
should restore negative
running disparity.

/I1/ and /I2/ occurrence violation after


configuration. /I1/ should be there if
running disparity at end is positive, else /I2/
to maintain running disparity negative.

GIGABIT_ETHERNET_TBI_
T_BEFORE_S_VIOLATION

/T/ code-group should not


come before /S/ code-group.

Terminate code-group /T/ should be there


only when frame ends.

GIGABIT_ETHERNET_TBI_
MISALIGNED_D_CG

/D/ code-group is found at


invalid location.

/D/ code-group not a part of frame, IDLE,


or Configuration.

GIGABIT_ETHERNET_TBI_
ERROR_OS_DETECTED_
DURING_FRAME

Error /V/ code-group detected


while frame in progress.

/V/ code-group found in frame.

GIGABIT_ETHERNET_TBI_
ERROR_OS_DETECTED_
DURING_IDLE

Error /V/ code-group detected


during idle.

/V/ code-group found in IDLE.

GIGABIT_ETHERNET_TBI_
INVALID_I_OS

Subsequent /I/ should be /I2/


to ensure negative running
disparity.

When /I/ is in progress then if running


disparity is negative, then /I/ should be /I2/
to maintain negative running disparity.

GIGABIT_ETHERNET_TBI_
SPD_NOT_BEFORE_I_OR_R_OS

SPD /S/ should follow either


/I/ or /R/ ordered set.

Start of packet delimiter /S/ should come


only after IDLE or in Burst frame.

Invalid configuration ordered


GIGABIT_ETHERNET_TBI_
INVALID_CONFIGURATION_OS set detected.

Configuration Ordered set not transferred


with /D/ code group defined.

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Monitor Checks

Table 8-32. TBI Checks (cont.)


Check ID

Violations

Descriptions

GIGABIT_ETHERNET_TBI_
RESERVED_K_CG_DURING_
FRAME

Reserved /K/ code-group


detected during frame.

Reserved value of /K/ codes detected in


frame.

GIGABIT_ETHERNET_TBI_
RESERVED_K_CG_DURING_
IDLE

Reserved /K/ code-group


detected during idle.

Reserved value of /K/ codes detected


during IDLE.

GIGABIT_ETHERNET_TBI_
DISPARITY_NEUTRAL_000111_
ERROR

Sub-blocks encoded as
000111 should be generated
only when the running
disparity at the beginning of
the sub-block is positive.

The 8B/10B transmission code rules


specify that the sub-blocks encoded as
000111b or 0011b are generated only when
the running disparity at the beginning of the
sub-block is positive. The monitor fires
when this is violated.

GIGABIT_ETHERNET_TBI_
DISPARITY_NEUTRAL_111000_
ERROR

Sub-blocks encoded as
111000 should be generated
only when the running
disparity at the beginning of
the sub-block is negative.

The 8B/10B transmission code rules


specify that the sub-blocks encoded as
111000b or 1100b are generated only when
the running disparity at the beginning of the
sub-block is negative. The monitor fires
when this is violated.

GIGABIT_ETHERNET_TBI_
DISPARITY_NEUTRAL_0011_
ERROR

Sub-blocks encoded as 0011


should be generated only
when the running disparity at
the beginning of the sub-block
is positive.

The 8B/10B transmission code rules


specify that the sub-blocks encoded as
000111b or 0011b are generated only when
the running disparity at the beginning of the
sub-block is positive. The monitor fires
when this is violated.

GIGABIT_ETHERNET_TBI_
DISPARITY_NEUTRAL_1100_
ERROR

Sub-blocks encoded as 1100


should be generated only
when the running disparity at
the beginning of the sub-block
is negative.

The 8B/10B transmission code rules


specify that the sub-blocks encoded as
111000b or 1100b are generated only when
the running disparity at the beginning of the
sub-block is negative. The monitor fires
when this is violated.

Table 8-33. XAUI Checks


Check ID

Violation

Description

GIGABIT_ETHERNET_XAUI_
10B_CODE_VIOLATION_P

Detected an invalid 10B


code group.

Valid 10B symbols should be detected on the


lanes. If the detected 10B code group does not
correspond to either (+ve or -ve running
disparity) column, then the symbol is
considered to be invalid. This check fires if an
invalid 10B code group is detected on the lane.

GIGABIT_ETHERNET_XAUI_
10B_CODE_VIOLATION_N

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Monitor Checks

Table 8-33. XAUI Checks (cont.)


Check ID

Violation

Description

GIGABIT_ETHERNET_XAUI_
ALIGN_COL_VIOLATION_P

In an Align column, all


the code-groups should
be K28.3.

Idle ordered sets (||I||) are transmitted in full


columns continuously and repetitively
whenever the XGMII is idle. If one of the lanes
carries a Align character, then all the lanes in
that column must carry Align characters. This
check fires when an Align character is detected
on at least one lane but not on all lanes.

The first ||I|| following


||T|| should not be ||A||
and should alternate
between ||A|| and ||K||.

The first ||I|| following ||T|| alternates between


||A|| or ||K||. This check fires when an ||A||
column is detected when ||K|| was expected.

Data character(s)
detected during idle
period between frames.

Once a frame has been terminated, the inter


frame gap until the start of next fame should be
filled with Idle. This check fires when a data
character is detected between two frames.

Disparity error detected.

The incoming 10B symbol may not be found in


the column being searched (as indicated by the
disparity). However, this would result in
disparity errors. This check fires for legal codes
that violate disparity.

Subblocks encoded as
000111 should be
generated only when the
running disparity at the
beginning of the subblock
is positive.

The 8B/10B transmission code rules specify


that the subblocks encoded as 000111b or
0011b are generated only when the running
disparity at the beginning of the subblock is
positive. The monitor fires when this is
violated.

Subblocks encoded as
0011 should be generated
only when the running
disparity at the beginning
of the subblock is
positive.

The 8B/10B transmission code rules specify


that the subblocks encoded as 000111b or
0011b are generated only when the running
disparity at the beginning of the subblock is
positive. The monitor fires when this is
violated.

GIGABIT_ETHERNET_XAUI_
ALIGN_COL_VIOLATION_N
GIGABIT_ETHERNET_XAUI_
ALIGNS_AFTER_SUCCESSIVE_
TERM_P
GIGABIT_ETHERNET_XAUI_
ALIGNS_AFTER_SUCCESSIVE_
TERM_N
GIGABIT_ETHERNET_XAUI_
DATA_CHAR_DURING_IDLE_P
GIGABIT_ETHERNET_XAUI_
DATA_CHAR_DURING_IDLE_N
GIGABIT_ETHERNET_XAUI_
DISPARITY_ERROR_P
GIGABIT_ETHERNET_XAUI_
DISPARITY_ERROR_N
GIGABIT_ETHERNET_XAUI_
DISPARITY_NEUTRAL_000111_
ERROR_P
GIGABIT_ETHERNET_XAUI_
DISPARITY_NEUTRAL_000111_
ERROR_N
GIGABIT_ETHERNET_XAUI_
DISPARITY_NEUTRAL_0011_
ERROR_P
GIGABIT_ETHERNET_XAUI_
DISPARITY_NEUTRAL_0011_
ERROR_N

276

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Gigabit Ethernet
Monitor Checks

Table 8-33. XAUI Checks (cont.)


Check ID

Violation

Description

GIGABIT_ETHERNET_XAUI_
DISPARITY_NEUTRAL_1100_
ERROR_P

Subblocks encoded as
1100 should be generated
only when the running
disparity at the beginning
of the subblock is
negative.

The 8B/10B transmission code rules specify


that the subblocks encoded as 111000b or
1100b are generated only when the running
disparity at the beginning of the subblock is
negative. The monitor fires when this is
violated.

Subblocks encoded as
111000 should be
generated only when the
running disparity at the
beginning of the subblock
is negative.

The 8B/10B transmission code rules specify


that the subblocks encoded as 111000b or
1100b are generated only when the running
disparity at the beginning of the subblock is
negative. The monitor fires when this is
violated.

When error control


character is present on
bus while frame is in
progress.

An Error Control Character should not be


present on bus while a frame is in progress.
This check fires when this requirement is
violated.

When error control


character is present on
bus while interframe in
progress.

An Error Control Character should not be


present on bus while a interframe gap is in
progress. This check fires when this
requirement is violated.

Control character other


than Terminate,
Sequence, or Error
detected during a frame.

The defined control characters are Start,


Terminate, Idle, Error, Sequence (used for fault
signalling). Of these, once a frame has
commenced, then the only legal control
characters are Terminate, Sequence, and Error.
This check fires when a control character other
than these is detected during frame reception.

Reserved control
characters should not be
detected during idle.

When no frame is in progress (during idle


period), the legal control characters are Start,
Terminate, Idle, Error, and Sequence. This
check fires when a control character other than
these is detected during idle.

GIGABIT_ETHERNET_XAUI_
DISPARITY_NEUTRAL_1100_
ERROR_N
GIGABIT_ETHERNET_XAUI_
DISPARITY_NEUTRAL_111000_
ERROR_P
GIGABIT_ETHERNET_XAUI_
DISPARITY_NEUTRAL_111000_
ERROR_N
GIGABIT_ETHERNET_XAUI_
ERROR_CTRL_CHAR_DURING_
FRAME_P
GIGABIT_ETHERNET_XAUI_
ERROR_CTRL_CHAR_DURING_
FRAME_N
GIGABIT_ETHERNET_XAUI_
ERROR_CTRL_CHAR_DURING_
IDLE_P
GIGABIT_ETHERNET_XAUI_
ERROR_CTRL_CHAR_DURING_
IDLE_P
GIGABIT_ETHERNET_XAUI_
INVALID_CTRL_CHAR_DURING_
FRAME_P
GIGABIT_ETHERNET_XAUI_
INVALID_CTRL_CHAR_DURING_
FRAME_N
GIGABIT_ETHERNET_XAUI_
INVALID_CTRL_CHAR_DURING_
IDLE_P
GIGABIT_ETHERNET_XAUI_
INVALID_CTRL_CHAR_DURING_
IDLE_N

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Monitor Checks

Table 8-33. XAUI Checks (cont.)


Check ID

Violation

Description

GIGABIT_ETHERNET_XAUI_
LOSS_OF_ALIGNMENT_P

When Alignment is lost


on bus.

||A|| column should be received on all lanes in


parallel. If any /A/ is received but not on all
lanes consecutively for 4 times, then this check
is fired.

When Synchronization is
lost on bus.

Four continuos invalid symbol should not be


received for proper synchronization. This check
fires when this requirement is violated.

No more than a
maximum of 31 non-||A||
columns should be
detected between two
||A|| columns.

The Align or ||A|| ordered_set consists of a


unique special code-group, also known as Align
or /A/ in each lane. /A/ is not used in any other
ordered_set. Each ||A|| is sent after r non-||A||
columns where r is a uniform randomly
distributed number between 16 and 31,
inclusive. This check fires when the two ||A||
violate the maximum |A|| interval requirements.

A minimum of 16 non||A|| columns should be


detected between two
||A|| columns.

The Align or ||A|| ordered set consists of a


unique special code-group, also known as Align
or /A/ in each lane. /A/ is not used in any other
ordered_set. Each ||A|| is sent after r non-||A||
columns where r is a uniform randomly
distributed number between 16 and 31,
inclusive. This check fires when two ||A|| did
not meet the minimum interval requirements.

The ||T|| should be


followed by an ||A|| or
||K|| in the next column.

The first ||I|| following the terminate column is


always an ||A|| or ||K||. This check fires when
the column that immediately follows a
terminate is neither an ||A|| nor a ||K||.

The second ||I|| following


a ||T|| should be an ||R|| or
||Q||.

The ||R|| (Skip ordered set) is included in the


PCS Idle sequence to allow for clock rate
compensation in the case of multiple clock
domains. ||R|| can be inserted anywhere in the
Idle stream starting with the second column
following the terminate column ||T||. Given that
an ||A|| can come on the first clock after ||T||, the
second clock after a ||T|| can be a ||Q|| since a
||Q|| has to follow an ||A||. This check fires when
the second column that follows a terminate is
neither an ||R|| nor a ||Q||.

GIGABIT_ETHERNET_XAUI_
LOSS_OF_ALIGNMENT_N
GIGABIT_ETHERNET_XAUI_
LOSS_OF_SYNC_P
GIGABIT_ETHERNET_XAUI_
LOSS_OF_SYNC_N
GIGABIT_ETHERNET_XAUI_
MAX_ALIGN_SPACING_
VIOLATION_P
GIGABIT_ETHERNET_XAUI_
MAX_ALIGN_SPACING_
VIOLATION_N
GIGABIT_ETHERNET_XAUI_
MIN_ALIGN_SPACING_
VIOLATION_P
GIGABIT_ETHERNET_XAUI_
MIN_ALIGN_SPACING_
VIOLATION_N
GIGABIT_ETHERNET_XAUI_
NON_ALIGN_OR_SYNC_AFTER_
TERM_P
GIGABIT_ETHERNET_XAUI_
NON_ALIGN_OR_SYNC_AFTER_
TERM_N
GIGABIT_ETHERNET_XAUI_
SECOND_COL_FROM_TERM_
NOT_SKP_OR_SEQ_P
GIGABIT_ETHERNET_XAUI_
SECOND_COL_FROM_TERM_
NOT_SKP_OR_SEQ_N

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Monitor Checks

Table 8-33. XAUI Checks (cont.)


Check ID

Violation

Description

GIGABIT_ETHERNET_XAUI_
SEQUENCE_ALIGNMENT_
VIOLATION_P

A sequence control
character should not be
placed on any lane other
than lane zero.

The Sequence or ||Q|| ordered set directly maps


to the XGMII Sequence control character on
lane 0 followed by three data characters in
XGMII lanes 1 through 3. ||Q|| indicates to the
PCS that a link status message has been
initiated. This check fires whenever a Sequence
control character is detected on a lane other
than 0.

A ||Q|| should always


follow an ||A||.

Sequence ordered-sets are always sent over the


PMA service interface in the column that
follows an ||A|| ordered set. The Sequence
ordered-sets do not otherwise interfere with the
randomized ||I|| sequence. This check fires
when a ||Q|| follows a non-||A|| column.

Lane to lane skew should


not be greater than the
maximum limit of 41BT.

The definition of a 10GBASE-X ordered set


guarantees that align code groups are
simultaneously initiated on all lanes at the
transmitter and the maximum allowable lane to
lane skew at the receive interface is 41 BTs.
This check fires when the skew at the receive
interface exceeds this maximum limit.

In a Skip column, all the


code-groups should be
K28.0.

Idle ordered sets (||I||) are transmitted in full


columns continuously and repetitively
whenever the XGMII is idle. If one of the lanes
carries a Skip character, then all the lanes in
that column must carry Skip characters. This
check fires when a Skip character is detected on
at least one lane but not on all lanes.

A start control character


should not be placed on
any lane other than lane
zero.

The Start or ||S|| ordered set directly maps to the


XGMII Start control character in lane 0
followed by any three data characters in XGMII
lanes 1 through 3. This check fires when a start
control character is detected on a lane other
than lane 0.

In a Sync column, all the


code-groups should be
K28.5.

Idle ordered sets (||I||) are transmitted in full


columns continuously and repetitively
whenever the XGMII is idle. If one of the lanes
carries a Sync character, then all the lanes in
that column must carry Sync characters, except
for the column in which a terminate is detected
(here it is a partial column of Sync characters).
This check fires when a Sync character is
detected on at least one lane but not on all
lanes.

GIGABIT_ETHERNET_XAUI_
SEQUENCE_ALIGNMENT_
VIOLATION_N
GIGABIT_ETHERNET_XAUI_
SEQUENCE_NOT_FOLLOWING_
ALIGN_P
GIGABIT_ETHERNET_XAUI_
SEQUENCE_NOT_FOLLOWING_
ALIGN_N
GIGABIT_ETHERNET_XAUI_
SKEW_LIMIT_VIOLATION_P
GIGABIT_ETHERNET_XAUI_
SKEW_LIMIT_VIOLATION_N
GIGABIT_ETHERNET_XAUI_
SKIP_COL_VIOLATION_P
GIGABIT_ETHERNET_XAUI_
SKIP_COL_VIOLATION_N
GIGABIT_ETHERNET_XAUI_
START_ALIGNMENT_
VIOLATION_P
GIGABIT_ETHERNET_XAUI_
START_ALIGNMENT_
VIOLATION_N
GIGABIT_ETHERNET_XAUI_
SYNC_COL_VIOLATION_P
GIGABIT_ETHERNET_XAUI_
SYNC_COL_VIOLATION_N

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Monitor Checks

Table 8-33. XAUI Checks (cont.)


Check ID

Violation

Description

GIGABIT_ETHERNET_XAUI_
SYNCS_AFTER_SUCCESSIVE_
TERM_P

The first ||I|| following


||T|| should not be ||K||
and should alternate
between ||A|| and ||K||.

The first ||I|| following ||T|| alternates between


||A|| or ||K||, except if an ||A|| is to be sent and
the ||A|| spacing counter has not expired, then a
||K|| is sent instead. This check fires when a ||K||
column is detected when ||A|| was expected.

The terminate code-group


should be followed by
sync code-groups in that
column.

The Terminate or ||T|| ordered set directly maps


to the XGMII Terminate control character
located in any lane, preceded by data characters
and followed by Idle characters if Terminate is
not in lane 3. These Idle characters must be
Sync characters. This check fires when the
terminate character is followed by a non-Sync
character in that column.

GIGABIT_ETHERNET_XAUI_
SYNCS_AFTER_SUCCESSIVE_
TERM_N
GIGABIT_ETHERNET_XAUI_
TERMINATE_OS_ERROR_P
GIGABIT_ETHERNET_XAUI_
TERMINATE_OS_ERROR_N

Table 8-34. BASER Checks


Check ID

Violation

Description

GIGABIT_ETHERNET_BASER_ Block type field should be


defined.
INVALID_BLOCK_TYPE

The control blocks begin with an 8-bit


block type field that indicates the format
of the remainder of the block. The block
type is a standard defined value,
depending on the contents of the block.
This check fires when an undefined value
is detected on the block type field.

GIGABIT_ETHERNET_BASER_ Control blocks of type 0x1E


should contain codes of either
INVALID_CTRL_CODE_
Idle or Error control characters.
TYPE_1E

The 10GBASE-R family of PHYs use the


64B/66B encoding scheme where every
64 bits of data is converted to either a
data block or a control block. A control
block with block type of 8'h1E should
have all 8 control characters and must be
used only for encoding idle or error
control characters. This check fires when
other control codes are tagged with this
block type.

GIGABIT_ETHERNET_BASER_
INVALID_O_CODE_
VIOLATION

280

The O-Code that encodes the /Q/


control character should be
encoded with all zeros or all
ones.

In 64B/66B encoding scheme, ordered


sets are encoded using a 4-bit O code.
The ||Q|| (sequence ordered set) is
encoded using an O-code of 4'b0. This
check fires when a ||Q|| is encoded with a
nonzero O-code value.

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Gigabit Ethernet
Monitor Checks

Table 8-34. BASER Checks (cont.)


Check ID

Violation

Description

GIGABIT_ETHERNET_BASER_ Synchronization header should


be either 2'b01 or 2'b10.
INVALID_SYNC_HEADER

In 64B/66B encoding scheme, 64-bits of


data is converted into one 66B block. The
lowest order two bits, called the
synchronization header, indicates
whether what follows is a data or a
control block. In addition, the
synchronization headers of the code
enable the receiver to achieve block
alignment on the incoming PHY bit
stream. The allowed values for sync
header are 2'b01 and 2'b10. This check
fires when a sync header contains 2'b00
or 2'b11.

GIGABIT_ETHERNET_BASER_ The null fields in a 66b block


should be encoded with zero on
NULL_VALUE_VIOLATION
transmit.

In the case of control blocks containing a


Start or Terminate character, that
character is implied by the block type
field. In these blocks, some bits are
unused and are null fields. These are sent
as zero and ignored upon receipt. This
check fires if these are nonzero on a
transmit interface.

GIGABIT_ETHERNET_BASER_ The control codes following a


TERMINATE_BLOCK_ERROR terminate character in a 66b
block should be zeros, indicating
Idles.

A terminate character must be followed


by idle control characters in all the lanes
in that column. This check fires when a
Terminate block has non-Idle control
codes on any of the lanes following the
terminate character.

GIGABIT_ETHERNET_BASER_ Block contains error control


character.
BLOCK_CONTAINS_ERROR_
CONTROL_CHARACTER

This check is fired whenever error code


for /E/ is found on the bus.

GIGABIT_ETHERNET_BASER_ Block contains reserved control


character.
BLOCK_CONTAINS_
RESERVED_CONTROL_
CHARACTER

This check is fired whenever control


character reserved0, reserved1,
reserved2, reserved3, reserved4, or
reserved5 is found on the bus.
This check is not valid for XLAUI/CAUI
interfaces.

GIGABIT_ETHERNET_BASER_
START_OR_IDLE_BLOCK_
EXPECTED

Block after an idle control block


reception is not a start control
block, Idle block and ordered set
control block.

While idle control blocks are being


received, only start control block, Idle
block, and ordered set control block
should follow. This check is fired when
this requirement is violated.

GIGABIT_ETHERNET_BASER_
TERMINATE_OR_CONTROL_
BLOCK_EXPECTED

Control block other than


terminate block or Error is
received during transmission of
data blocks.

While data blocks are being received,


only terminate block and Error Control
Blocks would be possible valid blocks.
This check fires when some other control
block is received.

GIGABIT_ETHERNET_BASER_
INVALID_CONTROL_
CHARACTER

Control character contains a


value other than 0x00, 0x1e,
0x2d, 0x33, 0x4b, 0x55, 0x66, or
0x78 (Section 49.2.4.6).

Control character should be among one of


the values: 0x00, 0x1e, 0x2d, 0x33, 0x4b,
0x55, 0x66,or 0x78 else the block is
invalid. This check is fired whenever
block contains a control character with
some other value.

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Monitor Checks

Table 8-34. BASER Checks (cont.)


Check ID

Violation

Description

GIGABIT_ETHERNET_BASER_ Sequence OS should not be


reserved values.
SEQUENCE_OS_VIOLATION

A sequence should have valid values.


This check is fired when this requirement
is not met.

GIGABIT_ETHERNET_BASER_ Bits 65:38 of ordered set block


should contain all zeros.
NON_ZERO_BITS_IN_O_
ORDERED_SET_P

This check is fired when bits 65 to 38 of


ordered set block is non-zero. This check
is only valid for XLAUI/ CAUI interface.

Table 8-35. XLAUI/CAUI Checks


Check ID

Violation

Description

GIGABIT_ETHERNET_BASER_
AM_INVLD_CNT_4

Four consecutive invalid


alignment marker received.

This check fires when am_invld_cnt


reaches 4 value and transitions from
INVALID_AM to SLIP state. This
represents the loss of AM lock.

GIGABIT_ETHERNET_BASER_
AM_COUNTER_EXPIRED

Alignment marker not received This check fires when alignment marker
after am_counter reached
not received after am_counter expires.
maximum value.
This check not valid for first alignment
marker after AM_RESET_CNT state.

GIGABIT_ETHERNET_BASER_
AM_BIP_ERROR

BIP error in received


alignment marker.

This check fires when expected BIP is


not present in received alignment
marker. This check is not valid for first
alignment marker after
AM_RESET_CNT state.

GIGABIT_ETHERNET_BASER_
AM_NOT_MATCHING

Alignment marker not


matching previous alignment
marker value on lane.

This check fires when dynamic lane


reorder happens. For example, if AM0
received on physical lane 0 first time and
then on physical lane 2 next time, this
check fires.

GIGABIT_ETHERNET_BASER_
AM_BIP_ON_M3_NOT_
MATCHING_BIP_ON_M7

BIP on position M3 is not


inversion of BIP on M7 in a
received alignment marker.

BIP7 is simply bit-wise inversion of


BIP3. This check fires if above rule is
violated.

GIGABIT_ETHERNET_BASER_
SH_INVLD_CNT_MAX

Sync header invalid count


reached maximum value.

This check fires when sh_invld_cnt


reaches 65 value and transitions from
INVALID_SH to SLIP state. This
represents the loss of lane lock.

GIGABIT_ETHERNET_BASER_
LANE_LOCK_FAIL_AFTER_
MAX_SLIP

Block lock not achieved after


maximum number of slip (64).

A receiving device should synchronize


to proper boundary within first 64 slips.
This check fires when lane lock is not
achieved within the first 64 slips.

GIGABIT_ETHERNET_BASER_
SKEW_MORE_THAN_MAX

Skew among lanes reached


maximum configured skew.

This check fires when skew among lanes


crosses a value of 1856 bits (29
symbols) in case of XLAUI and 928 (15
symbols) in case of CAUI.

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Monitor Checks

Table 8-35. XLAUI/CAUI Checks (cont.)


Check ID

Violation

Description

GIGABIT_ETHERNET_BASER_
AM_ON_FEWER_LANES_
AFTER_DSKEW_DONE

Alignment marker not received This check fires when there are
on all lanes after deskew done. alignment marker on at least one lane but
not on all lane. This check is not valid
for first alignment marker after
AM_RESET_CNT state.

GIGABIT_ETHERNET_BASER_
PARAM_PHYSICAL_LANE_
COUNT_ERR

Illegal value specified for


physical lane count parameter.

This is parameter check. Valid values


are:
XLAUI: 1, 2, and 4.
CAUI: 1, 2, 4, 5, 10, and 20.
This check fires if different value is set
for PHYSICAL_LANE_COUNT
parameter.

Table 8-36. 40/100G Auto-Negotiation Checks


Check ID

Violation

Description

GIGABIT_ETHERNET_AN_
MANCHESTER_DELIMITER_
VIOLATION

Manchester delimiter duration in


DME data should be valid.

Once the synchronization for DME


pages is achieved, Manchester
violation delimiter should be valid.

GIGABIT_ETHERNET_AN_
CLOCK_TRANSITION_
VIOLATION

Clock to clock transition in DME


data should be in prescribed
limits.

Clock transition not received within


maximum specified duration.

GIGABIT_ETHERNET_AN_
DATA_TRANSITION_
VIOLATION

Data to data transition in DME


data should be in prescribed
limits.

After a clock transition, data transition


should happen within the specified
duration range.

GIGABIT_ETHERNET_AN_
RSVD_OR_UNSUPPORTED_
ELECTOR_FIELD

Reserved or unsupported selector


field transmitted.

The selector field in link codeword


S[4:0] should be 00001 corresponding
to IEEE Std 802.3. Any other field
value shall be treated as a violation.

GIGABIT_ETHERENT_AN_
NON_ZERO_ECHOED_
NONCE_FIELD_WITH_ZERO_
ACK

Echoed nonce field transmitted is


non-zero while Acknowledge bit
is set to logical zero.

When Acknowledge is set to zero in


base link codeword, the bits in Echoed
nonce field should contain logical
zeros.

GIGABIT_ETHERNET_AN_
ECHOED_NONCE_DOES_
NOT_MATCH_TX_NONCE_
FROM_LP

Echoed nonce does not match


When Acknowledge is set to one in
nonce transmitted by link partner. base link codeword, the bits in Echoed
nonce field should contain the value
received from link partner.

GIGABIT_ETHERNET_AN_
NON_ZERO_RSVD_TECH_
ABILITY_FIELD

Reserved technology ability field


bits transmitted are non-zero.

Questa Verification Library Monitors Data Book, v2010.2

Reserved Technology ability field bits


should be transmitted as zero.

283

Gigabit Ethernet
Monitor Checks

Table 8-36. 40/100G Auto-Negotiation Checks


Check ID

Violation

Description

GIGABIT_ETHERNET_AN_
FEC_REQUESTED_WITH_
NO_ABILITY

FEC request sent by local device


without ability field set to one.

The FEC requested bit may be set to


logical one only if FEC ability bit is
set to logical one.

GIGABIT_ETHERNET_AN_
NULL_MESSAGE_CODE_
NOT_TRANSMITTED

Next page transmitted without


NULL message code even with
NP bit set to logical zero in
previous link codeword.

If a device has no next pages to send


and its link partner has set the NP bit
to logical one, it should transmit next
pages with NULL message code.

GIGABIT_ETHERNET_AN_
MP_BIT_UNSET_DURING_
NULL_MESSAGE_CODE

MP bit is set to logical zero in


next page transmitted with NULL
message code.

If a device has no next pages send and


its link partner has set the NP bit to
logical one, it should transmit message
next pages with MP bit set.

GIGABIT_ETHERNET_AN_
NULL_HCD_RESOLVED

On Auto-Negotiation completion, On entering AN GOOD CHECK state,


resolved HCD has value NULL. the resolved HCD technology happens
to be NULL. Although this is not a
protocol violation, this check is kept
for integrity.

GIGABIT_ETHERNET_AN_
NON_NULL_MESSAGE_
CODE_TRANSMITTED_
AFTER_NULL_MESSAGE_
CODE

Next page transmitted has non


NULL message code while
previous codeword has NULL
message code.

If a device has no next pages to send


and its link partner has set the NP bit
to logical one, it should transmit next
pages with NULL message code. All
following message codes should
contain NULL message code.

GIGABIT_ETHERNET_AN_
NP_BIT_SET_AFTER_NP_
BIT_UNSET

Next page transmitted with NP


set to logical one while previous
codeword has NP bit set to logical
zero.

If a device has no next pages to send,


it shall set NP bit to logical zero. This
check is fired if any subsequent page
contains NP bit set to logical one.

Toggle bit inverted even when


GIGABIT_ETHERNET_AN_
TOGGLE_BIT_TRANSMITTED_ NEXT PAGE WAIT has not
reached.
INVERSED

The toggle bit is inverted only during


a transition from COMPLETE
ACKNOWLEDGE state to NEXT
PAGE WAIT state. This check is fired
if toggle bit is inverted in any other
state.

GIGABIT_ETHERNET_AN_
NUMBER_OF_ACK_PAGES_
OUT_OF_RANGE

Number of codewords
transmitted in COMPLETE
ACKNOWLEDGE state is out of
range.

While in COMPLETE
ACKNOWLEDGE state, number of
frames transmitted should be from 6 to
8. This check is fired if the number of
frames fall out of this range

GIGABIT_ETHERNET_AN_
DISSIMILAR_PAGE_
TRANSMITTED

Current link codeword


transmitted should be the same as
previous link codeword.

The transmitted frame changes its


value only when either Acknowledge
bit is set during ACKNOWLEDGE
DETECT state or in the first
transmitted frame during NEXT
PAGE WAIT state. This check is fired
if transmitted frame changes in cases
excluding the mentioned ones.

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Monitor Corner Cases

Table 8-36. 40/100G Auto-Negotiation Checks


Check ID

Violation

Description

GIGABIT_ETHERNET_AN_
INVALID_ACK_BIT_
TRANSMISSION

Acknowledge bit transmitted has


an invalid value in current
transmitted codeword.

Acknowledge bit value transmitted


should be 1'b1 in ACKNOWLEDGE
DETECT and COMPLETE
ACKNOWLEDGE state only. It
should be switched to 1'b0 (when
toggle bit also toggles) when
switching to NEXT PAGE WAIT
state.

GIGABIT_ETHERNET_AN_
PAGE_DETECTED_AFTER_
AUTONEG_COMPLETION

Page detected after auto


negotiation completion.

On entering AN GOOD CHECK state,


AN frame should not be detected until
the break_link_timer is done.

Monitor Corner Cases


Table 8-37 shows the corner cases maintained by the Gigabit Ethernet monitor.
Table 8-37. Gigabit Ethernet Corner Cases
Corner Case

Description

66-bit blocks with terminate on octet 0

Number of 66-bit blocks with terminate on octet 0. This is


collected only by the BASER monitor.

66-bit blocks with terminate on octet 1

Number of 66-bit blocks with terminate on octet 1. This is


collected only by the BASER monitor.

66-bit blocks with terminate on octet 2

Number of 66-bit blocks with terminate on octet 2. This is


collected only by the BASER monitor.

66-bit blocks with terminate on octet 3

Number of 66-bit blocks with terminate on octet 3. This is


collected only by the BASER monitor.

66-bit blocks with terminate on octet 4

Number of 66-bit blocks with terminate on octet 4. This is


collected only by the BASER monitor.

66-bit blocks with terminate on octet 5

Number of 66-bit blocks with terminate on octet 5. This is


collected only by the BASER monitor.

66-bit blocks with terminate on octet 6

Number of 66-bit blocks with terminate on octet 6. This is


collected only by the BASER monitor.

66-bit blocks with terminate on octet 7

Number of 66-bit blocks with terminate on octet 7. This is


collected only by the BASER monitor.

Align ordered sets

Number of align ordered sets. This is collected only by the


XAUI monitor.

Blocks starting on octet 4 with an ordered set


on the first four octets

Number of blocks starting on octet 4 with an ordered set on the


first four octets. This is collected only by the BASER monitor.
This is not valid for XLAUI/CAUI interfaces.

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Gigabit Ethernet
Monitor Corner Cases

Table 8-37. Gigabit Ethernet Corner Cases (cont.)


Corner Case

Description

Blocks starting on octet 4 with idle on the first


four octets

Number of blocks starting on octet 4 with idle on the first four


octets. This is collected only by the BASER monitor.
This is not valid for XLAUI/CAUI interfaces.

Alignment marker blocks

Number of alignment marker received. This is only valid for


40/100G.

Blocks with start on octet 0

Number of blocks with start on octet 0. This is collected only


by the BASER monitor.

Carrier extensions

Number of carrier extensions. This is collected only by the


GMII monitor.

Collisions

Number of collisions. This is collected only by the GMII and


MII monitors.

Control frames

Number of control frames.

Data frames

Number of data frames.

Error blocks

Number of error blocks. This is collected only by the BASER


monitor.

False carriers

Number of false carriers. This is collected only by the GMII


and MII monitors.

Frame bursts

Number of back-to-back frames without idle in between. This


is collected only by the GMII monitor.

Frames with globally administered addresses

Number of frames with globally administered addresses.

Frames with individual addresses

Number of frames with individual addresses.

Frames with locally administered addresses

Number of frames with locally administered addresses.

Frames with multicast/group addresses

Number of frames with multicast/group addresses.

Frames with terminate on lane 0

Number of frames with terminate on lane 0. This is collected


only by the XLGMII/CGMII and XGMII monitors.

Frames with terminate on lane 1

Number of frames with terminate on lane 1. This is collected


only by the XLGMII/CGMII and XGMII monitors.

Frames with terminate on lane 2

Number of frames with terminate on lane 2. This is collected


only by the XLGMII/CGMII and XGMII monitors.

Frames with terminate on lane 3

Number of frames with terminate on lane 3. This is collected


only by the XLGMII/CGMII and XGMII monitors.

Frames with terminate on lane 4

Number of frames with terminate on lane 4. This is collected


only by the XLGMII/CGMII monitors.

Frames with terminate on lane 5

Number of frames with terminate on lane 5. This is collected


only by the XLGMII/CGMII monitors.

Frames with terminate on lane 6

Number of frames with terminate on lane 6. This is collected


only by the XLGMII/CGMII monitors.

Frames with terminate on lane 7

Number of frames with terminate on lane 7. This is collected


only by the XLGMII/CGMII monitors.

Idle blocks

Number of idle blocks. This is collected only by the BASER


monitor.

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Gigabit Ethernet
Monitor Statistics

Table 8-37. Gigabit Ethernet Corner Cases (cont.)


Corner Case

Description

Jumbo data frames

Number of jumbo data frames.

Local faults

Number of local faults. This is collected only by the XGMII


monitor.

Packets of max_frame_size

Number of packets of max_frame_size.

Packets of min_frame_size

Number of packets of min_frame_size.

Packets with padding

Number of packets with padding.

Priority tagged data frames

Number of priority tagged data frames.

Priority tagged jumbo frames

Number of priority tagged jumbo frames.

Priority tagged pause control frames

Number of priority tagged pause control frames.

Remote faults

Number of remote faults. This is collected only by the XGMII


monitor.

Skip ordered set

Number of skip ordered sets. This is collected only by the


XAUI monitor.

Sync ordered sets

Number of sync ordered sets. This is collected only by the


XAUI monitor.

Untagged data frames

Number of untagged data frames.

Untagged jumbo frames

Number of untagged jumbo frames.

Untagged pause control frames

Number of untagged pause control frames.

Valid 66-bit control blocks

Number of valid 66-bit control blocks. This is collected only


by the BASER monitor.

Valid 66-bit data blocks

Number of valid 66-bit data blocks. This is collected only by


the BASER monitor.

VLAN tagged data frames

Number of VLAN tagged data frames.

VLAN tagged jumbo frames

Number of VLAN tagged jumbo frames.

VLAN tagged pause control frames

Number of VLAN tagged pause control frames.

Monitor Statistics
Table 8-38 shows the statistics maintained by the Gigabit Ethernet monitor.
Table 8-38. Gigabit Ethernet Protocol Statistics
Statistic

Description

Total frames

Total number of frames.

Valid 66-bit blocks

Number of valid 66-bit blocks.

Frames with length between 1518 and 1536

Number of frames with length between 1518 and 1536.

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Monitor Statistics

Table 8-38. Gigabit Ethernet Protocol Statistics (cont.)

288

Statistic

Description

Total base pages

Number of base pages.

Total next pages

Number of next pages.

Message next pages

Number of message next pages.

Unformatted next pages

Number of unformatted next pages.

Null Message codes

Number of pages with Null message codes.

Questa Verification Library Monitors Data Book, v2010.2

Chapter 9
High-Definition Multimedia Interface (HDMI)
Introduction
This monitor checks the HDMI TMDS interface for compliance with HDMI 1.3a specification
and protocol.
HDMI 1.3a is designed to provide transmitting digital television audiovisual signals for DVD
players, set-top boxes and other audiovisual sources to television sets, projectors, and other
video displays.

Reference Documentation
This QVL HDMI monitor is modeled from the requirements provided in the following
documents:

High-Definition Multimedia Interface (HDMI), Specification Version 1.3a, November


10, 2006.

Supported Features
HDMI supports the following features:

HDMI is compatible with Digital Visual Interface (DVI), Revision 1.0, April 2, 1999.

HDMI link includes three Transition Minimized Differential Signaling (TMDS) Data
channels and a single TMDS Clock channel.

User configurable interfaces are as follows:


o

8-bits native interface per TMDS Data channel.

10-bits TMDS encoded interface per TMDS Data channel.

Serial interface per each TMDS Data channel.

User configurable TMDS Clock channel.

10-bits TMDS encoding and decoding.


o

Control Period Coding: 2 bits converted to 10 bits.

TMDS Error Reduction Coding (TERC4) Coding: 4 bits converted to 10 bits.

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o

Video Data Coding: 8 bits converted to 10 bits.

HDMI link operates in three modes: Video Data Period, Data Island Period, and Control
Period.

Preamble, near the end of every Control Period, indicates whether the next Data Period
is a Video Data Period or a Data Island Period.

Maximum 18 packets per Data Island and 16 packet types.

Data Island improves reliability by adding Error Correction Code (ECC) parity to each
packet: BCH(64,56) and BCH(32,24).

Video pixels carried across the link are in one of three different pixel encoding: RGB
4:4:4, YCBCR 4:4:4, or YCBCR 4:2:2.

Video Format Timing (number of pixels per line and number of lines per video field)
codes are supported.

Color Depth Modes 24-bit, 30-bit, 36-bit, and 48-bit are supported.

Monitor Placement and Instantiation


The HMDI monitor is instantiated in the interface between an HDMI source and HDMI sink. A
typical HDMI setup is shown in Figure 9-1.
Figure 9-1. HDMI Monitor Implementation
Option 1
QVL
Monitor
HDMI
Source

TMDS Channel [0-2]


TMDS Clock Channel

HDMI
Sink

Option 2
TMDS Channel [0-2]
HDMI
Source

290

TMDS Clock Channel

QVL
Monitor
HDMI
Sink

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High-Definition Multimedia Interface (HDMI)


Monitor Placement and Instantiation

Monitor Connectivity
Connect the HDMI monitor pins to internal signals as specified in the pin-out Table 9-1 and
illustrated in Figure 9-2.
Figure 9-2. HDMI Monitor Pins Diagram

clock
reset
areset
parallel_data_ch0
parallel_data_ch1
parallel_data_ch2
serial_data_ch0
serial_data_ch1
serial_data_ch2

HDMI Monitor

Table 9-1. HDMI Monitor Pins Description


Pins

Description

clock

Clock (TMDS clock) or serial data sample clock (10x TMDS clock).

reset

Synchronous reset, active high.

areset

Asynchronous reset, active high.

parallel_data_ch0

10-bit parallel channel 0 data.

parallel_data_ch1

10-bit parallel channel 1 data.

parallel_data_ch2

10-bit parallel channel 2 data.

serial_data_ch0

1-bit serial channel 0 data.

serial_data_ch1

1-bit serial channel 1 data.

serial_data_ch2

1-bit serial channel 2 data.

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Monitor Parameters
The parameters shown in Table 9-2 should be passed with appropriate values to configure the
HDMI monitor.
Table 9-2. HDMII Monitor Parameters
Order Parameters

Default

Description

1.

Constraints_Mode

This parameter configures the checks in the monitor


as constraints during formal analysis.

2.

NUMBER_DATA_CHANNELS

Number of TMDS data channels.

3.

DATA_CHANNEL_ENCODED_
WIDTH

10

Width of encoded character per TMDS clock cycle.

4.

DATA_CHANNEL_UNENCODED_
WIDTH

Width of unencoded character per TMDS clock


cycle.

5.

BYPASS_SERIAL_TO_PARALLEL

This parameter can be used to bypass the monitor


module that converts TMDS serial data to parallel.
Instead, the monitors clock input and
parallel_data_ch[2:0] are used as the TMDS clock
and encoded data channels, respectively. To enable
this bypass, just set this parameter != 0.

6.

USE_CLOCK_INPUT_TO_SAMPLE_
SERIAL_DATA

The monitors serial-to-parallel module can sample


the TMDS serial data either using the monitors
clock input or via an internally generated clock.
This parameter is "dont care" when
BYPASS_SERIAL_TO_PARALLEL != 0. To
enable using the monitors clock input to sample
the serial data, set this parameter != 0.

7.

CLOCK_10X_PERIOD

This parameter can be used to generate an internal


clock for TMDS serial data sampling. This
parameter is "dont care" when
BYPASS_SERIAL_TO_PARALLEL != 0. The
number specifies an internal clock period. For
example, setting this parameter to 2 would generate
an internal clock with period 2 timeunits.

8.

INVERT_CLOCK10X_OUT

When using an internally generated clock to sample


the TMDS serial channel data, you can invert that
clock if you set this parameter to a non-zero
number. This might be useful in avoiding a race
condition between the data and the active edge of
the clock.

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Table 9-2. HDMII Monitor Parameters (cont.)


Order Parameters

Default

Description

9.

This parameter can be used to bypass all 8-to-10 bit


encoding in the CTL, Data Island (TERC4) and
Video Data phase of TMDS channel data.

BYPASS_ENCODING

Setting parameter BYPASS_ENCODING to a


non-zero value causes the following assertions to
not be generated in the monitor:

HDMI_DATA_CHANNEL_DATA_ISLAND_
PERIOD_ILLEGAL_TERC4_ENCODING
HDMI_DATA_CHANNEL_VIDEO_DATA_
PERIOD_GT5_TRANSITIONS_PER_PIXEL_
CLK_ERR
HDMI_DATA_ISLAND_PERIOD_PACKET_
NOT_32_PIXEL_CLKS_MULTIPLE_ERR

These assertions do not exist in the monitor if the


BYPASS_ENCODING parameter is set to
non-zero since these do not make sense and are not
necessary with that parameter setting.
10.

ENABLE_SAFE_HIZ_RESET_
HANDLING

This parameter can be used when the reset signals


(reset and areset) are unconnected. This will set the
internal reset and areset signal to an inactive value.

11.

SET_VIDEO_FORMAT_16x8

This parameter can be used to over-ride the


programmed video format from what is commonly
720x480 to 16x8. This is useful for simulation and
formal verification as the time required to see
complete video fields is much smaller.

12.

PROGRAMMING_CHECK_OFF_
GENERAL_CONTROL_CD

This parameter is used when the parameter,


PROGRAMMING_CHECK_ENABLE, is reset to
0, which means that the programming of Data
Island Packet Types may not be following the rules,
and that the stimulus may not match what is
programmed. If that is the case, then you can use
this parameter as the color depth instead of what is
programmed by General Control data packets.
The default color depth is 24-bit mode.
The valid color depth modes are as follows:

24-bits per pixel


30-bits per pixel
36-bits per pixel
48-bits per pixel

Refer to the Color Depth Values table in


the HDMI Specification 1.3a for details.

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Table 9-2. HDMII Monitor Parameters (cont.)


Order Parameters

Default

Description

13.

This parameter is used when the parameter,


PROGRAMMING_CHECK_ENABLE, is reset to
0, which means that the programming of Data
Island Packet Types may not be following the rules,
and that the stimulus may not match what is
programmed. If that is the case, then you can use
this parameter as the RGB/YCbCr indicator instead
of what is programmed by AVI Infoframe data
packets.

PROGRAMMING_CHECK_OFF_
AVI_INFOFRAME_Y

The default RGB/YCbCr indicator is RGB 444.

0 = RGB 444
1 = YCbCr 444
2 = YCbCr 422
14.

PROGRAMMING_CHECK_OFF_
AVI_INFOFRAME_VI

This parameter is used when the parameter,


PROGRAMMING_CHECK_ENABLE, is reset to
0, which means that the programming of Data
Island Packet Types may not be following the rules,
and that the stimulus may not match what is
programmed. If that is the case, then you can use
this parameter as the video format ID code instead
of what is programmed by AVI Infoframe data
packets.
The default video format ID code is 720x480p @
59.94/60HZ.
The valid values are 1 to 59. Refer to the HDMI
Valid Pixel Repeat Values for Each Video Format
Timing table in the HDMI Specification 1.3a

for details.
15.

DATA_X_Z_CHECK_ENABLE

This parameter can be used to enable or disable


X / Z assertion checking on either the TMDS serial
or parallel data channel inputs (depending on
whether BYPASS_SERIAL_TO_PARALLEL ==
0 or not, respectively). Set this parameter to 1 to
enable checking or 0 to disable.

16.

PROGRAMMING_CHECK_
ENABLE

This parameter can be used to enable or disable


assertion checking on Data Island packets. Set this
parameter to 1 to enable checking or 0 to disable.

17.

PACKET_COVER_ENABLE

This parameter can be used to enable or disable


cover directive checking on Data Island Packet
Types. Setting this parameter to 1 would turn on
coverage for the 17 different packet types.

18.

PROGRAMMING_COVER_ENABLE

This parameter can be used to enable or disable


cover directive checking on various programming
modes: deep color modes, RGB and YCbCr video
format modes, and video format ID codes (for
example, 720x480p @ 59.94/60HZ). Set this
parameter to 1 to enable coverage and 0 to disable.

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Table 9-2. HDMII Monitor Parameters (cont.)


Order Parameters

Default

Description

19.

`QVL_COVER_
ALL (15)

This parameter can be used to filter cover


directives. The different coverage levels are as
follows:

COVERAGE_LEVEL_FILTER

`QVL_COVER_NONE == 0;
`QVL_COVER_SANITY == 1;
`QVL_COVER_BASIC == 2;
`QVL_COVER_CORNER == 4;
`QVL_COVER_STATISTIC == 8;
`QVL_COVER_ALL == 15.
Notice that `QVL_COVER_ALL is a bit-wise OR
of the other non-zero coverage levels.
20.

COVERAGE_LEVEL_MESSAGE_
FILTER

`QVL_COVER_
MESSAGE_ALL
(15)

This parameter can be used to enable or disable


cover directive messages. The cover directives are
unaffected. The different message filtering are as
follows:
`QVL_COVER_MESSAGE_NONE == 0;
`QVL_COVER_MESSAGE_SANITY == 1;
`QVL_COVER_MESSAGE_BASIC == 2;
`QVL_COVER_MESSAGE_CORNER == 4;
`QVL_COVER_MESSAGE_STATISTIC == 8;
`QVL_COVER_MESSAGE_ALL == 15.

Notice that `QVL_COVER_MESSAGE_ALL is a


bit-wise OR of the other non-zero cover message
filter levels.
If you explicitly assign parameters by name, then it is not required to specify the parameters in the above order.

HDMI Monitor Instantiation Example


Example 9-1 instantiates the HDMI monitor.
Example 9-1. HDMI Monitor Instantiation
qvl_hdmi_monitor #(
0,
/* Constraints_Mode */
3,
/* NUMBER_DATA_CHANNELS */
10,
/* DATA_CHANNEL_ENCODED_WIDTH */
8,
/* DATA_CHANNEL_UNENCODED_WIDTH */
0,
/* BYPASS_SERIAL_TO_PARALLEL */
0,
/* USE_CLOCK_INPUT_TO_SAMPLE_SERIAL_DATA */
0,
/* CLOCK_10X_PERIOD */
0,
/* INVERT_CLOCK10X_OUT */
0,
/* BYPASS_ENCODING */
0,
/* ENABLE_SAFE_HIZ_RESET_HANDLING */
0,
/* SET_VIDEO_FORMAT_16x8 */

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Compiler Directives
4,
/* PROGRAMMING_CHECK_OFF_GENERAL_CONTROL_CD */
0,
/* PROGRAMMING_CHECK_OFF_AVI_INFOFRAME_Y */
2,
/* PROGRAMMING_CHECK_OFF_AVI_INFOFRAME_VI */
1,
/* DATA_X_Z_CHECK_ENABLE */ */
1,
/* PROGRAMMING_CHECK_ENABLE */
1,
/* PACKET_COVER_ENABLE */
1,
/* PROGRAMMING_COVER_ENABLE */
15,
/* COVERAGE_LEVEL_FILTER */
15
/* COVERAGE_LEVEL_MESSAGE_FILTER */
)
HDMI_MONITOR (
.clock
(clock),
.reset
(reset),
.areset
(areset),
.parallel_data_ch0
(parallel_data_ch0),
.parallel_data_ch1
(parallel_data_ch1),
.parallel_data_ch2
(parallel_data_ch2),
.serial_data_ch0
(serial_data_ch0),
.serial_data_ch1
(serial_data_ch1),
.serial_data_ch2
(serial_data_ch2)
);

Compiler Directives
Table 9-3 describes the available Verilog and SystemVerilog compiler directives.
Table 9-3. Verilog and SystemVerilog Compiler Directives
Compiler Directive

Dependent Compiler Directive

Description

QVL_VERSION_PRINT_OFF

none

Turns off a DPI C function that


prints the current QVL version.

QVL_ASSERT_ON

none

Enables assertions.

QVL_XCHECK_OFF

QVL_ASSERT_ON

Can selectively turn off assertions


related to X and Z data checking.
Within QVL_ASSERT_ON
(meaning this compiler directive
must be true first).

QVL_COVER_ON

none

Enables cover directives and final


coverage statistics summary.

QVL_SV_COVER_DIRECTIVES_OFF QVL_COVER_ON

Can turn off cover directives


selectively.
Within QVL_COVER_ON
(meaning this compiler directive
must be true first).

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Table 9-3. Verilog and SystemVerilog Compiler Directives (cont.)


Compiler Directive

Dependent Compiler Directive

Description

QVL_MW_FINAL_COVER_OFF

QVL_COVER_ON

Can turn off final coverage


statistics summary selectively.
Within QVL_COVER_ON
(meaning this compiler directive
must be true first).

Monitor Checks
Table 9-4 shows the data channel serial and parallel X or Z (unknown) monitor checks
performed by the HDMI monitor.
The checks in Table 9-4 can be disabled if the parameter DATA_X_Z_CHECK_ENABLE is
set to 0.
Table 9-4. HDMI Data Channel Unknown Checks
Check ID

Violation

Description

HDMI_SERIAL_DATA_
CHANNEL_UNKNOWN_
OR_Z_DRIVEN

Data channel (serial mode) is not


driven to a valid level.

Checks that the TMDS Channel (0, 1,


or 2) serial data input is both known
(not X) and driven (not Z).

HDMI_PARALLEL_DATA_
CHANNEL_UNKNOWN_
OR_Z_DRIVEN

Data channel (parallel mode) is not


driven to a valid level.

Checks that the TMDS Channel (0, 1,


or 2) parallel data input is both known
(not X) and driven (not Z).

Table 9-5 shows the data integrity monitor checks performed by the HDMI monitor.
Table 9-5. HDMI Data Integrity Checks
Check ID

Violation

HDMI_DATA_CHANNEL_CTL_
PERIOD_ILLEGAL_ENCODING

Illegal encoding value on data Checks that the TMDS Channel data
channel during a CTL Period. input is properly encoded from the
two-bit control signal to a 10-bit
encoding 00 -> 0x354, 01 -> 0x0AB,
10 -> 0x154, 11 -> 0x2AB.

HDMI_DATA_CHANNEL_CTL_
PREAMBLE_ILLEGAL_
ENCODING

Illegal encoding value on data


channel during a CTL Period
Preamble.

Checks that the TMDS Channel data


input is properly encoded from the
two-bit control signal to a 10-bit
encoding 00 -> 0x354, 01 -> 0x0AB,
10 -> 0x154, 11 -> 0x2AB which are all
valid combinations for HVSYNC.

HDMI_DATA_CHANNEL_
DATA_ISLAND_PERIOD_
ILLEGAL_TERC4_ENCODING

Illegal terc4 encoding value


on data channel during a Data
Island Period.

Checks that the TMDS Channel 0 data


input is properly encoded from the 4-bit
to a 10-bit TERC4 encoding (print list
from the specification).

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Table 9-5. HDMI Data Integrity Checks (cont.)


Check ID

Violation

Description

HDMI_DATA_CHANNEL_
DATA_ISLAND_PERIOD_
UNEXPECTED_BCH_ECC_
VALUE

Unexpected BCH ECC value


on data channel during a Data
Island Period.

Data Island Period data BCH0(64,56)


8-bit ECC actual value matches the
expected value.

HDMI_DATA_CHANNEL_
VIDEO_DATA_PERIOD_
GT5_TRANSITIONS_PER_
PIXEL_CLK_ERR

Too many transitions (greater TMDS characters <=5 transitions per


than 5) on data channel during pixel clock during VIDEO DATA
a Video Data Period.
Period.

Table 9-6 shows the protocol monitor checks performed by the HDMI monitor.
Table 9-6. HDMI Protocol Checks
Check ID

Violation

Description

HDMI_CTL_PERIOD_LT12_PIXEL_
CLKS_MINIMUM_ERR

Not enough pixel clocks (12


minimum) during a CTL
Period.

All TMDS Control Periods shall be at


least 12 pixel clocks long.

HDMI_CTL_PERIOD_PREAMBLE_
GT8_PIXEL_CLKS_ERR

CTL Period Preamble error


where the preamble lasted
longer than 8 pixel clocks.

All TMDS Control Period Preambles


shall be 8 pixel clocks long.

HDMI_CTL_PERIOD_PREAMBLE_
ILLEGAL_CHARACTERS

CTL Period Preamble contain


illegal characters; legal
characters are CTL[3:0] ===
4'b0001 or 4'b0101.

The TMDS Control Period Preamble


has only two legal characters:
CTL[3:0] === 0001 (Video Data
Period) and
CTL[3:0] === 0101 (Data Island
Period).

HDMI_CTL_PERIOD_
PREAMBLE_NOT_8_PIXEL_
CLKS_ERR

Number of pixel clocks during


a CTL Period Preamble was
not 8.

All TMDS Control Period Preambles


shall be 8 pixel clocks long.

HDMI_DATA_ISLAND_PERIOD_
CH0_D3_ONE_AFTER_FIRST_
CLK_TERC4_ENCODING_ERR

Invalid value found on data


channel 0 after first pixel clock
of Data Island Period TERC4
encoding.

The TMDS Data Island Period Channel


0 D[3] value one clock after a leading
guard band is D[3] === 1 after the first
pixel clock of the TERC4 encoding
period until the trailing guard band.

HDMI_DATA_ISLAND_PERIOD_
CH0_D3_ZERO_AFTER_LEADING_
GUARD_BAND_ERR

Invalid value found on data


channel 0 at first pixel clock of
Data Island Period TERC4
encoding.

The TMDS Data Island Period Channel


0 D[3] value one clock after a leading
guard band is D[3] === 0.

HDMI_DATA_ISLAND_PERIOD_
GUARD_BAND_INVALID_VALUE

Invalid value found on data


channel during a Data Island
Period guard band.

The TMDS Data Island Period Channel


leading or trailing guard band value is
0x133.

HDMI_DATA_ISLAND_PERIOD_
GUARD_BAND_NOT_2_PIXEL_
CLKS_ERR

Leading or trailing guard band The leading and trailing guard bands
during Data Island Period not 2 are 2 pixel clocks in length during a
pixel clocks error.
Data Island Period.

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Monitor Checks

Table 9-6. HDMI Protocol Checks (cont.)


Check ID

Violation

Description

HDMI_DATA_ISLAND_PERIOD_
INVALID_PACKET_TYPE_
HEADER_ERR

During a Data Island Period,


an invalid packet type header
was detected.

Valid Packet Types include


0x00 -> 0x0A and 0x80 -> 0x85.

HDMI_DATA_ISLAND_PERIOD_
MAXIMUM_NUMBER_OF_
PACKETS_18_ERR

More than maximum (18)


number of data packets
transmitted during Data Island
Period.

The maximum number of packets


within a Data Island Period is 18.

HDMI_DATA_ISLAND_PERIOD_
MINIMUM_NUMBER_OF_
PACKETS_1_ERR

No data packet detected error


during Data Island Period.

The minimum number of packets


within a Data Island Period is 1.

HDMI_DATA_ISLAND_PERIOD_
PACKET_NOT_32_PIXEL_CLKS_
MULTIPLE_ERR

The length of packets within a


Data Island Period is not a
multiple of 32 pixel clocks.

A packet within a Data Island Period is


32 pixel clocks in length.

HDMI_DATA_ISLAND_PERIOD_
UNEXPECTED_DATA_AFTER_
TRAILING_GUARD_BAND_ERR

Unexpected data after a Data


Island Period trailing guard
band; expected CTL Period
encoded data.

Expected data after a Data Island


Period trailing guard band; expected
CTL Period encoded data.

HDMI_DATA_ISLAND_TO_
VIDEO_DATA_PERIOD_ERR

A Control Period is required


between any two non-Control
Periods; found a Data Island to
Video Data Period error.

A Control Period is required between


any two periods that are not Control
Periods; detected a Data Island Period
immediately followed by a Video Data
Period.

HDMI_INVALID_NUMBER_OF_
ACTIVE_PIXELS_PER_
PROGRAMMED_VALUE

The number of active video


pixels in a video data period
did not match the programmed
value.

The number of pixel clocks in one


active video transmission should match
the programmed value (for example,
720 active pixel clocks in a 720x480
video frame).

HDMI_MONITOR_STATE_
MACHINE_TO_RESET_
STATE_ERR

Unexpected data has caused


the HDMI Monitor to
transition into the reset state.

The HDMI Monitor state machine has


transitioned into the reset state due to
unexpected data.

HDMI_MONITOR_STATE_
MACHINE_UNKNOWN_STATE_
ERR

Unexpected data has caused


the HDMI Monitor to
transition into an unknown
state.

The HDMI Monitor state machine has


transitioned into an unknown state due
to unexpected data.

HDMI_ONE_DATA_ISLAND_
PERIOD_PER_TWO_VIDEO_
FIELDS_ERR

While transmitting video, at


least one Data Island shall be
transmitted during every two
video fields error.

While transmitting video, at least one


Data Island shall be transmitted during
every two video fields.

HDMI_VIDEO_DATA_PERIOD_
GUARD_BAND_INVALID_VALUE

Invalid value found on data


channel during a Video Data
Period guard band.

The TMDS Video Data Period Channel


0, 1, and 2 leading guard band values
are as follows:
ch0 === 0x2CC
ch1 === 0x133
ch2 === 0x2CC

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Table 9-6. HDMI Protocol Checks (cont.)


Check ID

Violation

Description

HDMI_VIDEO_DATA_PERIOD_
GUARD_BAND_NOT_2_PIXEL_
CLKS_ERR

Leading guard band during


Video Data Period not 2 pixel
clocks error.

The leading guard band is 2 pixel


clocks in length during a Video Data
Period.

HDMI_VIDEO_DATA_TO_DATA_
ISLAND_PERIOD_ERR

A Control Period is required


between any two non-Control
Periods; found a Video Data to
Data Island Period error.

A Control Period is required between


any two periods that are not Control
Periods; detected a Video Data Period
immediately followed by a Data Island
Period.

HDMI_VIDEO_DATA_TO_VIDEO_
DATA_PERIOD_ERR

A Control Period is required


between any two non-Control
Periods; found a Video Data to
Video Data Period error.

A Control Period is required between


any two periods that are not Control
Periods; detected a Video Data Period
immediately followed by a Video Data
Period.

Table 9-7 shows the programming monitor checks performed by the HDMI monitor.
The checks in Table 9-7 can be disabled if the PROGRAMMING_CHECK_ENABLE
parameter is set to 0.
Table 9-7. HDMI Programming Checks
Check ID

Violation

Description

HDMI_AUDIO_CLOCK_
REGENERATION_PACKET_ERR

Audio Clock Regeneration


packet contains undefined
programming data or non-zero
data that should be zero.

Audio Clock Regeneration (ACR)


packet contains either undefined
programming data for N or CTS, or it
contains non-zero data that should be
zero.

HDMI_AUDIO_CLOCK_
REGENERATION_SUBPACKET_
DIFF_ERR

Audio Clock Regeneration four Audio Clock Regeneration (ACR)


subpackets are not identical.
subpacket diff error; all four
subpackets should contain the same
data.

HDMI_AUDIO_SAMPLE_
PACKET_ERR

Audio Sample packet contains Audio Sample packet contains defined


undefined programming data or programming data or data that should
non-zero data that should be
be zero.
zero.

HDMI_GENERAL_CONTROL_
PACKET_ERR

General Control packet


contains undefined
programming data or non-zero
data that should be zero.

General Control (GC) packet contains


either defined programming data, or it
contains data that should be zero.

HDMI_GENERAL_CONTROL_
SUBPACKET_DIFF_ERR

General Control four


subpackets are not identical.

General Control (GC) subpacket diff


error; all four subpackets should
contain the same data.

HDMI_GENERAL_CONTROL_
PACKET_AVMUTE_
PROGRAMMING_ERR

General Control packet sets


both Clear_AVMute and
Set_AVMute flags
simultaneously.

General Control (GC) packet does not


set Clear_AVMute and Set_AVMute
flags simultaneously.

300

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Monitor Checks

Table 9-7. HDMI Programming Checks (cont.)


Check ID

Violation

Description

HDMI_GENERAL_CONTROL_
PACKET_CD_ZERO_PP_NOT_
ZERO_PROGRAMMING_ERR

General Control packet


programs CD[3:0] to zero but
PP[3:0] is not zero.

General Control (GC) packet programs


CD[3:0] to zero and PP[3:0] is zero.

HDMI_GENERAL_CONTROL_
PACKET_PP_RESERVED_
PROGRAMMING_ERR

General Control packet


programs PP[3:0] to a reserved
value.

The General Control (GC) Packet has


valid PP[3:0] values from 0x0 to 0x4;
values 0x5 to 0xF are reserved.

HDMI_GENERAL_CONTROL_
PACKET_CD_RESERVED_
PROGRAMMING_ERR

General Control packet


The General Control (GC) Packet has
programs CD[3:0] to a reserved valid CD[3:0] values from 0x4 to 0x7;
value.
values 0x1 to 0x3 and 0x8 to 0xF are
reserved; value 0x0 indicates Color
Depth not indicated.

HDMI_AUDIO_CONTENT_
PROTECTION_PACKET_ERR

Audio Content Protection


packet contains undefined
programming data or non-zero
data that should be zero.

Audio Content Protection (ACP)


packet contains either defined
programming data or data that should
be zero.

HDMI_AUDIO_CONTENT_
PROTECTION_PACKET_ACP_
TYPE_RESERVED_
PROGRAMMING_ERR

Audio Content Protection


packet programs
ACP_Type[7:0] to a reserved
value.

The Audio Content Protection (ACP)


Packet has valid ACT_Type[7:0] from
0x00 to 0x03; values 0x04 to 0xFF are
reserved.

HDMI_ISRC1_PACKET_ERR

ISRC1 packet contains


ISRC1 packet contains either defined
undefined programming data or programming data, or data that should
non-zero data that should be
be zero.
zero.

HDMI_ISRC2_PACKET_ERR

ISRC2 packet contains


ISRC2 packet contains either defined
undefined programming data or programming data, or data that should
non-zero data that should be
be zero.
zero.

HDMI_ONE_BIT_AUDIO_
SAMPLE_PACKET_ERR

One Bit Audio Sample packet


contains undefined
programming data or non-zero
data that should be zero.

One Bit Audio Sample (OBAS) packet


contains either defined programming
data, or data that should be zero.

DST Audio (DSTA) packet contains


HDMI_DST_AUDIO_PACKET_ERR DST Audio packet contains
undefined programming data or either defined programming data, or
non-zero data that should be
data that should be zero.
zero.
HDMI_HIGH_BITRATE_AUDIO_
STREAM_PACKET_ERR

High-Bitrate Audio Stream


packet contains undefined
programming data or non-zero
data that should be zero.

High-Bitrate Audio Stream (HBRAS)


packet contains either defined
programming data, or data that should
be zero.

HDMI_GAMUT_METADATA_
PACKET_ERR

Gamut Metadata packet


contains undefined
programming data or non-zero
data that should be zero.

Gamut Metadata (GM) packet contains


either defined programming data, or
data that should be zero.

HDMI_GAMUT_METADATA_
PACKET_GBD_PROFILE_
PROGRAMMING_ERR

Gamut Metadata packet


programs GBD_profile[2:0] to
a reserved value.

GM GBD_profile reserved values.

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High-Definition Multimedia Interface (HDMI)


Monitor Checks

Table 9-7. HDMI Programming Checks (cont.)


Check ID

Violation

Description

HDMI_GAMUT_METADATA_
PACKET_SEQ_NUM_
PROGRAMMING_ERR

Gamut Metadata packet


programs
Affected_Gamut_Seq_Num to
a value that is not
Current_Gamut_Seq_Num nor
Current_Gamut_Seq_Num+1.

Affected_Gamut_Seq_Num ===
Current_Gamut_Seq_Num or
Current_Gamut_Seq_Num + 1 is
required if No_Current_GBD === 0.

HDMI_INFOFRAME_PACKET_
ERR

InfoFrame packet contains


InfoFrame packet contains either
undefined programming data or defined programming data, or data that
non-zero data that should be
should be zero.
zero.

HDMI_INFOFRAME_PACKET_
INFOFRAME_LENGTH_
PROGRAMMING_ERR

InfoFrame packet
InfoFrame_length
programming exceeds the
maximum value of 27.

HDMI_INFOFRAME_PACKET_
SUBPACKET_CHECKSUM_ERR

InfoFrame subpacket checksum InfoFrame subpacket checksum


does not match expected
matches the expected checksum.
checksum.

HDMI_AVI_INFOFRAME_
PACKET_ERR

AVI InfoFrame packet contains AVI InfoFrame packet contains either


undefined programming data or defined programming data, or data that
non-zero data that should be
should be zero.
zero.

HDMI_AVI_INFOFRAME_
PACKET_INFOFRAME_
VERSION_PROGRAMMING_ERR

AVI InfoFrame packet


InfoFrame_version
programming not 0x02.

AVI InfoFrame packet contains


InfoFrame_version programming that
is 0x02.

HDMI_AVI_INFOFRAME_
PACKET_INFOFRAME_LENGTH_
PROGRAMMING_ERR

AVI InfoFrame packet


InfoFrame_length
programming is not 0x0D.

AVI InfoFrame packet contains


InfoFrame_length programming that is
0x0D.

HDMI_AVI_INFOFRAME_
PACKET_SUBPACKET_
CHECKSUM_ERR

AVI InfoFrame subpacket


checksum does not match
expected checksum.

AVI InfoFrame subpacket checksum


matches expected checksum.

HDMI_AVI_INFOFRAME_
PACKET_Y_RESERVED_
PROGRAMMING_ERR

AVI InfoFrame packet


programs Y[1:0] to a reserved
value.

The AVI InfoFrame Packet has valid


Y[1:0] values from 0x0 to 0x2; value
0x3 is reserved.

HDMI_AVI_INFOFRAME_
PACKET_VI_RESERVED_
PROGRAMMING_ERR

AVI InfoFrame packet


programs VI[1:0] to a reserved
value.

The AVI InfoFrame Packet has valid


VI[1:0] values from 0x01 to 0x3B;
other values are reserved.

HDMI_AUDIO_INFOFRAME_
PACKET_ERR

Audio InfoFrame packet


contains undefined
programming data or non-zero
data that should be zero.

Audio InfoFrame packet contains


either defined programming data, or
data that should be zero.

Audio InfoFrame packet


HDMI_AUDIO_INFOFRAME_
PACKET_INFOFRAME_VERSION_ InfoFrame_version
programming is not 0x01.
PROGRAMMING_ERR

302

InfoFrame packet contains


InfoFrame_length programming that
has a maximum value of 27.

Audio InfoFrame packet contains


InfoFrame_version programming that
is 0x01

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High-Definition Multimedia Interface (HDMI)


Monitor Coverage

Table 9-7. HDMI Programming Checks (cont.)


Check ID

Violation

Description

HDMI_AUDIO_INFOFRAME_
PACKET_INFOFRAME_LENGTH_
PROGRAMMING_ERR

Audio InfoFrame packet


InfoFrame_length
programming is not 0x0A.

Audio InfoFrame packet contains


InfoFrame_length programming that is
0x0A.

HDMI_AUDIO_INFOFRAME_
PACKET_SUBPACKET_
CHECKSUM_ERR

Audio InfoFrame subpacket


checksum does not match
expected checksum.

Audio InfoFrame subpacket checksum


matches the expected checksum.

Monitor Coverage
Table 9-8 shows the cover basic cases collected by the HDMI monitor.
Refer to the COVERAGE_LEVEL_FILTER and COVERAGE_LEVEL_MESSAGE_FILTER
parameters in Table 9-2 on page 292 for additional information.
Table 9-8. HDMI Cover Basic
Cover Basic

Description

HDMI_CONTROL_PERIOD

Covered a Control Period.

HDMI_CONTROL_PERIOD_DATA_ISLAND_PREAMBLE

Covered a Control Period Data Island Preamble.

HDMI_DATA_ISLAND_PERIOD

Covered a Data Island Period.

HDMI_DATA_ISLAND_PERIOD_PACKET

Covered a Data Island Period packet.

HDMI_CONTROL_PERIOD_VIDEO_DATA_PREAMBLE

Covered a Control Period Video Data Preamble.

HDMI_VIDEO_DATA_PERIOD

Covered a Video Data Period.

Table 9-9 shows the cover corner cases collected by the HDMI monitor.
Table 9-9. HDMI Cover Corner
Cover Corner

Description

HDMI_VIDEO_FRAME

Covered a Video Frame

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Monitor Coverage

Table 9-10 shows the packet cover statistics cases collected by the HDMI monitor.
The cover directives in Table 9-10 can be disabled if the PACKET_COVER_ENABLE
parameter is set to 0.
Table 9-10. HDMI Packet Cover Statistics
Packet Cover

Description

HDMI_DATA_ISLAND_PERIOD_NULL_PACKET

Covered a Data Island Period Null packet.

HDMI_DATA_ISLAND_PERIOD_AUDIO_CLOCK_
REGENERATION_PACKET

Covered a Data Island Period Audio Clock


Regeneration packet.

HDMI_DATA_ISLAND_PERIOD_AUDIO_SAMPLE_ Covered a Data Island Period Audio Sample packet.


PACKET
HDMI_DATA_ISLAND_PERIOD_GENERAL_
CONTROL_PACKET

Covered a Data Island Period General Control


packet.

HDMI_DATA_ISLAND_PERIOD_AUDIO_
CONTENT_PROTECTION_PACKET

Covered a Data Island Period Audio Content


Protection packet

HDMI_DATA_ISLAND_PERIOD_ISRC1_PACKET

Covered a Data Island Period ISRC1 packet

HDMI_DATA_ISLAND_PERIOD_ISRC2_PACKET

Covered a Data Island Period ISRC2 packet

HDMI_DATA_ISLAND_PERIOD_ONE_BIT_
AUDIO_SAMPLE_PACKET

Covered a Data Island Period One Bit Audio Sample


packet

HDMI_DATA_ISLAND_PERIOD_DST_AUDIO_
PACKET

Covered a Data Island Period DST Audio packet

HDMI_DATA_ISLAND_PERIOD_HIGH_BITRATE_
AUDIO_STREAM_PACKET

Covered a Data Island Period HBR Audio Stream


packet

HDMI_DATA_ISLAND_PERIOD_GAMUT_
METADATA_PACKET

Covered a Data Island Period Gamut Metadata


packet

HDMI_DATA_ISLAND_PERIOD_INFOFRAME_
PACKET

Covered a Data Island Period InfoFrame packet

HDMI_DATA_ISLAND_PERIOD_VENDOR_
SPECIFIC_INFOFRAME_PACKET

Covered a Data Island Period Vendor Specific


InfoFrame packet

HDMI_DATA_ISLAND_PERIOD_AVI_
INFOFRAME_PACKET

Covered a Data Island Period AVI InfoFrame packet

HDMI_DATA_ISLAND_PERIOD_SOURCE_
PRODUCT_DESCRIPTOR_INFOFRAME_PACKET

Covered a Data Island Period Source Product


Descriptor InfoFrame packet

HDMI_DATA_ISLAND_PERIOD_AUDIO_
INFOFRAME_PACKET

Covered a Data Island Period Audio InfoFrame


packet

HDMI_DATA_ISLAND_PERIOD_MPEG_SOURCE_
INFOFRAME_PACKET

Covered a Data Island Period MPEG Source


InfoFrame packet

304

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High-Definition Multimedia Interface (HDMI)


Monitor Coverage

Table 9-11 shows the programming cover statistics cases collected by the HDMI monitor.
The cover directives in Table 9-11 can be disabled if the parameter
PROGRAMMING_COVER_ENABLE is set to 0.
Table 9-11. HDMI Programming Cover Statistics
Programing Cover

Description

HDMI_VIDEO_DATA_PERIOD_24_BIT_COLOR_
DEPTH_MODE

Covered a Video Data Period that used a 24-bit


color depth mode

HDMI_VIDEO_DATA_PERIOD_30_BIT_DEEP_
COLOR_DEPTH_MODE

Covered a Video Data Period that used a 30-bit


deep color depth mode

HDMI_VIDEO_DATA_PERIOD_36_BIT_DEEP_
COLOR_DEPTH_MODE

Covered a Video Data Period that used a 36-bit


deep color depth mode

HDMI_VIDEO_DATA_PERIOD_48_BIT_DEEP_
COLOR_DEPTH_MODE

Covered a Video Data Period that used a 48-bit


deep color depth mode

HDMI_VIDEO_DATA_PERIOD_RGB_444_VIDEO_
FORMAT_MODE

Covered a Video Data Period that used a RGB 444


video format mode

HDMI_VIDEO_DATA_PERIOD_YCbCr_444_VIDEO_
FORMAT_MODE

Covered a Video Data Period that used a YCbCr


444 video format mode

HDMI_VIDEO_DATA_PERIOD_CbCr_422_VIDEO_
FORMAT_MODE

Covered a Video Data Period that used a YCbCr


422 video format mode

HDMI_VIDEO_DATA_PERIOD_40x480p_60HZ_
VIDEO_FORMAT_ID_CODE

Covered a Video Data Period that used a 640x480p


@ 60HZ video format id code

HDMI_VIDEO_DATA_PERIOD_720x480p_60HZ_
VIDEO_FORMAT_ID_CODE

Covered a Video Data Period that used a 720x480p


@ 59.94/60HZ video format id code

HDMI_VIDEO_DATA_PERIOD_1280x720p_60HZ_
VIDEO_FORMAT_ID_CODE

Covered a Video Data Period that used a


1280x720p @ 59.94/60HZ video format id code

HDMI_VIDEO_DATA_PERIOD_1920x1080i_60HZ_
VIDEO_FORMAT_ID_CODE

Covered a Video Data Period that used a


1920x1080i @ 59.94/60HZ video format id code

HDMI_VIDEO_DATA_PERIOD_720_1440x480i_60HZ_
VIDEO_FORMAT_ID_CODE

Covered a Video Data Period that used a


720(1440)x480i @ 59.94/60HZ video format id
code

HDMI_VIDEO_DATA_PERIOD_720_1440x240p_60HZ_
VIDEO_FORMAT_ID_CODE

Covered a Video Data Period that used a


720(1440)x240p @ 59.94/60HZ video format id
code

HDMI_VIDEO_DATA_PERIOD_2880x480i_60HZ_
VIDEO_FORMAT_ID_CODE

Covered a Video Data Period that used a 2880x480i


@ 59.94/60HZ video format id code

HDMI_VIDEO_DATA_PERIOD_2880x240p_60HZ_
VIDEO_FORMAT_ID_CODE

Covered a Video Data Period that used a


2880x240p @ 59.94/60HZ video format id code

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High-Definition Multimedia Interface (HDMI)


Monitor Coverage

Table 9-11. HDMI Programming Cover Statistics (cont.)


Programing Cover

Description

HDMI_VIDEO_DATA_PERIOD_1440x480p_60HZ_
VIDEO_FORMAT_ID_CODE

Covered a Video Data Period that used a


1440x480p @ 59.94/60HZ video format id code

HDMI_VIDEO_DATA_PERIOD_1920x1080p_60HZ_
VIDEO_FORMAT_ID_CODE

Covered a Video Data Period that used a


1920x1080p @ 59.94/60HZ video format id code

HDMI_VIDEO_DATA_PERIOD_720x576p_50HZ_
VIDEO_FORMAT_ID_CODE

Covered a Video Data Period that used a 720x576p


@ 50HZ video format id code

HDMI_VIDEO_DATA_PERIOD_1280x720p_50HZ_
VIDEO_FORMAT_ID_CODE

Covered a Video Data Period that used a


1280x720p @ 50HZ video format id code

HDMI_VIDEO_DATA_PERIOD_1920x1080i_50HZ_
VIDEO_FORMAT_ID_CODE

Covered a Video Data Period that used a


1920x1080i @ 50HZ video format id code

HDMI_VIDEO_DATA_PERIOD_720_1440x288p_50HZ_
VIDEO_FORMAT_ID_CODE

Covered a Video Data Period that used a


720(1440)x288p @ 50HZ video format id code

HDMI_VIDEO_DATA_PERIOD_720_1440x576i_50HZ_
VIDEO_FORMAT_ID_CODE

Covered a Video Data Period that used a


720(1440)x576i @ 50HZ video format id code

HDMI_VIDEO_DATA_PERIOD_2880x576i_50HZ_
VIDEO_FORMAT_ID_CODE

Covered a Video Data Period that used a 2880x576i


@ 50HZ video format id code

HDMI_VIDEO_DATA_PERIOD_2880x288_50HZ_
VIDEO_FORMAT_ID_CODE

Covered a Video Data Period that used a 2880x288


@ 50HZ video format id code

HDMI_VIDEO_DATA_PERIOD_1440x576p_50HZ_
VIDEO_FORMAT_ID_CODE

Covered a Video Data Period that used a


1440x576p @ 50HZ video format id code

HDMI_VIDEO_DATA_PERIOD_1920x1080p_50HZ_
VIDEO_FORMAT_ID_CODE

Covered a Video Data Period that used a


1920x1080p @ 50HZ video format id code

HDMI_VIDEO_DATA_PERIOD_1920x1080p_24HZ_
VIDEO_FORMAT_ID_CODE

Covered a Video Data Period that used a


1920x1080p @ 23.97/24HZ video format id code

HDMI_VIDEO_DATA_PERIOD_1920x1080p_25HZ_
VIDEO_FORMAT_ID_CODE

Covered a Video Data Period that used a


1920x1080p @ 25HZ video format id code

HDMI_VIDEO_DATA_PERIOD_1920x1080p_30HZ_
VIDEO_FORMAT_ID_CODE

Covered a Video Data Period that used a


1920x1080p @ 29.97/30HZ video format id code

HDMI_VIDEO_DATA_PERIOD_2880x480p_60HZ_
VIDEO_FORMAT_ID_CODE

Covered a Video Data Period that used a


2880x480p @ 59.94/60HZ video format id code

HDMI_VIDEO_DATA_PERIOD_2880x576p_50HZ_
VIDEO_FORMAT_ID_CODE

Covered a Video Data Period that used a


2880x576p @ 50HZ video format id code

HDMI_VIDEO_DATA_PERIOD_1920x1080i_1250_
TOTAL_50HZ_VIDEO_FORMAT_ID_CODE

Covered a Video Data Period that used a


1920x1080i (1250 total) @ 50HZ video format id
code

HDMI_VIDEO_DATA_PERIOD_1920x1080i_100HZ_
VIDEO_FORMAT_ID_CODE

Covered a Video Data Period that used a


1920x1080i @ 100HZ video format id code

306

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High-Definition Multimedia Interface (HDMI)


Monitor Coverage Count Totals

Table 9-11. HDMI Programming Cover Statistics (cont.)


Programing Cover

Description

HDMI_VIDEO_DATA_PERIOD_1280x720p_100HZ_
VIDEO_FORMAT_ID_CODE

Covered a Video Data Period that used a


1280x720p @ 100HZ video format id code

HDMI_VIDEO_DATA_PERIOD_720x576p_100HZ_
VIDEO_FORMAT_ID_CODE

Covered a Video Data Period that used a 720x576p


@ 100HZ video format id code

HDMI_VIDEO_DATA_PERIOD_720_1440x576i_100HZ_
VIDEO_FORMAT_ID_CODE

Covered a Video Data Period that used a


720(1440)x576i @ 100HZ video format id code

HDMI_VIDEO_DATA_PERIOD_1920x1080i_120HZ_
VIDEO_FORMAT_ID_CODE

Covered a Video Data Period that used a


1920x1080i @ 120HZ video format id code

HDMI_VIDEO_DATA_PERIOD_1280x720p_120HZ_
VIDEO_FORMAT_ID_CODE

Covered a Video Data Period that used a


1280x720p @ 119.88/120HZ video format id code

HDMI_VIDEO_DATA_PERIOD_720x480p_120HZ_
VIDEO_FORMAT_ID_CODE

Covered a Video Data Period that used a 720x480p


@ 119.88/120HZ video format id code

HDMI_VIDEO_DATA_PERIOD_720_1440x480i_120HZ_
VIDEO_FORMAT_ID_CODE

Covered a Video Data Period that used a


720(1440)x480i @ 119.88/120HZ video format id
code

HDMI_VIDEO_DATA_PERIOD_720x576p_200HZ_
VIDEO_FORMAT_ID_CODE

Covered a Video Data Period that used a 720x576p


@ 200HZ video format id code

HDMI_VIDEO_DATA_PERIOD_720_1440x576i_200HZ_
VIDEO_FORMATID_CODE

Covered a Video Data Period that used a


720(1440)x576i @ 200HZ video format id code

HDMI_VIDEO_DATA_PERIOD_720x480p_240HZ_
VIDEO_FORMAT_ID_CODE

Covered a Video Data Period that used a 720x480p


@ 239.76/240HZ video format id code

HDMI_VIDEO_DATA_PERIOD_720_1440x480i_240HZ_
VIDEO_FORMAT_ID_CODE

Covered a Video Data Period that used a


720(1440)x480i @ 239.76/240HZ video format id
code

Monitor Coverage Count Totals


Table 9-12 shows the coverage count totals collected by the HDMI monitor.
Table 9-12. Coverage Count Totals for HDMI 1.3a Monitor
Coverage

Description

Total CTL Periods

Total number of CTL Periods transmitted

Data preamble

Total Control Period Data Island Preambles

Video preamble

Total Control Period Video Data Preambles

Total Data Island Periods

Total number of Data Island Periods transmitted

Total Video Data Periods

Total number of Video Data Periods transmitted

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High-Definition Multimedia Interface (HDMI)


Monitor Coverage Count Totals

Table 9-12. Coverage Count Totals for HDMI 1.3a Monitor (cont.)
Coverage

Description

Total Data Island Period Packets

Total number of packets transmitted within Data Island Periods

Total Video Frames

Total number of video frames transmitted

Table 9-13 shows the statistics count totals collected by the HDMI monitor.
Table 9-13. Statistics Count Totals for HDMI 1.3a Monitor
Statistic

Description

Total [Null to MPEG Source InfoFrame]


per Packet Type

Total number of packets transmitted according to a specific Packet


Type [Null to MPEG Source InfoFrame] (should total 17 unique
packet types).
Refer to the Packet Types table in the HDMI Specification 1.3a for
details.

Total [640x480p to 720(1440)x480i] Video Total number of video period transmissions using individual video
Codes
codes [640x480p to 720(1440)x480i] (should total 37 unique
totals).
Refer to the HDMI Valid Pixel Repeat Values for Each Video
Format Timing table in the HDMI Specification 1.3a for details.
Total RGB 4:4:4 Transactions

Total number of video period transmissions using RGB 4:4:4.

Total YCBCR 4:4:4 Transactions

Total number of video period transmissions using YCBCR 4:4:4.

Total YCBCR 4:2:2 Transactions

Total number of video period transmissions using YCBCR 4:2:2.

Total 24-bit mode Deep Color Pixel


Packing

Total number of video period transmissions using 24-bit mode


Deep Color Pixel Packing.

Total 30-bit mode Deep Color Pixel


Packing

Total number of video period transmissions using 30-bit mode


Deep Color Pixel Packing.

Total 36-bit mode Deep Color Pixel


Packing

Total number of video period transmissions using 36-bit mode


Deep Color Pixel Packing.

Total 48-bit mode Deep Color Pixel


Packing

Total number of video period transmissions using 48-bit mode


Deep Color Pixel Packing.

308

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Chapter 10
I2C (Inter-IC) Monitor
Introduction
The I2C (Inter-IC) bus was originally developed by Philips Semiconductors to provide a simple
and uniform connectivity for a variety of peripheral and general-purpose devices such as
intelligent control, EEPROM, RAM, and LCD drivers.
The Mentor Graphics Corporation I2C QVL monitor is used to verify any I2C designs for
protocol correctness, and to measure the verification coverage through structural coverage
metrics. The I2C monitor contains assertion directives that track all I2C interface protocol rules.
The statistics block collects the occurrences of various protocol scenarios on the I2C bus.
This I2C Monitor can be simulated with Mentor Graphics Questa simulator and used with the
0-In Formal Verification tools (Search, Confirm, and Prove). With the 0-In Formal Verification
tools, the assertion directives in the I2C monitor can be used as Constraints and
Goals/Properties-to-prove-or-falsify, when used with the 0-In Formal Verification tools.
Figure 10-1 illustrates the I2C System Topology.
Figure 10-1. I2C System Topology

I2C Slave

I2C Master

I2C Bus

I2C Slave

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I2C Master

309

I2C (Inter-IC) Monitor


Reference Documentation

Reference Documentation
This QVL I2C monitor is modeled from the requirements provided in the following documents:

The I2C-Bus Specification, Version 2.1, January 2000

I2C Monitor
I2C is a multiple master, multiple slave interface. Any I2C device can be of the following types:

Master only function

Slave only function

Master and Slave functions in a single package

The following top modules are provided:

qvl_i2c_master_monitor to track Master only I2C devices

qvl_i2c_slave_monitor to track Slave only I2C devices

qvl_i2c_master_slave_monitor to track Master/Slave I2C devices

Figure 10-2 illustrates the I2C Monitor Connectivity.


Figure 10-2. I2C Monitor Connectivity
I2C Master

I2C Slave

I2C Master Monitor

I2C Slave Monitor

I2C Bus

I2C Master/Slave Monitor


I2C Master

I2C Slave

As shown in Figure 10-2, if you want to track multiple I2C Master/Slave and Master-Slave
devices simultaneously, then multiple instances of the appropriate I2C Master, or Slave, or
Master/Slave top modules are needed.

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I2C (Inter-IC) Monitor


I2C Monitor

Monitor Connectivity
Connect the I2C Master, or Slave, or Master/Slave monitor pins to internal signals as specified
in the pin-out Table 10-1 and illustrated in Figure 10-3, Figure 10-4, and Figure 10-5.
Figure 10-3. I2C Master Monitor Pins Diagram
clock
reset
areset
sda_out
sda_out_en_n
sda_in
scl_out
scl_out_en_n
scl_in
clock_prescale_count

I2C Master Monitor

Figure 10-4. I2C Slave Monitor Pins Diagram


clock
reset
areset
sda_out
sda_out_en_n
sda_in
scl_out
scl_out_en_n
scl_in
slave_addr
clock_prescale_count

I2C Slave Monitor

Figure 10-5. I2C Master/Slave Monitor Pins Diagram


clock
reset
areset
sda_out
sda_out_en_n
sda_in
scl_out
scl_out_en_n
scl_in
slave_addr
clock_prescale_count

Questa Verification Library Monitors Data Book, v2010.2

I2C Master/Slave
Monitor

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I2C Monitor

Table 10-1. I2C Monitor PINs Description


Pins

Description

areset

Asynchronous reset signal. Active HIGH.

clock

Clock signal. Positive edge active. This clock signal should be at least twice as
fast as scl_out/scl_in to be able to sample the scl_out/scl_in.

clock_prescale_count

Clock prescaler value/sampling enable signal. 16-bit wide. When the


configurable parameter, CLOCK_PRESCALE_EN (see Table 10-3 on page 315)
is set to 1, pass a nonzero positive integer to this signal. If the configurable
parameter CLOCK_PRESCALE_EN is set to 0, then connect an external
sampling enable signal to 0th bit of this signal by appending a leading 15'b0.
When the CLOCK_PRESCALE_EN parameter is set to 1, this monitor internally
generates a slower sampling signal using this prescaler value.
Recommendation: If the clock signal speed is equal, or just twice the speed of
SCL, then it is recommended to connect 1'b1or an external sampling enable
signal to the 0th bit of this signal.

reset

Synchronous reset signal. Active HIGH.

scl_in

I2C clock signal. The serial clock (SCL) input signal to the DUT.

scl_out

I2C clock signal. Input to the tristate buffer. SCL output signal to the DUT.

scl_out_en_n

SCL clock enable signal. Active LOW. Enable to the tristate buffer.

sda_in

I2C data signal. The serial data (SDA) input signal to the DUT.

sda_out

I2C data signal. SDA output signal from the DUT. Input to the tristate buffer.
Control and data signal.

sda_out_en_n

SDA output enable signal. Active LOW. Enable to the tristate buffer.

slave_addr

Slave address input. 10-bits wide. Both 7-bit address or 10-bit address can be
connected. When a 7-bit address is passed, 3'b0 should be appended with the
actual 7-bit address.
Note that as per the protocol, an I2C device can be configured with an address
through the hardware general call address. Hence, this monitor takes this input as
a configured address until a hardware general call address is issued on the bus, or
there is no hardware general call address at all on the bus.
Note that this signal is not available with the Master only monitor (see
Example 10-1 on page 314).

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I2C Monitor

Monitor Parameters
The parameters shown in Table 10-2 should be passed with appropriate values to configure the
I2C monitor to track the I2C Master, I2C Slave, or I2C Master/Slave devices.
Table 10-2. I2C Monitor Parameters
Order Parameters

Default Description

0.

Constraints_Mode

Common enable/disable for all assertions as


constraints to the 0-In Formal tools (Search,
Confirm, and Prove).
To use a group of assertions of this monitor as
constraints with the 0-In Formal tools, pass the value
1 to this parameter.

1.

MAX_TXN_LENGTH

Maximum Transaction Length Limit.


A check fires if this monitor finds an I2C transaction
that is longer than the length specified to this
parameter.
This check is disabled if this parameter is passed
with 0. To activate this check, pass any nonzero
positive number.

2.

CLOCK_PRESCALE_EN

Clock Prescaler Enable.


If set to 1, then pass a nonzero positive value to the
clock_prescale_count signal.
If set to 0, then connect an external sampling enable
to the 0th bit of the clock_prescale_count signal by
appending 15'b0 at the leading position.

3.

OUTPUT_ENABLES_ON

Output Enables ON or OFF.


If the I2C design has tristate compatible signals, then
pass 1 to this parameter, and connect the
corresponding enable signals to sda_out_en_n and
scl_out_en_n.
If the I2C design does not have output enable signals,
then pass 0 to this parameter and connect 1'b0 to both
sda_out_en_n and scl_out_en_n signals.

I2C Monitor Instantiation Examples


I2C Master Monitor
Example 10-1 instantiates the I2C Master monitor with no output enables, clock prescaler value
as 16'd20.

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I2C Monitor

Example 10-1. I2C Master Monitor Instantiation for a Master Only Design
qvl_i2c_master_monitor #(.Constraints_Mode (1),
.CLOCK_PRESCALE_EN (1) ) MAS_ONLY0
(.clock (CLOCK),
.reset (!RESETN),
.areset (!RESETN),
.sda_out (OSDA),
.sda_out_en_n (1'b0),
.sda_in (ISDA),
.scl_out (OSCL),
.scl_out_en_n (1'b0),
.scl_in (ISCL),
.clock_prescale_count (16'd20) ) ;

I2C Slave Monitor


Example 10-2 instantiates the I2C Slave monitor with no output enables, clock prescaler value
as 16'd20, and the Slave address as 10'h3a5.
Example 10-2. I2C Slave Monitor Instantiation for a Slave Only Design
qvl_i2c_slave_monitor #(.Constraints_Mode (1),
.CLOCK_PRESCALE_EN (1) ) SLV_ONLY0
(.clock (CLOCK),
.reset (!RESETN),
.areset (!RESETN),
.sda_out (OSDA),
.sda_out_en_n (1'b0),
.sda_in (ISDA),
.scl_out (OSCL),
.scl_out_en_n (1'b0),
.scl_in (ISCL),
.slave_addr (10'h3a5),
.clock_prescale_count (16'd20) ) ;

I2C Master/Slave Monitor


Example 10-3 instantiates the I2C Master/Slave monitor for an I2C design that has Master and
Slave functions, with output enables present, no clock prescaler value, external sampling
enable, and the Slave address as 10'h07f.
Note that Example 10-3 assumes that Fast-mode and High-speed mode (Hs-mode) have
separate external sampling enables in the design. You can bitwise OR them when you connect
them as an external sampling enable signal to the clock_prescale_count of the monitor.
Example 10-3. I2C Master/Slave Monitor Instantiation for a Master/Slave Design
qvl_i2c_master_slave_monitor #(.Constraints_Mode (1),
.CLOCK_PRESCALE_EN (0) ) MAS_SLV0
(.clock (CLOCK),

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Master Checks
.reset (!RESETN),
.areset (!RESETN),
.sda_out (OSDA),
.sda_out_en_n (OSDA_en_n),
.sda_in (ISDA),
.scl_out (OSCL),
.scl_out_en_n (OSCL_en_n),
.scl_in (ISCL),
.slave_addr (10'h07f),
.clock_prescale_count ( {15'b0,
(FS_MODE_SAMPLING_ENABLE | HS_MODE_SAMPLING_ENABLE) } ) );

Master Checks
Table 10-3 shows the Master checks performed by the I2C monitor.
Table 10-3. I2C Master Checks
Check ID

Violation

Description

I2C_m_cbus_not_needed_
in_fast_or_hs_mode

CBUS is not allowed in


Fast-mode or Hs-mode.

This check will fire if the CBUS transaction


is issued when the Hs-mode transaction is
entered.

I2C_m_cbus_transaction_
ends_with_stop

CBUS transactions should


always end with STOP.

This check will fire if a CBUS transaction


ends with a restart.

I2C_m_during_address_
phase_master_should_drive_
sda_and_scl

During the address phase, the


Master should drive SDA and
SCL.

Once a Master issues the START, it should


continue to own the bus until the end of the
address phase.

I2C_m_during_arbitration_
if_own_address_master_to_
switch_role_as_slave

An I2C device that has Master


and Slave functions together.
During arbitration, if the
Slave address matches with
its own Slave address, then
the Master should abruptly
terminate the arbitration cycle
to provide sufficient time for
its Slave to respond to the
transaction.

This check is applicable for an I2C device


that has both Master and Slave as active
functions. When such a device starts a
transaction as a Master, and if there is
another Master on the bus that is also
initiating a transaction at the same time, then
the Masters should resolve the winner
through the arbitration process.

Note that Slaves are not


involved in the arbitration
procedure.

If a Master incorporates a Slave function and


it loses arbitration during the addressing
stage, then it is possible that the winning
Master is trying to address it. Therefore, the
losing Master must switch over immediately
to its Slave mode.
Note that this check is disabled when the
DUT is a Master only function.

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Master Checks

Table 10-3. I2C Master Checks (cont.)


Check ID

Violation

Description

I2C_m_during_write_data_
master_should_drive_scl_
during_data_txn

During write transactions, the


Master should drive SCL
during data transfer.

In write transactions, the Master will be in


the data transmitting mode. During the data
phase of the write transaction, the active
Master should own the SDA and SCL bus. It
should drive the SDA with valid values, and
it should toggle the SCL line to transmit the
data.
This check will fire during the data phase of
the write transaction if the SCL line is not
toggled by the Master, which initiated the
write transaction.

I2C_m_during_write_data_
master_should_drive_sda_
during_data_txn

For write transactions, the


Master should drive SDA
during data transfer.

In write transactions, the Master will be in


the data transmitting mode. During the data
phase of the write transaction, the active
Master should own the SDA and SCL bus. It
should drive the SDA with valid values, and
it should toggle the SCL line to transmit the
data.
This check will fire during the data phase of
the write transaction if the SDA line is not
driven by the master, which initiated the
write transaction.

I2C_m_except_start_byte_
start_to_follow_at_least_
one_data_phase

Except for START byte


transfer, every START signal
should follow at least one data
phase.

This is more of a Warning. As per the I2C


protocol, only the START byte does not have
any data phase. This check monitors if all
other transactions have at least one data
phase before it stops or restarts.

I2C_m_for_read_txn_mas_
should_assert_ack_or_nack

For read data transactions, the


Master should assert ACK.

For all data phases during read transactions,


the Master should issue ACK/NACK.

I2C_m_for_write_txn_mas_
should_deassert_sda_out_
during_ack_or_nack

For write transactions, the


Master should de-assert the
sda_out_en signal during
ACK/NACK.

This check ensures that the bus is owned by


Slave during the read data phases, and Master
de-asserts SDA by either deactivating the
*_out_en_n signals or driving SDA to open
collector HIGH.

I2C_m_gcall_address_2nd_
byte_8b00_not_allowed

On the second byte of the


GCALL address, 8'h00 is not
allowed.

The second byte of general call address


should not have all bits zero.

I2C_m_mas_to_stop_or_
restart_if_slv_issues_slave_nack

Master to restart/stop the


transaction if the Slave issues
NACK.

If Slave responds with NACK, then the


Master should terminate the current
transaction by issuing STOP or restart.

I2C_m_master_to_issue_
gcall_address_first_before_
any_valid_txn

After reset, the Master should


issue the GCALL address
before any other transfer.

I2C protocol says that the general call address


should be issued before any valid transaction
is issued on the bus. This check will fire if,
after reset, the monitor observes a valid
read/write transaction before a general call
address transaction.

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Master Checks

Table 10-3. I2C Master Checks (cont.)


Check ID

Violation

Description

I2C_m_max_txn_len_to_
equal_length_parameter_value

Master should signal STOP or


restart if the read/write
transaction length reaches the
configured value of the
maximum transaction length
count parameter
MAX_TXN_LENGTH.

This is a custom check. Protocol does not


enforce this rule. This could be more useful
as constraints to the 0-In Formal tools.

Reserved addresses that


should not be issued.

The I2C protocol specification sets aside a


few addresses as reserved. This monitor
ensures that those reserved addresses are not
issued by the Master on the interface.

I2C_m_reserved_addresses_
not_allowed

This check is disabled if the


MAX_TXN_LENGTH parameter is assigned
with 0.

Ignore this firing if it is legal for your design


that allows an address that comes under the
addresses that are categorized as reserved
addresses in the I2C protocol specification.
I2C_m_reseved_addresses_
not_allowed_in_hs_mode

The reserved address,


8'b0000_1000, is not allowed
in Hs-mode.

Similar to the above check. When the device


enters into Hs-mode, the protocol
specification mentions a few more addresses
as reserved.
This check will fire when Hs-mode is entered
and the addresses that are marked as reserved
are seen on the I2C bus.

I2C_m_sda_to_be_stable_
as_long_as_slave_asserts_
scl_low_towards_slave_wait

SDA should be held stable as


long as SCL is LOW.

When Slave asserts SCL LOW on the


9-bits boundary towards a Slave wait state,
Master should hold the value on the SDA
stable.

I2C_m_serial_data_length_
always_8_bits_wide

Every data phase is only


8-bits wide.

This check ensures that every data phase that


is sent serially does not stop toggling before
transmitting all 8-bits of data.

I2C_m_start_byte_to_
follow_repeated_start

START byte transfer should


follow repeated START.

This check will fire if a START byte


transaction ends with a STOP.

I2C_m_why_same_address_
of_slave_which_is_part_
of_same_device

If the I2C device has Master


and Slave functions, then as a
Master, it should not issue the
address that addresses its own
Slave.

Custom Check. This is not enforced by the


protocol. Could be more useful as constraints
with the formal tools.
This check ensures that the Master of the I2C
DUT that contains both the Master and Slave
functions in a single package, does not
generate an address that addresses a Slave
that is part of the same DUT.
Note that this check is disabled when the
DUT is a Master only function.

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Slave Checks

Table 10-3. I2C Master Checks (cont.)


Check ID

Violation

Description

I2C_ms_after_clock_sync_
high_width_to_be_equal_
that_of_device_had_
shortest_high

Once clock synchronization is


over, the HIGH period of SCL
should be equal to that of the
shortest HIGH that was
observed during the clock
synchronization.

This check ensures that after the clock


synchronization, the SCL HIGH width of the
Master DUT is synchronized, and also the
HIGH period is equal to that of the I2C
device on the bus that had the shortest SCL
HIGH width.

I2C_ms_no_arb_and_clk_
sync_allowed_in_hs_mode

Arbitration and clock


synchronization are not
allowed in Hs-mode.

When the Master device enters into


Hs-mode, clock synchronization and
arbitration functions are not allowed.

I2C_ms_no_scl_low_when_
sda_high_bus_idle

When the bus is IDLE, SCL


and SDA should be high, and
SCL should not toggle.

This rule applies when the I2C bus is idle.


This check is applicable for the I2C Master
and Slave. It ensures that when the I2C bus is
idle and SDA is HIGH, then SCL should be
HIGH and it should not toggle.

Slave Checks
Table 10-4 shows the Slave checks performed by the I2C monitor.
Table 10-4. I2C Slave Checks
Check ID

Violation

Description

I2C_ms_no_scl_low_when_
sda_high_bus_idle

When the bus is IDLE, SCL


and SDA should be high, and
SCL should not toggle.

This rule applies when the I2C bus is idle.


This check is applicable for the I2C Master
and Slave. It ensures that when the I2C bus
is idle and SDA is HIGH, then SCL should
be HIGH and it should not toggle.

I2C_s_address_should_match_
when_the_slave_device_
responds_for_a_txn

When Slave claims the


transaction by signaling ACK
during the address phase, the
address seen on the bus should
match with its address.

This check ensures that the Slave asserts


ACK/NACK towards claiming/not claiming
the transaction when the address on the I2C
bus does/does not match the configured
address.

I2C_s_bit_level_hand_shake_
is_not_allowed_by_stretching_
scl_low

Slave interruption through


signaling SCL LOW can be
only at the 8-bits boundary; it
cannot be between the
data/address bits.

The I2C Slave devices can insert a wait state


by stretching the SCL signal LOW only at
the 8-bits of address/data boundary
(i.e., 8-bits + 1-bit of ACK/NACK), and not
on the middle of the address/data phases.

I2C_s_during_read_data_
slave_should_drive_sda_
during_data_txn

For read transactions, the Slave The check ensures that the SDA is driven by
should drive SDA during data the Slave during the read data phases.
transfer.

I2C_s_for_read_txn_slv_
should_deassert_sda_out_en_
n_during_ack_or_nack

For read transactions, the Slave This check ensures that for a read
should de-assert sda_out_en
transaction the ACK/NACK bit is driven by
during ACK/NACK.
the Master, and the Slave stops driving the
SDA bit to avoid contention.

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Assertion Checks

Table 10-4. I2C Slave Checks (cont.)


Check ID

Violation

Description

I2C_s_for_write_txn_slv_
should_assert_ack_or_nack

For write transactions, the


Slave should assert
ACK/NACK.

For the address/data phases of the write


transactions, the Slave should assert the
ACK or NACK bits.
This check fires for the following
conditions:

If the Slave device does not own the

bus by asserting sda_out_en_n to 1'b0


(if the I/O contains a tristate buffer).

The SDA is LOW, and it is not driven

by the Slave that is addressed (I/O bus


has an open collector).

I2C_s_hs_mode_signaling_
should_be_followed_w_nack

Hs-mode signaling should


always be followed with
NACK.

The Hs-mode signaling is common for all


I2C devices that exist on the bus. Hence,
none of the devices should assert ACK.

I2C_s_no_ack_for_cbus_cycle

No ACK is issued for the


CBUS cycle.

The CBUS signaling is a special


transaction. Hence, regular I2C devices that
exist on the bus should not assert ACK.

I2C_s_start_byte_to_follow_
nack

START byte should always


follow NACK.

The START byte transaction is common for


all I2C devices that exist on the bus. Hence,
none of the devices should assert ACK.

Assertion Checks
Table 10-5 shows the Assertion checks performed by the I2C monitor.
Table 10-5. I2C Assertion Checks
Check ID

Violation

Description

I2C_KNOWN_sda_out

Control signal, sda_out, should


not be X or Z

Checks that control signal sda_out


is both known (not X) and driven
(not Z)

I2C_KNOWN_sda_in

Control signal, sda_in, should not


be X or Z

Checks that control signal sda_in is


both known (not X) and driven
(not Z)

I2C_KNOWN_sda_out_en_n

Control signal, sda_out_en_n,


should not be X or Z

Checks that control signal scl_out


is both known (not X) and driven
(not Z)

I2C_KNOWN_scl_out

Control signal, scl_out, should


not be X or Z

Checks that control signal scl_out


is both known (not X) and driven
(not Z).

I2C_KNOWN_scl_out_en_n

Control signal, scl_out_en_n,


should not be X or Z

Checks that control signal


scl_out_en_n is both known (not
X) and driven (not Z).

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Master Corner Cases

Table 10-5. I2C Assertion Checks (cont.)


Check ID

Violation

Description

I2C_KNOWN_scl_in

Control signal, scl_in, should not


be X or Z

Checks that control signal scl_in is


both known (not X) and driven
(not Z).

I2C_KNOWN_clock_prescale_count

Clock prescale value should not


be X or Z.

Checks that control signal


clock_prescale_count is both
known (not X) and driven (not Z).

Master Corner Cases


Table 10-6 shows the corner cases maintained by the I2C Master monitor.
Table 10-6. I2C Master Corner Cases
Name

Description

Total 7-Bit Addresses

Number of 7-bit addresses issued.

Total 10-Bit Addresses

Number of 10-bit addresses issued.

Master Statistics
Table 10-7 shows the statistics maintained by the I2C Master monitor.
Table 10-7. I2C Master Statistics

320

Name

Description

Total Starts

Number of starts issued.

Total Reads

Number of read transactions performed.

Total Writes

Number of write transactions performed.

Total Stops

Number of stops issued.

Total Repeated Starts

Number of repeated starts issued.

Total Valid Transactions

Number of read and write transactions.

Total Valid Data Phases

Number of data phases with proper ACK.

Total Arbitration Losses

Number of times Master lost in arbitration.

Total Gcall Addresses

Number of general call address transactions.

Total Gcall Slave Resets

Number of general call addresses with Slave reset.

Total Gcall No Slave Resets

Number of general call addresses with no Slave reset.

Total Hardware Gcalls

Number of hardware general call address.

Total Hs-mode Entries

Number of Hs-mode entries.

Total Start Bytes

Number of start byte transactions.

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I2C (Inter-IC) Monitor


Slave Corner Cases

Table 10-7. I2C Master Statistics (cont.)


Name

Description

Total ACKs

Number of positive acknowledgements (ACKs).

Total NACKs

Number of negative acknowledgements (NACKs).

Total CBUS Transactions

Number of CBUS transactions.

Slave Corner Cases


Table 10-8 shows the corner cases maintained by the I2C Slave monitor.
Table 10-8. I2C Slave Corner Cases
Name

Description

Total 7-Bit Addresses

Number of 7-bit addresses received.

Total 10-Bit Addresses

Number of 10-bit addresses received.

Slave Statistics
Table 10-9 shows the statistics maintained by the I2C Slave monitor.
Table 10-9. I2C Slave Statistics
Name

Description

Total Starts

Number of start signals issued.

Total Reads

Number of read transactions performed.

Total Writes

Number of write transactions performed.

Total Stops

Number of stop signals received.

Total Repeated Starts

Number of repeated starts received.

Total Valid Transactions

Number of read and write transactions.

Total Valid Data Phases

Number of data phases with proper ACK.

Total Gcall Addresses

Number of general call address transactions received.

Total Gcall Slave Resets

Number of general call addresses with Slave reset.

Total Gcall No Slave Resets

Number of general call addresses with no Slave reset.

Total Hardware Gcalls

Number of hardware general call address received.

Total Hs-mode Entries

Number of Hs-mode entries.

Total Start Bytes

Number of START byte transactions received.

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Slave Statistics

Table 10-9. I2C Slave Statistics (cont.)

322

Name

Description

Total ACKs

Number of positive acknowledgements (ACKs).

Total NACKs

Number of negative acknowledgements (NACKs).

Total CBUS Transactions

Number of CBUS transactions.

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Chapter 11
Low Pin Count (LPC)
Introduction
The Low Pin Count (LPC) bus interface is designed to enable a system without ISA or X-bus
interfaces. The LPC interface reduces the cost of traditional X-bus devices while meeting or
exceeding the data transfer rate of X-bus. LPC performs the same cycle types as the X-bus:
Memory, I/O, DMA, and Bus Master.

Reference Documentation
This LPC monitor is modeled from the requirements provided in the following document:

Low Pin Count (LPC) Interface Specification, Rev. 1.0, September 29, 1997.

Monitor Placement and Instantiation


To use the LPC monitor, place an instance of the monitor inside the host or peripheral device as
shown in the block diagram in Figure 11-1.
Figure 11-1. LPC Monitor Implementation

PCI
Host Bus

ISA

SuperIO

Host

LPC
Monitor

LPC
Monitor
LPC Local Bus

Monitor Connectivity
Connect the LPC monitor pins to internal signals as specified in the pin-out Table 11-1 and
illustrated in Figure 11-2.

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Monitor Placement and Instantiation

Figure 11-2. LPC Monitor Pin Diagram


lclk
lreset_n
lframe_n
lad
ldrq_n
serirq
clkrun_n
pme_n
lpcpd_n
lmsi_n

LPC Monitor

Table 11-1. LPC Monitor Pins


Pin

Description

clkrun_n

Clock Run. Stopping the clock is not supported by the monitor. The signal
is active low.

lad

The multiplexed command, address and data bus which is 4-bits wide.

lclk

The clock of the LPC interface.

ldrq_n

Encoded DMA / Bus Master request. The signal is active low.

lframe_n

Indicates the start of a cycle or the termination of a broken cycle. The


signal is active low.

lmsi_n

SMI on I/O instruction for retry is not supported by the monitor. The signal
is active low.

lpcpd_n

Power Down. This is not supported by the monitor. The signal is active
low.

lreset_n

The reset signal for the LPC interface. The signal is active low.

pme_n

Power Management Event. This is not supported by the monitor. The


signal is active low.

serirq

Serialized IRQ. Interrupt support is not supported by the monitor. The


signal is active high.

Monitor Parameters
The parameters shown in Table 11-2 configure the LPC monitor.
Table 11-2. LPC Monitor Parameters
Order Parameter

Default Description

1.

Constraints_Mode

Set this parameter to 1 if the checks in the monitor are


to be used as constraints for formal analysis.

2.

LDRQ_WIDTH

Specifies the number of LDRQ# lines.

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Monitor Placement and Instantiation

Table 11-2. LPC Monitor Parameters (cont.)


Order Parameter

Default Description

3.

RETAIN_DMA_ON_
ABORT

on a particular channel when the device does not


respond within the time-out period and the host aborts
the cycle. The default value of 1 indicates that the
monitor retains DMA requests even after an abort
cycle.

4.

CHECK_RESERVED_VALUE

Set this parameter to 1 if the monitor should fire for


reserved SYNC values sent on the LAD bus. The
default value of 0 indicates that the monitor will not
fire for reserved values on the bus.

5.

ALLOW_LARGE_DMA_
TRANSFERS

Set this parameter to 0 if 16-bit/32-bit DMA on 8-bit


channels and 32-bit DMA on 16-bit channels are not
allowed. The default value of 1 indicates that these
transfers are allowed.

6.

ALLOW_DMA_AFTER_
DEACTIVATION

Set this parameter to 0 if the host is not allowed to


initiate DMA transfers on deactivated channels. The
default value of 1 allows the host to initiate DMA
transfers on channels deactivated using an LDRQ
message.

The parameters must be specified in the above order.

When the Constraints_Mode parameter is set to 0, the Constraints Mode feature is disabled, and
all the checks are used as targets when running formal analysis.

Instantiation Example
Example 11-1 instantiates the LPC monitor.
Example 11-1. LPC Monitor Instantiation
qvl_lpc_monitor #(
0,
/* Constraints_Mode */
2,
/* LDRQ_WIDTH */
1,
/* RETAIN_DMA_ON_ABORT */
0,
/* CHECK_RESERVED_VALUE */
1,
/* ALLOW_LARGE_DMA_TRANSFERS */
1
/* ALLOW_DMA_AFTER_DEACTIVATION */ )
lpc_mon (
.lclk
(lclk),
.lreset_n
(lreset_n),
.lframe_n
(lframe_n),
.lad
(lad),
.ldrq_n
(ldrq),
.serirq
(serirq),
.clkrun_n
(clkrun_n),
.pme_n
(pme_n),
.lpcpd_n
(lpcpd_n),
.lsmi_n
(lsmi_n) );

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Low Pin Count (LPC)


Monitor Checks

Monitor Checks
Table 11-3 shows the checks performed by an LPC monitor.
Table 11-3. LPC Checks
Check ID

Violation

Description

LPC_lframe_n

lframe_n has a X or Z value.

lframe_n must always have a valid value.

LPC_ldrq_n

ldrq_n has a X or Z value.

ldrq_n must always have a valid value.

LPC_serirq

serirq has a X or Z value.

serirq must always have a valid value.

LPC_clkrun_n

clkrun_n has a X or Z value.

clkrun_n must always have a valid value.

LPC_pme_n

pme_n has a X or Z value.

pme_n must always have a valid value.

LPC_lpcpd_n

lpcpd_n has a X or Z value.

lpcpd_n must always have a valid value.

LPC_lsmi_n

lsmi_n has a X or Z value.

lsmi_n must always have a valid value

LPC_1

Invalid Cycle Type and Direction


detected (4.2.1.2).

The Cycle Type and Direction specified is


not valid.

LPC_2

Value on lad port is not 4'b1111


during the turnaround cycle
(4.2.1.4).

During a turnaround cycle, lad must be set


to 4'b1111.

LPC_3

CHANNEL cycles can only occur


in DMA operations (4.2.1.6).

A Channel cycle is detected in a non-DMA


operation.

LPC_4

ADDR cycles can only occur in


non-DMA operations (4.2.1.6).

An ADDR cycle is detected in a DMA


operation.

LPC_5

Value on lad port was not constant The lad port during a SYNC cycle indicates
across contiguous synchronization the type of synchronization. This value
cycles (4.2.1.8).
must remain constant across contiguous
SYNC cycles.

LPC_6

The host does synchronization


cycles only in bus master
operations (4.2.1.8).

The host can only perform SYNC cycles in


the bus master operations.

LPC_7

The lad port has an invalid SYNC


value (4.2.1.8).

An invalid SYNC is detected.

LPC_8

The lad port has a reserved SYNC


value (4.2.1.8).

A reserved value is detected on the lad port


during a SYNC cycle.

LPC_9

The peripheral should not be


synchronizing in a bus master
operation (4.2.1.8).

The peripheral can only perform SYNC


cycles in the non-bus master operations.

LPC_10

The lad port has an invalid SIZE


value (4.2.1.3).

An invalid value is detected on the lad port


during a SIZE cycle.

LPC_11

SIZE cycles can only happen in


non-host initiated operations
(4.2.1.3).

A SIZE cycle is detected in a host initiated


operation.

LPC_12

lad[3:2] must be 2'b00 in a SIZE


cycle (4.2.1.3).

lad[3:2] is not 2'b00 in a SIZE cycle.

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Monitor Checks

Table 11-3. LPC Checks (cont.)


Check ID

Violation

Description

LPC_14

The lad port has a reserved


START type (4.2.1.1).

The lad port has a reserved value during a


START cycle.

LPC_15

The lad port does not have value


4'b1111 when lframe_n asserts to
abort the transfer (4.2.2.2).

When an operation is aborted via lframe_n,


lad must be set to 4'b1111.

LPC_16

lframe_n must be asserted for 4


contiguous cycles when aborting
the transfer (4.2.2.2).

When an operation is aborted via lframe_n,


lframe_n must be asserted for 4 contiguous
cycles.

LPC_17

DMA is requested with the


reserved channel number 4 (6.4).

A DMA is requested on the reserved


channel number 4.

LPC_18

DMA operation is occurring on a


channel that did not send a request
for a DMA operation via the ldrq
port (6.4).

A DMA operation has been started on a


channel that did not have a DMA request
outstanding.

LPC_19

Peripheral Initiated Bus Master


operation is occurring on a
channel that did not send a request
for that via the ldrq port (7.3).

A Bus Master operation has been started on


a channel that did not have a Bus Master
operation request outstanding.

LPC_20

A Short Wait is indicated, but it


took more than 8 clocks to SYNC
(4.2.1.8).

A Short Wait is indicated on a SYNC


cycle. However, the device took more than
8 clocks to SYNC. A Long Wait should
have been indicated.

LPC_21

Cycle and Start type mismatch on


the bus master operation (7.2).

A Bus Master operation is indicated on a


CYCTYPE cycle, but a Bus Master
operation is not indicated on the START
cycle.

LPC_22

A request for a peripheral initiated


bus master operation is received
on ldrq port
[",8d48+s[WIDTH_OF_LDRQ_
WIDTH:0],"] when another bus
master request is outstanding
(7.3).

A bus master request is received when


another bus master request is still
outstanding. Only one bus master request
can be outstanding at any time.

LPC_23

The sequence of values on the


An illegal sequence of values is detected on
ldrq port
the ldrq port.
[",8d48+s[WIDTH_OF_LDRQ_
WIDTH:0],"] do not match a valid
DMA or Bus Master request (6.2).

LPC_24

A DMA deactivation request is


received on the ldrq port
[",8d48+s[WIDTH_OF_LDRQ_
WIDTH:0],"] for a channel that
does not have a DMA request
outstanding (6.3).

A DMA abort request is received via the


ldrq port for a channel that does not have a
DMA request outstanding.

LPC_25

Invalid start type.

An invalid start type encoding is detected


on the lad port.

LPC_26

Invalid size.

An invalid size encoding is detected on the


lad port.

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Low Pin Count (LPC)


Monitor Checks

Table 11-3. LPC Checks (cont.)


Check ID

Violation

Description

LPC_27

A '0000b' (Ready) or '1010b'


(Ready with Error) encoding sent
on the SYNC field of an odd byte
during a read operation on a 16-bit
DMA channel (6.4.3).

Indicating a '0000b' or '1010b' (Ready or


Ready with Error) encoding on the SYNC
field of an odd byte of a 16-bit DMA
channel is an error condition. In case of
DMA read transfers, these encodings must
not be sent by the peripheral after the first
byte has been received. A violation of this
rule causes this check to fire.

LPC_28

A '0000b' (Ready) or '1010b'


(Ready with Error) encoding sent
on the SYNC field of an odd byte
during a write operation on a 16bit DMA channel (6.4.3).

Indicating a '0000b' or '1010b' (Ready or


Ready with Error) encoding on the SYNC
field of an odd byte of a 16-bit DMA
channel is an error condition. In case of
DMA write transfers, these encodings must
not be sent by the peripheral before the first
byte has been transferred. A violation
causes this check to fire.

LPC_29

Larger DMA transfer attempted


on a device which does not
support large transfer sizes (6.1).

If the peripheral is not capable of larger


transfers, then 16-bit/32-bit DMA must not
be performed on channels 0-3 and 32-bit
DMA must not be performed on channels
5-7. A violation causes this check to fire.

LPC_30

A DMA request sent on ldrq port


[",8d48+s[WIDTH_OF_LDRQ_
WIDTH:0],"] for a channel that
has already been requested by
another ldrq port.

No two devices can request DMA transfers


on the same channel number. The monitor
fires if it detects more than one LDRQ#
port requesting DMA transfers using the
same channel number (except channel
number 4).

LPC_31

A Bus Master request sent on ldrq


port
[",8d48+s[WIDTH_OF_LDRQ_
WIDTH:0],"] that is not allowed
to perform Bus Master cycles as
two other ports have already
registered Bus Master requests.

The LPC protocol allows 2 devices capable


of performing bus-master cycles. The
monitor fires if it detects more than 2
devices requesting bus-master cycles.

LPC_32

A message started on ldrq port


[",8d48+s[WIDTH_OF_LDRQ_
WIDTH:0],"] prior to 8 clocks
from de-assertion of a DMA
request using SYNC field (6.4.4).

Since DMA transfers on LPC are requested


through an LDRQ# assertion message and
are ended through a SYNC field during the
DMA transfer, the peripheral must not
assert another message for 8 LCLKs after a
de-assertion is indicated through the SYNC
field. A violation of this rule causes the
monitor to fire.

LPC_unsupported_serirq

Serialized IRQ mode is not


currently supported.

The LPC monitor does not support


serialized IRQ mode.

LPC_unsupported_clkrun_n

Clock Run is not currently


supported.

The LPC monitor does not support clock


run.

LPC_unsupported_pme_n

PME (power management) mode


is not currently supported.

The LPC monitor does not support power


management mode.

LPC_unsupported_lpcpd_n

Power Down mode is not


currently supported.

The LPC monitor does not support power


down mode.

LPC_unsupported_lsmi_n

SMI is not currently supported.

The LPC monitor does not support SMI.

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Low Pin Count (LPC)


Monitor Corner Cases

Monitor Corner Cases


The corner cases captured by the LPC monitor are shown in Table 11-4. These corner cases are
collected separately on the master and target controllers.
Table 11-4. LPC Monitor Corner Cases
Corner Case

Description

Host Initiated I/O Read Transfers

Number of host initiated I/O read operations.

Host Initiated I/O Write Transfers

Number of host initiated I/O write operations.

Host Initiated Memory Read Transfers

Number of host initiated memory read operations.

Host Initiated Memory Write Transfers

Number of host initiated memory write operations.

DMA Read Transfers

Number of DMA read operations.

DMA Write Transfers

Number of DMA write operations.

Peripheral Initiated I/O Read Transfers

Number of peripheral initiated I/O read operations.

Peripheral Initiated I/O Write Transfer

Number of peripheral initiated I/O write operations.

Peripheral Initiated Memory Read Transfers

Number of peripheral initiated memory read operations.

Peripheral Initiated Memory Write Transfers

Number of peripheral initiated memory write operations.

Back to Back Transfers

Number of back to back operations.

Aborted Transfers

Number of operations that are aborted.

8-bit Data Transfers

Number of operations with 8-bit data.

16-bit Data Transfers

Number of operations with 16-bit data.

32-bit Data Transfers

Number of operations with 32-bit data.

DMA Transfers On Deactivated Channels

Number of times the host went ahead with the DMA


transfer even after the peripheral deactivated the channel.

Monitor Statistics
The statistics captured by the LPC monitor are shown in Table 11-5. These statistics are
collected separately on the master and target controllers.
Table 11-5. LPC Monitor Statistics
Statistic

Description

Total Transfers

Total number of transfer operations.

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Low Pin Count (LPC)


Monitor Statistics

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Chapter 12
Open Core Protocol (OCP)
Introduction
The Open Core Protocol (OCP) is a core-centric protocol that comprehensively describes the
system level integration requirements of intellectual property (IP) cores. The OCP supports very
high performance data transfer models ranging from simple request-grants through pipelined
and multi-threaded objects. Higher complexity SOC communication models are supported
using thread identifiers to manage out-of-order completion of multiple concurrent transfer
sequences. The QVL OCP monitor is designed for checking the OCP interfaces.

Reference Documentation
This OCP monitor is modeled from the requirements provided in the following documents:

Open Core Protocol Specification 2.1, Document Revision 1.0, Part number: 161000125-0003.

Open Core Protocol Specification 2.2, Document Revision 1.1

Please refer to Instantiation Modification is Required for OCP 2.1 Users on page 333 for
additional information.

Supported Features
Commands

Basic Commands: Read, Write, Idle.

Five command extensions: WriteNonPost, Broadcast, ReadExclusive, ReadLinked, and


WriteConditional.

Data Transfers

Pipelined data transfers.

Non-Pipelined data transfers.

Bursts

Precise Bursts with single address.

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Open Core Protocol (OCP)


Supported Features

Precise Bursts with successive command address.

Imprecise Bursts with successive command address.

Bursts with combined request and data.

Bursts with optional Last signals.

Supports WRAP, INCR, STRM, XOR, and BLCK (two-dimensional) type bursts.

Response Signaling

All types of responses: NULL, DVA, FAIL, and ERR.

Tags

Out-of-order return of responses.

Out-of-order commit of write data.

Threads and Connections

Out-of-order thread processing.

Supports exact ThreadBusy semantics.

Data buses

Partial word transfer using MByteEn and MDataByteEn.

Inband Signaling.

Data transfers with Data Handshake Phase.

Synchronization

Locked Synchronization.

Lazy Synchronization.

Sideband Signals

332

Reset Signals.

Control and Status Signals.

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Open Core Protocol (OCP)


Supported Features

OCP Disconnect Proposal Revision 0.6

Three disconnect signals: mconnect, sconnect, and swait

Parameter CONNECTION and tie-off signal as per the OCP disconnect proposal.

Refer to Instantiation Modification is Required for OCP 2.1 and 2.2 Users on page 334 for
additional information.

Unsupported Features

Scan Interface, Clock Control Interface, Debug and Test Interface.

The monitor will assume the data as-is and will not perform endianness conversion.

Interleaving of transfers on any of the phases is not supported if the dataflow transfer
checks are enabled. Dataflow transfer checks are enabled by enabling the parameter
ENABLE_INTER_PHASE_TRANFER_CHECKS.

Instantiation Modification is Required for OCP 2.1 Users


The OCP monitor now supports Open Core Protocol Specification 2.2, Document Revision 1.1.
As a result, the monitor has more ports, more bits in some configuration ports, and more
parameters added in its interface.
A user supporting only Open Core Protocol Specification 2.1, Document Revision 1.0 does not
need to be concerned about the OCP 2.2 parameters (detailed in the subsection below) as these
parameters are located at the bottom of the parameter order in the monitor implementation and
they carry their own default values.

Ports Added for OCP 2.2 Compliance


Following are the new ports added for OCP 2.2 compliance (see Table 12-1 on page 341):

enableclk

mareset_n

sareset_n

mblockheight

mblockstride

mdatarowlast

mreqrowlast

sresprowlast

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Open Core Protocol (OCP)


Supported Features

The two asynchronous reset ports should each be connected to 1'b1; the remainder of the ports
should be unconnected for a OCP 2.1 specification use model.

Configuration Port Changes for OCP 2.2 Compliance


Following are the configuration ports that have changes for OCP 2.2 compliance (see
Table 12-1 on page 341:

basic_group OCP 2.2 has 8-bits instead of 7-bits in width in OCP 2.1.

burst_ext_group OCP 2.2 has 23-bits instead of 17-bits in width in OCP 2.1.

thread_ext_group OCP 2.2 has 10-bits instead of 7-bits in width in OCP 2.1.

The new higher order bits are all set to 0 when connecting these configuration ports for a OCP
2.1 specification use model.

Parameters Added for OCP 2.2 Compliance


The following parameters are added to the end of the order of the existing parameters, and they
all have default values (see Table 12-2 on page 350):

BLOCKHEIGHT_WDTH

BLOCKSTRIDE_WDTH

These parameters can be ignored for a OCP 2.1 specification use model instance of the monitor.

Instantiation Modification is Required for OCP 2.1 and 2.2


Users
The following ports and parameters are part of OCP Disconnect Proposal (version 0.6) that
require special handling by the OCP 2.1 and OCP 2.2 users:

Parameter CONNECTION: Leave at default value 0.

Ports mconnect, sconnect, swait: Leave these ports unconnected.

Following is the configuration port change for OCP Disconnect Proposal compliance:

sideband_sig_group Port has support for 7-bit width instead of 6-bit width in OCP
2.1 and OCP 2.2 (see Table 12-1 on page 341).

The new higher order bits are all set to 0 when connecting these configuration ports for a OCP
2.1 or 2.2 specification use model.

Example Instance of the Monitor Using OCP 2.1 Specification


A typical example instance of the monitor for the OCP 2.1 specification use model is as follows:
qvl_ocp_monitor #(

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Open Core Protocol (OCP)


Supported Features
0,
/* Constraints_Mode */
0,
/* INTERFACE_TYPE */
8,
/* ADDR_WDTH */
16,
/* DATA_WDTH */
4,
/* BURSTLENGTH_WDTH */
3,
/* ATOMICLENGTH_WDTH */
3,
/* THREADS */
2,
/* THREADID_WDTH */
1,
/* CONNID_WDTH */
2,
/* ADDRSPACE_WDTH */
16,
/* MDATAINFO_WDTH */
4,
/* MDATAINFOBYTE_WDTH */
10,
/* REQINFO_WDTH */
10,
/* RESPINFO_WDTH */
16,
/* SDATAINFO_WDTH */
4,
/* SDATAINFOBYTE_WDTH */
4,
/* CONTROL_WDTH */
4,
/* STATUS_WDTH */
3,
/* TAGS */
2,
/* TAGID_WDTH */
1,
/* TAG_INTERLEAVE_SIZE */
1,
/* ENABLE_INTER_PHASE_TRANFER_CHECKS */
16
/* MAX_OUTSTANDING_REQ */
// Neglected OCP 2.2 and disconnect specification relevant
// parameters
)
OCP_MONITOR ( .clk(Clk),
.enableclk(), // Unconnected OCP 2.2 specific port
.areset_n(1'b1),
.mdata(MData),
.mdatavalid (MDatavalid),
.mrespaccept(MRespaccept),
.scmdaccept(SCmdaccept),
.sdata(SData),
.sdataaccept(SDataaccept),
.sresp(SResp),
.maddrspace(MAddrSpace),
.mbyteen(MByteen),
.mdatabyteen(MDatabyteen),
.mdatainfo(MDataInfo),
.mreqinfo(MReqInfo),
.sdatainfo(SDataInfo),
.srespinfo(SRespInfo),
.matomiclength(MAtomicLength),
.mburstlength(MBurstLength),
.mburstprecise(MBurstPrecise),
.mburstseq(MBurstSeq),
.mburstsinglereq(MBurstSingleReq),
.mdatalast(MDatalast),
.mreqlast(MReqLast),
.sresplast(SResplast),
.mdatatagid(MDataTagID),
.mtagid(MTagID),
.mtaginorder(MTagInOrder),
.stagid(STagID),
.staginorder(STagInOrder),
.mconnid(MConnID),
.mdatathreadid(MDataThreadID),

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Open Core Protocol (OCP)


Supported Features
.mthreadbusy(MThreadBusy),
.mthreadid(MThreadID),
.sdatathreadbusy(SDataThreadBusy),
.sthreadbusy(SThreadBusy),
.sthreadid(SThreadID),
.mreset_n(MReset_n),
.sreset_n(SReset_n),
.mareset_n(1'b1), // OCP 2.2 specific async reset tied to 1'b1
.sareset_n(1'b1), // OCP 2.2 specific async reset tied to 1'b1
.control(4'd0),
.controlbusy(1'b0),
.controlwr(1'b0),
.status(4'd0),
.statusbusy(1'b0),
.statusrd(1'b0),
.base(8'b0),
.phase_options_group(3'b001),
.basic_group(8'b0111_1111), // The 8th bit position is set to 0.
.simple_ext_group(7'b001_0100),
.burst_ext_group(23'b000_0000_0110_1011_0000_0001), // 18th - 23rd
// bit positions are all set to 0s
.tag_ext_group(1b0),
.thread_ext_group(10b00_0111_1111), // 8th - 10th bit positions
// are all set to 0s.
.sideband_sig_group(7'b000_0000),
.cmd_enable_group(6'b00_0011)
.mblockheight(), // OCP 2.2 specific ports are left unconnected
.mblockstride(),
.mdatarowlast(),
.mreqrowlast(),
.sresprowlast(),
.mconnect(), // Disconnect specific ports are left unconnected
.sconnect(),
.swait()
);

Refer to Instantiation Examples on page 352 for OPC 2.2 typical examples.

Example Instance of the Monitor Using OCP 2.2 Specification


A typical example instance of the monitor for the OCP 2.2 specification use model is as follows:
qvl_ocp_monitor #(
0,
/* Constraints_Mode */
0,
/* INTERFACE_TYPE */
8,
/* ADDR_WDTH */
16,
/* DATA_WDTH */
4,
/* BURSTLENGTH_WDTH */
3,
/* ATOMICLENGTH_WDTH */
3,
/* THREADS */
2,
/* THREADID_WDTH */
1,
/* CONNID_WDTH */
2,
/* ADDRSPACE_WDTH */
16,
/* MDATAINFO_WDTH */
4,
/* MDATAINFOBYTE_WDTH */
10,
/* REQINFO_WDTH */
10,
/* RESPINFO_WDTH */
16,
/* SDATAINFO_WDTH */

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Open Core Protocol (OCP)


Supported Features
4,
4,
4,
3,
2,
1,
1,
16,
0,

/*
/*
/*
/*
/*
/*
/*
/*
/*

SDATAINFOBYTE_WDTH */
CONTROL_WDTH */
STATUS_WDTH */
TAGS */
TAGID_WDTH */
TAG_INTERLEAVE_SIZE */
ENABLE_INTER_PHASE_TRANFER_CHECKS */
MAX_OUTSTANDING_REQ */
BLOCKHEIGHT_WDTH; To ensure backward compatibility, this parameter must be 0
for 2.1 use model as this is disabled in the configuration for 2.1 */
4
/* BLOCKSTRIDE_WDTH */
// Neglected disconnect specification relevant parameters
)
OCP_MONITOR ( .clk(Clk),
.enableclk(), // Unconnected OCP 2.2 specific port
.areset_n(1'b1),
.mdata(MData),
.mdatavalid (MDatavalid),
.mrespaccept(MRespaccept),
.scmdaccept(SCmdaccept),
.sdata(SData),
.sdataaccept(SDataaccept),
.sresp(SResp),
.maddrspace(MAddrSpace),
.mbyteen(MByteen),
.mdatabyteen(MDatabyteen),
.mdatainfo(MDataInfo),
.mreqinfo(MReqInfo),
.sdatainfo(SDataInfo),
.srespinfo(SRespInfo),
.matomiclength(MAtomicLength),
.mburstlength(MBurstLength),
.mburstprecise(MBurstPrecise),
.mburstseq(MBurstSeq),
.mburstsinglereq(MBurstSingleReq),
.mdatalast(MDatalast),
.mreqlast(MReqLast),
.sresplast(SResplast),
.mdatatagid(MDataTagID),
.mtagid(MTagID),
.mtaginorder(MTagInOrder),
.stagid(STagID),
.staginorder(STagInOrder),
.mconnid(MConnID),
.mdatathreadid(MDataThreadID),
.mthreadbusy(MThreadBusy),
.mthreadid(MThreadID),
.sdatathreadbusy(SDataThreadBusy),
.sthreadbusy(SThreadBusy),
.sthreadid(SThreadID),
.mreset_n(MReset_n),
.sreset_n(SReset_n),
.mareset_n(1'b1), // OCP 2.2 specific async reset tied to 1'b1
.sareset_n(1'b1), // OCP 2.2 specific async reset tied to 1'b1
.control(4'd0),
.controlbusy(1'b0),
.controlwr(1'b0),
.status(4'd0),

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Monitor Placement and Instantiation
.statusbusy(1'b0),
.statusrd(1'b0),
.base(8'b0),
.phase_options_group(3'b001),
.basic_group(8'b0111_1111), // The 8th bit position is set to 0.
.simple_ext_group(7'b001_0100),
.burst_ext_group(23'b000_0000_0110_1011_0000_0001), // 18th - 23rd
// bit positions are all set to 0s
.tag_ext_group(1b0),
.thread_ext_group(10b00_0111_1111), // 8th - 10th bit positions
// are all set to 0s.
.sideband_sig_group(7'b000_0000),
.cmd_enable_group(6'b00_0011)
.mblockheight(), // OCP 2.2 specific ports are leftunconnected
.mblockstride(),
.mdatarowlast(),
.mreqrowlast(),
.sresprowlast(),
.mconnect(), // Disconnect specific ports are left unconnected
.sconnect(),
.swait()
);

Monitor Placement and Instantiation


The QVL OCP monitor can be placed on the master or slave side to provide interface checks.
The checks in the OCP monitor can also be used as search targets and check constraints while
running formal analysis on the OCP master or slave devices. A typical OCP setup is shown in
Figure 12-1.
Figure 12-1. OCP Monitor Implementation
OCP
Interface
OCP
Compliant
Device
(Master)

OCP
MW

System / Core

OCP
MW

OCP
Compliant
Device
(Slave)

Core / System

In Figure 12-1, the Core / System side means the IP block side. The System / Core side means
the interconnect side (if any), or simply the bus wrapper interface module.
The four parameter values for the INTERFACE_TYPE parameter (see Table 12-2 on page 350)
comes from the four possible locations of the OCP monitor instance in reference to the system
configuration diagram shown in Figure 12-2. The required INTERFACE_TYPE parameter values
at specific locations in the whole system as per monitor instances are as follows:

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If the user connects the monitor to the OCP Master DUT, then set as follows:
INTERFACE_TYPE = 0

If the user connects the monitor to the OCP Slave DUT, then set as follows:
INTERFACE_TYPE = 1

If the user connects the monitor to the Master side of the interconnect/bus wrapper
module, then set as follows:
INTERFACE_TYPE = 2

If the user connects the monitor to the Slave side of the interconnect/bus wrapper
module, then set as follows:
INTERFACE_TYPE = 3

Note that these parameter values come into play only when the Constraints_Mode parameter
is set to 1 (see Table 12-2 on page 350).
The system configuration block diagram (Figure 12-2) depicts the configuration around three
possible DUTs: Master DUT, Slave DUT, and both the Master DUT and Slave DUT.

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Figure 12-2. OCP Monitor


System Initiator

System Initiator / Target

Core

System Target
Core

Core

INTERFACE_TYPE=0

INTERFACE_TYPE=0

INTERFACE_TYPE=1

INTERFACE_TYPE=1

DUT Master

DUT Master

DUT Slave

DUT Slave

Response

OCP

Bus
wrapper
interface
module

Request

Slave

Slave

Master

Master

INTERFACE_TYPE=3

INTERFACE_TYPE=3

INTERFACE_TYPE=2

INTERFACE_TYPE=2

Bus Initiator

Bus Initiator / Target

Bus Target

On-Chip Bus

Note:
This figure illustrates the OPC system configuration showing the OPC monitor INTERFACE_TYPE
parameter value with regards to the monitor instance location.

Monitor Connectivity
Connect the OCP monitor pins as specified in the pin-out Table 12-1 and illustrated in
Figure 12-3.

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mconnid
mdatathreadid
mthreadbusy
mthreadid
sdatathreadbusy
sthreadbusy
sthreadid

maddrspace
mbyteen
mdatabyteen
mdatainfo
mreqinfo
sdatainfo
srespinfo

OCP
Monitor

matomiclength
mblockheight
mblockstride
mburstlength
mburstprecise
mburstseq
mburstsinglereq
mdatalast
mdatarowlast
mreqlast
mreqrowlast
sresplast
sresprowlast

mreset_n
mareset_n
sreset_n
sareset_n
control
controlbusy
controlwr
status
statusbusy
statusrd
mconnect
sconnect
swait
phase_options_group
basic_group
simple_ext_group
burst_ext_group
tag_ext_group
thread_ext_group
sideband_sig_group
cmd_enable_group

areset_n
base

Tag
Extensions
Thread
Extensions

mdatatagid
mtagid
mtaginorder
stagid
staginorder

Sideband Signals

clk
enableclk
maddr
mcmd
mdata
mdatavalid
mrespaccept
scmdaccept
sdata
sdataaccept
sresp

Monitor Signals

Burst Extensions

Simple Extensions

Basic Signals

Figure 12-3. OCP Monitor Pin Diagram

Table 12-1. OCP Monitor Pin


Port

Width (bits)

Description

areset_n

Asynchronous reset signal (active low). This signal is not part of OCP
interface.

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Table 12-1. OCP Monitor Pin (cont.)


Port

Width (bits)

Description

base

configurable

BASE address for the XOR (exclusive OR) bursts. Width of this signal
is same as the maddr signal. This signal is required only if XOR bursts
are enabled.
The parameter BASE_PORT_SPECIFIED determines if the value at
this port matters. This parameter specifies if the base address for XOR
bursts is calculated by the user and passed to the monitor, or the monitor
should self-calculate the base address value for a XOR burst type
transaction. See the description of the BASE_PORT_SPECIFIED
parameter for more information.

basic_group

Bit position
0
1
2
3
4
5
6
7
See Note 2.

burst_ext_group

23

Bit position
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

clk

Input clock to OCP.

cmd_enable_group

Bit position
0
1
2
3
4
5

control

configurable

Core control information

342

Parameter
ADDR
CMDACCEPT
DATAACCEPT
MDATA
SDATA
RESPACCEPT
RESP
ENABLECLK
Parameter
BURSTSEQ_INCR_ENABLE
BURSTSEQ_STRM_ENABLE
BURSTSEQ_WRAP_ENABLE
BURSTSEQ_XOR_ENABLE
BURSTSEQ_DFLT1_ENABLE
BURSTSEQ_DFLT2_ENABLE
BURSTSEQ_UNKN_ENABLE
ATOMICLENGTH
BURSTLENGTH
BURSTPRECISE
BURSTSEQ
BURSTSINGLEREQ
REQLAST
DATALAST
RESPLAST
BURST_ALIGNED
FORCE_ALIGNED
BURSTSEQ_BLCK_ENABLE
BLOCKHEIGHT
BLOCKSTRIDE
DATAROWLAST
REQROWLAST
RESPROWLAST

Parameter
READ_ENABLE
WRITE_ENABLE
WRITENONPOST_ENABLE
BROADCAST_ENABLE
RDLWRC_ENABLE
READEX_ENABLE

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Table 12-1. OCP Monitor Pin (cont.)


Port

Width (bits)

Description

controlbusy

Hold control information

controlwr

Control information has been written

enableclk

Gating signal for the input clock to derive the OCP clock. This signal is
effective when the OCP parameter enableclk is set to 1 (configured
under basic signal group, refer to Note 6 below).

maddr

configurable

Transfer address

maddrspace

configurable

Address space

mareset_n

Active low asynchronous master reset signal. If the OCP application


supports asynchronous reset, then this signal must be connected to
appropriate asynchronous master reset signal and the monitors
synchronous master reset signal input mreset_n should be tied HIGH
(always inactive synchronous reset). However, if the application
supports synchronous reset only, then this signal should be tied to HIGH
(always inactive asynchronous reset) and the monitors synchronous
master reset signal input mreset_n must be connected to appropriate
synchronous master reset signal.

matomiclength

configurable

Length of atomic burst

mblockheight

configurable

Number of rows in a block burst

mblockstride

configurable

Address difference between the first data word in each consecutive row
in a block burst.

mburstlength

configurable

Burst length

mburstprecise

Given burst length is precise

mburstseq

Address sequence of burst

mburstsinglereq

Burst uses single request / multiple data protocol

mbyteen

configurable

Request phase byte enables

mcmd

Transfer command

mconnect

Master signal for OCP disconnect/connect control

mconnid

configurable

Connection identifier

mdata

configurable

Write data

mdatabyteen

configurable

Datahandshake phase write byte enables

mdatainfo

configurable

Additional information transferred with the write data

mdatalast

Last write data in burst

mdatarowlast

Last dataphase in a row in a block burst

mdatatagid

configurable

Ordering tag for write data

mdatathreadid

configurable

Write data thread identifier

mdatavalid

Write data valid

mreqinfo

configurable

Additional information transferred with the request

mreqlast

Last request in burst

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Table 12-1. OCP Monitor Pin (cont.)


Port

Width (bits)

Description

mreqrowlast

Last request phase in a row in a block burst

mreset_n

Synchronous master reset (also see description for mareset_n)

mrespaccept

Master accepts response

mtagid

configurable

Ordering tag for request

mtaginorder

Do not reorder this request

mthreadbusy

configurable

Master thread busy

mthreadid

configurable

Request thread identifier

phase_options_group

Bit position
0
1
2
See Note 2.

sareset_n

Active low asynchronous slave reset signal. If the OCP application


supports asynchronous reset, then this signal must be connected to
appropriate asynchronous slave reset signal and the monitors
synchronous slave reset signal input sreset_n should be tied HIGH
(always inactive synchronous reset). However, if the application
supports synchronous reset only, then this signal should be tied to HIGH
(always inactive asynchronous reset) and the monitors synchronous
slave reset signal input sreset_n must be connected to appropriate
synchronous slave reset signal.

scmdaccept

Slave accepts command transfer

sconnect

Slave signal for OCP disconnect/connect request

sdata

configurable

Read data

sdataaccept

Slave accepts write data

sdatainfo

configurable

Additional information transferred with the read data

sdatathreadbusy

configurable

Slave write data thread busy

sideband_sig_group

Bit position
0
1
2
3
4
5
6

344

Parameter
DATAHANDSHAKE
REQDATA_TOGETHER
WRITERESP_ENABLE

Parameter
CONTROL
CONTROLBUSY
CONTROLWR
STATUS
STATUSBUSY
STATUSRD
CONNECTCAP

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Table 12-1. OCP Monitor Pin (cont.)


Port

Width (bits)

Description

simple_ext_group

Bit position
0
1
2
3
4
5
6
See Note 2.

sreset_n

Synchronous slave reset (also see description for sareset_n)

sresp

Transfer response

srespinfo

configurable

Additional information transferred with the response

sresplast

Last response in burst

sresprowlast

Last response phase in a row in a block burst

stagid

configurable

Ordering tag for response

staginorder

This response is not reordered

status

configurable

Core status information

statusbusy

Status information is not consistent

statusrd

Status information has been read

sthreadbusy

configurable

Slave request thread busy

sthreadid

configurable

Response thread identifier

swait

Slave signal for insert/bypass wait states for disconnect/connect events

tag_ext_group

Bit position
Parameter
0
TAGINORDER

thread_ext_group

10

Bit position
Parameter
0
MTHREADBUSY_EXACT
1
SDATATHREADBUSY_EXACT
2
STHREADBUSY_EXACT
3
CONNID
4
MTHREADBUSY
5
SDATATHREADBUSY
6
STHREADBUSY
7
MTHREADBUSY_PIPELINED
8
SDATATHREADBUSY_PIPELINED
9
STHREADBUSY_PIPELINED

tieoff_connectcap

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
OCP disconnect parameter ConnectCap.

tieoff_control

configurable

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port control is configured through this port.

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Parameter
ADDRSPACE
BYTEEN
MDATABYTEEN
MDATAINFO
REQINFO
RESPINFO
SDATAINFO

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Table 12-1. OCP Monitor Pin (cont.)


Port

Width (bits)

Description

tieoff_controlbusy

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port controlbusy is configured through this port.

tieoff_controlwr

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port controlwr is configured through this port.

tieoff_enableclk

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port enableclk is configured through this port.

tieoff_maddr

configurable

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port maddr is configured through this port.

tieoff_maddrspace

configurable

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port maddrspace is configured through this port.

tieoff_matomiclength

configurable

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port matomiclength is configured through this port.

tieoff_mblockheight

configurable

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port mblockheight is configured through this port.

tieoff_mblockstride

configurable

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port mblockstride is configured through this port.

tieoff_mburstlength

configurable

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port mburstlength is configured through this port.

tieoff_mburstprecise

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port mburstprecise is configured through this port.

tieoff_mburstseq

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port mburstseq is configured through this port.

tieoff_mburstsinglereq 1

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port mburstsinglereq is configured through this port.

tieoff_mbyteen

configurable

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port mbyteen is configured through this port.

tieoff_mconnid

configurable

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port mconnid is configured through this port.

tieoff_mdata

configurable

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port mdata is configured through this port.

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Table 12-1. OCP Monitor Pin (cont.)


Port

Width (bits)

Description

tieoff_mdatabyteen

configurable

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port mdatabyteen is configured through this port.

tieoff_mdatainfo

configurable

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port mdatainfo is configured through this port.

tieoff_mdatalast

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port mdatalast is configured through this port.

tieoff_mdatarowlast

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port mdatarowlast is configured through this port.

tieoff_mdatatagid

configurable

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port mdatatagid is configured through this port.

tieoff_mdatathreadid

configurable

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port mdatathreadid is configured through this port.

tieoff_mdatavalid

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port mdatavalid is configured through this port.

tieoff_mreqinfo

configurable

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port mreqinfo is configured through this port.

tieoff_mreqlast

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port mreqlast is configured through this port.

tieoff_mreqrowlast

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port mreqrowlast is configured through this port.

tieoff_mrespaccept

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port mrespaccept is configured through this port.

tieoff_mtagid

configurable

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port mtagid is configured through this port.

tieoff_mtaginorder

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port mtaginorder is configured through this port.

tieoff_mthreadbusy

configurable

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port mthreadbusy is configured through this port.

tieoff_mthreadid

configurable

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port mthreadid is configured through this port.

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Table 12-1. OCP Monitor Pin (cont.)


Port

Width (bits)

Description

tieoff_scmdaccept

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port scmdaccept is configured through this port.

tieoff_sdata

configurable

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port sdata is configured through this port.

tieoff_sdataaccept

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port sdataaccept is configured through this port.

tieoff_sdatainfo

configurable

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port sdatainfo is configured through this port.

tieoff_sdatathreadbusy configurable

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port sdatathreadbusy is configured through this port.

tieoff_sresp

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port sresp is configured through this port.

tieoff_srespinfo

configurable

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port srespinfo is configured through this port.

tieoff_sresplast

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port sresplast is configured through this port.

tieoff_sresprowlast

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port sresprowlast is configured through this port.

tieoff_stagid

configurable

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port stagid is configured through this port.

tieoff_staginorder

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port staginorder is configured through this port.

tieoff_status

configurable

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port status is configured through this port.

tieoff_statusbusy

configurable

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port statusbusy is configured through this port.

tieoff_statusrd

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port statusrd is configured through this port.

tieoff_sthreadbusy

configurable

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port sthreadbusy is configured through this port.

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Table 12-1. OCP Monitor Pin (cont.)


Port

Width (bits)

Description

tieoff_sthreadid

configurable

This port is applicable when macro QVL_OCP_TIEOFF_CONFIG_ON


is enabled while compiling the monitor. Custom tie-off value for the
port sthreadid is configured through this port.

Notes:
1. Refer to the parameters section for description of parameters that configure the width of
the ports.
2. Bit 0 is the Least Significant Bit. Device parameters are configured as shown in the
following examples.
Example (a): If the design under test (DUT) supports the DATAHANDSHAKE
feature, then bit 0 of the port phase_options_group is set to 1'b1.
Example (b): If the design under test (DUT) supports Status signal, then bit 3 of the
port sideband_sig_group is set to 1'b1.
Example (c): If the design under test (DUT) supports disconnect protocol of OCP,
then the highest order bit 6 of the port sideband_sig_group is set to 1'b1.
3. If a signal is not configured for an interface, then the corresponding monitor port can be
left unconnected. A default tie-off value (as specified by the specification) for that signal
is assumed by the monitor. In the case where the design uses a tie-off value other than
default tie-off, the signal should be configured and tied to the tie-off value used in the
design.
The monitor also supports configuring tie-off values through additional ports in the
monitor interface. For such mode of tie-off configuration, the user has to do the
following:
i. Add +define+QVL_OCP_TIEOFF_CONFIG_ON to the command line while
compiling the monitor.
ii. The respective signal to be tied off to a custom value should not be configured in
the configuration ports.
iii. Connect the custom tie-off values to the tie-off configuration specific ports listed
in Table 12-1 on page 341.
4. Reset signals (mreset_n, sreset_n) should be tied to the proper system reset or to the
inactive condition (1'b1).
5. OCP specifies that the reset signals (mreset_n and sreset_n) should be asserted for at
least 16 clock cycles. Monitor does not check for this and enters in to reset state in the
first clock cycle on which reset is sampled asserted.

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6. If the signal enableclk is added to the OCP interface, then the 8th bit in the monitor
configuration port, basic_signal_group should be set to 1. Then the derived OCP
clock used by the monitor is controlled by the enableclk signal. However, if the
signal enableclk is not added to the OCP interface, then the 8th bit in the same
configuration port should be set to the OCP recommended default 0. Then the derived
OCP clock used by the monitor is the same as the input clock.

Monitor Parameters
The parameters shown in Table 12-2 configure the OCP monitor.
Table 12-2. OCP Monitor Parameters
Order Parameter

Default

Description

1.

Constraints_Mode

Set this parameter to 1 if the checks in the monitor


are to be used as constraints for formal analysis.

2.

INTERFACE_TYPE

Set this parameter depending on the interface on


which the monitor is instantiated:
0 => Master interface on core side
1 => Slave interface on core side
2 => Master interface on system side
3 => Slave interface on system side

3.

ADDR_WDTH

32

Configures the width of maddr signal.

4.

DATA_WDTH

32

Configures the width of mdata / sdata signal.

5.

BURSTLENGTH_WDTH

Configures the width of mburstlength signal.

6.

ATOMICLENGTH_WDTH

Configures the width of matomiclength signal.

7.

THREADS

Number of threads.

8.

THREADID_WDTH

Configures the width of mthreadid / mdatathreadid /


sthreadid signal.

9.

CONNID_WDTH

Configures the width of mconnid signal.

10.

ADDRSPACE_WDTH

Configures the width of maddrspace signal.

11.

MDATAINFO_WDTH

Configures the width of mdatainfo signal.

12.

MDATAINFOBYTE_WDTH

The number of bits in mdatainfo associated with


each data byte in mdata signal.

13.

REQINFO_WDTH

Configures the width of mreqinfo signal.

14.

RESPINFO_WDTH

Configures the width of srespinfo signal.

15.

SDATAINFO_WDTH

Configures the width of sdatainfo signal.

16.

SDATAINFOBYTE_WDTH

The number of bits in sdataInfo associated with


each data byte in sdata signal.

17.

CONTROL_WDTH

Configures the width of control signal.

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Table 12-2. OCP Monitor Parameters (cont.)


Order Parameter

Default

Description

18.

STATUS_WDTH

Configures the width of status signal.

19.

TAGS

Number of tags.

20.

TAGID_WDTH

Configures the width of mtagid / mdatatagid / stagid


signal.

21.

TAG_INTERLEAVE_SIZE

Defines the interleaving granularity for the


responses.

22.

ENABLE_INTER_PHASE_
TRANFER_CHECKS

Set this parameter to 1 to enable inter phase


dataflow transfer checks.

23.

MAX_OUTSTANDING_REQ

16

Defines the maximum number of outstanding


requests. This parameter indicates the depth of the
outstanding requests memory in the monitor.

24.

BLOCKHEIGHT_WDTH

Defines the width of the port blockheight.


blockheight_wdth must be 0 if blockheight is
disabled.
blockheight_wdth must be greater than 1 if
blockheight is enabled.
To ensure backward compatibility, this parameter
must be 0 for 2.1 use model as this is disabled in the
configuration for 2.1.

25.

BLOCKSTRIDE_WDTH

Defines the width of the port blockstride.

26.

BASE_PORT_SPECIFIED

This parameter specifies if the base address for


XOR bursts is calculated by the user and passed to
the monitor. A value of 0 indicates that the base
address is calculated internally by the monitor. A
value of 1 (or other than 0) indicates that the base
address is supplied by the user through the port
base.

27.

CONNECTION

Parameter for disconnect support.


Default value 0 denotes that OCP disconnect is not
supported by default and both master and slave are
considered to be always connected.
Set this parameter to 1 to support OCP disconnect
proposal.

28.

DATA_X_Z_CHECK_ENABLE

This parameter can be used to enable / disable


checking X / Z on read and/or write data bus. By
default these checks are enabled.
Set this parameter to 0 to disable both write and read
data checks.
Set this parameter to 3 to enable both write and read
data checks.
Set this parameter to 1 to enable only write data
checks.
Set this parameter to 2 to enable only read data
checks.

Notes:
1. The parameters must be specified in the above order.

Questa Verification Library Monitors Data Book, v2010.2

351

Open Core Protocol (OCP)


Monitor Connectivity

Instantiation Examples
Example 1
Example 12-1 instantiates an OCP monitor on a master interface of the core side. The OCP
interface has an address width of 16 bits and data width of 64-bits. Datahandshake and response
phases are enabled. The interface supports all types of burst address sequences and all type of
commands. All tag extensions, thread e