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# Experiment 5

Sampling & Delta Modulation
5.1 Objective
1- To evaluate and analyze an implementation of a sample and hold (S/H) circuit.
2- To introduce Delta Modulation and test its main characteristics in a simple
circuit implementation.

5.2 Basic Information
Introduction to sampling
A/D circuits require the input signal to remain constant during the conversion
process; however, real world signals may fluctuate rapidly. The Sample and Hold
(S/H) is a device that makes its output follow the input until it is told to hold this
value. It then maintains the output as steady as possible, regardless of fluctuations of
the input, until released to follow the input again. This assures that the A/D is not
trying to hit a moving target.

(a)
(b)
Figure 5.1. (a) A simple S/H circuit. (b) A practical S/H circuit.
In its simplest form, the S/H circuit consists of a switch (S) and a capacitor (C)
as in figure 5.1(a). When the switch S is closed, the capacitor C is charged to the
value of the input voltage, the sample stage. Afterwards the switch is opened and the
capacitor retains its charge, the hold stage. The resulting output is shown in figure
5.2-b. This alternation between sample and hold modes is repeated as long as the
switch keeps toggling. The switching rate is controlled by a clock signal whose
frequency should satisfy the Nyquist sampling criterion.
A practical implementation of the S/H circuit is shown in figure 5.1(b). The
switch is a FET whose gate is controlled by the clock pulse. Buffers are placed at the
input and output to isolate the circuit.
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the acquisition time and the droop rate. In reality this is not possible since we do not know the frequency of the original signal and we do not know if aliasing has occurred in the first place.e. 3. the value being held should remain constant. This will appear as a new signal at a different frequency. Aliasing If the Nyquist rate for sampling is not satisfied. This is called the aperture time. causing the voltage being held to change slightly. Unfortunately.Signal Droop: The voltage being held on the capacitor starts to slowly decrease over time if the signal is not sampled often enough. Things are complicated further if the original signal is composed of many frequencies. (c) Capacitor droop.2(c). It appears that since we know what has happened we can recover the original signal. the sampling rate is increased. (b) Sample and hold cycles. some below the Nyquist rate and some above. the sampled signal can be slightly off. The third source of error is reduced by selecting a special kind of capacitor. 2. Much depends on the quality of the charging capacitor. This new frequency looks like it is folded back around the original signal.Figure 5. I. Lossy standard capacitors are slow which reduces the sampling rate. If by mistake this signal is sampled at 3kHz. if a signal was sampled at a rate less than double its maximum frequency aliasing will occur. For example if the signal to be sampled has a frequency of 2kHz. . It is responsible for regulating the hold step. The S/H has three sources of error: 1. It must be sampled at a minimum of 4kHz. Therefore we must make sure aliasing does not occur in the first place. This is accomplished by two things. some signal does bleed through the switch to the capacitor.Signal Feedthrough: When the S/H is not connected to the i/p signal. The frequency of the new signal will be at 1kHz.Finite Aperture Time: The S/H takes a period of time to capture a sample of the signal. The absorption of the dielectric used in the hold capacitor is extremely important. Since the signal will vary during this time.2 (a) Original signal. see figure 5. To reduce the first and second sources of error. Polystyrene and polypropylene capacitors are best suited for S/H circuits. a new signal will appear instead of the original signal.

Amplifier A is bipolar with low output offset voltage and wide bandwidth. The hold capacitor with different values is selected through switches c1 and c2. Selection of input is through switches c7 and c8. figure 5.3 LF398 block diagram and S/H experiment circuit connections. the charge on the capacitor follows the analog input signal. which is turned on when the logic input drops below the reference voltage. the capacitor is connected to the output of the input amplifier A. and a digital switch. Amplifier B is a unity gain follower. and during the hold mode.3. The analog input is selected to be DC (+5 to -5V) through a pot. During the sample mode. The LF398 S/H Integrated Circuit The LF398 is a basic and common S/H monolithic IC. or clocked S/H through switches c4 or c5. The sample and hold modes are chosen as continuous sample mode by switch c6 and a reset switch. During the sample mode. The capacitor is discharged by the follower amplifier. It consists of an input and output buffer amplifiers. In the hold mode. and by limiting the upper frequency of the original signal through a low pass filter (anti-aliasing filter). Amplifier C is a digital switch. the input amplifier is disconnected and the capacitor holds the charge. A resistor is connected in .sampling at a rate higher than the Nyquist (over-sampling).3 is built around the LF398 IC. of FET type for high input and low output resistances. or AC through Vin. The external capacitor is charged from a current source through the logic controlled switch. The output of amplifier B is fed back to amplifier A. The Sample & Hold Experiment Circuit The experiment circuit in figure 5. Figure 5. The hold capacitor is connected externally. to the input of the output amplifier B.

To generate delta modulation the amplitude of each sample of the message signal m(t) is compared with the amplitude of the previous sample. See figure 5. To avoid this case.parallel to the hold capacitor through switch c3 to clarify the effect of capacitor droop. the amplitude of each sample in the message signal is converted into an 8-bit word. This is called delta modulation.5 shows this distortion. The resulting stream of bits is transmitted to the receiver. and the small amount of hardware required to implement it. However. and the binary sequence output eq(t). the sampling rate is increased to a value much higher than the Nyquist rate. The output mq(t) is a staircase approximation of the original message. The simple logic behind it. In PCM. The step size is fixed to a certain value Δ while the sample period is denoted by TS.4. Figure 5. There are two sources of error in Δ modulation. To increase the correlation between consecutive samples. there is a strong similarity between consecutive samples.4 The message signal m(t). This implies that we can decrease the number of bits per sample if we utilize the information we have about the previous sample. audio signals do not have a large amplitude variation from one sample to the next. a 1 is sent to indicate that the new sample is larger than its predecessor. Figure 5. In the simplest method. make it the most attractive for new systems. the staircase approximation of the message signal mq(t) . This offers high resolution of the signal amplitude. the slope of the .e. while a zero is sent otherwise. this distortion occurs when the input signal rises or drops (increases or decreases in amplitude) at a rate higher than the slope of the staircase approximation of the signal. This results in a close approximation to the original message. i. The first is Slope Overload Distortion. the information sent indicates whether the sample is merely larger or smaller than the previous one. PCM is one of these techniques. Introduction to Delta Modulation Various techniques exist for converting analog message signals into a digital stream of bits. The staircase approximation of the message signal mq(t) is given by the relation mq ( n T S ) = mq ( n T S − T S ) + eq ( n T S ) 5-1 where eq ( n T S ) = Δsign[m( n T S ) − mq ( n T S − T S )] 5-2 The main advantage of Δ modulation over other methods is its simplicity.

The solution to this case seems to be in reducing the step size. when the change in signal amplitude is small.input signal must be less than the staircase approximation. whose output is high or low depending on the difference between the input signal and its approximation. Inversely. The product is also fedback through an integrator (LPF) to the summing junction of the limiter. When the signal increases rapidly (large slope). . Delta Modulation Block Diagram The transmitter consists of a hard limiter (comparator). Figure 5. This product is transmitted through the channel to the receiver. which occurs when the change in the amplitude of the input signal is smaller than the step size Δ.5. this is satisfied under the condition: Δ ≥ max TS dm( t ) dt 5-3 In the case of a sinusoidal signal this condition simplifies to Δ ≥ 2πA f m 5-4 TS where A is the amplitude of the sinusoid and fm is its frequency. This causes the staircase approximation to hunt up and down around the signal. Such systems use sophisticated circuits and are mainly utilized in areas where signal reproduction quality vastly outweighs cost. See figure 5. See figure 5. the step size is reduced to decrease granular noise.6. the step size is increased until the error is reduced. Advanced Δ modulation techniques use a variable step size that adapts to the signal at hand. However this contradicts the condition for avoiding slope overload. The second source of error is Granular Noise. The output of the limiter is multiplied with the sampling clock.5 Slope overload distortion and granular noise in delta modulation.

The D-type flip-flop (74LS74) performs multiplication with the clock. the same as the LPF in the feedback loop. So the output of the receiver is identical to the output of the feedback loop (Rx o/p). shown in figure 5. Delta Modulator circuit diagram. The output of the modulator is a stream of high and low digital bits (Tx o/p). The receiver is a LPF.7.7. In this system. It is composed of a comparator (LM339). . which acts as a summer and hard limiter. Figure 5.Figure 5.6 Block diagram of a Delta modulation system. the parameters of step size. The integrator in the feedback path is a simple RC low pass filter circuit. 5.7.3 Prelab Use parts C and D of the procedure to do a complete simulation of circuit 5. sample rate and integrator (LPF) cutoff frequency are related by the formula: −π Δ = V clock (1 − e T S f cutoff ) 5-5 Experimental circuit The circuit is quite simple.

Measured No. of samples/cycle 7. Repeat step 6. of samples/cycle Theoretical .Set the supply voltages on the power supply base to +10V. Measured Theoretical No. and use it as the trigger for the oscilloscope.8kHz at TP6 (in section BSAMPLE/HOLD). 2. Record this clock.5 Procedure Part A.5. 5. And connect it to the input of the IC at TP5.Count the number of samples/cycle.Record the sampling output at TP7 through ch2 of the oscilloscope.Universal Clock section of the test board) to get a sampling frequency 4.Set the function generator to 3VPkPk sine wave at 200Hz. Adjust R1 potentiometer (in section A. 4.Clocked sampling for a continuous signal 1.4 Equipment Digital Communications Panel (SIP397-1) Power Supply Base (S300PSB) Function Generator Oscilloscope Frequency Counter Digital Multimeter 5.Close switches b4 & c5 to feed a sampling clock to the LF398 IC. Also connect ch1 of the oscilloscope to TP5. 6.Increase the input frequency to 800Hz.Connect 30nF hold capacitor to pin 6 of the IC by closing switch c1. Adjust the Hold-Off on the oscilloscope for best display. Clock Amplitude (V) Frequency (kHz) 3.

5ms/div and find the alias frequency..Capacitor droop observation 1.8. 3. c1 and close sw c2 and c3.. ………………………………………………………………………………… ………………………………………………………………………………. 9.Increase the input frequency to 5kHz. add 220kΩ resistor in parallel with the 0. 2.Open all c switches (c1 to c8). 4. ……………………………………………………………………………………… ……………………………………………………………………………………… ……………………………………………………………………………………… ……………………………………………………………………………………… 5. Record the output.003μF capacitor. Describe the display and explain what has happened. open sw. Measured Theoretical Alias Frequency Part B.Compare and describe what happens to the shape of segments between steps 1 & 4..To simulate a lossy capacitor. Record the sampled output. .Set the oscilloscope to 0.Change the input signal to a triangular wave at 400Hz.Record the o/p at TP7.

Adjust R1 to get 300kHz at TP3.7. 2. Open a2 and close a3. Open sw. and the error amplitude. Draw the error and note the areas of slope overload. Increase the clock rate to 300kHz. Open sw.8VPP sine wave at 1kHz with 2V dc offset. Set the function generator to 1..Part C. granular noise. Record the error between both signals by subtracting the Rx o/p signal from Vin on the oscilloscope. Adjust R1 to get 100kHz at TP3. Use the Universal Clock from the test board to obtain a 100kHz clock for your circuit. b4 and close sw. Increase the signal frequency to 1..… …………………………………………………………………………………………. 6. Compare and draw the input at Vin with the staircase approximation at Rx (Receive) o/p. 4. Use jumper wires to connect TP3 to the clock input in your circuit.3kHz. a3. ………………………………………………………………………………………. And connect the circuit ground to the ground on the board 3. and connect it to the input marked Vin.Delta Modulator 1. a2.. Return the clock to 100kHz. …………………………………………………………………………………………. 5. ………………………………………………………………………………………… ………………………………………………………………………………………… ………………………………………………………………………………………… 7. Note the effect on the output and the error. a3 and close sw. Adjust R1 to get 100kHz at TP3. Note the effect on the output and the error. . Build the circuit in figure 5.

6 and 7 to the equation 5-4. Observe the digital Tx (Transmit) output. . relate your results in steps 4. Calculate the cutoff frequency of the LPF and relate it to the previous results. Restore the signal to 1kHz. Calculate the step size. In your report. Draw the digital signal in relation to the analog input. 10.8. Filter Cutoff (kHz) Step Size (V) 11. 9.