OVM Video Slides

macros automate housekeeping (inline substitution of systemverilog code


Tom Fitzpatrick, Mentor Graphics Verification Technologist

Circles = exports Squares = ports Diamonds = analysis ports Know when to stop running useless cycles or when coverage is not increasing. Try to figure out how to run in half-the-time. Simulation cycles are non-renewal resource. Once it’s used it’s gone.

u1 = red, u2 = red

set_type_override (u1= blue, u2 = blue) set_inst_override (u1=green, u2= blue) set_config_string (u1=green, u2 = green)


add a fork join to wait for all child processes to complete

tests are components from the factory

Kathleen Meade, Application Engineer, Systemverilog, Cadence

Vi = virtual interface

aka UVM

See ovm-1.0/examples/xbus/sv/xbus_env.sv

one sequencer on a driver at a time

Easy to deply all key randomization concepts !

everytime do is executed the sequence is randomized

Doug Smith, Senior Engineer & Trainer at Doulos

test is hard instantied but only used for example

use packages to avoid scoping issues run_test kicks off the simulation

random is not good enough

should one use OVM transaction or OVM sequence? It depends upon the situation.

to add more drivers : AHB, PCIE, add more ovm_sequencers

not an OVM sequencer Use virtual sequencer

can have multiple scoreboards

check to see iterations. If none set then use default

wrap up objects, structures and then use factory or virtual interface downside of using strings, is that systemverilog has to do searching for objects and OVM plans to add checking for mistyped strings.

can run test by itself

Sign up to vote on this title
UsefulNot useful

Master Your Semester with Scribd & The New York Times

Special offer for students: Only $4.99/month.

Master Your Semester with a Special Offer from Scribd & The New York Times

Cancel anytime.