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Fall Project Report

ECE 506

AIM
1. Implementing a multiple voltage domain and study of AOCV

2. Static Timing Analysis


3. Clock Domain Crossing Analysis
Multiple Voltage domain system
In-order to define a multi voltage system a simple design with two modules one
working at 1 V and other at 2V is created. The pre characterized NAND and Inverters
will be used in this design. For this to happen the library file path will be modified in
the encounter.conf file to include the library file with the new standard cells for 2V.
The design must have a level converter in-order to convert the output from the low
voltage domain to the high voltage domain.

Multi Voltage Design


PD1 PD2
PM1 1 V
0V
PM2 1 V
2V
Control signal is PM_INST
Here in the above design the instance in PD2 works in the Power domain with 2V
and rest of the gates works in default power domain which is 1V.
In-order to enable the design to work in different voltage domain we will have to
create either Unified Power Format (UPF) or Common Power Format ( CPF). Here I
proceeded with creating a CPF file. State retention cell must be defined, when PD2
is off the state of the cell must be held. Isolation cell may not be required since PD2
output is not supplied to any other module as input
CPF file
#define the design
set_design top
#setup logic structure for all domains
create_power_domain -name PD1 -default
create_power_domain -name PD2 -instances {inst_A}\
-shutoff _condition {!PM_INST}

#define static behavior of power domains and specify the timing constraints
create_nominal_condition -name high -voltage 2.0
create_nominal_condition -name low -voltage 1.0
create_power_mode -name PM1 -domain_conditions{PD1@high PD2@low}
create_power_mode -name PM2 -domain_conditions{PD1@high PD2@high}
#setup state retention, isolation rules
create_state_retension_rule -name sr -domain PD2\
-restore_edge {!PM_INST}
#define level convertors required
create_level_shifter_rule -name lvl_conv -from {PD1} to { PD2}
end_design
Verilog code for the design
Below is a sample code for the design. However cadence library is not having cells
for level shifter. Hence will have to create a new one and characterize it entirely
module PD1 (Y0, B, A, C, OM_INST);
output Y0, OUT1;
input B, A, C;
wire INT1,INT2;
nand2cell G1(Y, B, INT);
notcell G2(INT, A);
nand2cell G3(Y, INT, C);
notcell G4 (INT2,Y);
and2cell G5 (OUT1, INT2, PM_INST);
and2cell G6 (Y0, INT2, PM_INST);
endmodule
module PD2 (Y1, Y2, H, J, I);
output Y1, Y2;
input I, H, J;
wire INT3;
nand2cell G1(Y1, H, I);
nand2cell G2(Y2, J, I);
endmodule
module TOP(Y0, Y1, Y2, B, A, C, H, J, PM_INST);
output Y0, Y1, Y2;
input B, A, C, H, J, PM_INST;
wire I;

PD1 P1(Y0, OUT1, A, B, C);


PD2 P2(Y1, Y2, H, J, I);
LSCELL LS1(I, OUT1);
endmodule
In-order to implement this design the encounter.conf must be modified to include
the lib path of the modified .lib file with standard cells.
LEF(Library Exchange Format) file understanding:
This describes the physical layout in ASCII format and it contains design rules and
information of cells.
A LEF file has mainly
Technology section
Site
Macros
Technology:
This is described through LAYER and VIA statements.
TYPE: routing, cut(contact), masterslice(poly,active)
width, pitch, spacing rules
Direction (horizontal or vertical)
resistance and capacitance per unit square
Each layer is described with its properties
ex:
LAYER layername
TYPE: cut
SPACING: min distance between cuts in the same or different nets
SAMENET SPACING : this can be used to override the SPACING value
mentioned above
END layername
Similarly Cut layer, Implant layer, Masterslice layer, routing layer etc can be
described.
MANUFACTURINGGRID value;
This is used for the geometry alignment. Cells are placed in location values which
are multiples of grid value
VIA definition : This is used to define the vias from one metal to the other
Ex:
VIA M2_M1_via DEFAULT
LAYER metal1;

RECT: give coordinates;


LAYER via1;
RECT: give coordinates;
LAYER metal2;
RECT: give coordinates;
END M2_M1_via
VIARULE.. GENERATE:
This is used in cases where we need to define special wirings which is not otherwise
defined.
MACRO definition:
This definition describes the attributes of a cell. location of input pins, output pins,
VDD and GND.
OBS statement:
Used to define the obstruction in layout
PIN statement
Defines a PIN in the layout. Attributes are Direction, USE, SHAPE etc.
All the above specifications are used for Design rule checks by verification tools.
I have gone through the syntax of Layer definition, Via definition, VIARULE
GENERATE, SMAENET SPACING statement, SITE definition, MACRO definition, MACRO
Obstruction statement, PIN Statement etc and the syntax to define all these.

Power grid creation and APR


1. Import Design

Verilog file is selected to import the design. This generates a generic floor plan in
the screen. The customisation is done using the specify Floorplan option
2. Specify Floorplan
This option helps s to define the Aspect ratio, Core utilization, Or else we can
specifically give the width and height. ALos Core margins can be set Core to IO or
core to Die options. The distances can be given by specifying the values required in
the core to left, core to right core to top and core to bottom boxes.

The above shows the floorplan with Core to IO boundary with offset 10 from left
right top and bottom.
3. Add ring
Ppower planning is th enext step as per our decision either we can go for only rings
or rings and stripe so as to provide Vdd and Gnd connections across the chip. which
reduces wiring and rc parasitics. For this the global nets Vdd and Gnd are selected
and metel layer for the same is specified along with the width of rings.

4. Add stripe

Adding stripe will create vdd and gnd connection across the chip either vertically or
horizontally. The spacing between each stripes can be specified.

5. Special routing
This is used to route the Vdd and Gnd connections for each row of Standard cells,
After this Std cells will be placed

6. Placement
After routing the Vdd and Gnd connections STD cells are placed using the placement
tab.

7. Routing

Nanoroute option in Encounter

Design after APR


Then the global routing is done after the completion of placement of cells this will
connect the cells together as per the netlist connections.
RC extraction

RC extraction step in the Encounter


After routing parasitic are extracted from the routed layout. This extracts the RC
component values from the design which can be later used to get the proper timing
of the design
Timing check
Timing can be verified using the timing tab in the encounter. the option for using RC
parasitic ca be selected in order to get the proper Timing specification of the

system. This can be verified with the initial specs to check everything is working as
expected at designated speed.

Clock tree
If your system is clocked you can display the clock tree created using the Clock tab
and Display clock option.

Clock tree highlighted


In order to avoid the DRC violations I have changed the pin positions using the PIN
editor of cadence encounter.

Pin edit option of Cadence Encounter

After Pin editing the DRC violations were removed from the design

APR after pin editing(and b bus on metal3 sum at metal 5)


Checking for timing violations after the pin editing. Timing of the design was again
checked and it resulted in positive slack which is not a timing violation.

Synthesized clock from UI and again ran timing check which resulted in some
change in the parameters

Clock tree synthesized in the design

Since there are no timing violation for 100MHz frequency was increased to 10Ghz
which created DRC as well as timing violations.

Timing for 10Ghz

APR of 64 bit adder at 10GHz


Rearranged pins to resolve the DRC issue.

After Pin editing

Timing after rearranging the pins

In order to see the path violation, frequency was increased to 10Ghz from 100MHz
and APR is done. which produced many timing violations. The way to solve them are
using the debug timing option of encounter. Which gives a histogram and net wise
delay details. Schematic view can also be found from this as below.

selecting an instance and the corresponding schematic view of it

Adding buffer using the Interactive Eco option

After the buffer insertion step the refreshed schematic view appears as above.
Checking timing after this to check whether this has solved the issue or not.

optDesign postCTS
This command optimizes the timing by fixing DRV's, reclaiming area and then fixes
setup violations

Challenges faced
While adding buffers in the clock path to reduce the violations, the schematic view
didn't show any buffers added to the net.

AOCV
As the size of the transistors shrink, the effect of variation is increasing. Now we can
see on chip variation and wafer to wafer variations.
Scope of Variation:
Global
Which means Die to die,
wafer to wafer this variation is consistent
throughout the die.
On-Chip
This type of variation is local to each die and the effect is increasing as the
process node decreases.
Types of Variation:
Random Variation:
This affects individual transistors. This can occur due to the variation in the doping,
gate oxide thickness variation etc.
Systematic Variation:
This type of variation affects the local transistors and nets similarly. This variation
increases with length. This occurs due to the variations in thickness, lithography,
CMP etc. This alters the characteristics of transistors.

Variation causes the characteristics of the transistors and dies to change. Thus it
becomes important to consider the variation during design phase especially below
90nm. Main variations affecting delay are Channel length (Le) variation and
Threshold voltage variation(Vt). And as mentioned above these two parameters
have their own random and systematic variation components.
Derating factor:
Scaling factor applied either to the entire chip or to particular nets to account for
variation. Generally derating factors are provided by the foundry/vendor or derived
through measurements.
Different OCV methods for derating factors:
Traditional OCV:
In this to account for the worst case and safely model for variation the worst case is
considered for finding the derating factor and this derating factor is applied to all
the clock paths or the data paths. This approach is pessimistic since in a chip all the
paths does not require adjustment.
Local OCV:
Location Based:
This considers the placement into consideration. Derating factor
depends on the
diagonal of the bounding box that encloses all
instances on data path or clock path.
Level Based:
Derating factor is a variable depending on the logic levels on a data
path or clock
path. If a path has more logic levels and another
path has less logic levels then different
derating factors will be
applied for these paths
OCV derating factor tables:
This is a table which describes the level and location effects. This table is generally
provided by library teams. These tables are used with SDF's(Standard Delay file) to
figure out the derating factor.

At one timing check one table is applied to either data path or clock path.
Combination will be MAX Hold, Max Setup, MIN Hold, MIN Setup.MAX SDF contains
the delays under worst case scenario hence derating factors are less than 1 and MIN
SDF will have derating factors greater than one since it accounts for the best delay

conditions. Logic levels are generally from 0 to 32 (level based) and Distances are
taken from 0 to 16000um.
Single mode vs. Double
Single mode: Either a data path or clock path is considered and derating factor is
applied at a timing check(setup or hold)
Double mode: In each timing check 1 table is applied to data path and another table
is applied to clock path.
In order to figure out how to turn the AOCV option off I have analyzed majority of
the files and scripts used and some commands too in the rc.tcl, encounter.tcl files.
In order to make the analysis as Advanced On chip verification the setAnalysisMode
command of encounter must be used along with its -aocv option.
setAnalysisMode Command
This command is used in the encounter.tcl file. This command is used to set the
type of timing analysis to be performed on the design. The syntax of this command
is as below
setAnalysisMode
[-help]
[-reset]
[-analysisType {single | bcwc | onChipVariation}]
[-asyncChecks {async | noAsync | asyncOnly}]
[-caseAnalysis {true | false}]
[-checkType {setup | hold}]
[-clkNetsMarking {beforeConstProp | afterConstProp}]
[-clkSrcPath {true | false}]
[-clockGatingCheck {true | false}]
[-clockPropagation {sdcControl | forcedIdeal | autoDetectClockTree}]
[-aocv {true | false}]
[-cppr {none | both | setup | hold}]
[-enableMultipleDriveNet {true | false}]
[-honorActiveLogicView {true | false}]
[-honorClockDomains {true | false}]
[-log {true | false}]
[-propSlew {true | false}]
[-sequentialConstProp {true | false}]
[-skew {true | false}]
[-timeBorrowing {true | false}]
[-timingEngine {statistical | static | pathBasedSSTA}]
[-timingSelfLoopsNoSkew {true | false}]
[-usefulSkew {true | false}]
[-useOutputPinCap {true | false}]
[-warn {true | false}]

This command will set the constants to be propagated during the building of the
timing graph. These constants are obtained from the timing constraint file or from
the netlist information. This command allow the system to accept module level or
the system level set_input_delay or and set_output_delay variables for the timing
analysis of the I/O's.
[-analysisType {single | bcwc | onChipVariation}]
single:
Encounter uses one set of PVT corners for the timing analysis
bcwc:
Best case Worst case timing analysis. Encounter uses one corner for the best
case and
one corner for the worst case analysis. Both corners are considered
at the same run. setup check in this mode will use the maximum delay possible
and for the hold check uses the minimum delay possible.
onChipVariation:
Calculates delay for one path based on maximum operating condition and
other based on
minimum operating condition.
[-aocv {true | false}]
This option sets the analysis mode to advanced on chip verification
However the Library does not contain any AOCV based libraries hence the AOCV
analysis cannot be performed
The AOCV based timing for 8 bit adder

timedesign summary of 8 bit adder with AOCV option (Since no AOCV libraries have
been read, this analysis cannot be performed . The analysis will continue without
AOCV based derating applied.)

Output of the APR of 8 bit adder with clock tree highlighted

CDC design:
Very simple design is considered. For clk1 input is given to internal output and for clk2 internal output is
given to the output
// At clk1 din is given to internal wire, at clk2 dout_internal is passed t dout_reg
module CDC ( clk1, clk2, rst, din, dout);
input clk1;
input clk2;
input rst;
output dout;
input din;
reg dout_internal;
reg dout;
reg dout_reg;
always @ (posedge clk1)
begin
dout_internal <= din;
end
always @ (posedge clk2 or negedge rst)
begin
if (! rst)
begin
dout_reg <= 1'b0;
end
else
begin
dout_reg <= dout_internal;
end

assign dout = dout_reg;


end
endmodule
Schematic as per Xilinx

Schematic view of verilog design using Xilinx


CDC test design in encounter
module cdc_check ( clock1, clock2, rst_n, data_in, data_out);
input clock1;
input clock2;
input rst_n;
output [63:0] data_out;
input [63:0] data_in;
reg [63:0] data_out_meta;
reg [63:0] data_out_reg;
reg [63:0] data_out_reg_r;
wire[63:0] data_out;
// Assign statements
assign data_out = data_out_reg_r;
// Always block to declare synchronous logic from source clock domain
always @ (posedge clock1)
begin
data_out_meta <= data_in;
end

always @ (posedge clock2 or negedge rst_n)


begin
if (! rst_n)
begin
data_out_reg <= 'b0;
data_out_reg_r <= 'b0;
end
else
begin
data_out_reg <= data_out_meta;
data_out_reg_r <= data_out_reg;
end
end
endmodule
The rc.tcl, encounter.tcl files must be modified to correctly perform the APR of the design
#**************************************************/
#* Script for Cadence RTL Compiler synthesis */
#*
*/
#* To run: rc < rc.tcl
*/
#*
*/
#* Author: Varun Devaraj,PSU
*/
#* vdevaraj@pdx.edu
*/
#**************************************************/
# Set a working directory to put the results.
set WORKDIR ./
# All HDL files, separated by spaces
set hdl_files cdc.v
# The Top-level Module, change example multiplyadd
set DESIGN cdc_check
# Set clock pin name in design. If clk just leave untouched,
# otherwise change clk
set clkpin1 clock1
set clkpin2 clock2
# Target frequency in MHz for optimization
set delay1 50
set delay2 166
#**************************************************/
# NO further changes past this point
set osucells $env(OSU_FREEPDK)
set_attribute hdl_search_path {./} /
set_attribute lib_search_path $osucells/lib/files

set_attribute information_level 6 /
set_attribute library gscl45nm.lib
read_hdl -sv ${hdl_files}
elaborate $DESIGN
# Apply Constraints
set clock [define_clock -period ${delay1} -name ${clkpin1} [clock_ports]]
external_delay -input 0 -clock clock1 [find / -port ports_in/*]
external_delay -output 0 -clock clock1 [find / -port ports_out/*]

//define clock1

set clock [define_clock -period ${delay2} -name ${clkpin2} [clock_ports]]


external_delay -input 0 -clock clock2 [find / -port ports_in/*]
external_delay -output 0 -clock clock2 [find / -port ports_out/*]
# Sets transition to default values for Synopsys SDC format, fall/rise
# 400ps and 500ps
dc::set_clock_transition .4 clock1
dc::set_clock_transition .5 clock2

//define clock2

//clock one transition


//clock2 trasition

check_design -unresolved
report timing -lint
#report timing -from clock1 -to clock2
#*Synthesis
synthesize -to_mapped
report timing > ${WORKDIR}timing.rep
report gates > ${WORKDIR}cell.rep
report power > ${WORKDIR}power.rep
write_hdl -mapped > ${WORKDIR}${DESIGN}.vh
write_sdc > ${WORKDIR}${DESIGN}.sdc
puts \n
puts "Synthesis Finished!
"
puts \n
puts "Check timing.rep, area.rep, gate.rep and power.rep in the workdir for synthesis results"
puts \n
quit
Encounter.tcl file
###################################
# Run the design through Encounter
# File downloaded from OSU kit
# Edited on 01/27/2010 by Varun Devaraj
# Fixed some of the old commands to support the new commands
###################################

set WORKDIR ./
# Setup design and create floorplan
loadConfig ${WORKDIR}encounter.conf
# Create Initial Floorplan
floorplan -r 1.0 0.6 20 20 20 20
# Create Power structures
addRing -spacing_bottom 5 -width_left 5 -width_bottom 5 -width_top 5 -spacing_top 5 -layer_bottom
metal5 -width_right 5 -around core -center 1 -layer_top metal5 -spacing_right 5 -spacing_left 5
-layer_right metal6 -layer_left metal6 -nets { gnd vdd }
# Place standard cells
placeDesign
# Route power nets
sroute -noBlockPins -noPadRings
# Perform trial route and get initial timing results
setTrialRouteMode -maxRouteLayer 6 -minRouteLayer 1
trialRoute
buildTimingGraph
timeDesign -reportOnly -pathReports -slackReports -numPaths 50 -outDir timingReports
# Run in-place optimization
# to fix setup problems
setUsefulSkewMode -maxSkew false -noBoundary false
setOptMode -effort high -usefulSkew true
setOptMode -fixCap true -fixTran true -fixFanoutLoad true
optDesign -preCTS
# Run Clock Tree Synthesis
setCTSMode -specMultiMode true
createClockTreeSpec -output cdc_encounter.ctstch
specifyClockTree -file encounter.ctstch
clockDesign -clk clock1 -check -outDir timingReports
ckSynthesis -check -clk clock1
set_attribute lp_insert_clock_gating true /
#displayClockTree -clk clock1
#ckSynthesis -clk clock2 -ignoreLoopDetect -fix_added_buffers
# Output Results of CTS
trialRoute -highEffort -guide clock.rguide
extractRC
reportClockTree -postRoute -localSkew -report skew.post_troute_local.ctsrpt
reportClockTree -postRoute -report report.post_troute.ctsrpt

# Run Post-CTS Timing analysis


setAnalysisMode -setup -noasync -skew -clockGatingCheck true -honorClockDomains true
buildTimingGraph
timeDesign -reportOnly -pathReports -slackReports -numPaths 50 -expandReg2Reg -outDir
timingReports
# Perform post-CTS IPO
setOptMode -fixCap true -fixTran true -fixFanoutLoad true
optDesign -postRoute -drv
# Fix all remaining violations
setExtractRCMode -detail -assumeMetFill
extractRC
# Run Post IPO-2 timing analysis
timeDesign -reportOnly -pathReports -slackReports -numPaths 50 -outDir timingReports
# Add filler cells
addFiller -cell FILL -prefix FILL -fillBoundary
# Connect all new cells to VDD/GND
globalNetConnect vdd -type tiehi
globalNetConnect vdd -type pgpin -pin vdd -override
globalNetConnect gnd -type tielo
globalNetConnect gnd -type pgpin -pin gnd -override
# Run global Routing
globalDetailRoute
# Get final timing results
setExtractRCMode -detail -noReduce
extractRC
timeDesign -reportOnly -pathReports -slackReports -numPaths 50 -outDir timingReports
# Output GDSII
streamOut ${WORKDIR}final.gds2 -mapFile ./gds2_encounter.map -stripes 1 -units 1000 -mode ALL
saveNetlist -excludeCellInst FILL final.v
global dbgLefDefOutVersion
set dbgLefDefOutVersion 5.6
# Output DSPF RC Data
rcout -spf ${WORKDIR}final.dspf
# Run DRC and Connection checks
verifyGeometry
verifyConnectivity -type all
win

puts "**************************************"
puts "* Encounter script finished
*"
puts "*
*"
puts "* Results:
*"
puts "* -------*"
puts "* Layout: final.gds2
*"
puts "* Netlist: final.v
*"
puts "*
*"
puts "* Type 'exit' to quit
*"
puts "*
*"
puts "**************************************"
APR result of encounter

Clock tree display for the cdc design for clock1

Clock tree display for the cdc design for clock2

Clock tree display for the cdc design

Timing of the cdc design


Conclusion
APR of adder and CDC design was done. Need to find methods to resolve the timing
violations using adding buffer etc. Study of AOCV and the options to perform aocv
were done. Study about Implementation of multiple Voltage domain was also done.