# Chapter 8

Sequential Circuits for Registers and Counters

Lesson 5 Synchronous and Asynchronous Counters

Ch16L5- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006

2

Outline • Synchronous counter • Asynchronous clear, preset and LOAD (JAM) in a counter • Asynchronous clear, preset and LOAD (JAM) in a counter

Ch16L5- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006

3

Problem with asynchronous counters • Asynchronous counters have a characteristic that first FF at input stage has a propagation delay of tp and last stage has n× tp delay. Hence, counter shows next count correctly only after n× tp delay
Ch16L5- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 4

Synchronous counters
• Synchronous counters use additonal circuits such that all FFs undergoes transition simultaneously. A characteristic is first FF at input stage has a propagation delay of tp and last stage also has tp delay. Hence, counter shows next count correctly after tp delay
Ch16L5- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 5

• The J and K inputs connect together in each flip-flop, and are connected to a logic combinational circuit. J and K inputs are held ‘0’ so that Qs don’t change up to the final stage gets the counting input. As soon as final stage gets the input, the J and K of all FFs will simultaneously equal to ‘1’ and toggle as per the inputs (See Text for circuit)
Ch16L5- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 6

Timing Diagram when -ve edge Synchronous counter

CLK (shift)
All QA QB, QC and QD identical delay from clock edge QA QB QC QD
Ch16L5- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 7

t

Outline • Synchronous counter • Synchronous clear, preset and LOAD (JAM) in a counter • Asynchronous clear, preset and LOAD (JAM) in a counter

Ch16L5- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006

8

Clear and Preset Operations
• There may be a need to reset all Qs as 0s at the start of the counter. [For example, in a up counter.] It is called CLEAR operation. • There may be a need to reset all Qs as 1s at the start of the counter. [For example, in a down counter.] It is called PRESET operation.
Ch16L5- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 9

• There may be a need to set certain Qs as 1s and remaining as 0s at the start of the counter It is called JAM operation.

Ch16L5- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006

10

• TTL 74163 or CMOS 74HC163 has synchronous clear and synchronous load facility. • In that case, the clear, preset or load inputs must be properly defined at a time, ts, called setup time, before a clock edge at the input is activated.

Ch16L5- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006

11

Synchronous Operation
• The effects of the CLR (clear) or PR (preset) or load inputs appear in the outputs only after a time equal to ∆TFF from the clock input transition i.e. activation (net time taken > ts+ ∆TFF). Here the ∆TFF is propagation delay within a FF of the counter
Ch16L5- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 12

Outline • Synchronous counter • Synchronous clear, preset and LOAD (JAM) in a counter • Asynchronous clear, preset and LOAD (JAM) in a counter

Ch16L5- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006

13

Asynchronous Operation
• The effects of the CLR (clear) or PR (preset) or load inputs appear in the outputs only after a time equal to m × ∆TFF from the n clock input transitions i.e. activation (net time taken > ts+ m × ∆TFF). Here the ∆TFF is propagation delay within a FF of the counter and m × ∆TFF is propagation delay between first stage and last stage FFs and combinational; circuits at a counter
Ch16L5- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 14

Summary

Ch16L5- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006

15

We learnt
• Operations in a counter are counting, clear of all Qs to 1s, presetting of all Qs to 1s and loading the Qs. • Two type of operations— synchronous and asynchronous

Ch16L5- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006

16

End of Lesson 5 Synchronous and Asynchronous Counters

Ch16L5- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006

17

THANK YOU

Ch16L5- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006

18