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[ /Title

(CD74
HC373
,
CD74
HCT37
3,
CD54
HC573
,
CD74
HC573
,
CD74
HCT57
3)
/Sub-

Data sheet acquired from Harris Semiconductor
SCHS182

November 1997

CD74HC373, CD74HCT373,
CD54HC573, CD74HC573,
CD74HCT573
High Speed CMOS Logic
Octal Transparent Latch, Three-State Output

Features

Description

• Common Latch Enable Control

The Harris CD74HC373, CD74HCT373, CD54HC573,
CD74HC573, and CD74HCT573 are high speed Octal Transparent Latches manufactured with silicon gate CMOS technology. They possess the low power consumption of standard
CMOS integrated circuits, as well as the ability to drive 15
LSTTL devices. The CD74HCT373 and CD74HCT573 are
functionally as well as pin compatible with the standard
74LS373 and 74LS573.

• Common Three-State Output Enable Control
• Buffered Inputs
• Three-State Outputs
• Bus Line Driving Capacity
• Typical Propagation Delay = 12ns at VCC = 5V,
CL = 15pF, TA = 25oC (Data to Output for HC373)

The outputs are transparent to the inputs when the latch
enable (LE) is high. When the latch enable (LE) goes low the
data is latched. The output enable (OE) controls the threestate outputs. When the output enable (OE) is high the
outputs are in the high impedance state. The latch operation
is independent to the state of the output enable. The 373 and
573 are identical in function and differ only in their pinout
arrangements.

• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs

Ordering Information

• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V

TEMP. RANGE
(oC)

PACKAGE

CD54HC573F

-55 to 125

20 Ld CERDIP

F20.3

CD74HC373E

-55 to 125

20 Ld PDIP

F20.3

CD74HCT373E

-55 to 125

20 Ld PDIP

E20.3

CD74HC573E

-55 to 125

20 Ld PDIP

E20.3

CD74HCT573E

-55 to 125

20 Ld PDIP

E20.3

CD74HC373M

-55 to 125

20 Ld SOIC

M20.3

CD74HCT373M

-55 to 125

20 Ld SOIC

M20.3

CD74HC573M

-55 to 125

20 Ld SOIC

M20.3

CD74HCT573M

-55 to 125

20 Ld SOIC

M20.3

PART NUMBER

• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH

PKG.
NO.

NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer or die for this part number are available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1997

1

File Number

1679.1

CD74HCT373 (PDIP.CD74HC373. CD74HCT373. CERDIP) TOP VIEW OE 1 20 VCC OE 1 Q0 2 19 Q7 D0 2 19 Q0 D0 3 18 D7 D1 3 18 Q1 20 VCC D1 4 17 D6 D2 4 17 Q2 Q1 5 16 Q6 D3 5 16 Q3 Q2 6 15 Q5 D4 6 15 Q4 D2 7 14 D5 D5 7 14 Q5 D3 8 13 D4 D6 8 13 Q6 Q3 9 12 Q4 D7 9 12 Q7 GND 10 11 LE GND 10 11 LE Functional Block Diagrams CD74HC373. CD74HCT373. SOIC) TOP VIEW CD54HC573. CD74HCT573 Pinout CD74HC373. CD74HCT573 (PDIP. L = Low Voltage Level. CD74HCT573 D0 D1 D G D2 D G O D3 D G O D4 D D G O D5 G O D6 D G O D7 D G O D G O O LE OE O0 O1 O2 O3 O4 O5 O6 O7 CD74HCT573 D0 D1 D O D2 D G O D3 D G O D4 D G O D5 D G O D6 D G O D7 D G O D G O G LE OE O0 O1 O2 O3 O4 O5 O6 O7 TRUTH TABLE OUTPUT ENABLE LATCH ENABLE DATA OUTPUT L H H H L H L L L L l L L L h H H X X Z NOTE: H = High Voltage Level. X = Don’t Care. 2 . CD74HC573. Z = High Impedance State. CD74HC573. SOIC. h = High voltage level one set-up time prior to the high to low latch enable transition. CD54HC573. l = Low voltage level one set-up time prior to the high to low latch enable transition. CD74HC573.

. . -0. . .15 - 3. .98 - - 3. . . . . .15 - V 6 4.9 - V -6 4. . . . .5 - 0. . . ICC . . . . . . . . . . . . . . .5 3. . . . . . . . . CD74HCT573 Absolute Maximum Ratings Thermal Information DC Supply Voltage. .5 4. .7 - V -7.CD74HC373. .1 - 0. . . . .±25mA DC VCC or Ground Current. . . . . . . . . . . . .5V to 5. . . 125 N/A CERDIP Package . . . . . . .5V . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . .±50mA Thermal Resistance (Typical. . . . . . per Output. IIK For VI < -0. . . . . θJA (oC/W) θJA (oC/W) PDIP Package . . . .5 V 4. . . .5 3.4 - - 4. .15 - - 3. . . . . . .5 - - 0. . . . . . . . . . . . This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. . . . . . . . . . . .5 - - 1. . .8 6 5. . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. . . 120 N/A Maximum Junction Temperature (Plastic Package) . . 1000ns (Max) 4.1 - ±1 - ±1 µA ICC VCC or GND 0 6 - - 8 - 80 - 160 µA 3 . .Lead Tips Only) Operating Conditions Temperature Range. CD74HCT373.5 - - 0. . .2V to 6V HCT Types .8 V -0. . . . . . . . . . . . . .48 - - 5. . . . . .4 - 4. .5 - - 1.4 V II VCC or GND - 6 - - ±0. .02 2 1. . . . . . . . . . . . . . .1 - 0. . . . . . . . . .5V . . . . . .5 - 0.5V . . . .26 - 0. . . . . -55oC to 125oC Supply Voltage Range. . . . . . CD74HC573. . . . . . . IOK For VO < -0. . .1 V 0. . . .35 - 1.9 - - 5.35 - 1. .34 - 5. . . . . . . . . . TA . . . . .5V. . .±35mA DC Output Source or Sink Current per Output Pin.26 - 0. . .4 V 7. VI. .02 4. 300oC (SOIC .1 - 0. . .9 - - 1.±20mA DC Output Diode Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 V 0. . . .9 - 5.2 - V 0. . . . . . . . . . .33 - 0. . . . . .5V or VI > VCC + 0. .5V or VO < VCC + 0.8 6 - - 0. . . . . . . . . .1 - 0.2 - V HC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads VIL VOH - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current - - 2 - - 0. . . . . . . .5 - V 4. . . . . . . . . 85 24 SOIC Package . . . . . . CD54HC573. . . . .1 - 0. θJA is measured with the component mounted on an evaluation PC board in free air. . . . . . . . . .02 2 - - 0. .35 V 6 - - 1. . . . . . . . . .5V.±20mA DC Drain Current. .02 6 5. . . . .33 - 0. . . .5V or VO > VCC + 0. . . . . . VCC HC Types . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) .8 - 1.5V to 7V DC Input Diode Current. . . . . VO . . . . .8 - 1. . . .5V < VO < VCC + 0. 150oC Maximum Storage Temperature Range . . . . . . . 500ns (Max) 6V . . VCC . .1 - 0. . . . .2 - 4. . . . . . . . .4. . . . . IO For VO > -0. . . . . .9 - V -0.9 - 1. . . . . . .5 - 1. . . . . . . NOTE: 3. . .1 V 6 4. .02 6 - - 0. . . . .5V DC Input or Output Voltage. . . . . .2 - - 4. . .4 - V -0. Note 3). .02 4. .84 - 3. . . . . . DC Electrical Specifications TEST CONDITIONS PARAMETER SYMBOL VI (V) VIH - 25oC IO (mA) VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 2 1. . . IO For -0. . .

VCC = 5.5 1.4V..8 6 - - 0.5 2 - - 2 - 2 - V - - 4.5 - - 0.33 - 0.8 - 0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.4 V 7.02 4.g.48 - - 5.84 - 3.5 - - 0. HCT Input Loading Table UNIT LOADS INPUT HCT373 HCT573 OE 1. 360µA max at 25oC.5 to 5. 4 .8 - 0.2 - V 0.5 3.8 6 5.5 - ±5 - ±10 µA - 4.4 - 4.8mA. CD54HC573.4 0.1 - 0.5 - - 0. For dual-supply systems theoretical worst case (VI = 2.5V) specification is 1.25 Dn 0.1 V 6 4.02 4.3 LE 0.26 - 0.1 - 4. CD74HCT373.8 V VIH or VIL -0.1 - 0.6 0.CD74HC373.4 - V -6 4. CD74HCT573 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC SYMBOL VI (V) IO (mA) VCC (V) - VIL or VIH VO = VCC or GND High Level Input Voltage VIH - Low Level Input Voltage VIL High Level Output Voltage CMOS Loads VOH PARAMETER Three-State Leakage Current -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 6 - - ±0.34 - 5.65 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Specifications table.5 4.98 - - 3.26 - 0.4 V HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads II VCC to GND - 5.5 - - 8 - 80 - 160 µA Three-State Leakage Current - VIL or VIH VO = VCC or GND 6 - - ±0.5 - 100 360 - 450 - 490 µA Input Leakage Current Quiescent Device Current NOTE: 4. e. CD74HC573.5 - ±5 - ±10 µA Additional Quiescent Device Current Per Input Pin: 1 Unit Load (Note 4) ∆ICC VCC -2.4 - - 4.33 - 0.7 - V -7.5 to 5.5 - - ±0.5 to 5.

5 - 35 44 53 ns 6 - 30 37 45 ns CL = 15pF 5 14 - - - ns CL = 50pF 2 - 175 220 265 ns 4. tPHL tPLH. tf = 6ns SYMBOL TEST CONDITIONS tPLH.5 10 - - 13 - 15 - ns 6 9 - - 11 - 13 - ns HC TYPES LE Pulse Width Set-up Time Data to LE tSU Hold Time. CD74HCT573 Prerequisite For Switching Specifications PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tW - 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns Set-up Time Data to LE tw - 4. Data to LE (373) - tH - 2 40 - - 50 - 60 - ns 4. Data to LE tH - 4.5 10 - - 13 - 15 - ns Switching Specifications PARAMETER Input tr.5 - 35 44 53 ns 6 - 30 37 45 ns 5 14 - - - ns HC TYPES Propagation Delay.5 5 - - 5 - 5 - ns 6 5 - - 5 - 5 - ns HCT TYPES LE Pulse Width tw - 4. CD54HC573.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns 2 50 - - 65 - 75 - ns 4.5 - 30 38 45 ns 6 - 26 33 38 ns CL = 15pF 5 12 - - - ns CL = 50pF 2 - 175 220 265 ns 4. LE to Qn tPLH.5 8 - - 10 - 12 - ns 6 7 - - 9 - 10 - ns 2 5 - - 5 - 5 - ns 4.CD74HC373. Data to Qn (HC/HCT373) Propagation Delay. tPHL CL = 50pF 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) TYP MAX MAX MAX UNITS 2 - 150 190 225 ns 4.5 13 - - 16 - 20 - ns Hold Time. tPHL CL = 15pF 5 . Data to LE (573) - tH Hold Time. Data to Qn (HC/HCT573) Propagation Delay. CD74HCT373. CD74HC573.

tPZH tTLH. tTHL Input Capacitance CI - - - 10 10 10 pF Three-State Output Capacitance CO - - - 20 20 20 pF Power Dissipation Capacitance (Notes 5. LE to Qn tPLH. 6 . Data to Qn (HC/HCT573) tPLH. tPHZ tTLH. tPZH CL = 50pF tPLZ.5 - 30 38 45 ns 6 - 26 33 38 ns CL = 15pF 5 12 - - - ns CL = 50pF 2 - 60 75 90 ns 4. CL = Output Load Capacitance.5 - 35 44 53 ns CL = 15pF 5 14 - - - ns CL = 50pF 4. tPHL Propagation Delay. per latch. Data to Qn (HC/HCT373) tPLH. tPHL Propagation Delay.5 - 35 44 53 ns CL = 15pF 5 14 - - - ns CL = 50pF 4.5 - 35 44 53 ns CL = 15pF 5 17 - - - ns CL = 50pF 4.CD74HC373.5 - 12 15 18 ns HCT TYPES Propagation Delay.5 - 12 15 18 ns 6 - 10 13 15 ns Input Capacitance CI - - - 10 10 10 pF Three-State Output Capacitance CO - - - 20 20 20 pF Power Dissipation Capacitance (Notes 5.5 - 30 38 45 ns 6 - 26 33 38 ns CL = 15pF 5 12 - - - ns CL = 50pF 2 - 150 190 225 ns 4. CD74HCT573 Switching Specifications PARAMETER Output Enabling Time Output Disabling Time Output Transition Time Input tr. CD74HC573.5 - 35 44 53 ns CL = 15pF 5 14 - - - ns CL = 50pF 4. tf = 6ns (Continued) SYMBOL TEST CONDITIONS tPZL. tPZH Output Disabling Time Output Transition Time tPLZ. CPD is used to determine the no-load dynamic power consumption. VCC = Supply Voltage.5 - 32 40 48 ns CL = 15pF 5 13 - - - ns CL = 50pF 4. CD74HCT373. tTHL 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) TYP MAX MAX MAX UNITS 2 - 150 190 225 ns 4. 6) CPD - 5 51 - - - pF CL = 50pF 4. tPHL Output Enabling Time tPZL. 6) CPD - 5 53 - - - pF NOTES: 5. CD54HC573. PD (total power per latch) = VCC2 fi (CPD + CL) where fi = Input Frequency. 6.

3V 1. input duty cycle = 50%. RESET OR PRESET tfCL = 6ns CLOCK 50% 50% tWL CLOCK INPUT tWL + tWH = trCL = 6ns VCC 90% CLOCK I fCL CL 50pF FIGURE 6. COMBINATION LOGIC tPLH FIGURE 4.3V 1. REMOVAL TIME. HCT SETUP TIMES. AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS tPHL 1. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES. input duty cycle = 50%.3V GND IC CL 50pF GND 90% tPLH 50% IC tSU(L) tPHL tPLH I fCL 3V NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. HOLD TIMES. HC SETUP TIMES. tREM VCC SET.3V 10% tPLH 10% GND tTHL 90% 50% 10% 90% 3V 2. REMOVAL TIME.7V 1. CD74HCT573 Test Circuits and Waveforms tWL + tWH = tfCL trCL 50% 10% 10% tf = 6ns tr = 6ns tTLH 90% INVERTING OUTPUT tPHL FIGURE 3. For fMAX. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES. VCC 90% 50% 10% 1. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH INPUT 2. AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS 7 .3V GND tSU(H) tSU(H) tSU(L) tTLH 90% OUTPUT tTHL 90% 50% 10% tTLH 90% 1. HOLD TIMES.3V 0. CD74HCT373. RESET OR PRESET GND tTHL 1.7V 0.3V 0.3V tWL tf = 6ns tPHL 1.3V tWH FIGURE 1. CD74HC573. CD54HC573. For fMAX.3V 10% FIGURE 5.CD74HC373.3V GND tTHL trCL tWH FIGURE 2. COMBINATION LOGIC trCL tfCL VCC tfCL GND 1.3V 0.3V 1.3V GND tr = 6ns DATA INPUT 50% tH(L) 3V 1.3V GND tH(H) tH(L) VCC DATA INPUT 3V 2. HCT CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH INPUT INVERTING OUTPUT GND NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table.3V OUTPUT tREM 3V SET.7V CLOCK INPUT 50% tH(H) tTLH 1.

3V OUTPUTS DISABLED OUTPUTS ENABLED FIGURE 8.7 1.3 10% tPHZ tPZH 90% 3V tPZL tPLZ OUTPUT LOW TO OFF 50% OUTPUT HIGH TO OFF 6ns GND 10% tPHZ tf OUTPUT DISABLE tPZL tPLZ OUTPUT LOW TO OFF 6ns tr VCC 1.3V tPZH 90% OUTPUTS ENABLED OUTPUTS ENABLED 0.3 OUTPUT HIGH TO OFF 50% OUTPUTS DISABLED FIGURE 7. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT 8 . FIGURE 9. CD74HCT373.CD74HC373. The test circuit is Output RL = 1kΩ to VCC. HC THREE-STATE PROPAGATION DELAY WAVEFORM OTHER INPUTS TIED HIGH OR LOW OUTPUT DISABLE IC WITH THREESTATE OUTPUT GND 1. HCT THREE-STATE PROPAGATION DELAY WAVEFORM OUTPUT RL = 1kΩ CL 50pF VCC FOR tPLZ AND tPZL GND FOR tPHZ AND tPZH NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. CL = 50pF. CD74HC573. CD74HCT573 Test Circuits and Waveforms 6ns (Continued) 6ns OUTPUT DISABLE 90% 50% 10% OUTPUTS ENABLED 2. CD54HC573.

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