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Apr 28, 2015

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CONVERTERS

The first step in designing an electronic circuit uses models for the

used electronic devices. Mathematical functions describe their behavior and

they allow global estimation of the whole circuit function. The used model

is closer to the real circuit behavior (but also more difficult to use) when the

used mathematical equations are more numerous (more parameters

considered) and complex (better approximation of real dependencies).

Obviously, simple models are used in first steps of the design

process. Subsequently, the design needs to be verified and validated,

making sure that it is close enough to the desired behavior. There are two

possible ways to check that:

Experimental model - is a real circuit built in lab conditions, but trying

to reflect as close as possible the real technology to use by final (series)

production process. The designer uses a set of components to build a small

number of products (sometimes a single one). The method is expensive,

time consuming and assumes some risk (malfunction can lead to component

damage or other unwanted effects).

On the other hand, the measured results represent the behavior of a

particular set of used components. The effect of parameter spreading (in the

range allowed by the component specifications) is hard to emphasize. For

example, the design includes an operational amplifier for which the data

book specifies an offset error in the range +/- 5mV. The particular used OA

exhibits +2mV offset. How would the circuit behave using a -4mV or +5mV

offset OA? To find that, such AO should be looked for and tested in the

experimental model.

Simulation of an electronic circuit computes the behavior functions

using mathematical models. As many as possible parameters are considered,

approximated by as close as possible mathematical functions. For complex

devices, the implied calculus is laborious requiring the computer speed and

power. The programming time could be large, but the method is much

cheaper. It reduces the component and assembly costs, allows simple

1

changing the parameter values, to emphasize the effect of each one on the

overall circuit behavior. The risk is significantly reduced and theoretical

aspects can be easily studied.

On the other hand, even the best component models are not perfect.

Simulation is an efficient analysis method, but it doesnt replace the

experimental model at all.

THE LAB PURPOSE

The lab intends to help students in understanding the behavior basics

of several feedback analog-to-digital circuit types, previously discussed at

class: counter, tracking and Successive Approximation Register (SAR)

ones. All of them are studied in both voltage- and current-comparison

versions.

A dedicated program simulates the ADCs, emphasizing several nonideal parameters of the used components also (slew rate, setting time, etc.).

The parameter values can be set in specific ranges.

THE LAB FLOW

The students perform steps similar to building and testing of an

experimental model:

- choosing a converter type,

- designing it (setting values for devices parameters),

- setting supply voltage and clock frequency,

- applying the input analog signal,

- analyzing the circuit behavior based on simulated time diagrams,

- understanding the (dis)advantages of each studied conversion

principle,

- emphasizing the error sources, modifying the circuit to improve it.

CHOOSING A CONVERTER TYPE

Three command logic types are available:

2

G

tact

Counter ADC

As the name shows, the

V bit

Sta rt/Stop

command logic is build around a nonreversible binary counter. PP (main

AO

gate) allows the clock pulses to reach

Logica

R

Reset

the counter input when Vbit=1, meaning

the voltage drop across R is less than the

instantaneous value of Vin. Each active

R

Ck

slope of the clock signal increments the

CNA

counter content, increasing the voltage

Bipola r

Numarator

drop across R by VLSB (the voltage

corresponding to the least significant

...

bit) The process continues until bringing

Iref

a1 a2

an

the actual voltage drop across R slightly

Rref

{A }

greater than the instantaneous value of

Vin. At this moment, Vbit (comparators

V ref

Fig. 1 Counter ADC voltage output) falls to logical 0 and closes PP.

comparison. Block diagram.

The conversion is done; its result is the

current counter content. It is held a

G

R

tact

while to be read by subsequent

COMP

V in

+

circuits, then the counter is reset.

V bit

Sta rt/Sto p

The voltage drop across R is zero,

basically less than Vin, Vbit rises

Logica

to logical 1, pointing a new

Reset

conversion begin. The conversion

R

Ck

period is proportional to the

CNA

instantaneous value of Vin, i.e.

Bipola r

Numarator

changes from a conversion to

another. The worst case happens

...

when

Vin=VFS;

then

the

Iref

a1 a2

an

conversion takes 2n-1 tact periods.

COMP

V in

PP

Io

Io

...

Io

Io

...

Rref

{A }

V ref

comparison. Block diagram.

3

COMP

V in

G

tact

Tracking ADC

This time, the binary

counter is reversible. PPU (UP

AO

PPD

main gate) allows the clock

R

pulses to reach up-count input,

while Vbit=1 (voltage drop

across R less than instantaneous

CD

CU

value of Vin). PPD (DOWN main

CNA

gate) allows the clock pulses to

Bipola r

Numarator

reach down-count input, while

...

Vbit=0 (voltage drop across R

greater than instantaneous value

Iref

a1 a2

an

of Vin). The counter content

Rref

{A }

increases or decreases 1LSB at

each clock active slope, such a

V ref

Fig. 3 Tracking ADC voltage way to lead to a voltage drop

across R as close as possible to

comparison. Block diagram.

the current value of Vin

G

tact

(approximating it with either

R

COMP

PPU

positive or negative error).

V in

+

V bit

Anyhow, the approximation

error module is less than VLSB.

PPD

The

counter

content

represents at any time the

conversion result. To keep the

CD

CU

converter able to track Vin,

CNA

this one is not allowed to

Bipola r

Numarator

change faster then the R

...

voltage drop maximum speed:

Iref

a1 a2

an

|dVin/dt| < VLSB/Ttact

+

V bit

PPU

Io

Io

...

Io

Io

...

Rref

{A }

V ref

Block diagram.

4

COMP

V in

V bit

Io

Io

AO

R

...

CNA

Bipola r

RA S

...

Iref

an

G

tact

a1 a2

Rref

{A }

V ref

comparison. Block diagram.

R

COMP

V in

V bit

Io

Io

...

CNA

+

Rref

RA S

...

a1 a2

Iref

Bipola r

an

{A }

V ref

comparison. Block diagram.

G

tact

The command logic is now a SAR

(Successive Approximation Register) and

works based on halving principle. Prior

to a conversion begin, Vin is assumed to

belong to its definition range; for an

unipolar converter: Vin[0,VFS). That is

the initial search-range, which halves

each conversion step (at each active slope

of clock signal). To perform that, the

SAR delivers such a number to determine

(via DAC) a voltage drop on R to halve

the previous step search-range. The first

step considers the whole definition range,

halved by VFS/2. The SAR generated

number

is

{A}=1/2=0,100...02.,

a1=MSB=1, and ai=0,i=2...n

If Vbit=1, then Vin>VFS/2 belongs to

the upper half of its definition range:

Vin[VFS,VFS). This sub-range (current

search-range) is halved in the next step

by the VFS value. SAR generates the

number {A}=3/4=0,110...02, where the

final value of a1=1 is established (no

subsequent steps of same conversion

could change it).

Otherwise, Vbit=0 shows that

Vin[0, VFS). This sub-range (current

search-range) is halved in the next step

by the VFS value. SAR generates the

number {A}=1/4=0,010...02, where the

final value of a1=0 is established.

Similarly, the remaining bits are

determined step by step.

5

SIMCAN PROGRAM PRESENTATION

The command menu includes the structure shown below:

C: Configuring

A: Supplies

- voltage supplies (0...+/-50V)

- clock frequency (0.001...10000kHz)

T: comparison Type 1 = voltage comparison

- slew rate AO (0.1...100V/s)

-open loop gain (1...1000000)

-resistance (0.1...100k)

2 = current comparison

- resistance (0.1...100K)

C: Converter

L: command Logic

- Reference current (0.001...10mA)

- DAC setting time (0...1000ns)

1: Tracking

2: Counter

3: Successive Approximation Register

G: signal Generator:

- Frequency (0...10000KHz)

- Offset (-50...+50V)

- Amplitude (0...50V)

- Shape

1 = Sinus

2 = Triangle

3 = Rectangle

O: Oscilloscope

- Time base

S: Simulate

X: eXit

6

1 = 1/3 tact/div

2 = 1 tact/div

3 = 3 tact/div

4 = 10 tact/div

5 = 100 tact/div

6 = 1000 tact/div

The displayed signal set depends on the chosen time base (each time

the most relevant):

For time bases

1 and 2:

Vin, Vcmp, Vbit, Clk, {A}cmp

3 and 4:

Vin, Vcmp, Vbit, Clk, {A}

5 and 6:

Vin, V{A}

The above signal meaning is:

Vin input voltage (from signal generator).

Vcmp comparison voltage (feedback to the inverting compatator

input).

By voltage comparison, Vcmp is the operational amplifier output

voltage:

Vcmp Io R Iref {A}cmp R

(1)

where Iref is the reference current. Vcmp is proportional to the partial result

{A}cmp and is compared to Vin.

By current comparison, Vcmp is the voltage in the Io pin of DAC IC:

Vcmp Vin Io R Vin Iref {A}cmp R

(2)

It represents the difference between Vin and the voltage drop across

R and it is compared to zero. Obviously, the following comparisons are

logically equivalent:

Vcmp (7.1) Vin Vbit 1

(3)

(4)

Consequently, the command logic circuit behaves identically for the two

comparison types.

7

Vbit the comparator output signal.

Clk clock signal. Any state change of the command state machine can

only occur on the active (rising) slope of the Clk signal. Correspondingly,

the value of the input signal Vbit is relevant for the circuit behavior only at

these moments. For correct behavior, the Clk period should be greater than

the sum of setting times for all the components in the feedback loop:

command logic, DAC, comparator and, eventually, operational amplifier.

{A}cmp - partial result for the current conversion step. In step i, bits

a1...ai-1 are already determined (they already have the values they will have

in the final result also), bit ai is logical 1 (halves the current search-range of

Vin) and bits ai+1...an are logical 0 yet.

{A} - final digital result of the conversion. It is updated at the end of

each conversion and keeps its value during the whole next conversion.

V{A} graphic representation of binary number {A}. Could be seen as

Vin signal re-build, trough an analog-to-digital-to-analog conversion.

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