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In our present day for any processor memory is basic constraint.

Designing a
optimum memory cell is very important.FLIP -FLOP (FF) is one of the basic storage our paper we are going to design an optimum size low power multiple
usage pulse trigger flipflop(Lpff).we use flipflop elements in many practical memory
applications like fifo,stack,queue,barell we need to optimize our flipflop to
construct optimum processor.FF Working mainly depends on clock signal(CLK).CLK
consumes maximum power of our chip so we need to optimize our wiring which is in
out of bound for a circuit designer.For a designer perspective optimization of pulse
generation circuit is of atmost we are going to design a custom pulse
generation circuit along with a novel d flipflop.along for a multiple usage
functionality purpose we use a dual mode functionality circuit which makes the
flipflop work for double edge trigger or for a single edge trigger.we are going to
compare the functionality with existing flipflop architrctures.our entire paper is
divided into following parts(1)flipflop (2)dual mode circuit(3)pulse generator
circuit(4)custom flipflop architecture(5)result(6)conclusion.
Flipflop is a transition detection circuit which latches on the data during transition
from 0-1 or 1-0 depending on the application.the basic parts of a flipflop are pulse
generation circuit and flipflop circuit.depending upon applications flipflop are
broadly categorized as two types:1)intensive flipflop2)extensive flipflops.for
intensive flipflop pg is included within its circuitry itself .but for extensive flipflop pg
is not included in is external which is given as an input to a group of
flipfops.generally both these flipflops have there own pros and cons.for the case of
intensive flipflop the wire delay is very less.but for the case of extensive flipflop
since it is give as a common input there is a high fanout node and also the wire
capacitive delay is also more.But for vlsi applications it is generally feasible to have
extensive flipflop instead of intensive flipflop.
Flipflop architectures:
for the case of case steady we are going to study about few novel architectures like
extensive pulse dco,cdff,static cdff,mhlff architectures.if we look into fig[1] there are
two back to back connected inverter which forms a basic latch circuit.two directly
connected latch circuit forms master slave latch which is nothing but this
at the juncture of inverters (inv1 , inv2) &( inv3 , inv4) .There is a high power
dissipation node which has discharge irrespective of any sort of condition.This leads
to greater switching activity because of which there is a great deal of dynamic
power dissipation.hence instead of the data close to output architecture(dco) we
use conditional discharge this instead of using inverter pair we use a
nmos combo with our inverter by doing so we have reduced the fanin at node x.And
also discharge during 1 state is also reduced.But even though switching activity is
reduced to a great deal but this node suffers from high switching activity node
.same goes for static cdff it also has worst case delay effect which limits the of the great progress is hybrid architecture in which we use pull up

pmos circuit.but this architecture suffers from floating node problem.

Fig[1]:ep dco

Fig [2]cdff


In our architecture we use signal injection mechanism coupled with pseudo nmos
logic style in the first stage.In this we use a small pass transistor to properly inject
the charge carriers and we reduce the worst case delay of the second stage
node.This pass transistor is also used for proper discharge of our signal.let us
consider first case where in which clock signal arrives but there is no change in data
during this stage pass transistor (mnx)is turned on and the data signal is directly
driven which is captured by the latch pair in the second the same timethe
pull down path is in off stage mainly because qfdbk is in off stage so therefore p2 is
in off state.for the case of 0-1 transition first p2 is turned on because pull down path
is activated because qfdbk is addition to this at the interface there is a signal
boosting because of mnx transistor but because periodic switch off and on of mnx
there are spike signals.these can be reduce by proper sizing of mnx transistor.For
the case of 1-0 scenario it provide a proper discharge path.Beyond all when you
compare with exisisting architectures the number of transistors used is considerably

For a pulse signal:

For a low pulse width signal: