model quiestion paper AMV

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model quiestion paper AMV

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You are on page 1of 6

Instructions to candidates:

Autonomous Institution Affiliated to VTU

VI Semester B.E. Examination, Model paper 1

Electronics and Communication Engineering

Analog & Mixed mode VLSI design 12EC62

Maximum Marks: 100

PART - A

1.1.

1.2.2

Determine the change in ID if VDS rises to 1 V and = 0.1 V-1. Calculate the

output impedance of the device .

Unity gain frequency of MOSFET is 50 Mhz. It has internal capacitances,

Cgs = 2 pF, Cgd = 0.5 pF. Calculate its gm.

Fig 1.3

1.3.

1.4.

1.5.

1.6.

1.7.

1.8.

1.9.

M BT

1

2

CO

1

Fig 1.5

Calculate the small signal voltage gain of the circuit in Fig 1.3 , given ID = 4 mA,

Kn(W/L)1 = 2 mA/V2, (W/L)3= 20, (W/L)2 = 10, RL = 5 k

For the differential gain of 86dB and CMRR of 74dB, if the differential input is

1V and the common input is 100V, calculate the output voltage.

Calculate the output Impedance of the unity gain buffer depicted in Fig 1.5.

Assume gmN = 1mA/V, gmP = 2mA/V, roN = 10K, roP = 20K

Calculate the number of pole associated with the circuit shown in Fig 1.6

Fig. 1.6

For the NMOS current source, calculate the total thermal noise current in drain

current for a band from 1 Hz to 1MHz at room temperature for gm = 2mA/V.

An amplifier with a forward gain of A0 has two coincident poles at . Calculate

the maximum value of A0 for a PM = 60 with a closed-loop gain of unity.

For the given circuit in Fig. 1.9, calculate the minimum and maximum on

resistance of M1. Assume Kn = 50 A/V2, W/L = 10/1, Vth = 0.7 V, VDD = 3V

and = 0. Also assume Vout Vin.

1.10.

1.11.

1.12.

1.13.

Fig 1.9

Fig1.10

For the circuit shown in Fig 1.10, (W/L)1 = 20/0.5 in m, VDD = 3V, VTHn = 0.7

V, Cox = 140 fF/ m2 and CH = 1pF, compute the maximum error at the output

due to charge injection.

Compute the dynamic range of a 16-bit DAC in dB

If a 16-bit ADC yielded an SNRD of 88 dB, then calculate the effective

resolution of the converter.

In a 3-bit successive approximation ADC, if Vin = 5.5 V, list out the values of

D2D1D0 with the appropriate Vout at each step.

1

1

2

2

2

2

3

3

4

3

2

3

PART B

2.

3.

Unit -1

a. Calculate the gain of the circuit shown in Fig 2.1. Mention the limitation

of the circuit. How can the circuit be modified to overcome this

limitation.

b. For the NMOS Differential circuit given in Fig. 2.2, the gm of Q1 is

9mA/V, calculate the small-signal differential gain, Vo/Vid.(Assume that

the bias values of Vin1 and Vin2 are equal)

Fig 2.1

Fig. 2.2

Fig. 2.3

2

c. Given: = 1, = 20 , = 20, = 2, = 0, R =

10k, = 5. Calculate i) the small signal gain, ii)the largest allowable

input-swing for the circuit shown in Fig 2.3.

OR

a. In the cascode stage of Fig 3.1, assume (W/L)1=50/0.5, (W/L)2=10/0.5, ID1 =

ID2 = 0.5 mA, and RD = 1k. . Assume Vth = 0.7V, VDD = 3V, Kn = 20

mA/V2, n = 0.1 V-1 and = 0.

i.

Calculate Vb such that M1 is 50mV away from the triode region.

ii. Calculate the small-signal voltage gain

iii. Using the value of Vb found in part (i), calculate the maximum

output swing.

16

iv.

10

Fig 3.1

4.

Unit -2

a. Explain the need of a common mode feedback? Discuss how a CMFB could

can be implemented using triode device in telescopic op-amp. Also mention

its drawback.

b. The circuit of Fig. 4.2 is designed for a nominal gain of 10. Determine the

minimum value of A1 for a gain error of 1%.

Fig 4.2

5.

OR

a. Calculate the output impedance of the circuit shown in Fig 5.1

Fig 5.1

b. Consider the feedback amplifier depicted in Fig 5.2, where C1 and C2 set

the closed loop gain.

i.

Determine the small signal step response of the circuit

ii. Calculate the positive and negative slew rates

16

10

Fig 5.2

6.

Unit -3

a. In the two stage op-amp of Fig 6.1, W/L = 50/0.5, for all transistors except

for M5,6, for which W/L = 60/0.5. Also, ISS = 0.25 mA and each output

branch is biased at 1 mA. Assume VDD = 3V, Kn = 20 mA/V2, kp = 6

mA/V2, n = 0.1 V-1, P = 0.2 V-1, and = 0, Vth = 0.7V of both PMOS &

NMOS.

i.

Determine the CM level at nodes X and Y.

ii. Calculate the maximum output voltage swing.

iii. If each output is loaded by 1 pF capacitor, compensate the op-amp

by miller multiplication for a phase margin of 60 in unity gain

feedback. Calculate the pole and zero positions after compensation.

Fig 6.1

7.

OR

a. Calculate the input referred thermal noise voltage of the amplifier shown in

Fig 7.2, assuming both transistors are in saturation. Also, determine the total

output thermal is the circuit drives a load capacitance CL. what is the output

SNR if a low-frequency sinusoid of amplitude Vm is applied to the input.

Fig 7.2

b. Explain why the input referred noise representation is preferred over output

noise representation. Also explain how to represent it with a neat sketch.

8.

9.

Unit -4

Consider the switched capacitor amplifier depicted in Fig. 8.1, where the

common mode feedback is not shown. Assume (W/L)1-4 = 50/0.5, ISS = 1mA,

C1 = C2 = 2 pF, C3 = C4 = 0.5 pF, and the output CM level is 1.5 V. Neglect

the transistor capacitances. Assume VDD = 3V, Kn = 20 mA/V2, kp = 6

mA/V2, n = 0.1 V-1, P = 0.2 V-1, and = 0, Vth = 0.7V of both PMOS &

NMOS.

i.

What is the maximum allowable output voltage swing in the

amplification mode?

ii. Determine the gain error of the amplifier.

iii. What is the small signal time constant in the amplification mode?

3

2

2

2

16

Fig 8.1

OR

a. The circuit of Fig. 9.1, samples the input on C1 when CK is high and connects 10

C1 and C2 when CK is low. Assume (W/L)1 = (W/L)2 and C1 = C2.

i.

What is the maximum error in Vout due to charge injection and clock feedthrough of M1 and M2? Assume the channel charge of M2 splits equally

between C1 and C2.

ii. Determine the sampled KT/C noise at the output after M2 turns off.

Fig 9.1

b. Determine the maximum DNL (in LSBs) for a 3-bit DAC, which has the

following characteristics. Does the DAC have 3-bit accuracy? If not, what is

the resolution of the DAC having this characteristic? Assume Vref= 5 V

Digital input

000

001

010

011

100

101

110

111

10.

11.

12

4

2

2

2

2

Voltage output

0V

0.625 V

1.5625 V

2V

2.5 V

3.125 V

3.4375 V

4.375 V

Unit -5

a. An 8-bit resistor string DAC was fabricated with a nominal resistance

value of 1 k. If the process was able to provide matching of resistors to

within 1%, find the effective resolution of the converter. What is the

maximum INL and DNL of the converter? Assume VREF = 5V.

b. Derive an expression for the quantization noise voltage spectral density

and show how averaging technique impacts it along with the

corresponding spectrum

OR

a. Explain the working principle of SAR ADC with a neat block diagram.

b. Perform the operation of a 3-bit successive approximation ADC with Vref =

8V. Make a table which shows the binary search algorithm of the converter

for Vin = 5.5V.

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