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EE247

Lecture 20
ADC Converters
Comparator design
• Single-stage open-loop amplifier
• Cascade of open-loop amplifiers
• Problem associated with DC offset
– Cascaded output series cancellation
– Input series cancellation
– Offset cancellation through additional input pair plus
offset storage capacitors
• Latched comparators
• Comparator examples
EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 1

Voltage Comparators
VDD

Vi+ +
Vout (Digital Output)
Vi- -

Play an important role in majority of ADCs


Function: Compare the instantaneous value of two analog signals &
generate a digital output voltage based on the sign of the
difference:

If Vi+ -Vi- > 0 Æ Vout=“1”


If Vi+ -Vi- < 0 Æ Vout=“0”

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 2


Voltage Comparator
Architectures
Comparator architectures:
• High gain amplifier with differential analog input & single-ended large
swing output
– Output swing has to be compatible with driving digital logic circuits
– Open-loop amplificationÆ no frequency compensation required
– Precise gain not required

• Latched comparators; in response to a strobe (clock edge), input stage


disabled & digital output stored in a latch till next strobe
– Two options for implementation :
• Latch-only comparator
• Low-gain preamplifier + high-sensitivity latch

• Sampled-data comparators
– T/H input
– Offset cancellation

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 3

Comparator Built with High-Gain Amplifier

Amplify Vin(min) to VDD


Æ Vin(min) determined by ADC
resolution

Example: 12-bit ADC with:


- VFS= 1.5VÆ 1LSB=0.36mV
- VDD=1.8V

Æ For 1.8V output & 0.5LSB


precision:

1.8V
Av Mi n = ≈ 10,000
0.18mV

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 4


Comparators
1-Single-Stage Amplification
• Amplifier maximum Gain-Bandwidth product (fu) for a given technology,
typically a function of maximum device ft
f
fu = un i t y-g a i n f r e q uency, fo=- 3d B f r eq u en cy fo = u
AV
Example: fu=10 GHz & AV = 10,000
Magnitude
1 0GH z
fo = ≈ 1MHz
1 0,0 00 Av
1
τ set t li ng = = 0 . 16 μ s ec
2π fo fu=0.1-10GHz
A l l o w a f ew τ f or ou t p u t t o s et t l e
1 f0 fu freq.
fCMax.
l ock → ≈ 1 .2 6MHz
5τ s ett li ng Assumption: Single pole amplifier
Too slow for majority of applications!
Æ Try cascade of lower gain stages to broaden frequency of operation

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 5

Comparators
2- Cascade of Open Loop Amplifiers

The stages identical Æ small-signal model for the cascades:

One stage:

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 6


Open Loop Cascade of Amplifiers

Example: N=4, AT=10000Æ ωoN=430 ωo1

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Open Loop Cascade of Amplifiers


For |AT(DC)|=10,000
Example:
N=3, fu=10GHz & AT ( 0 ) = 10000
10GHz
foN = 21/ 3−1 ≈ 237MHz
(10,000 )1/ 3
1
τ settling = = 0.7n sec
2π fo
Allow a few τ for output to settle
Max. 1
fClock → ≈ 290MHz
5τ settling

fmax improved from 1.26MHz to 290MHz Æ X236

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 8


Open Loop Cascade of Amplifiers
Offset Voltage

• From offset point


of view: high
gain/stage is
preferred

• Choice of # of
stage
Æbandwidth vs
offset tradeoff

Input-referred offset Æ

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 9

Open Loop Cascade of Amplifiers


Step Response
• Assuming linear behavior (not slew limited)

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 10


Open Loop Cascade of Amplifiers
Step Response
•Assuming linear behavior

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 11

Open Loop Cascade of Amplifiers


Delay/(C/gm)
Delay/(C/gm)
1/ N
C ⎡ ⎤
τ D = ⎛⎜ ⎞⎟ ⎢( N ! ) ⎛⎜ out ⎞⎟⎥
V
g
⎝ m ⎠⎣ V
⎝ i n ⎠⎦

• Minimum total delay broad


function of N
• Relationship between # of stages
resulting in minimize delay (Nop)
and gain (Vout/Vin) approximately:

No p t ≈ 1 + l og2 AT f or A < 1000

No p t ≈ 1.2l n AT for A ≥ 1000

Ref: J.T. Wu, et al., “A 100-MHz pipelined CMOS comparator ” IEEE Journal of Solid-State
Circuits, vol. 23, pp. 1379 - 1385, December 1988.

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 12


Offset Cancellation
• In sampled-data cascade of amplifiers Vos can be cancelled
Æ Store on ac-coupling caps in series with amp stages

• Offset associated with a specific amp can be cancelled by


storing it in series with either the input or the output of that
stage

• Offset can be cancelled by adding a pair of auxiliary inputs


to the amplifier and storing the offset on capacitors
connected to the aux. inputs during offset cancellation
phase
Ref: J.T. Wu, et al., “A 100-MHz pipelined CMOS comparator ” IEEE Journal of Solid-State
Circuits, vol. 23, pp. 1379 - 1385, December 1988.

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 13

Offset Cancellation
Output Series Cancellation
• Amp modeled as ideal
+ Vos (input referred)

1- Store offset:
• S1, S4Î open
• S2, S3Æ closed
Æ VC=AxVOS

Ref: J.T. Wu, et al., “A 100-MHz pipelined CMOS comparator ” IEEE Journal of Solid-State
Circuits, vol. 23, pp. 1379 - 1385, December 1988.

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 14


Offset Cancellation
Output Series Cancellation
2- Amplify:
• S2, S3Æ open
• S1, S4Î closed
ÆVC=AxVOS

Circuit requirements:
• Amp not saturate during offset
storage
• High-impedance (C) load Æ Cc not
discharged
• Cc >> CL to avoid attenuation
• Cc >> Cswitch avoid excessive offset
due to charge injection

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 15

Offset Cancellation
Cascaded Output Series Cancellation

Note: Offset storage


capacitors in series with the
amplifier outputs

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 16


Offset Cancellation
Cascaded Output Series Cancellation

1- S1Æ open, S2,3,4,5 closed

VC1=A1xVos1
VC2=A2xVos2
VC3=A1xVos3

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 17

Offset Cancellation
Cascaded Output Series Cancellation

2- S3Æ open first


• Feedthrough from S3 Æ offset on X
• Switch offset , ε3 induced on node X
• Since S4 remains closed, offset associated with ε3 Æ stored on C2

VX= ε3
VC1=A1xVos1- ε3
VC2=A2x(Vos2+ ε3)

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 18


Offset Cancellation
Cascaded Output Series Cancellation

3- S4Æ open
• Feedthrough from S4 Æ offset on Y
• Switch offset , ε4 induces error on node Y
• Since S5 remains closed, offset associated with ε4 Æ stored on C3
VY= ε4
VC2=A2x(Vos2+ ε3) – ε4
VC3=A3x(Vos3+ ε4)

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 19

Offset Cancellation
Cascaded Output Series Cancellation

4- S2Æ open, S5Æ open , S1Æ closed


• S2 open & S1 closed Æ since input connected to low impedance
source charge injection not of major concern
• Switch offset , ε5 introduced due to S5 opening

VX = A1x(Vin+Vos1) – VC1
= A1x(Vin+Vos1) – (A1.Vos1- ε3)
=A1.Vin+ ε3

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 20


Offset Cancellation
Cascaded Output Series Cancellation

Vy = A2x(Vx+Vos2) – VC2
= A2x(A1Vin + ε3 + Vos2) – [A2.(Vos2+ε3) - ε4]
=A1.A2.Vin + ε4

Vout = A3x(Vy+Vos3) – VC3


= A3.(A2xA1Vin + ε4 + Vos3) – [A3.(Vos3+ε4) - ε5]
= A1.A2.A3.Vin + ε5

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 21

Offset Cancellation
Cascaded Output Series Cancellation

Vout = A1.A2.A3.(Vin + ε5 /A1.A2.A3)


Input-Referred Offset = ε5 /A1.A2.A3

Example:
3-stage open-loop differential amplifier with series offset cancellation +
output amplifier (see Ref.)

ATotal(DC) = 2x106 = 126dB


Input-referred offset < 5μV

Ref: :R. Poujois and J. Borel, "A low drift fully integrated MOSFET operational amplifier," IEEE
Journal of Solid-State Circuits, vol. 13, pp. 499 - 503, August 1978.

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 22


Offset Cancellation
Output Series Cancellation

• Advantages:
– Almost compete cancellation
– Closed-loop stability not required

• Disadvantages:
– Gain per stage must be small
– Offset storage C in the signal path Æ could slow
down overall performance

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 23

Offset Cancellation
Input Series Cancellation

Ref: :R. Poujois and J. Borel, "A low drift fully integrated MOSFET operational amplifier," IEEE
Journal of Solid-State Circuits, vol. 13, pp. 499 - 503, August 1978.

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 24


Offset Cancellation
Input Series Cancellation
1- Store offset

Note: Mandates
closed-loop
stability

Ref: :R. Poujois and J. Borel, "A low drift fully integrated MOSFET operational amplifier," IEEE
Journal of Solid-State Circuits, vol. 13, pp. 499 - 503, August 1978.

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 25

Offset Cancellation
Input Series Cancellation
2- Amplify

S2, S3 Æ open
S1Æ closed

Example: A=4
ÆInput-referred
offset =Vos/5

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 26


Offset Cancellation
Cascaded Input Series Cancellation

ε2 Æcharge injection associated with


opening of S4

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Offset Cancellation
Input Series Cancellation

• Advantages:
– In applications such as C-array successive
approximation ADCs can use C-array to store
offset

• Disadvantages:
– Cancellation not complete
– Requires closed loop stability
– Offset storage C in the signal path- could slow
down overall performance

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 28


CMOS Comparators
Cascade of Gain Stages
Fully differential gain stages Æ 1st order cancellation of switch
feedthrough offset

1- Output series offset cancellation

2- Input series offset cancellation

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 29

CMOS Comparators
Cascade of Gain Stages
3-Combined input & output series offset cancellation

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 30


Offset Cancellation
• Cancel offset by additional pair of inputs
+ offset storage Cs + an extra clock
phase for offset storage (Lecture 18
slide 46 -48)

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 31

Latched Comparators
Vi+ Vi+ - Vi-
+ Vout
Vi - - (Digital Output)

t
Latch

Latch
Compares two input voltages
at time tx & generates a digital
output:
tx t
Vout
If Vi+ -Vi- > 0 Æ Vout=“1” “1”
If Vi+ -Vi- < 0 Æ Vout=“0”
“0”
t

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 32


CMOS Latched Comparators
Comparator amplification need not be linear
Æ can use a latch Æ regeneration

LatchÆ Amplification + positive feedback

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 33

Simplest Form of CMOS Latch

VDD VDD

M3 M4

M1 M2 M1 M2

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CMOS Latched Comparators
Small Signal Model

Latch can be modeled as a:


Æ Single-pole amp + positive feedback

Small signal ac half circuit

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 35

CMOS Latched Comparator


Latch Delay
V dV
g mV = +C
RL dt
gm ⎛ 1 ⎞ dV gm ⎛ 1 ⎞ dV
1− V= 1− dt =
C ⎜⎝ g m RL ⎟⎠ dt C ⎜⎝ g m RL ⎟⎠ V
gm ⎛ 1 ⎞ t2 V2 1 ⎛ a1 a⎞
g m RL ⎟⎠ ∫t1
dt = ∫ ⎜ ∫b dx = ln x b = ln a − ln b = ln ⎟
a
Integrating both sides: 1− dV
C ⎜⎝ V1 V ⎝ x b⎠
Latch Delay:
C ⎛ 1 ⎞ ⎛ V2 ⎞
tD = t2 − t1 = ⎟ ln ⎜ V ⎟
gm ⎜ 1 − 1
⎜⎜ ⎟⎟ ⎝ 1 ⎠
⎝ g m RL ⎠
For g m RL >> 1

C ⎛ V2 ⎞
tD ≈ ln
g m ⎜⎝ V1 ⎟⎠

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 36


CMOS Latched Comparators
Normalized Latch Delay

tD
C
gm
C ⎛ V2 ⎞
tD ≈ ln
g m ⎜⎝ V1 ⎟⎠
τD(3-stage amp)=
V2 18.2(C/gm)
→ Latch Gain = AL
V1
C
→ tD ≈ ln AL
gm Compared to a 3-stage open-loop
cascade of amps for equal overall gain
of 1000
ÆLatch faster by about x3

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 37

Latch-Only Comparator
• Much faster compared to cascade of open-
loop amplifiers

• Main problem associated with latch-only


comparator topology:
– High input-referred offset voltage (as high
as 100mV!)
• Solution:
– Use preamplifier to amplify the signal and
reduce overall input-referred offset

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 38


Pre-Amplifier + Latch
Overall Input-Referred Offset
fs
VosPreamp VosLatch
Vi+ Do+
Vi-
Av Latch
Do-
Preamp

Latch offset attenuated by preamp gain when referred to preamp input.


Assuming the two offset sources are uncorrelated:

2 1 2
σ Input − Re ferred _ Offset = σ Vos _ Pr eamp + 2
σ Vos _ Latch
APr eamp

Example : σ Vos _ Pr eamp = 4mV & σ Vos _ Latch = 50mV & APr eamp = 10
1
σ Input − Re ferred _ Offset = 42 + 502 = 6.4mV
102

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 39

Pre-Amplifier Tradeoffs
fs
Vi+ Do+
Vi-
Av Latch
Do-
Preamp
• Example:
– Latch offset 50 to 100mV
– Preamp DC gain 10X
– Preamp input-referred latch offset 50 to 100mV
– Input-referred preamplifier offset 2 to 10mV
– Overall input-referred offset 5.5 to 14mV

Æ Addition of preamp reduces the latch input-referred offset


reduced by ~7 to 9X Æ ~allows extra 3-bit resolution for ADC!

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 40


Comparator Preamplifier Gain-Speed Tradeoffs
• Amplifier maximum Gain-Bandwidth product (fu)for a given technology, typically a
function of maximum device ft
fu =unity gain frequency, f 0 = −3dB frequency & τ 0 = settling time
fu
f0 =
Apreamp
Magnitude
For example assuming preamp has a gain of 10:
fu 1GHz Av
f0 = = = 100 MHz
Apreamp 10 fu=0.1-10GHz
1 Apreamp
τ0 = = = 1.6n sec f0 fu freq.
2π f 0 2π fu
- Tradeoff:
• To reduce the effect of latch offset Æ high preamp gain desirable
• Fast comparator Æ low preamp gain
Æ Choice of preamp gain: compromise speed v.s. input-referred latch offset

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 41

Latched Comparator
fs

Vi+ Do+
Av Latch
Vi- Do-

Preamp

Important features:
– Maximum clock rate fs Æ settling time, slew rate, small signal bandwidth
– ResolutionÆ gain, offset
– Overdrive recovery
– Input capacitance (and linearity of input capacitance!)
– Power dissipation
– Input common-mode range and CMR
– Kickback noise
–…

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 42


Comparator Overdrive Recovery
Linear model for a single-pole amplifier:

UÆ amplification after time ta

During reset amplifier settles


exponentially to its zero input Example: Worst case input/output waveforms
condition with τ0=RC
Previous input Æ max. possible e.g. VFS
Assume Vm Æ maximum input Current input Æ min. input-referred signal
normalized to 1/2lsb (=1) (0.5LSB)

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 43

Comparators Overdrive Recovery

Example: Worst case input/output


waveforms

ƒ If recovery time is not long enough to allow output to discharge (recover) from
previous state- then it may not be able to resolve the current input Æ error
ƒ To minimize this effect:
1. Passive clamp
2. Active restore
3. Low gain/stage

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 44


Comparators Overdrive Recovery
Limiting Output Voltage

Active Restore
Clamp
After outputs are latched by following stage
Adds parasitic capacitance
Æ Activate φR & equalize output nodes

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 45

CMOS Preamplifier + Latched Comparator


Delay in Response

Latch delay previously found:

C ⎛ V2 ⎞
τD ≈ ln
g m ⎜⎝ V1 ⎟⎠

Assuming gain of Av for the preamplifier then :V1 = Av × Vin

C ⎛ V0 ⎞
τD ≈ ln
g m ⎜⎝ AvVin ⎟⎠

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 46


Latched Comparator Including Preamplifier
Example
VDD

M5 M3 M4 M6

-
Vo
CLK +
Preamplifier gain:
M1 M2
g mM 1 (VGS − Vth ) +
M3 M3

Av = = Vin M9
g mM 3 (VGSM 1 − VthM 1 ) -

bias M7 M8
Comparator delay:
(for simplicity, preamp delay ignored)
C ⎛ V0 ⎞
τD ≈ ln
g m ⎜⎝ AvVin ⎟⎠ Preamp Latch

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 47

Comparator Dynamic Behavior


Comparator Reset Comparator Decision

CLK

TCLK

τdelay

vOUT

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 48


Comparator Resolution

CLK

VIN =10mV
1mV
0.1mV
vOUT 10μV

Δt = (gm/C).ln(Vin1/Vin2)

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 49

Comparator Voltage Transfer Function


Non-Idealities
Vout
ε

VOffset

-0.5LSB 0.5LSB

Vin

VOffset Æ Comparator offset voltage


ε Æ Meta-Stable region (output ambiguous)

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 50


CMOS Comparator Example

• Flash ADC: 8bits, +-1/2LSB INL @ fs=15MHz (Vref=3.8V, LSB~15mV)


• No offset cancellation
Ref: A. Yukawa, “A CMOS 8-Bit High-Speed A/D Converter IC,” JSSC June 1985, pp. 775-9

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 51

Comparator with Auto-Zero

Note:
Reference & input
both differential

Ref: I. Mehr and L. Singer, “A 500-Msample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel
Applications,” JSSC July 1999, pp. 912-20.

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 52


Flash ADC
Comparator with Auto-Zero
Voffset

VC + −VC − =
(VR e f + −VR e f − ) −VO ffs et

Ref: I. Mehr and D. Dalton, “A 500-Msample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel
Applications,” JSSC July 1999, pp. 912-20.

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 53

Flash ADC
Comparator with Auto-Zero
Voffset

Vo

Vo = AP1 ∗ AP2 [(VIn+ − VI n− ) − (VC + − VC − ) − VOff s et ]

S u b st i t u t i n g f o r (VC + − VC − ) f r o m p r evio u s c yc le :

Vo = AP1 ∗ AP2 ⎡⎣(VIn+ − VIn− ) − (VRe f + − VRe f − )⎤⎦

N o t e: O f fs et i s ca n cel l ed & d i f f er ence b et w een


i np u t & r ef er en ce es t a b l i s hed
Ref: I. Mehr and D. Dalton, “A 500-Msample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel
Applications,” JSSC July 1999, pp. 912-20.

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 54


Flash ADC
Using Comparator with Auto-Zero

Ref: I. Mehr and D. Dalton, “A 500-Msample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel
Applications,” JSSC July 1999, pp. 912-20.

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 55

Auto-Zero Implementation

Ref:I. Mehr and L. Singer, “A 55-mW, 10-bit, 40-Msample/s Nyquist-Rate CMOS ADC,” JSSC
March 2000, pp. 318-25

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 56


Comparator Example
• Variation on Yukawa latch
used w/o preamp

• Good for low resolution


ADCs (in this case
1.5bit/stage for a pipeline)

• Note: M1, M2, M11, M12


operate in triode mode
x
• M11 & M12 added to vary
comparator threshold

• Conductance at node X is
sum of GM1 & GM11
Ref: T. B. Cho and P. R. Gray, "A 10 b, 20 Msample/s, 35 mW pipeline A/D converter," IEEE
Journal of Solid-State Circuits, vol. 30, pp. 166 - 172, March 1995

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 57

Comparator Example (continued)


• M1, M2, M11, M12 operate in triode
mode with all having equal L
• Conductance of input devices:
μCox
G1 = × ⎣⎡W1 (VI1 − Vt h ) + W11 (VR − − Vt h )⎦⎤ VVo1
o1 Vo2
L
μCox
G2 = × ⎡⎣W1 (VI 2 − Vt h ) + W11 (VR + − Vt h )⎤⎦
L
μCoxW1 ⎡ V − V − W11 V − V
→ ΔG = × ⎢( I1 I 2 ) ( R + R − )⎤⎥
L ⎣ W1 ⎦

• To 1st order, for W1= W2 & W11=W12


Vthlatch = W11/W1 x VR G1 G2
where VR = VR+ - VR-
Æ VR fixed W11, 12 varied from
comparator to comparatorÆ Eliminates
need for resistive divider
Ref: T. B. Cho and P. R. Gray, "A 10 b, 20 Msample/s, 35 mW pipeline A/D converter," IEEE
Journal of Solid-State Circuits, vol. 30, pp. 166 - 172, March 1995

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 58


Comparator Example
• Used in a pipelined ADC with digital
correction
Æno offset cancellation required
Differential reference & input
• M7, M8 operate in triode region
• Preamp gain ~10
• Input buffers suppress kick-back

• φ1 high Æ Cs charged to VR & φ2B is also


high Æ current diverted to latchÆ
comparator output in hold mode

• φ2 highÆ Cs connected to S/Hout &


comparator input (VR-S/Hout), current sent
to preamp Æ comparator in amplify mode

Ref: S. Lewis, et al., “A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter”


IEEE JSSC ,NO. 6, Dec. 1987

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 59

Bipolar Comparator Example

• Used in 8bit 400Ms/s &


6bit 2Gb/s flash ADC
• Signal amplification
during φ1 high, latch
operates when φ1 low
• Input buffers suppress
kick-back & input current
• Separate ground and
supply buses for front-
end preamp Æ kick-back
noise reduction
Preamp Latched Comparator

Ref: Y. Akazawa, et al., "A 400MSPS 8b flash AD conversion LSI," IEEE International Solid-State Circuits
Conference, vol. XXX, pp. 98 - 99, February 1987
Ref: T. Wakimoto, et al, "Si bipolar 2GS/s 6b flash A/D conversion LSI," IEEE International Solid-State Circuits
Conference, vol. XXXI, pp. 232 - 233, February 1988

EECS 247- Lecture 20 Nyquist Rate ADCs © 2008 H.K. Page 60