Faculty of Engineering
Electronics and Communications Department
Submitted by:
Supervised by:
Prof. Dr. Hany Fikry
Prof. Dr. Hisham Haddara
Cairo 2009
Curriculum Vitae
Name: Mohammad Adel Elbadry
Date of Birth: 20/8/1983
Place of Birth: Heliopolis, Egypt
First University Degree: B.Sc. in Electrical Engineering
Name of University: Ain Shams University
Date of Degree: June 2005
ii
Statement
This dissertation is submitted to Ain Shams University for the degree of
Master of Science in Electrical Engineering (Electronics and Communica
tions Engineering).
The work included in this thesis was carried out by the author at the Elec
tronics and Communications Engineering Department, Faculty of Engineer
ing, Ain Shams University, Cairo, Egypt.
No part of this thesis was submitted for a degree or a qualiﬁcation at any
other university or institution.
iii
Acknowledgments
All praise is due to Allah, Most Merciful, the Lord of the Worlds, Who taught man what he knew
not. I would like to thank God Almighty for bestowing upon me the chance, strength and ability
to complete this work.
I wish to express my gratitude to my supervisors, Professor Hany Fikry and Professor Hisham
Haddara for their exceptional guidance, encouragement, ﬂexibility, insightful thoughts and useful
discussions.
I am deeply indebted to Dr. Ayman Elsayed, design manager at SiWare systems, whose help,
stimulating suggestions and encouragement helped me in all the time of research for and writing
of this thesis. I have learned a lot form him, on both the technical and personal levels. I am in
no way capable of appropriately thanking him for his great help to me.
I am also grateful to Dr. Hassan Aboushady, of LIP6, University of Paris VI, for his help and
support in the system level studies. His help was a great boost to my work.
Special thanks goes to my colleagues at SiWare systesm: Botros George, Ahmed Elshennawy,
Ahmed Safwat, Ahmed Shaban and Mohamed Elkholy for the many fruitful discussions, encour
agement, as well as helping me revise the thesis.
I would like also to thank Amr Misbah and Bichoy Waguih, my colleagues at IC Lab, Ain Shams
University, for their generous help and support in IT problems.
Many thanks are also due to my Professors and colleagues at IC Lab, Ain Shams University, for
their knowledge, help and support.
Finally I would like to express my love and gratitude to my parents and my brother for their
unconditional love and unlimited support.
iv
Abstract
Mohammad Adel Elbadry, ”Force Feedback in MEMS Inertial Sensors”, Master of
Science dissertation, Ain Shams University, 2009.
This thesis presents analysis of the nonidealities in the feedback path of ΣΔ ForceFeedback
MEMS inertial sensors as well as the circuit implementation of the reference voltage for the
feedback. A highperformance MEMS accelerometer sensing system is used as a testvehicle for
the presented analysis and design.
On the system level, analysis is performed on the eﬀect of clockjitter in the feedback path
on the signaltonoise (SNR) ratio of the accelerometer system. The eﬀect of both white jitter
and cumulative jitter are investigated. It is shown that cumulative jitter has negligible eﬀect on
the SNR of high performance ΣΔ ForceFeedback systems. On the other hand, it is shown that
white jitter can severely limit the SNR of ΣΔ ForceFeedback systems. Analytical relations are
derived for the eﬀect of Jitter on SNR.
Analysis is also performed on the eﬀect of the reference voltage noise, in the feedback path,
on the SNR of ΣΔ ForceFeedback systems. Analytical relations are derived that describe the
eﬀect of the reference noise on the achievebale SNR. It is shown that the reference noise does
not limit the sensitivity of the system; it only aﬀects the maximum achievable SNR. It is also
shown that the maximum SNR will be independent on the signal level; it will only depend on the
Reference VoltagetoReference voltage noise ratio.
Based on the systemlevel analysis, specs are derived for the voltage reference for achieving
a 110dB SNR on system level. The various referencevoltage technologies are overviewed, and
bandgap technology is chosen. Circuit implementation of a lownoise bandgap reference circuit is
then performed on a SiGe 0.35μm BiCMOS technology. Three diﬀerent topologies of the bandgap
voltage are implemented and simulated.
The 1st bandgap circuit is a conventional CMOS implementation of the bandgap circuit
with a 1st order temperature compensation. Chopping is used to overcome 1/f noise. Circuit
implementation is made to enable trimming the reference for minimum temperature coeﬃcient
in case of process variations. This reference achieves a total integrated noise of 1μV from 1 mHz
to 100Hz with a reference voltage value of 1.2V.
The 2nd circuit is also a 1st order compensated bandgap that makes use of the npn bipolars
available in the technology to achieve the lowﬂicker noise target. The circuit is capable of
v
generating a 1.2V and a 2.4V references simultaneously and achieves a total integrated noise of
less than 2μV (in the 1mHz100Hz range) on the 2.4V reference.
In the 3rd circuit, a new higherorder temperature compensation technique is proposed and
implemented. The circuit achieves a 0.55ppm/◦ C temperature coeﬃcient over the 40◦ C125◦ C
temperature range. The integrated noise, however, is an order of magnitude larger than the other
two implementations.
Key words: Voltage Reference, Bandgap, LowNoise, Temperature Compensation, MEMS,
Inertial Sensor, Accelerometer, chopping, Jitter, BiCMOS, SiGe, PTAT, CTAT, ΣΔ, Force
Feedback, Forcebalancing
vi
Summary
Chapter 1 is an introduction to the thesis.
Chapter 2 is an overview on MEMS Inertial Sensors and Interface circuits. Both MEMS ac
celerometers and MEMS gyroscopes are overviewed and their operating principles are presented.
The diﬀerent interface options (openloop and closeloop) are presented and discussed
Chapter 4 presents an overview of the diﬀerent reference voltage generation technologies. The
performance metrics of voltage references are ﬁrst deﬁned. This is followed by an overview on
voltage reference technologies in both literature and industrial designs
Chapter 5 presents extensive analysis of bandgap references followed by three diﬀerent imple
mentations of lownoise references for use in high performance forcefeedback systems, including
a new temperaturecompensation technique for achieving low temperature drift. The reference
specs are ﬁrst derived (based on a MEMS accelerometer sensing system), then analysis is made for
the various performance metrics of bandgap references. Finally, circuit designs and simulations
are presented
vii
Contents
List of Symbols xx
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Thesis Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
viii
3.2 The acceleration sensing system . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 Nonidealities in ΣΔ ForceFeedback systems . . . . . . . . . . . . . . . . . 17
3.3.1 Pulse Shape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3.2 Eﬀect of Clock Jitter in ΣΔ ForceFeedback systems . . . . . . . . 20
3.3.2.1 Eﬀect of Jitter in Continuous time ΣΔ modulators . . . . 20
3.3.2.2 Decreasing sensitivity to Jitter . . . . . . . . . . . . . . . 24
3.3.2.2.1 Using Multibit Feedback DAC . . . . . . . . . . 24
3.3.2.2.2 Using Linear DAC pulseshaping . . . . . . . . . 25
3.3.2.2.3 Using Quadratic DAC pulseshaping . . . . . . . 26
3.3.2.3 Eﬀect of Jitter in the acceleration sensing system . . . . . 27
3.3.2.4 Jitter Simulations . . . . . . . . . . . . . . . . . . . . . . 29
3.3.2.4.1 Using Multibit Feedback DAC . . . . . . . . . . 32
3.3.2.4.2 Using Linear DAC pulseshaping . . . . . . . . . 32
3.3.2.4.3 Using Quadratic DAC pulseshaping . . . . . . . 33
3.3.2.5 Accumulated Jitter . . . . . . . . . . . . . . . . . . . . . . 33
3.3.2.5.1 Eﬀect of jitter for diﬀerent jitter frequencies . . . 34
3.3.2.5.2 Maximum allowable closein jitter . . . . . . . . . 35
3.3.2.5.3 Eﬀect of clock with both white and accumulated jitter 35
3.3.2.6 Conclusions on Jitter . . . . . . . . . . . . . . . . . . . . . 36
3.3.3 Reference Voltage Noise . . . . . . . . . . . . . . . . . . . . . . . . 38
3.3.3.1 Reference Voltage multiplication . . . . . . . . . . . . . . 38
3.3.3.2 Eﬀect of Reference Noise on SNR . . . . . . . . . . . . . . 39
3.3.3.2.1 Ff b ref n is dominant . . . . . . . . . . . . . . . . 40
3.3.3.2.2 Ff b qnref is dominant . . . . . . . . . . . . . . . . 42
3.3.3.2.3 Ff b qn is dominant . . . . . . . . . . . . . . . . . 44
3.4 Proposed System and DAC specs . . . . . . . . . . . . . . . . . . . . . . . 46
ix
4.2 Reference Voltage Technologies . . . . . . . . . . . . . . . . . . . . . . . . 49
4.2.1 ZenerBased References . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.2.1.1 Review of ZenerBased References . . . . . . . . . . . . . 52
4.2.2 XFET references . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.2.3 FloatingGate References . . . . . . . . . . . . . . . . . . . . . . . . 57
4.2.3.1 Introduction to FloatingGate transistors . . . . . . . . . . 57
4.2.3.2 Programming Techniques for Floating Gate transistors . . 58
4.2.3.3 Review of ﬂoatinggate references . . . . . . . . . . . . . . 59
4.2.4 Bandgap References . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.2.4.1 Introduction to Bandgap references . . . . . . . . . . . . . 63
4.2.4.2 Review of Bandgap References . . . . . . . . . . . . . . . 65
4.2.4.2.1 Diﬀerential Bandgap references . . . . . . . . . . 67
4.2.4.2.2 LowVoltage Bandgap References . . . . . . . . . 70
4.2.4.2.3 HigherOrder Compensated Bandgap References . 70
4.2.4.3 Performance of Commercial bandgap references . . . . . . 72
4.2.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5 Circuit Implementation 73
5.1 Choosing Reference Voltage Technology . . . . . . . . . . . . . . . . . . . . 73
5.2 Reference Voltage Specs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.2.1 Reference Voltage Value . . . . . . . . . . . . . . . . . . . . . . . . 75
5.2.2 Output Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.2.3 Drift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.3 The Basic Bandgap Circuit: An overview . . . . . . . . . . . . . . . . . . . 76
5.3.1 Lateral versus Vertical PNP in bandgap circuits . . . . . . . . . . . 80
5.3.2 Longterm drift in bandgaps . . . . . . . . . . . . . . . . . . . . . . 83
5.3.3 Stability of the CMOScompatible bandgap . . . . . . . . . . . . . 84
5.3.3.1 Evaluating the Loop Gain . . . . . . . . . . . . . . . . . . 84
5.3.3.2 Eﬀect of output node choice on stability . . . . . . . . . . 88
5.3.4 Opamp Gain Requirement in the CMOScompatible bandgap . . . 92
5.3.5 Supply Rejection in the CMOScompatible Bandgap Circuit . . . . 95
5.3.5.1 DC Supply Rejection . . . . . . . . . . . . . . . . . . . . . 96
x
5.3.5.2 High Frequency Supply Rejection . . . . . . . . . . . . . . 101
5.3.6 Noise in the CMOScompatible Bandgap Circuit . . . . . . . . . . . 111
5.3.6.1 Opamp Noise Contribution . . . . . . . . . . . . . . . . . 112
5.3.6.2 RP T Noise Contribution . . . . . . . . . . . . . . . . . . . 113
5.3.6.3 RCT Noise Contribution . . . . . . . . . . . . . . . . . . . 114
5.3.6.4 Mp1 Noise Contribution . . . . . . . . . . . . . . . . . . . 116
5.3.6.5 Mp2 Noise Contribution . . . . . . . . . . . . . . . . . . . 117
5.3.6.6 Q2 Noise Contribution . . . . . . . . . . . . . . . . . . . . 118
5.3.6.7 Q1 Noise Contribution . . . . . . . . . . . . . . . . . . . . 120
5.3.6.8 Summary and discussion of noise contributions . . . . . . 122
5.3.7 Mismatch errors in the CMOScompatible Bandgap Circuit . . . . . 123
5.3.7.1 Eﬀect of Opamp’s inputoﬀset voltage . . . . . . . . . . . 124
5.3.7.2 Eﬀect of mismatch of PMOS current sources . . . . . . . . 125
5.3.7.3 Eﬀect of mismatch of the BJT transistors . . . . . . . . . 127
5.3.7.4 Eﬀect of resistor mismatch . . . . . . . . . . . . . . . . . . 128
5.4 Bandgap Reference Voltage Implementation . . . . . . . . . . . . . . . . . 130
5.4.1 Conventional Bandgap Reference: circuit 1 . . . . . . . . . . . . . . 130
5.4.1.1 Circuit 1: Bipolar transistor choice . . . . . . . . . . . . . 130
5.4.1.2 Circuit 1: Opamp choice and biasing . . . . . . . . . . . . 130
5.4.1.2.1 Noise Considerations in Opamp Design . . . . . . 132
5.4.1.2.2 SelfBias Loop for the Opamp . . . . . . . . . . . 133
5.4.1.2.3 Bias of the cascode transistors . . . . . . . . . . . 136
5.4.1.3 Circuit 1: PMOS currentmirror and resistors . . . . . . . 137
5.4.1.4 Circuit 1: Startup circuit . . . . . . . . . . . . . . . . . . 139
5.4.1.5 Circuit 1: DC performance . . . . . . . . . . . . . . . . . 140
5.4.1.6 Circuit 1: Supply rejection . . . . . . . . . . . . . . . . . . 141
5.4.1.7 Circuit 1: Loop Stability . . . . . . . . . . . . . . . . . . . 142
5.4.1.8 Circuit 1: Noise Performance . . . . . . . . . . . . . . . . 143
5.4.1.9 Circuit 1: Using a Chopped Opamp . . . . . . . . . . . . 146
5.4.1.9.1 Choosing the chopping frequency . . . . . . . . . 146
5.4.1.9.2 Eﬀect of Chopped Oﬀset on SNR . . . . . . . . . 148
xi
5.4.1.9.3 Chopping conﬁgurations . . . . . . . . . . . . . . 150
5.4.1.9.4 Eﬀect of switches on Stability . . . . . . . . . . . 151
5.4.1.9.5 Filtering the Chopped reference . . . . . . . . . . 152
5.4.1.9.6 Noise Performance of the Chopped bandgap . . . 153
5.4.1.10 Circuit 1: Trimming for Temperature Coeﬃcient . . . . . 154
5.4.2 BiCMOS Bandgap Reference: Circuit 2 . . . . . . . . . . . . . . . . 158
5.4.2.1 Circuit 2: Voltage Headroom . . . . . . . . . . . . . . . . 158
5.4.2.2 Circuit 2: Expressions of Vbg2 and Vbg1 . . . . . . . . . . . 160
5.4.2.3 Circuit 2: BiCMOS Opamp . . . . . . . . . . . . . . . . . 161
5.4.2.3.1 Opamp headroom considerations . . . . . . . . . 161
5.4.2.3.2 Opamp tail current . . . . . . . . . . . . . . . . . 162
5.4.2.4 Choosing I . . . . . . . . . . . . . . . . . . . . . . . . . . 163
5.4.2.5 Circuit 2: DC performance . . . . . . . . . . . . . . . . . 163
5.4.2.6 Circuit 2: Supply rejection . . . . . . . . . . . . . . . . . . 163
5.4.2.7 Circuit 2: Noise Performance . . . . . . . . . . . . . . . . 163
5.4.3 Higher Order Compensated Bandgap: Circuit 3 . . . . . . . . . . . 166
5.4.3.1 Circuit 3: Basic Concept . . . . . . . . . . . . . . . . . . . 166
5.4.3.1.1 Previous Implementation . . . . . . . . . . . . . . 168
5.4.3.1.2 Suggested Implementation: A currentmode approach169
5.4.3.2 Circuit 3: DC performance . . . . . . . . . . . . . . . . . 178
5.4.3.3 Circuit 3: Supply rejection . . . . . . . . . . . . . . . . . . 179
5.4.3.4 Circuit 3: Noise Performance . . . . . . . . . . . . . . . . 181
5.4.3.5 Circuit 3: Comparison with other compensation techniques 182
5.4.4 Performance Comparison . . . . . . . . . . . . . . . . . . . . . . . . 183
Conclusions 184
Appendices 186
xii
B Opamp Behavioral model 188
References 190
xiii
List of Tables
xiv
List of Figures
xv
3.17 Spectra for Sinusoidal 100ps rms jitter with diﬀerent frequencies . . . . . . 34
3.18 Output spectrum for 100ns rms sinusoidal jitter . . . . . . . . . . . . . . . 35
3.19 Realistic clock with white noise ﬂoor and closein noise skirt . . . . . . . . 36
3.20 Output spectra for a realistic clock and a clock with only white jitter . . . 37
3.21 Illustration of Vref multiplication . . . . . . . . . . . . . . . . . . . . . . . 38
3.22 Spectra for ideal system and system with dominant reference noise . . . . 41
3.23 Illustrating noisefolding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.24 Spectra for ideal system and system with wideband ref. noise . . . . . . . . 43
3.25 Spectra for three diﬀerent input accelerations . . . . . . . . . . . . . . . . 44
xvi
5.2 CMOScompatible bandgap circuit . . . . . . . . . . . . . . . . . . . . . . 78
5.3 A cross section of a lateral PNP transistor in CMOS technology [Pertijs 06] 81
5.4 A cross section of a vertical PNP transistor in CMOS technology [Pertijs 06] 82
5.5 CMOScompatible bandgap with positive and negative feedback indicated . 85
5.6 AC model used for evaluating Loop Gains in CMOScompatible bandgap . 86
5.7 Equivalent AC model of the overall negativefeedback . . . . . . . . . . . . 88
5.8 Loop Gain and Phase for CL connected to Voutp and Vout . . . . . . . . . . 90
5.9 Model for evaluating the eﬀect of ﬁnite Opamp gain . . . . . . . . . . . . . 93
5.10 Bandgap circuit with Oﬀset voltage representing eﬀect of ﬁnite gain . . . . 93
5.11 Model used for PSR evaluation . . . . . . . . . . . . . . . . . . . . . . . . 96
5.12 P SR0 versus Gop0 illustrating the possibility of a zero P SR0 . . . . . . . . 100
5.13 PSR and Loop Gain for Cc connected to ground . . . . . . . . . . . . . . . 105
5.14 PSR and Loop Gain for Cc connected to ground . . . . . . . . . . . . . . . 106
5.15 PSR and Loop Gain for Cc connected to Vdd and to ground . . . . . . . . . 108
5.16 PSR for Cc connected to Vdd at diﬀerent Gop0 . . . . . . . . . . . . . . . . 109
5.17 Real Opamp used for validation of PSR . . . . . . . . . . . . . . . . . . . . 109
5.18 PSR for Cc connected to Vdd and ground for real Opamp . . . . . . . . . . 110
5.19 Noise sources in the CMOScompatible bandgap circuit . . . . . . . . . . . 111
5.20 AC model for noise contribution of vnop . . . . . . . . . . . . . . . . . . . . 112
5.21 AC model for noise contribution of vnrpt . . . . . . . . . . . . . . . . . . . 113
5.22 AC model for noise contribution of vnrct1 . . . . . . . . . . . . . . . . . . . 115
5.23 AC model for noise contribution of inmp1 . . . . . . . . . . . . . . . . . . . 117
5.24 AC model for noise contribution of inmp2 . . . . . . . . . . . . . . . . . . . 118
5.25 AC model for noise contribution of inq2 . . . . . . . . . . . . . . . . . . . . 119
5.26 AC model for noise contribution of inq1 . . . . . . . . . . . . . . . . . . . . 121
5.27 Bandgap with Chopped Opamp . . . . . . . . . . . . . . . . . . . . . . . . 124
5.28 Bandgap with mismatch in PMOS current mirror . . . . . . . . . . . . . . 126
5.29 Bandgap with mismatch in BJT’s . . . . . . . . . . . . . . . . . . . . . . . 127
5.30 Bandgap with mismatch in resistors . . . . . . . . . . . . . . . . . . . . . . 129
5.31 Schematic for circuit 1 (startup not shown) . . . . . . . . . . . . . . . . . . 131
5.32 CommonCentroid Layout of BJT’s with 1:8 ratio . . . . . . . . . . . . . . 132
xvii
5.33 Possible solutions for biasing the Opamp . . . . . . . . . . . . . . . . . . . 134
5.34 Selfbias for the Opamp in circuit 1 . . . . . . . . . . . . . . . . . . . . . . 135
5.35 Selfbias Loop Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
5.36 Bias of the PMOS cascodes . . . . . . . . . . . . . . . . . . . . . . . . . . 137
5.37 Bias of the NMOS cascodes . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.38 Bandgap’s BJT’s with dummies . . . . . . . . . . . . . . . . . . . . . . . . 138
5.39 Startup circuit for circuit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
5.40 Circuit 1: Output voltage versus Temperature . . . . . . . . . . . . . . . . 140
5.41 Circuit 1: Supply Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . 141
5.42 Eﬀect of ﬁlter on stability . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
5.43 Gain and Phase Response for Circuit 1 . . . . . . . . . . . . . . . . . . . . 144
5.44 Circuit 1: Noise PSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
5.45 Illustrating chopping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
5.46 Chopped noise spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
5.47 MonteCarlo Simulation results for Oﬀset . . . . . . . . . . . . . . . . . . . 148
5.48 Output bandgap with chopping (unﬁltered) . . . . . . . . . . . . . . . . . 149
5.49 Eﬀect of chopping on ΣΔ Output . . . . . . . . . . . . . . . . . . . . . . . 150
5.50 Chopping Conﬁgurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
5.51 Postchopping ﬁltering options . . . . . . . . . . . . . . . . . . . . . . . . . 152
5.52 Noise on the bandgap (after ﬁlter) . . . . . . . . . . . . . . . . . . . . . . . 153
5.53 Digital trimming of RCT (3bit example) . . . . . . . . . . . . . . . . . . . 155
5.54 Trimming by changing PMOS mirror ratio . . . . . . . . . . . . . . . . . . 155
5.55 Worst Corner DC performance . . . . . . . . . . . . . . . . . . . . . . . . . 157
5.56 Schematic for circuit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
5.57 Headroom limitation for direct npn connection . . . . . . . . . . . . . . . . 160
5.58 Output Noise versus Opamp tail current . . . . . . . . . . . . . . . . . . . 162
5.59 Output bandgap voltage Vbg2 versus temperature . . . . . . . . . . . . . . . 164
5.60 PSR of Vbg2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
5.61 Noise PSD of Vbg2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
5.62 Higher Order compensated bandgap of [Meijer 82] . . . . . . . . . . . . . . 168
5.63 Current mode approach for ZeroTC . . . . . . . . . . . . . . . . . . . . . 170
xviii
5.64 Conceptual generation of Ivbe lin . . . . . . . . . . . . . . . . . . . . . . . . 171
5.65 Generating Ivbem0 and Ivbem1 . . . . . . . . . . . . . . . . . . . . . . . . . . 172
5.66 Generating Vbem0 and Vbem1 . . . . . . . . . . . . . . . . . . . . . . . . . . 173
5.67 Generating the PTAT compensation current IP T . . . . . . . . . . . . . . . 173
5.68 Schematic for circuit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
5.69 Schematic of PTAT compensation circuit used in circuit 3 . . . . . . . . . 176
5.70 Schematic for Opamp used in circuit 3 . . . . . . . . . . . . . . . . . . . . 177
5.71 DC performance for higherorder compensation versus temperature . . . . 178
5.72 Higherorder and ﬁrstorder compensation for smallest resistance corner . . 179
5.73 Higherorder and ﬁrstorder compensation for largest resistance corner . . . 180
5.74 PSR of Circuit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
5.75 Noise PSD of circuit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
xix
List of Symbols
xx
Vbe Bipolar transistor baseemitter voltage, in Volts
Vgs GateSource Voltage of a FET, in Volts
Vp PinchOﬀ Voltage of a JFET, in Volts
Idss JFET drain current at zero bias, in Volts
Silicon Dielectric Constant, in F/m
ND Donor Concentration, in m−3
NA Acceptor Concentration, in m−3
VT Thermal Voltage, in Volts
Ic BJT Collector Current, in Amperes
Is BJT Saturation Current, in Amperes
Vg0 BandGap voltage of Silicon at 0K, in Volts
Tr Reference Temperature, in Kelvins
gm Transconductance, in Siemens
β BJT CommonEmitter Current Gain
α BJT Commonbase Current Gain
W MOSFET transistor Width, in meters
L MOSFET transistor Length, in meters
Cox Oxide Capacitance per unit area, in F/m2
Vth Threshold Voltage, in Volts
Vef f Overdrive Voltage, in Volts
Cc Compensation Capacitance, in Farads
CL Load Capacitance, in Farads
fchop Chopping Frequency, in Hz
fcorner Noise Corner Frequency, in Hz
fBW Bandwidth, in Hz
Vpp PeaktoPeak Voltage, in Volts
Vrms RootMeanSquare Voltage, in Volts
xxi
List of Abbreviations
xxii
CTAT Complementary To Absolute Temperature
BJT Bipolar Junction Transistor
PSR Power Supply Rejection
CDS Correlated Double Sampling
DEM Dynamic Element Matching
LG Loop Gain
LDO Low DropOut regulator
SiGe SiliconGermanium
xxiii
Chapter 1
Introduction
1.1 Motivation
Inertial sensors, which comprise gyroscopes and accelerometers, are used to measure either
the rotation rate or the acceleration of a body with respect to an inertial frame of reference
[Saukoski 08].
Traditionally, inertial sensors are not MEMSbased. These traditional inertial sensors
have extremely high sensitivity. However, they are very expensive, bulky and power con
suming, restriciting their use to military and aerospace applications where size and power
consumption are secondary concerns [Jiang 03].
Micromachined (MEMS) inertial sensors have signiﬁcantly potential cost, size and
weight advantages over traditional sensors. This has resulted in a proliferation of the
applications in which such sensors can be used [Barbour 01]. MEMS accelerometers have
their automotive applications, where they are used to activate safety systems, including air
bags, to implement vehicle stability systems and electronic suspension. They are also used
in biomedical applications for activity monitoring; in numerous consumer applications,
such as active stabilization of picture in camcorders, headmounted displays and virtual
reality, threedimensional mouse, and sport equipment; in industrial applications such as
robotics and machine and vibration monitoring; in many other applications, such as track
ing and monitoring mechanical shock and vibration during transportation and handling of
a variety of equipment and goods; and in several military applications, including impact
1
2 Chapter 1. Introduction
and void detection and saﬁng and arming in missiles and other ordnance. Highsensitivity
accelerometers are crucial components in selfcontained navigation and guidance systems,
seismometry for oil exploration and earthquake prediction, and microgravity measurements
and platform stabilization in space. The impact of lowcost, small, highperformance, mi
cromachined accelerometers in these applications is not just limited to reducing overall size,
cost, and weight. It opens up new market opportunities such as personal navigators for
consumer applications, or it enhances the overall accuracy and performance of the systems
by making formation of large arrays of devices feasible [Yazdi 98].
Micromachined gyroscopes for measuring rate or angle of rotation have also attracted
a lot of attention during the past few years for several applications. They can be used
either as a lowcost miniature companion with micromachined accelerometers to provide
heading information for inertial navigation purposes or in other areas, including automotive
applications for ride stabilization and rollover detection; some consumer electronic applica
tions, such as videocamera stabilization, virtual reality, and inertial mouse for computers;
robotics applications; and a wide range of military applications. Conventional rotating
wheel as well as precision ﬁberoptic and ring laser gyroscopes are all too expensive and
too large for use in most emerging applications. Micromachining can shrink the sensor size
by orders of magnitude, reduce the fabrication cost signiﬁcantly, and allow the electronics
to be integrated on the same silicon chip [Yazdi 98].
In high performance inertial sensing systems, forcebalancing (also known as force
feedback) can be used to raise the linearity, bandwidth and dynamic range of the system.
ΣΔ modulation is particularly attractive for implementing forcefeedback because it is sim
ple, provides a direct digital output and can be easily implemented in high density CMOS
technologies [Lemkin 97]. Achieving high performance in a feedback system translates to
achieving high performance in the system’s feedback path. Hence, this thesis discusses
the nonidealities in the feedback path of ΣΔ forcefeedback systems. The reference volt
age circuitry, which is a crucial component of the feedback electronics, is also designed to
achieve the high performance target.
1.2. Thesis Outline 3
4
2.1. MEMS Accelerometers 5
x(s) 1
= 2 (2.1)
a(s) s + s. mb + k
m
where x is the displacement of the proof mass from its rest position with respect to a
reference frame, a is the acceleration to be measured, b is the damping coeﬃcient, m is
the mass of the proof mass, k is the mechanical spring constant of the suspension system,
and s is the Laplace operator. This equation can be, more conveniently, expressed in the
form [Beeby 04]:
x(s) 1
= 2 (2.2)
a(s) s + s. ωQn + ωn2
√
k
where ωn = m
is the system’s natural resonant frequency, and Q = k.mb
is the
system’s quality factor. The mechanical system is, in essence, a second order ﬁlter for
6 Chapter 2. Overview on MEMS Inertial Sensors and Interface Circuits
the input acceleration. Since the force F = m.a, the above equations can also be used to
relate the proof mass’s displacement with the applied inertial force by simply scaling the
righthandside by m1 (i.e. Fx(s)
(s)
= m1 . x(s)
a(s)
).
The displacement x can, then, be sensed and measured to give an indication of the
acceleration. Many types of sensing mechanisms have been reported; the most common
of which is capacitive sensing [Yazdi 98]. Many commercial products are based on MEMS
accelerometers with capacitive sensing, such as the famous ADXL series by Analog devices
[Yazdi 98].
Figure 2.2 shows the structure of a MEMS accelerometer that measures inplane ac
celerations [Yazdi 98]. A proof mass made of Silicon is suspended by Silicon springs that
are tied to the Silicon substrate. Two sets of electrodes are present that form parallel
plate capacitors with the proof mass: one set of electrodes is used for sensing and the
second is used for actuation (for use in forcebalancing acceleration measurement). An in
plane acceleration would caused the proof mass to move relative to the electrodes, in eﬀect
changing the parallel plate capacitance between the proof mass and the sense electrodes.
2.2. MEMS Gyroscopes 7
× vr
FCoriolis = 2.m.Ω (2.3)
1
any change in velocity, in either magnitude or direction, implies an applied force
8 Chapter 2. Overview on MEMS Inertial Sensors and Interface Circuits
where m is the mass of the moving point. As can be seen from equation 2.3, the Coriolis
force is linearily proportional to the applied angular rate Ω and can, thus, be used as a
measure of its magnitude.
In ﬁgure 2.4, a lumped model of a simple gyroscope suitable for a micromachined
implementation is shown. The proof mass is excited to oscillate along the xaxis with a
constant amplitude and frequency. Rotation about the zaxis (the applied angular rate to
be measured) couples energy into an oscillation along the yaxis (through Coriolis eﬀect)
whose amplitude is proportional to the rotational velocity. The Coriolis force causes a
change in the position of the proof mass in a manner that can be described by equation
2.2. The displacement can, then, be sensed and measured to give an indication of the
Coriolis force and, hence, give indication of the angular rate. It is to be noted that MEMS
accelerometers and gyros have, basically, the same structure. The only diﬀerence is that
singleaxis gyros need two degreesoffreedom, whereas singleaxis accelerometers only need
one degree of freedom.
An example of a MEMS gyroscope is shown in [Clark 96] (ﬁgure 2.5). Comb drive
actuators are used to excite the structure to oscillate along one inplane axis (xaxis). Any
angular rate signal about the outofplane axis (zaxis) excites a secondary motion along
the other inplane axis (yaxis). This is, then, sensed by means of capacitive sensing (C/V)
2.3. Interface circuits 9
to give a voltage readout of the applied angular rate. Other implementations of the same
principle are also present in literature, as well as in industry [Beeby 04].
digital bangbang type feedback. The digital option allows a ΣΔ loop to be built around
the inertial sensor and, hence, the system’s output will be directly the desired digital read
out; no extra ADC would be needed. This type of feedback is widely used in capacitive
MEMS accelerometers and, more recently, in MEMS gyroscopes.
1. Smaller electronic interface and, hence, lower cost than closedloop counterparts
2. Open loop sensing is easier to design. The stability issues, that are inherently present
in any closed loop system, are of no concern in open loop systems.
3. Open loop sensing can operate at lower supply voltages (since no actuation is in
volved; actuation voltages are usually high) than closed loop.
On the other hand, the open loop sensing architecture suﬀers from a number of draw
backs:
1. It has a smaller dynamic range than the closed loop architecture. In open loop
architectures, the proof mass is left to move freely. This means that for large applied
forces, the proof mass gets closer to the ﬁxed structure. Eventually, the proof mass
might collide with the structure which limits the maximum allowable input force.
2. It has lower linearity than the closed loop counterpart. This can be, again, attributed
to the motion of the proof mass. At large displacements, nonlinearities in the spring
appear (the spring restoring force is no more a linear function of displacement) caus
ing a nonlinear forcetodisplacement relation.
12 Chapter 2. Overview on MEMS Inertial Sensors and Interface Circuits
3. It has smaller bandwidth than the closed loop counterparts. This is specially trou
blesome in vacuumpackaged MEMS components that have very high quality factors.
Such components are often needed to achieve low mechanical losses and, hence, higher
perfromance.
Nevertheless, open loop sensing remains valuable for lowcost, lowend applications
that require low to medium resolutions. For instance, the Analog Devices ADXL series
uses open loop sensing architectures [Beeby 04] and acheieve reasonable dynamic ranges.
F = αvf .V 2 (2.4)
For combdrives, the factor αvf is constant. For parallelplate electrostatic actuation,
however, αvf is a nonlinear function of the gap distance [Beeby 04]. Hence, the voltage
toforce conversion process is highly nonlinear imposing diﬃculties for feedback.
While Analog feedback is possible in MEMS inertial sensors, digital feedback is more
convenient and is gaining more interest in both the literature and the industry [Beeby 04].
Digital feedback places the inertial sensor in a ΣΔ feedback loop, with the inertial sensor
as the ﬁrst stage of the loop ﬁlter and the electrostatic actuator performing the DAC
2.3. Interface circuits 13
function [Petkov 05]. A block diagram of such a system is shown in ﬁgure 2.7. In this
block diagram, the only ﬁlter is the inertial sensor itself (recall from section 2.1.1 that
the mechanical sensor itself is in essence a second order ﬁlter). The input acceleration
(applied acceleration in case of accelerometer or Coriolis acceleration in case of a gyroscope)
causes the movement of the proof mass. This, in turn, causes a displacement that is
sensed by the C/V and converted into a voltage signal that is quantized by means of a
comaparator. Based on the comparator decision, the interface applies a feedback voltage
pulse to the sensor, generating electrostatic force, which attracts the proof mass in the
direction opposite its original deﬂection. The rate at which the comparator generates
decisions is much faster than the dynamics of the mechanical sensor, and therefore the
feedback pulse stream maintains the proof mass approximately neutral [Petkov 05]. The
digital output is an oversampled pulsedensity modulated representation of the signal and,
thus, needs electronic ﬁltering (decimation ﬁlter) to obtain the desired digital output.
The second order ΣΔ forcefeedback systems shown in ﬁgure 2.7 has a limited resolution
[Petkov 05]. For higher resolutions, a higher order ΣΔ modulator is needed [Petkov 05].
This can be done by incorporating additional electronic ﬁlters to the loop of ﬁgure 2.7.
14 Chapter 2. Overview on MEMS Inertial Sensors and Interface Circuits
Examples of such systems exist in [Petkov 05] [Wu 02] [Dong 05].
The major advantages of closed loop sensing are [Boser 96]:
• Improved accuracy as the sensing system becomes less sensitive to the nonidealities
in the forward path (that includes the sensor). The performance burden is laid on
the feedback path (i.e. feedback DAC of the ΣΔ system)instead.
• Improved dynamic range due to much smaller displacement of the proof mass
• Improved linearity since the limited motion of the proof mass prevents the springs
from exhibiting nonlinear behavior
2.4 Conclusion
In this chapter, a brief overview on MEMS inertial sensors and their interfaces was pre
sented. It is shown that ΣΔ forcefeedback systems are ideally suited for highperformance
sensors that require high dynamic ranges, better linearity, larger bandwidths and smaller
sensitivity to the mechanical sensor nonidealities. With ΣΔ forcefeedback, the high per
formance burden is laid on the feedback DAC. Hence, the next chapter is dedicated to the
discussion of the nonidealities in the feedback of ΣΔ forcefeedback systems.
Chapter 3
Feedback Nonidealities in ΣΔ
ForceFeedback Systems
In this chapter, the nonidealities in the feedback path of ΣΔ forcefeedback systems are
discussed. A ΣΔ MEMS acceleration sensing system is used for the discussion. First,
the acceleration sensing system is brieﬂy introduced. This is followed by a discussion of
the nonidealities of forcefeedback systems, with application to the acceleration sensing
system. Based on this discussion, the DAC specs are deﬁned for the accelerometer system
to achieve a maximum SNR of 110dB (corresponding to an ENOB of 18). While the
discussions are performed on the accelerometer system, they remain valid for any MEMS
based inertial ΣΔ forcefeedback system.
15
16 Chapter 3. Feedback Nonidealities in ΣΔ ForceFeedback Systems
bit (twolevel) feedback is used instead. Using twolevel feedback simpliﬁes the feedback
DAC which boils down to a voltage reference and a set of switches. Depending on the
reference voltage technology used, a multiplying Opamp might be needed following the
voltage reference circuit to generate the desired reference voltage Vref .
The eﬀect of rise and fall time asymmetry on the performance of the system is tested
using Eldo R
. Figure 3.3 shows the system’s output spectrum for diﬀerent values of rise
fall time diﬀerence (ΔTrf ). The 3rd order system with fs = 1.6834MHz is used in this
simulation. The FFT conditions are: fs = 1.6834MHz, Nf f t = 219 , window=Hann.
It can be seen from ﬁgure 3.3 that the risefall time mismatch adds white noise as
expected. Besides, it adds a DC oﬀset to the output stream. For a random bit stream,
the number of rising and falling edges will be equal. Having a mismatch between rise
and fall times will thus cause a residual oﬀset. The Signal to Noise ratio versus ΔTrf is
shown in Figure 3.4 (excluding the eﬀect of the DC oﬀset). To achieve a SNR of 120dB, a
ΔTrf less than 20ps is required. This is a stringent requirement. This problem is usually
solved by using fullydiﬀerential DACs or using RZ pulses instead of NRZ ones [Cherry 00]
[Schreier 05]. RZ pulses do not suﬀer from the asymmetry of rise and fall times because
each pulse has a rising and a falling edge. Hence, the total area of the pulsestream is not
patterndependent. This is illustrated in ﬁgure 3.2(b)
3.3. Nonidealities in ΣΔ ForceFeedback systems 19
Jitter in continuous time ΣΔ modulators causes errors in two points as shown in ﬁgure
3.5:
1. At the sampling point (before the quantizer). The time error Δt is converted into
a corresponding voltage error as shown in ﬁgure 3.6 . This error, however, is noise
shaped in the same manner as the quantization noise and thus has a limited eﬀect
on the modulator’s noise [Cherry 00] [Ortmanns 06]
3.3. Nonidealities in ΣΔ ForceFeedback systems 21
2. At the feedback DAC. Since the loop is a continuous time ΣΔ loop, the exact pulse
shape is important. Jitter will cause the area of the feed back pulses to change
randomly, eﬀectively adding random noise to the feedback pulses. This noise is not
noiseshaped and actually sees the same transfer function as the input signal as
shown in ﬁgure 3.5. This makes the DAC feedback jitter a major and critical noise
source in high performance / high speed continuous time ΣΔ modulators. The DAC
jitter has a much less pronounced eﬀect in Discretetime ΣΔ modulators. This is
because in discrete time modulators, only the value of the sample  and not its area
 is important. Since the jitter hits the pulse at the tail of the exponential step
characteristics, it has a limited eﬀect [Cherry 00] [Ortmanns 06] (refer to ﬁgure 3.7,
dotted lines represent the jittered clock)
The above statements are true for pulsewidth jitter (i.e. jitter that results in random
variations in the width of feedback pulse). It was shown in [Oliaei 98] that pulsedelay jitter
has a minor eﬀect on continuous time ΣΔ modulators. This can be intuitively explained
by the fact that pulsedelay jitter will have no impact on the area of the DAC pulse and
hence no net noise is added.
In the presence of a timing jitter tj , the total area of the feedback pulse (the integrated
voltage over oneperiod) is:
βTs +tj
I= Vdac .dt = Vdac ((β − α) Ts + tj ) (3.1)
αTs
The error in the integrated value (diﬀerence between the integrated value with jitter
and without jitter) is thus:
∞ 2
1 −t2
Mean = μj = Error ∗ √ e 2σt dt = zero (3.3)
2π
−∞
Where σt is the rms jitter in seconds. Hence, the variance of the integration error is:
∞ 2
1 −t2
σe2 = (Error − μj )2 ∗ √ e 2σt dt = Vdac
2
∗ σt2 (3.4)
2π
−∞
Hence, the voltage noise power due to jitter will be given by:
σt2
Ej2 = Vdac
2
∗ (3.5)
Ts2
This noise is spread over the f2s band. Only a fraction of this noise will aﬀect the
inband region. Hence, the inband noise power (IBN) can be given by:
Ej2 ∗ A 2 σ2 A
IBN = = Vdac ∗ t2 ∗ (3.6)
OSR Ts OSR
Where:
fs
OSR is Over Samplig Ratio = 2∗BW
A is Activity Factor ( Number of transitions per clock cycle ); A = 2 for RZ DACs
while A = 0.7 for NRZ DACs [Cherry 00] [Ortmanns 06]
24 Chapter 3. Feedback Nonidealities in ΣΔ ForceFeedback Systems
Hence, the Signal to Jitter Noise Ratio (SJNR) can be written as:
⎛ ⎞
Vin2
SJNR = 10 ∗ Log ⎝ σ2
⎠ (3.7)
2
2∗ Vdac ∗ Tt2 ∗ A
OSR
s
The following notes can be made on the above equation (equation 3.7):
• The SJNR improves by 20 dB/decade of the rms Jitter. This means that if rms jitter
(σt ) decreases 10 times, SJNR improves by 20 dB
• Since OSR = fs
2.BW
, equation 3.7 can be rewritten as:
Vin2
SJNR = 10 ∗ Log 2
(3.8)
2 ∗ Vdac ∗ σt2 ∗ fs .2.BW
From this equation, it can be observed that SJNR would degrade by 10 dB/decade
of fs for constant BW and similarly would degrade by 10 dB/decade of BW for
constant fs . This agrees with intuition; increasing BW means more noise power is
taken degrading SJNR and increasing fs means that jitter would be a larger fraction
of the clock period adding more noise
Jitter can easily become the dominant noisesource in high speed/performance continuous
time ΣΔ nodulators. This is often regarded as the major disadvantage of continuoustime
ΣΔ modulators [Cherry 00]. To decrease the sensitivity of continuoustime ΣΔ Modulators
to clock jitter, a number of methods can be used including: using multibit feedback DAC
[Ortmanns 06], using linear, quadratic or exponential DAC pulseshaping [Ortmanns 06],
using sinusoidal DAC pulse shaping [Ortmanns 06] [Luschas 02] ,using switchedC DAC
[van Veldhoven 03] and using FIR DAC [Oliaei 03] [Putter 04] . In the following section,
some of these methods are explained brieﬂy.
3.3.2.2.1 Using Multibit Feedback DAC Using a multibit Feedback DAC will
result in a multilevel Feedback waveform. In a multibit DAC, the diﬀerence between two
3.3. Nonidealities in ΣΔ ForceFeedback systems 25
adjacent pulses will always be very near 1 LSB. Thus jitter will cause a smaller change in
the area of the feedback waveform. Hence, the eﬀect of jitter will be greatly reduced. It is
to be noted, however, that this reduction will only happen for an NRZ feedback pulse. In
the case of a RZ waveform, the reduction will be much less pronounced since the pulse will
always return to zero (Figure 3.9). The improvement in clock jitter will almost be 6 dB
for each bit of the DAC (for NRZ pulses only) [Ortmanns 06]. The DAC used, however,
will be the limiting factor to the system’s linearity (it has to be as linear as the system).
(a) NRZ
(b) RZ
3.3.2.2.2 Using Linear DAC pulseshaping In this method, the DAC pulse takes
a linearly decaying shape as shown in ﬁgure 3.10.This will eﬀectively reduce the area error
caused by jitter since jitter will only cause a change in the area of the pulsetail; a region
26 Chapter 3. Feedback Nonidealities in ΣΔ ForceFeedback Systems
with a small amplitude. Following a similar procedure as that used to calculate the IBN
for a rectangular pulseshape, it can be shown that the IBN in the case of a linearly shaped
DAC pulse will be [Ortmanns 06]:
2
Vdac σt4 A
IBN = 2 ∗ 4
∗ (3.9)
2 (β − α) Ts OSR
The IBN is inversely proportional to the fourth power of the rms jitter σt , instead of
the second power as in the square pulseshape. Hence, for the same σt the linear pulse
shape will produce smaller noise. Similarly, the SJNR for the linear pulse shape will have
40dB/decade slope with σt . The use of a linear DAC pulse shape will come, however,
at the cost of a smaller allowable maximum input (since the area of the linear pulse is
half that of the rectangular pulse). To retain the same dynamic range, the linear pulse
amplitude has to be scaled. Moreover, all the ΣΔ coeﬃcients need to be recalculated for
the new pulseshape [Aboushady 02]
3.3.2.2.3 Using Quadratic DAC pulseshaping In this method, the DAC pulse
takes a quadratically decaying shape as shown in ﬁgure 3.11. The reduced jitter sensitivity
comes from the smaller amplitude of the decaying tail. This reduces jitter sensitivity even
more than the linearly decaying case. It can be shown that the IBN in this case will
be [Ortmanns 06]:
3.3. Nonidealities in ΣΔ ForceFeedback systems 27
2
5Vdac σt6 A
IBN = 4 ∗ 6
∗ (3.10)
3 (β − α) Ts OSR
Hence, The IBN is inversely proportional to the sixth power of the rms jitter σt , and the
SJNR has a 60dB/decade slope with σt . The quadratic pulse shape suﬀers from the same
problems of the linear pulse namely: reduced dynamic range and the need for recalculating
the loop coeﬃcients
It is to be noted that higher order pulseshaping will result in higher order reduction
in jitter sensitivity as can be seen from equations 3.9 and 3.10. Ultimately, exponential
pulse shaping can provide a jitterimmunity similar to that of discretetime systems [Ort
manns 06].
ﬁlter). Hence, the system will have the same sensitivity to jitter as a continuoustime ΣΔ
modulator.
The eﬀect of jitter on the acceleration sensing system can be analyzed as in [Ort
manns 06]. If a rectangular feedback pulse is assumed, the signaltojitter noise ratio
(SJNR) will be similar to equation 3.7. However, this expression needs to be modiﬁed to the
speciﬁc case of the acceleration sensing system. The signal of interest in the acceleration
sensing system is the force rather than the voltage. Therefore, the SJNR expression is a
force signal to force noise ratio rather than a voltage signal to voltage noise ratio. The
input force signal can be given as:
F = ms ∗ a (3.11)
Where:
ms is the mass of the MEMS accelerometer proof mass
a is the acceleration
The feedback voltage is converted in the accelerometer into a feedback force. The
relation between the feedback force and the feedback voltage can be given by:
Where:
αvf is the Voltage to Force conversion factor
Vdac is the Singleended DAC feedback voltage
Hence, the force signal to force jitter noise ratio for the accelerationsensing system is
given by: (basically equation 3.7 with voltage replaced by force)
⎛ ⎞
2
Fin /2
SJNRacc = 10 ∗ Log ⎝ ⎠ (3.13)
2 σ2
Ff eedback ∗ Tt2 ∗ A
OSR
s
To test the performance of the acceleration sensing system in presence of clock jitter, the
system’s model is built on Mentor Graphics’ DAIC R
environment using Eldo’s Macro
models [Men 07]. The discretetime part of the system is built using the spice function
”FNZ” [Men 07]. This function performs implicit sample and hold operation, so no sample
and hold block is needed. A snapshot of the system is shown in ﬁgure 3.13 (more details
on the model can be found in Appendix A). The RZ DAC is implemented by multiplying
the comparator output by a 50% dutycycle clock with jitter added to it as shown in ﬁgure
3.14. This clock is built using a Matlab code and read into the model using the ”.chrent”
Eldo command [Men 07]. The 3rd order system with fs = 1.683MHz is used in this section.
Simulations of the system in ﬁgure 3.13 were performed using Eldo (with fs = 1.683MHz,
Nf f t = 219 , window=Hann). The clock jitter is modeled as white noise with Gaussian dis
tribution. The simulation results for 25ps, 100ps and 1ns of rms jitter are shown in Figure
3.15. The achieved Signal to Jitter Noise Ratios are 103dB, 95dB, and 75dB respectively.
It can be seen that the SJNR decreases by 20 dB/decade as predicted by equation 3.14.
Figure 3.16 shows the SJNR versus the rms jitter . The simulated results are veriﬁed
against the derived equation (equation 3.14 ). The deviation from the equation increases
at lower jitter values because jitter noise becomes a less dominant noise contributor.
30 Chapter 3. Feedback Nonidealities in ΣΔ ForceFeedback Systems
The simulation results suggest that the jitter noise might be the dominant noise source
in the sensing system. To achieve the target SNR of 110dB, we choose to set the SJNR
to 120dB (to give margin for other noise sources). Using equation 3.13, the required value
for the rms jitter is σt ≈ 3.5ps which is a tough requirement.
In section 3.3.2.2, a number of methods to decrease the eﬀect of jitter were discussed
for electrical ΣΔ modulators. In the following sections, the use of these methods in the
acceleration sensing system is discussed
3.3.2.4.1 Using Multibit Feedback DAC This method decreases the jitterinduced
noise by 6 dB/bit in electrical ΣΔ modulators (with NRZ feedback). However, it imposes
tough requirements on the DAC since the multibit DAC has to be as linear as the whole
system. Achieving a high linearity in a multibit DAC is hard (as opposed to a singlebit
DAC which is inherently linear). The problem is even worse in the case of the sensing
system due to the nonlinear relation between the force and the voltage (equation 3.12 ).
Using a multibit DAC in this case would introduce a severe nonlinearity into the system.
Thus, this method is not suitable for the acceleration sensing system.
3.3.2.4.2 Using Linear DAC pulseshaping This method can be used to improve
the jitter performance signiﬁcantly. Due to the quadratic relation between force and volt
age, a linearly shaped DAC pulse would give the same performance improvement as a
quadratic shaped DAC pulse in an electrical ΣΔ modulator. For a pulse of the shape shown
in ﬁgure 3.10, the expected SJNR expression would be: (adopted from [Ortmanns 06] and
replacing voltage with force)
⎛
⎞
(ms ∗ a)2
SJNRacc = 10 ∗ Log ⎝ 2
σt6
⎠ (3.15)
5 2 2
3(β−α)4
∗ (2 ∗ αvf ∗ Vdac ) ∗ Ts6
∗ A
OSR
As can be seen from equation 3.15, using a linear DAC pulse shape improves the jitter
immunity signiﬁcantly over the square pulse shape. The SJNR vs σt slope is 60 dB/decade
as opposed to 20 dB/decade for the square pulse shape. However, in order to preserve
the system’s dynamic range, the shaped pulse has to be scaled so that the area under the
shaped force pulse is the same as that of the rectangular case. This can be expressed as:
3.3. Nonidealities in ΣΔ ForceFeedback systems 33
√
Ff eedback dt = αvf Vsq2 Tsq ⇒ Vdac = Vsq ∗ 3 (3.16)
Where:
Vdac is the DAC peak voltage in the case of linearly shaped pulse
Vsq is the DAC voltage for rectangular pulse
This means that using this shaping technique comes at the expense of higher voltage
levels, which might not be available (depending on the used technology). Furthermore, the
actual implementation of this shape will be harder than that of a rectangular pulse.
3.3.2.4.3 Using Quadratic DAC pulseshaping Although this option will cause a
large relaxation in the jitter requirements, it will be much harder to implement than the
linearly shaped pulse. Besides, the DAC peak voltage will need to be signiﬁcantly increased
to achieve the same dynamic range.
In the previous sections, the eﬀect of white jitter noise on the performance of ΣΔ force
feedback systems was discussed. Since the inertial sensing systems are usually narrowband
(few tens of Hertz to few hundred Hertz), the accumulated (closein) jitter can be of great
importance. Hence, this section discusses its eﬀect. For this purpose, the 4th order system
with fs = 409.6kHz is used. This is the system that will be used hereafter throughout the
thesis.
To study the eﬀect of closein jitter, a deterministic jitter signal in the form of a sine
wave with a low frequency (≈ 10 Hz) and amplitude equal to the peak jitter value is
added to the feedback pulse. The edges of the pulse were modulated by the sine wave with
amplitude of 100ps. The output spectrum is the same as the ideal spectrum (with no clock
jitter). This can be intuitively explained as follows: since the modulating sine wave has a
very low frequency compared to the clock (clock frequency = 409.6 KHz, jitter frequency
= 10 Hz), the amount of time Δt by which each edge is jittered will almost be equal (i.e.
if the 1st edge moves by Δt1 and the 2nd edge moves by Δt2 , then Δt1 ≈ Δt2 ). This in
turn means that the pulse width remains almost constant (no pulsewidth jitter). The only
34 Chapter 3. Feedback Nonidealities in ΣΔ ForceFeedback Systems
pronounced eﬀect is a shift in the pulse position (pulse position jitter). This was shown
in [Oliaei 98] to have negligible eﬀect on signaltonoise ratio.
Based on this result, more simulations are made to evaluate the performance of the
system in the presence of closein (low frequency) jitter noise. These are shown in the next
section. For all simulations in this section fs = 409.6kHz, Nf f t = 219 , and window=Hann.
3.3.2.5.1 Eﬀect of jitter for diﬀerent jitter frequencies The aim of this simulation
is to explore how low ”lowfrequency” jitter is. To do so, a deterministic jitter with
sinusoidal shape is used to modulate the RZ pulse edges. The frequency of the sinusoidal
jitter is swept from 10 Hz to 100kHz (10Hz, 100Hz, 1kHz, 10kHz, 100kHz). The amplitude
of the jitter signal is kept constant at 100ps. The simulation results are shown in ﬁgure
3.17. It can be seen that jitter with frequencies up to 10kHz has negligible eﬀect on the
output spectrum. At 100kHz and beyond, the SJNR is degraded to 86dB (as opposed to
the ideal 139dB). This is slightly worse than the SJNR obtained using a 100ps rms white
Gaussian jitter.
Figure 3.17: Spectra for Sinusoidal 100ps rms jitter with diﬀerent frequencies
3.3. Nonidealities in ΣΔ ForceFeedback systems 35
3.3.2.5.2 Maximum allowable closein jitter The aim of this simulation is to de
termine the maximum amount of allowable closein jitter that would not degrade the
signaltonoise ratio. For this purpose, a sinusoidal jitter with 10Hz frequency is used to
modulate the RZ pulses and its amplitude is swept.The simulation result at a jitter am
plitude of 100ns is shown in ﬁgure 3.18. The SJNR is 96dB. Since the SJNR improves by
20dB for each decade of decrease in jitter, the maximum tolerable closein jitter is 5ns rms
(for a SJNR of 120dB). This is three order of magnitude higher than the white jitter value,
indicating that closein jitter has a negligible eﬀect on the system performance.
3.3.2.5.3 Eﬀect of clock with both white and accumulated jitter The aim of
this simulation is to evaluate the eﬀect of a realistic clock source that would have both a
white jitter noise ﬂoor and a closein jitter noise skirt. For this purpose, a clock is built
that has a white jitter noise ﬂoor corresponding to white Gaussian noise wit 10ps rms value
and a closein noise skirt formed by the cumulative summation (running integration) of
the white jitter samples. The spectrum of the clock is shown in ﬁgure 3.19
36 Chapter 3. Feedback Nonidealities in ΣΔ ForceFeedback Systems
Figure 3.19: Realistic clock with white noise ﬂoor and closein noise skirt
The results are shown in ﬁgure 3.20. It can be seen that the closein jitter has no
noticeable eﬀect on the output spectrum. The noise performance is the same as that of
a clock subject to only white jitter (the clock’s white noise ﬂoor). Simulations with 10
times higher noise ﬂoor and closein noise show the same eﬀect; only the white noise ﬂoor
determines the system SJNR performance.
Based on the previous discussion, the following conclusions and decisions can be made
regarding the system’s clock and its jitter:
• White Jitter degrades the output SNR. The relation between rms jitter value and
output SignatoJitterNoiseRatio (SJNR) can be given by equation 3.14. Based
3.3. Nonidealities in ΣΔ ForceFeedback systems 37
Figure 3.20: Output spectra for a realistic clock and a clock with only white jitter
on this equation, the required rms jitter (σt ) for a 120dB SJNR is σt ≈ 3.5ps for
fs = 1.6834MHz and σt ≈ 7ps for fs = 409.6kHz
38 Chapter 3. Feedback Nonidealities in ΣΔ ForceFeedback Systems
As shown in ﬁgure 3.1, the feedback force Ff b in a ΣΔ force feedback system is formed
by converting the feedback voltage into force through the voltagetoforce conversion block
(the voltagetoforce conversion is not an actual ”block” but, rather, a physical process).
2
The ΣΔ’s output is a stream of 1’s and 0’s. If the output is ’1’, a positive force (αvf .Vref ) is
applied in the feedback by applying a voltage equal to +Vref on the positiveforce actuator.
3.3. Nonidealities in ΣΔ ForceFeedback systems 39
2
If the output is ’0’, a negative force (−αvf .Vref ) is applied in the feedback by applying a
voltage equal to +Vref on the negativeforce actuator. This can be regarded as having
an output bitstream of ”1”s and ”1”s that is multiplied by the scaled squared reference
2
voltage (αvf .Vref ). The ”1”  ”1” bitstream is a pulse density modulated representation
of the output (it is equal to the input signal + quantization noise). Thus, in eﬀect, the
feedback force is the multiplication of the output signal and the scaled squared reference
2
voltage (αvf .Vref ) as shown in ﬁgure 3.21
The eﬀect of reference noise on SNR can be evaluated by ﬁnding the SNR in the feedback
force Ff b . This stems from the fact that the feedback force is applied to the input of
the system, in a similar manner to the input force. Thus, if the system’s nonlinearity is
ignored, the SNR at the output due to reference noise will be equal to the SNR of the
feedback signal Ff b .
As discussed in the previous section, the feedback force Ff b is the multiplication of the
”1””1” representation of the output bit stream (b (t)) and the scaled squared reference
2
voltage (αvf .Vref ). It is to be noted, however, that Vref is the summation of the ideal
reference voltage Vref ideal and the reference voltage noise. Hence, Ff b can be expressed as:
2
Ff b = b (t) . αvf .Vref (3.17)
And Vref can be expressed as:
2
Where the term vnref (t) has been ignored. This can further be expanded into:
2 2
Ff b = αvf . s (t) .Vref ideal + 2.Vref ideal .s (t) .vnref (t) + qn (t) .Vref + 2.Vref
(t) .vnref (t)
ideal ideal .qn
(3.21)
The expression of Ff b in equation 3.21 contains one signal component and three noise
2
components. The signal component (Ff b sig ) is the term αvf .s (t) .Vref ideal . The three
2
noise components are: a quantization noise component (Ff b qn ) equal to αvf .qn (t) .Vref ideal ,
a reference noise component (Ff b ref n ) equal to αvf .2.Vref ideal .s (t) .vnref (t) and a noise
component that is a multiplication of reference noise and quantization noise (Ff b qnref )
and is equal to αvf .2.Vref ideal .qn (t) .vnref (t). Hence, the forcesignal to forcenoise ratio in
the feedback will be given by:
Ff2b sig
SNRf b = 10. log (3.22)
Ff2b qn + Ff2b ref n + Ff2b qnref
Where the various noise components are assumed uncorrelated and hence are added in
an rms sense. Depending on which noise term is dominant, the expression of SNRf b will
change. The diﬀerent cases will be discussed in the following sections.
3.3.3.2.1 Ff b ref n is dominant If the voltage reference noise is the dominant noise
source, then SNRf b can be expressed as:
Ff2b sig
SNRf b = 10. log Ff2b ref n
s(t)2 .Vref
4
ideal
= 10. log 2 (3.23)
.vnref (t)
2 2
4.Vref ideal .s(t)
2
Vref ideal
= 10. log 2
4.vnref (t)
3.3. Nonidealities in ΣΔ ForceFeedback systems 41
This is an interesting result. The SNR due to reference voltage noise is essentially
independent on the signal level. This can be explianed by the multiplicative nature of the
reference voltage noise. The equivelant noise at the feedback is the multiplication of the
reference voltage noise and the signal. Hence, noise scales with the signal making the SNR
signalindependent. Note that this result was obtained assuming that the other two noise
sources are nondominant.
To verify this conclusion, a simulation is made on the accelerometersensing system
using Matlab Simulink R
. By design, the inband quantization noise term Ff b qn is non
dominant (the ideal SNR is 139 dB). To make sure that the Ff b qnref noise component
(resulting from a multiplication of reference noise and quantization noise) is nondominant,
noise is added as a determinstic sine wave with low frequency (≈ 10Hz). This ensures
that multiplication of reference noise and quantization noise will not result in outofband
quantization noise folding back inband (as will be shown in next section).
Figure 3.22: Spectra for ideal system and system with dominant reference noise
With a sinusoidal noise voltage (vnoise . sin(ωn .t)), the dominant noise component Ff b ref n
42 Chapter 3. Feedback Nonidealities in ΣΔ ForceFeedback Systems
.10−6 . The
V
Based on this result, achieving a 120 dB SNR would require vnoise = ref√ideal
2
simulation was performed with Vref ideal = 5V and vnoise = √52 μV ≈ 3.5μV . The result is
shown in ﬁgure 3.22. The SNR is 120 dB as expected. The sinusoidal noise appears as an
AM signal around the sinusoidal input signal.
3.3.3.2.2 Ff b qnref is dominant If the term Ff b qnref is the dominant noise source,
then SNRf b can be expressed as:
Ff2b
sig
SNRf b = 10. log Ff2b qnref
(3.27)
2
Vref ideal
= 10. log 2
4.vnref (t).qn (t)
The Ff b qnref contains the multiplication of the quantization noise and the reference
voltage noise. This term can become a problem if the reference noise is wideband. In
such a case, the high frequency reference noise will be multiplied by the large outofband
quantization noise of the ΣΔ causing folding of the outofband quantization noise into the
inband region. This is illustrated in ﬁgure 3.23.
3.3. Nonidealities in ΣΔ ForceFeedback systems 43
Figure 3.24: Spectra for ideal system and system with wideband ref. noise
44 Chapter 3. Feedback Nonidealities in ΣΔ ForceFeedback Systems
To verify this conclusion, white noise is added to Vref ideal instead of the sinusoidal noise
added in the previous section. The total integrated inband noise is chosen to be equal
to the previous section for the sake of comparison. It is found that the SNR degraded by
almost 20 dB, acheiving an SNR of 101 dB as opposed to the 120 dB of the narrowband
reference noise case. The simulation result is shown in ﬁgure 3.24.
3.3.3.2.3 Ff b qn is dominant The SNRf b in presence of the three noise sources can
be expanded into the form:
2
s (t) .V 2
ref ideal
SNRf b = 10. log 2
2.Vref ideal .s (t) .vnref (t)2 + qn (t) .Vref
2
ideal
+ 2.Vref ideal .qn (t) .vnref (t)2
(3.28)
3.3. Nonidealities in ΣΔ ForceFeedback systems 45
2
For the quantization noise term Ff b qn = qn (t) .Vref ideal to be dominant, the other noise
terms have to be nondominant. This can be done by: decreasing the input signal (which
would decrease the noise added by any term multiplied by s (t)), and making the reference
noise bandlimited (to decrease the eﬀect of outofband quantization noise folding). By
doing so, the SNR would be dominated by the quantization noise term Ff b qn and will,
thus, be given by:
s (t)2
SNRf b = 10. log (3.29)
qn (t)2
Equation 3.29 shows that SNR with quantization noise as the dominant source is signal
dependent. This means that for small input signals (i.e. input signals which make quanti
zation noise dominant), the SNR will depend on the signal level. This is the opposite case
for large input signals where the reference noise will be dominant and hence, SNR will be
signalindependent. The important conclusion to be drawn from this discussion is that the
reference noise doesn’t limit the sensitivity of the system (i.e. doesn’t limit the minimum
detectable signal). This is due to the multiplicative nature of the reference noise which
makes this noise decrease as the input signal decreases.
To verify these conclusions, a simulation is made in which the reference noise is a low
frequency sinusoidal signal (the same as that used in section 3.3.3.2.1). Three input signals
are used: an acceleration signal of magnitude 3g, a signal of magnitude 0.3g and a signal
of magnitude 0.03g. With a factor of 10 between each two successive signals, the expected
diﬀerence in SNR between successive signals is 20 dB. The simulation result is shown in
ﬁgure 3.25
The SNR’s for the 3g, the 0.3g and the 0.03g signals are 120dB, 117dB and 99dB
respectively. Although the 3g and the 0.3g signals are 20dB apart, the output SNR due to
both signals only diﬀers by 3dB. This supports the claim of a signalindependent SNR for
large input signals. The 0.03g signal, on the other hand, is separated from the 0.3g signal
by 20 dB. The SNR diﬀerence between the two is close to 20 dB. This supports the claim
for a signaldependent SNR for small input signals.
46 Chapter 3. Feedback Nonidealities in ΣΔ ForceFeedback Systems
• In section 3.3.2.4, the rms white jitter for an SNR of 120dB was calculated to be
equal 3.5ps. This, however, was based on a clock frequency of 1.6834MHz. For the
409.6KHz clock, this value can be recalculated using equation 3.13 to be equal to
7ps. The closein jitter has negligible eﬀect and is not included in the noise budget
• The total integrated noise in the band 1mHz100Hz for an SNR of 120dB can be
calculated using equation 3.26 to be equal to 3.5μV (based on an actuation volt
age value of 5V). Alternatively, using the same equation the ratio Vrefvnideal can be
calcualted to be equal to 0.7μ (to achieve the 120dB SNR target)
• To avoid the problems arising from the mismatch between the rise and fall time of
the feedback pulse, RZ feedback is used with 50% duty cycle
With the above specs, it is clear that the voltage reference design is challenging. A
very low noise spec is required in the lowfrequency range which is plagued by the 1/f
noise. Hence, the rest of this thesis focuses on the design and implementation of the
voltage reference for this system. Chapter 4 presents an overview of the reference voltage
technologies. This is followed by chapter 5 which presents the design and implementation
of the reference voltage circuitry.
Chapter 4
This chapter presents an overview on the various technologies used to generate voltage
references. The common deﬁnitions of the voltage reference specs are ﬁrst presented. This
is followed by overview on four reference generation technologies, namely: Zenerbased
References, XFET R
references, ﬂoatinggate references and Bandgap references. Both
industrial implementations and literature implementations are presented.
4.1 Deﬁnitions
Various parameters are used to characterize voltage references. In the following sections,
three basic parameters are deﬁned.
47
48 Chapter 4. Reference Voltage Generation: An Overview
initial accuracy can therefore only be speciﬁed after statistical analysis of a large sample
size.
A more formal deﬁnition of Initial Accuracy is the ratio of the 3σ variation (3.σvref )
of a reference, over a large number of samples, to the mean value (μvref ), and is given
by [Gupta 07]:
3σvref
InitialAccuracy = ± (4.1)
μvref
Vmax − Vmin
TC = ∗106 ppm/◦ C (4.2)
Vnom (Tmax − Tmin )
Two types of Zenerdiodes are available: surfaceZeners and buriedZeners. The pn
junction that constitutes a surfacezener is a surface pn junction (i.e. formed by lateral
conncection of p and n type Silicon regions) as shown in ﬁgure 4.4(a) [AMI 05]. This makes
them susceptible to surface contamination making them noisy devices with unpredictable
drift. Surface Zeners are widely used in integrated circuits for ESDprotection, EPROMs
and as Zapdevices for trimming or memory applications [Lin 99]. Buried Zeners, on the
4.2. Reference Voltage Technologies 51
other hand, are formed by buried pn junctions i.e. pn junctions below the surface of the
substrate, formed by vertical stacking of p and n regions as shown in ﬁgure 4.4(b) [AMI 05].
The circuit shown in ﬁgure 4.5 is the core of the National Semiconductor LM199 Zener
based references. This reference is a shunttype reference (i.e. a twoterminal reference).
The reference voltage is the sum of a Zener voltage (Vz ) and a bipolar transistor’s base
emitter voltage Vbe to compensate for the PTAT behavior of Vz . Furthermore, the inte
grated circuit is equipped with a temperature stabilizer (i.e. heating circuit, not shown)
to minimize the temperature variations of the Zener. It achieves a longterm drift of
20ppm/1000hr and a maximum temperature drift of 1ppm/◦ C [Nat 05a].
The circuit shown in ﬁgure 4.6 is reported in [Laude 80]. It is a Zenerbased reference
that uses a baseemitter voltage for 1st order compensation of the PTAT Zener voltage
Vz . The circuit employs thermalfeedback to temperaturestabilize the Zenerdiode; the
4.2. Reference Voltage Technologies 53
Zener voltage Vz is compared with the internally generated reference voltage and the chip
temperature is adjusted accordingly (by controlling the current of a powerBJT). The
circuit achieves a very low temperature coeﬃcient of 0.3ppm/◦ C but at the cost of a hefty
power consumption (1W). The extrapolated longterm drift is 300ppm/1000hr.
Table 4.1 shows the important specs of some of the commercially available Zener based
references. It can be seen that they are capable of achieving low temperature coeﬃcients
and low longterm drift. The major drawback is their high power consumption (due to the
large bias current needed to reversebias the Zener diode), as well as their incompatibility
with modern CMOS processes; buried Zeners are found in only few proprietary technologies
and surfacezeners are noisy and have unpredictable drifts.
54 Chapter 4. Reference Voltage Generation: An Overview
I I
=W (4.5)
Idss L
βVp2
Where β is a process constant. By adjusting the current densities of J1 and J2 to be
equal (i.e. WI1 = WI2 ) the gatetosource voltage diﬀerence reduces to:
1/ 2/
L1 L2
ΔVgs = ΔVp (4.6)
The pinchoﬀ voltage of a JFET transistor can be given by:
a2 qND NA
Vp = 1+ − ψo (4.7)
2ε ND
Where:
a is half the channel width
ε is Silicon’s dielectric constant
ND is the donor concentration in the Nwell
NA is the channel’s acceptor concentration
kT NA ND
ψo is the gatechannel builtin potential = q ln n2i
Hence, ΔVp reduces to:
a2 qNd1 a2 qNd2
ΔVp = 2ε
1+ NA1
− 2ε
1 + NNA2 − Δψo
ND
D (4.8)
a2 qNd1 a2 qNd2
= 2ε
1+ NA1
ND
− 2ε
1 + NNA2
D
− kT
q
ln NA1
NA2
The ﬁrst two terms of the above equation (equation 4.8) have very weak temperature
dependence. The last term, however, is a linear CTAT term that can be controlled by
adjusting the implant ratio N A1
NA2
. Hence, one of the two matched JFETs J1 and J2 is given
an extra channel implant (and is, hence, dubbed XFET). Precision control of this extra
implant allows precision control of the corresponding CTAT slope.
Refering to ﬁgure 4.7(b), the output voltage of the XFET reference generation circuit
can be given by:
R1 + R2 + R3
Vo = ΔVp + IP T AT .R3 (4.9)
R1
56 Chapter 4. Reference Voltage Generation: An Overview
TM
Figure 4.7: The XFET reference
4.2. Reference Voltage Technologies 57
The PTAT current component is used to compensate for the CTAT characteristics of
the ΔVp term, allowing for lower variation across temperature. The advantage of the XFET
approach over the bandgap approach is that the CTAT slope in the XFET is lower and
more linear than the CTAT slope of the bipolar’s Vbe . This allows for smaller variation
across temperature as well as lower noise. Furthermore, the CTAT slope is obtained by
matched components (as opposed to the absolute Vbe used in bandgap) which allows for
better longterm drift. Table 4.2 summarizes the key specs of the commercially available
XFET reference ADR425 [Ana 02].
Floating gate technology is the technology used in ﬂash memories. A ﬂoating gate is a
polysilicon gate surrounded by SiO2 . Charge on the ﬂoating gate is stored permanently,
providing a longterm memory, because it is completely surrounded by a highquality in
sulator [Hasler 99]. To prevent charge leakage, no resistive path should exist between the
storing node and either supplies; the storage node is, thus, ﬂoating. Figure 4.8 shows a
ﬂoatinggate transistor [Guillermo 07]. There is no direct access to its gate but, rather, the
gate is accessed through the capacitors Ctun and Cin . Furthermore, the ﬂoating gate is usu
ally formed by a single continuous poly line to avoid any contacts or diﬀusions [Ahuja 05].
In normal operation, the input to the ﬂoating gate transistor is applied through the capac
itor Ctun . If the total charge on the ﬂoatinggate node is Q, and the total capacitance of
the ﬂoatinggate node is CT then the ﬂoating gate voltage Vf g in the presence of an input
voltage Vg can be given by [Guillermo 07]:
Cin Q
Vf g = Vg + (4.10)
CT CT
58 Chapter 4. Reference Voltage Generation: An Overview
The stored charge on the ﬂoating gate, in eﬀect, changes the threshold voltage of the
transistor Mf g . Hence, Mf g can be used as a programmable transistor as well as an
analog memory cell. Floating gates are used in a widerange of applications such as rail
torail input Opamps [RamrezAngulo 01], in analog trimming [Jackson 01], and in voltage
references [Guillermo 07] [Ozalevli 06] [Ahuja 05].
Two techniques are used for programming ﬂoating gates, namely: FowlerNordheim tunnel
ing [Guillermo 07] [Ahuja 05] and HotCarrier Injection (HCI) [Guillermo 07] [Ozalevli 06].
In [Guillermo 07] and [Ozalevli 06], FowlerNordheim tunneling is used for coarse pro
gramming and HCI is used for ﬁne tuning. In [Ahuja 05], however, only FowlerNordheim
tunneling is used for programming. Tunneling is performed through the tunneling capaci
tor Ctun , whereas HCI is performed through the ﬂoating gate transistor Mf g as shown in
ﬁgure 4.9
FowlerNordheim tunneling is the process by which electrons can tunnel through a
dielectric material. By applying a high positive voltage Vtun to the capacitor Ctun , electrons
tunnel from the ﬂoating gate to the voltage source Vtun eﬀectively increasing the ﬂoating
gate voltage Vf g [Guillermo 07] [Ahuja 05]. FowlerNordheim tunneling can also be used
to decrease the ﬂoatinggate voltage if a large negative voltage Vtun is used [Ahuja 05].
4.2. Reference Voltage Technologies 59
Hot carrier injection occurs in MOS transistors at high draintosource voltages whereby
energetic carriers cause generation of electronhole pairs by impact ionozation near the
drain. If the control potential Vg is positive, some of the energitic hot electrons can move
into the ﬂoating gate eﬀectively lowering its potential [Guillermo 07].
A number of voltage references based on ﬂoating gates are available in literature [Guillermo 07]
[Cook 04] [Ahuja 05]. These designs exploit the charge retention capabilities of ﬂoating
gates to implement a voltage reference. The designs in [Guillermo 07] represent volt
ages that are referenced to the supply and, hence, will not be discussed. The designs
in [Cook 04] and [Ahuja 05] are voltage reference referenced to ground and will be dis
cussed below.
The design in [Cook 04] is shown in ﬁgure 4.10. The block diagram, shown in ﬁgure
4.10(a), consists of a ﬂoatinggate followed by a buﬀer. The ﬂoating gate transistor will
constitute one of the inputpair transistors of the buﬀer. The buﬀer is composed of two
stages: a transconductance stage followed by a transimpedance stage. This arrangement
is used to reduce the parasitic coupling from the drain and source of the ﬂoating gate
transistor to the ﬂoating gate. The transimpedance stage is simply the input pair stage,
having a high impedance output. This is followed by a transimpedance stage (TIA) which
has a lowinput impedance. Hence, the drain of the ﬂoating gate transistor is kept at
lowimpedance, reducing the parasitic coupling from the drain to the ﬂoating gate, as can
be seen in ﬁgure 4.10(b). This circuit achieves a temperature coeﬃcient of 54.6ppm/◦ C.
60 Chapter 4. Reference Voltage Generation: An Overview
Since the ﬂoating gate charge remains constant after programming (versus time and tem
perature), the temperature coeﬃcient of this reference is dominated by the capacitor’s
temperature coeﬃcient [Ahuja 05].
The design in [Ahuja 05] uses a diﬀerential dual ﬂoating gate architecture (shown
in ﬁgure 4.11) to overcome the temperature coeﬃcient limitation of the previous design
in [Cook 04]. Two capacitors are used instead of a single capacitor: capacitor CS carries
a common mode voltage VCM and capacitor CF carries a voltage equal to VCMVREF
(where VREF is the desired reference voltage value). When CF is connected in closed loop
(with initial value VCMVREF), the output voltage will be equal to VREF. While the
use of two capacitors didn’t add an advantage in terms of the reference voltage value, it
represents a great improvement to the temperature variation problem. The capacitors CS
and CF are poly capacitors whose temperature coeﬃcients depend on the bias volatge. It
4.2. Reference Voltage Technologies 61
is shown in [Ahuja 05] that the temperature coeﬃcient of VREF (T CV REF ) is given by:
V CM
T CV REF ≈ −αcf + (αcf − αcs ) ∗ (4.11)
V REF
Where αcf and αcs are the temperature coeﬃcients of the poly capacitors CF and CS,
respectively.
Hence, for a given reference voltage VREF, there exists a certain value for VCM that
achieves the minimum possible T CV REF
Opamp will hold the same potential VCM as its positive terminal by virtue of feedback.
Due to symmetry, the same voltage VCM will be applied on the capacitor CS.
Bandgap references are, by far, the most popular references in integrated circuits. The
term ”Bandgap” referes to the energy band gap of Silicon, which is typically around 1.2V.
A conceptual implementation of a bandgap reference is shown in ﬁgure 4.13 [Holman 94].
The baseemitter voltage of a bipolar transistor is CTAT (Complementary To Absolute
Temperature), and its value at absolute Zero (i.e. Zero Kelvin) is almost equal to the
bandgap voltage of silicon Vg0 . By adding a scaled version of the thermal voltage VT = k.T
q
(which is PTAT i.e. Proportional To Absolute Temperature) to Vbe , a constant voltage can
be obtained that is independent on temperature (to a 1st order) and almost equal to Vg0 .
Vbe has a slope of 1.5mV  2mV /K, whereas VT has a slope of 86μV/K. Hence, the scaling
factor K (in ﬁgure 4.13) should be around 17 to 23 [Razavi 01].
Generating a PTAT voltage can be easily done, as shown conceptually in ﬁgure 4.14,
by taking the diﬀerence between the baseemitter voltages (ΔVbe ) of two matched bipolar
transistors operating at diﬀerent current densities [Razavi 01]. The collector current Ic of
a bipolar transistor is given by:
Vbe
Ic = Is .e VT (4.12)
Where Is is the transistor’s saturation current.
Hence, ΔVbe can be expressed as:
ΔVbe = VT ln I1
− VT ln I2
Is1
Is2
I1 Is2
= VT ln . (4.13)
I2 Is1
I1
= VT ln I2
.N
By adjusting the area ratio N and the current ratio II12 , the slope of the PTAT voltage
can be adjusted. The factor ln N. II12 is, however, not enough to cancel the CTAT slope
of Vbe (since ln is a weak function of its argument); an extra gain factor is needed.
4.2. Reference Voltage Technologies 65
Bandgap technology is widely used in both industry and literature. In this section, a brief
overview is given of literature and some of the industrial implementations.
A widely used bandgap architecture is the Brokaw bandgap, shown in ﬁgure 4.15
[Brokaw 74]. The negative feedback loop formed by the Opamp forces the two Opamp
terminals to have equal voltages. Hence, both BJT’s will carry equal currents (since the
two bias resistors are equal and have equal voltage drops across them). The voltage drop
across the resistor R2 is the PTAT voltage ΔVbe . Thus, the current in Q1 (I1 ) and the
current in Q2 (I2 ) will be equal and given by:
I1 = I2 = I = VT . ln(N) (4.14)
Where N is the ratio of the areas of Q1 and Q2 . The current in resistor R1 will be equal
to 2.I, and hence the output voltage can be given by:
R1
Vout = Vbe1 + 2. .VT . ln (N) (4.15)
R2
66 Chapter 4. Reference Voltage Generation: An Overview
The factor R
R2
1
is used to adjust the slope of the PTAT voltage to be equal to that
of the CTAT Vbe voltage. This architecture has the advantage of having a low output
impedance due to the shunt feedback at the output. This allows its output to be used
directly without the need for extra buﬀering. A variation of this architecture is used in the
commercial voltage reference AD580 [Pease 90], allowing the generation of output voltages
that are scaled versions of the bandgap voltage. The modiﬁed architecture is shown in
ﬁgure 4.16
Another popular industrial design is that of the LM4040 product [Nat 05b]. It is a
shunttype reference, as shown in ﬁgure 4.17. Shuntshunt feedback is used since the input
to the circuit is current (rather than voltage) and the circuit’s output is the reference
voltage. An elegant feature of this circuit is the way the ΔVbe is generated. An Opamp is
used whose input pair transistors are not equal in area, but rather have the area ratio of 1:N.
Both transistors are biased by equal currents. The inputs of these transistors are connected
across a resistor and, hence, the current in this resistor would be a PTAT current ΔVRbe .
The advantage of this approach is that the ΔVbe generation transistors are simultaneously
4.2. Reference Voltage Technologies 67
used as the input stage of an Opamp that provides extra gain for the feedback loop.
R3
Vout = Vbe1 + .VT . ln (10) (4.16)
R1
Hence the diﬀerential voltage Vr is equal to the bandgap voltage. Another diﬀerential
implementation of the bandgap reference is shown in ﬁgure 4.19 [Nicollini 91]. This cir
68 Chapter 4. Reference Voltage Generation: An Overview
Vf 1 dVf
+ I= (4.17)
R R3
If the diodes are implemented by diodeconnected pnp substrate transistors, then Vf 1 =
Vbe1 and dVf = ΔVbe = VT .ln(N). The output voltage is simply the current I multiplied
by the output resistance R4 . Hence, the generated reference voltage Vref can be given as:
V ref = I.R4 = R4 V f 1 + R
dV f
R
R3
R4 R
= R Vbe1 + R3 ΔVbe (4.18)
R4 R
= R Vbe1 + R3 .VT . ln(N)
The term in the parantheses is the conventional 1.2V bandgap reference. It can be seen
in equation 4.18 that the conventional 1.2V bandgap voltage is scaled by the factor RR3 ,
allowing for sub1.2V references and eliminating the supply limitation.
k.Tr k T
Vbe (T ) = Vg0 + (η − m) . − λ.T + (η − m) . . T − Tr − T. ln (4.19)
q q Tr
4.2. Reference Voltage Technologies 71
Where:
Vg0 is the extrapolated bandgap voltage of Silicon at 0 Kelvin
λ is a constant that represents the slope of the linear component of Vbe (T )
Tr is the reference temperature
η is a process constant
m is the temperature
exponent of the collector current Ic 1
The term Vg0 + (η − m) . k.T r
in the above equation is the constant term of Vbe , the
q
term −λ.T is the linear CTAT term and the term (η − m) . kq . T − Tr − T. ln TTr is the
nonlinear term. Higher order compensation schemes try to cancel, or minimize, this term.
For example, the circuit in [Song 83] tries to decrease the higher order term by adding
a P T AT 2 voltage to Vbe (i.e. a voltage that is proportinal to T 2 ). This is made possible
by generating ΔVbe from two transistors: one biased by the sum of a PTAT current and a
constant current and the other biased by the diﬀerence between a constant current and a
PTAT current. The Taylor expansion of such a ΔVbe contains PTAT and P T AT 2 terms.
The circuit in [Gunawan 93] genertaes a nonlinear correction current IN L which results
from the ΔVbe of two bipolars: one biased by a PTAT current IP T AT , and the other biased
by the sum of a constant current and IN L . The term IN L can be adjusted, under speciﬁc
conditions, to minimize the nonlinear Vbe term. The output voltage is formed by dumping
IN L , Ivbe and IP T AT into a reference resistor Rref (Ivbe is a CTAT current proportional to
1
It is assumed that Ic ∝ T m . For a PTAT Ic , m=1. For a constant Ic , m=0
72 Chapter 4. Reference Voltage Generation: An Overview
For the purpose of comparison with the other reference voltage technologies, table 4.4 shows
the key performance metrics of some of the commercially available bandgap reference chips.
Only commercial designs are included for a fair comparison with the other technologies (and
also because longterm drift is rarely reported in literature).
4.2.5 Conclusions
In this chapter, four diﬀerent reference voltage technologies were overviewd namely: Zener
Based References, XFET R
references, Floatinggate references and Bandgap references.
The discussions in this chapter are the basis for the next chapter which presents the
reference voltage implementation.
Chapter 5
Circuit Implementation
This chapter presents the design and the implementation of the reference voltage circuit
for the ΣΔ forcefeedback acceleration sensing system proposed in section 3.4. The chapter
starts by discussing which technology to use for reference voltage generation, followed by a
discussion of the required specs. Then a detailed analysis is presented for the chosen circuit
topology. Finally, three circuit designs are presented to achieve the target specs. The
designs are implemented on austriamicrosystems AMS 0.35μm SiGe BiCMOS technology.
• ZenerBased references are the best in terms of longterm drift (on the commercial
scale). They have low temperature drifts as well. While these characterisitics make
them favorable, ZenerBased references have many drawbacks. They generally have
high power consumption and require supply voltages of 5V or more [Tha 00b] [Lin 95].
Besides, BuriedZeners  which are needed for high performance Zener references
[Tex 99]  are not a standard option in current CMOS technologies. Hence, Zener
Based references are inherently imcompatible with modern CMOS technologies.
• XFETTM provides low voltage operation together with low temperature and longterm
73
74 Chapter 5. Circuit Implementation
drifts. It can achieve a long term drift comparable to that of ZenerBased references.
XFETTM technology is, however, a properiatary technology that is patented by Ana
log Devices Incorporation [Bowers 98]. This technology is, thus, not a standard
option in CMOS technologies.
Based on the above discussion, Bandgap Technology will be adopted in this work. At
tempts will be made to overcome the inherent performance limitations of CMOScompatible
Bandgaps. In the following section, the basic bandgap circuit implementation is presented
and various aspects of its performance are analyzed.
5.2. Reference Voltage Specs 75
the 1.2V bandgap circuit is multiplied by 2.5 to get the 3V reference, the output noise from
the 1.2V bandgap circuit should be around 0.9μV in the band from 1mHz100Hz.
5.2.3 Drift
No speciﬁc value is required for the drift (which includes both drift with temperature and
longterm drift). Nevertheless, minimizing drift can help reduce system cost by reducing
the time intervals between which the system needs to be recalibrated. Towards this end,
a discussion is presented in section 5.3.2 on the measures that can be taken to reduce
longterm drift. Furthermore, a new temperature compensation technique is presented in
section 5.4.3 to achieve low temperature drift.
V1 = V2 = Vbe1 (5.1)
where Vbe1 is the baseemitter voltage of the diodeconnected transistor Q1 . Hence, the
current ﬂowing in the resistor RP T will be given by:
Vbe1 − Vbe2
I2 = (5.2)
RP T
But:
I1
Vbe1 = VT ln (5.3)
Is1
I2
Vbe2 = VT ln (5.4)
Is2
5.3. The Basic Bandgap Circuit: An overview 77
Where Is1 and Is2 are the reverse saturation currents of transistors Q1 and Q2 , respec
tively. Therefore:
Vbe1 − Vbe2 VT I1 Is2
I2 = = ln . (5.5)
RP T RP T I2 Is1
If transistors Q1 and Q2 are matched (i.e. made up of the same unit element), then the
ratio IIs2
s1
is simply the ratio of the number of unit elements of both transistors, i.e. :
Is2
=N (5.6)
Is1
Where it is assumed that transistor Q1 is made up of a single unitelement, whereas
transistor Q2 is made up of N unit elements. On the other hand, the currents I1 and I2
can be calculated as:
I1 RCT 2
= (5.9)
I2 RCT 1
Hence, equation 5.5 can be rewritten as:
VT RCT 2
I2 = . ln .N (5.10)
RP T RCT 1
RCT 2
If the resistors RCT 1 and RCT 2 are matched with the ratio RCT 1
equal to M, then I2
can be rewritten as:
VT
I2 = . ln (M.N ) (5.11)
RP T
Hence, the output voltage Vout can be expressed as:
Substituting from equations 5.1 and 5.11 into equation 5.12, then Vout can be expressed
as:
RCT 2
Vout = Vbe1 + .VT . ln (N.M ) (5.13)
RP T
Equation 5.13 is the equation of a bandgap voltage. As discussed in section 4.2.4,
the term Vbe is the CTAT term whereas the VT ln (N.M) term is the PTAT term. Since
the slope of the PTAT term with temperature is smaller than that of the CTAT term,
the factor RRCT
PT
2
is introduced to make both slopes equal and, hence, acheive the desired
reference that is constant with temperature (to a 1st order) [Razavi 01].
The circuit shown in ﬁgure 5.1 is thus a basic implementation of the Bandgap reference.
However, this circuit suﬀers from two major drawbacks:
1. NPN Bipolar transistors are used which are incompatible with the modern CMOS
technologies (which predominantly use Ptype substrates) [Razavi 01]
2. The Opamp used has to supply the DC currents I1 and I2 , which complicates the
design of the Opamp. The presence of a resistive load decreases the eﬀective gain of
the Opamp, dictating the use of a lowimpedance output stage
RCT
Vout = Vbe1 + .VT . ln (N.M ) (5.14)
RP T
The following notes can be observed on the bandgap circuit in ﬁgure 5.2:
• The Opamp in ﬁgure 5.2 is not resistively loaded. Instead, it controls the gate
of the PMOS current mirrors. Hence, it is capacitively loaded. This relaxes the
requirements on the Opamp, making the use of singlestage topologies a viable option.
Singlestage topologies are generally more powereﬃcient than twostage topologies
and they are, generally, easier to stabilize. This is a deﬁnite advantage over the
implementation in ﬁgure 5.1
80 Chapter 5. Circuit Implementation
• The NPN transistors in ﬁgure 5.1 are replaced by PNP transistors. PNP transistors
are readily available in all CMOS technologies. Two types of PNP transistors are
available for CMOS technologies, namely: verticalPNP and lateralPNP transistors
[Pertijs 06]. A discussion of which PNP type to use is presented in section 5.3.1
• The loop gain of the circuit in ﬁgure 5.2 is higher than that of the circuit in ﬁgure 5.1.
This can be attributed to the addition of an active element (the PMOS transistor) in
the feedback path of the circuit in ﬁgure 5.2. The circuit in ﬁgure 5.1, on the other
hand, has a purely passive feedback and, hence, a lower loop gain. This, in turn,
means that a higher Opamp gain would be required for the circuit in ﬁgure 5.1 than
that of ﬁgure 5.2 if the same error is to be achieved. A discussion of the Opamp gain
requirement is presented in section 5.3.4
In the following sections, a more elaborate discussion is presented on the various per
formance aspects of the CMOScompatible bandgap circuit (shown in ﬁgure 5.2). For this
discussion, the special (but very common) case of M=1 will be used.
emitter to ﬂow vertically into the substrate rather than laterally into the p+ collector. The
resulting Ie  Vbe characteristic is very nonideal. Lateral pnp transistors therefore have to
be biased via their collector, which precludes their use in a diodeconnected conﬁguration.
Moreover, their Ic Vbe characterisitics are far from ideal due to the presence of two paths
for the lateral current: a direct lateral path and a curved lateral path. At low currents,
the directlateral current dominates whereas the curved lateral component dominates at
higher currents (due to currentcrowding) [Pertijs 06].
Figure 5.3: A cross section of a lateral PNP transistor in CMOS technology [Pertijs 06]
A cross section of a vertical PNP transistor is shown in ﬁgure 5.4 [Pertijs 06]. This is es
sentially the same device as the parasitic transistor associated with lateral pnp transistors.
The emitter is formed by a P+ diﬀusion in an NWell, the NWell itself forms the base of
the transistor and the collector is formed by the Psubstrate outside the NWell. As a con
sequence, the collector of a vertical PNP transistor has to be always connected to ground.
The base width of vertical PNP transistors is relatively large, as it is mainly determined
by the depth of the Nwell (typically a few microns). As a result, the commonemitter
currentgain (β) of these transistors is very low compared to that of lateral PNP transis
tors. Moreover, the current ﬂow in verical PNP transistors is much more onedimensional
than in lateral PNP transistors. As a result, their Ic Vbe characteristic closely follows the
ideal exponential behavior over several decades of current. This, together with the fact
82 Chapter 5. Circuit Implementation
that the commonemitter currentgain (β) is constant over a wide range of emittercurrents,
results in an ideal Ie Vbe characteristic that makes them suitable for use as diodeconnected
transistors. Another advantage of the wide base of substrate pnp transistors is that varia
tions in the depth of the Nwell or the P+ diﬀusion will have relatively little eﬀect on the
transistors saturation current. If the transistors emitter area is large enough, variations
due to lithographic errors will also be small. A lateral PNP transistor, in contrast, will have
an eﬀective emitter area that varies with the depth of the P+ implant. Moreover, litho
graphic errors will have a much larger eﬀect, because they aﬀect the relatively small base
width. Therefore, the relative spread of the saturation current of lateral PNP transistors is
expected to be larger than that of vertical PNP transistors in the same process [Pertijs 06].
Figure 5.4: A cross section of a vertical PNP transistor in CMOS technology [Pertijs 06]
Another advantage of vertical PNP over lateral PNP concerns the longterm stability.
Mismatches in the thermal coeﬃcients of expansion (TCE) of diﬀerent materials of the
wafers and packages cause mechanical stress that is temperature and time dependent.
These stresses, in turn, induce changes in the Ic Vbe characteristic of bipolar transistors.
This is known as the Piezojunction eﬀect. Piezojunction eﬀect is found to be the main cause
of the longterm drift in bandgap circuits. It was found that vertical PNP transistors are
less prone to the Piezojunction eﬀect and are , hence, favorable when it comes to longterm
drift [Meijer 01] [Creemer 01].
5.3. The Basic Bandgap Circuit: An overview 83
It can thus be concluded that vertical PNP transistors are a better choice for the imple
mentation of highperformance bandgap circuits.
the Vbe voltage. Since the PTAT voltage is formed by the diﬀerence between the Vbe ’s of two
matched transistors, piezojunction eﬀect has a limited eﬀect on it [Fruett 03]. On the other
hand, the Vbe voltage is more sensitive to the piezojunction eﬀect. It is shown in [Fruett 03]
that the eﬀect of stress on Vbe is the major source of longterm drift in bandgap circuits.
To minimize the piezojunction eﬀect, it is recommended to use substrate (i.e. vertical)
PNP transistors (rather than lateral PNP transistors or NPN transistors) [Creemer 01].
Another possible measure to reduce this eﬀect is to place the Vbe generating transistor in
the chip corner. As shown in [Bastos 97], the stress at the corner of the chip is minimal
(but the stress gradient is maximum). Since the Vbe generating transistor is also a part of
the ΔVbe generating circuitry (that depends on matching), placing it at the chip corner will
compromise matching (due to increased stress gradients at chip corner). The advantage of
such a measure requires experimental veriﬁcation, however.
To summarize, reducing the longterm drift in bandgap circuits translates to reducing
the eﬀect of stress. Towards this end, the possible measures that can be taken include:
• Placing the Vbe generating transistor at the chip corner (this is a suggestion that
lacks experimental veriﬁcation, however)
The bandgap circuit in ﬁgure 5.2 includes both positive and negative feedback loops
[Razavi 01]. Figure 5.5 indicates both loops on the CMOScompatible bandgap circuit.
It is to be noted that the positive feedback loop is associated with the negative terminal of
the Opamp, whereas the negative feedback loop is associated with the positive terminal of
5.3. The Basic Bandgap Circuit: An overview 85
Figure 5.5: CMOScompatible bandgap with positive and negative feedback indicated
the Opamp. This can be attributed to the presence of the PMOS transistor which forms
an inverting commonsource stage in the feedback path.
For stable operation, the gain around the negative feedback loop must be higher than
the gain around the positive feedback loop. This explains the choice of the Opamp connec
tions; the negative terminal (associated with positivefeedback) is connected to the loop
with the smaller gain whereas the positive terminal (associated with negativefeedback) is
connected in the loop with the higher gain. To further explain this point, consider ﬁgure
5.6 which shows the AC model for both loops. To calculate the loop gain around the neg
ative feedback loop, the positive feedback loop is deactivated by grounding the Opamp’s
negative terminal. To get the gain around the positive feedback loop, on the other hand,
the Opamp’s positive terminal is grounded.
Hence, the gain around the negative feedback loop Af b− will be given by:
1
Af b− = Aop .gmp . RP T + (5.15)
gmQ2
Where:
86 Chapter 5. Circuit Implementation
1
Af b+ = Aop .gmp . (5.17)
gmQ2
Figure 5.6: AC model used for evaluating Loop Gains in CMOScompatible bandgap
Comparing the expressions of Af b− and Af b+ , it can be seen that the negative feedback
loop gain is higher than the positive feedback loop gain making the overall loop a negative
feedback loop. The overall negative feedback loop gain (LG) can now be expressed as:
Aop0 (dB) RP T (kΩ) gmp (μS) Loop Gain simulated (dB) Loop Gain calculated (dB)
10 35.4 50.88 50.98
60
5 49.28 47.69 47.83
10 35.02 70.78 70.87
80
5 48.8 67.75 67.61
This means that, in eﬀect, the overall negativefeedback loop is as shown in ﬁgure 5.7.
TM
To validate this conclusion, a number of simulations (using Spectre circuit simulator)
are made on the CMOScompatible bandgap circuit of ﬁgure 5.2 in which a behavioral
Opamp is used (the behavioral model is shown in Appendix B). Two diﬀerent values are
used for Aop and two other values are used for RP T . For each combination of Aop and RP T
the loop gain is simulated and is also calculated by the equation 5.18. Table 5.1 shows
the comparison between simulation and calculation results. It can be seen that they are
in close agreement.
It is to be noted that the expression of LG given in equation 5.18 can be obtained
from the expression of Af b− by simply ignoring gm1Q2 as compared to RP T . While this may
sound as a reasonable assumption at a ﬁrst glance, careful analysis shows that it is not. In
ignoring gm1Q2 , one would be tempted by the fact that bipolars have large transconductances
hence making the term gm1Q2 negligible. However, analysis shows that:
Ic α.I
gmQ2 = = (5.19)
VT VT
Where α is the commonbase current gain of the bipolar transistor [Sedra 98]. The
current I is PTAT and can be found by setting M=1 in equation 5.11. Doing so and
reevaluating gm1Q2 , it is found that:
1 RP T
= (5.20)
gmQ2 α. ln (N)
The value of N is commonly chosen to be eight to allow a symmetrical commoncentroid
layout of the bipolars [Mok 04]. Hence, ln(N) is equal to about two. Furthermore, α is
88 Chapter 5. Circuit Implementation
signiﬁcantly less than one since verticalPNP transistors have low β [Pertijs 06]. Conse
quently, it can be concluded that the term gm1Q2 cannot be ignored compared to RP T .
To assess the stability of the bandgap’s negative feedback loop, it is important to locate
the nodes that correspond to the dominant and nondominant poles. Inspection of ﬁgure
5.5 suggests that there are two major poles: one located at the output of the Opamp and
the other located at the drain of the PMOS transistor on which the output is taken. The
Opamp’s output node is expected to have higher impedance (since highimpedance would
be required for large Opamp gain)1 . Hence, the dominant pole will be set by the Opamp’s
output impedance and the gatecapacitance of the PMOS transistor (the capacitance of
the twomirror transistors has to be taken into consideration). The load capacitance at
the PMOS drain together with the output resistance seen into the drain determine the
nondominant pole.
As shown in ﬁgure 5.5, the output can be taken at either of the two nodes Vout or Voutp .
The voltage Vout is the output of the negative feedback loop, whereas Voutp is the output
1
This assumes a singlestage Opamp. If a twostage Opamp is used, the highest impedance node would
be an internal Opamp node
5.3. The Basic Bandgap Circuit: An overview 89
of the positive feedback loop; both outputs have the desired DC bandgap characteristics.
From a stability point of view, however, they are diﬀerent. By intuition, it is better to
take the output voltage at Voutp : the output of the positive feedback loop. By doing so,
the load capacitance (CL ) is placed at the output of the positive feedback loop where it is
unlikely to disrupt stability. To verify this conclusion, a simulation is made on a bandgap
circuit with a behavioral Opamp (the behavioral model is shown in Appendix B). The
load capacitance is placed once on Vout and once on Voutp , then the loop gain magnitude
and phase is simulated for each case. The results, shown in ﬁgure 5.8, are in agreement
with the intuitive conclusion; the phase margin for the Vout case is negative (almost 20o)
as opposed to a positive phase margin (almost +90o ) for the Voutp case.
To get a better understanding of this result, the loop’s frequency response needs to be
evaluated for both cases. In both cases, the Opamp determines the dominant pole. Hence,
the Opamp’s frequencydependent gain Aop (s) implicitly contains the dominant pole.
Consider ﬁrst the case where CL is connected to Voutp . In this case, the overall negative
feedback loop gain (LG) will be given by:
LG = Af b− (s) − Af b+ (s)
„ «
RCT + gm1 . sC1 1
(5.21)
1
−
Q L gmQ
= Aop (s).gmp . RP T + RCT + gm1 + sC1
.R 1
gmQ CT + gm
Q L Q
Where:
LG is the overall Loop Gain
gmQ is the transconductance of the Bipolar transistors (both transistors have the same
transconductance)
LG in equation 5.21 can be further reduced to:
1
1
LG = Aop (s).gmp . RP T + gmQ
− sCL
RCT + gm1 + sC1
. gm1 Q
Q L
(5.22)
1 „ 1 «. 1
= Aop (s).gmp . RP T + gmQ
− gmQ
1+sCL . RCT + gm1
Q
1
Let the term RCT + gmQ
be denoted by Reqp . Hence, LG can further be reduced to:
90 Chapter 5. Circuit Implementation
Figure 5.8: Loop Gain and Phase for CL connected to Voutp and Vout
5.3. The Basic Bandgap Circuit: An overview 91
1
1
LG = Aop (s).gmp .RP T . 1 + gmQ .RP T − 1+sCL .Reqp .
gmQ .RP T
(s).gmp .RP T 1
= Aopgm . (gm Q .R PT + 1) − .
Q .RP T 1+sCL .Reqp
Aop (s).gmp .RP T 1
= gmQ .RP T . (gmQ .RP T + 1) . 1 − gm .R +1 .(1+sC .R ) . (5.23)
( Q P T ) L eqp
From equation 5.24, it can be seen that taking the output at Voutp will cause the loop
gain equation to have a Left Half Plane (LHP) zero and a pole. The pole and zero are
very near in frequency (recall that gmQ .RP T =α.ln (N)≈2). They, thus, form a polezero
doublet. In the magnitude response, the pole and zero almost cancel each other (as they
are close in frequency). In the phase response, however, the LHP zero enhances stability
by increasing the phase. This can be clearly seen in ﬁgure 5.8(a)
Now, consider the case where CL is connected to Vout . In this case, the overall negative
feedback loop gain (LG) will be given by:
⎛ ⎞
1 1 1
sCL
RCT + RP T + gmQ RP T + 1 ⎠
LG = Aop (s).gmp . ⎝
gmQ
1 1 . 1 − (5.25)
sCL
+ RCT + RP T + gmQ
RCT + RP T + gmQ
gmQ
1
Let RCT + RP T + gmQ
be denoted by Reqn . Hence, LG can further be reduced to:
RP T + gm1
1
LG = Aop (s).gmp . 1+s.CL .Reqn
Q
− gmQ
gmp gmQ .RP T +1 (5.26)
= Aop (s). gm . −1
Q 1+s.CL .Reqn
gmp gmQ .RP T −s.CL .Reqn
= Aop (s). gmQ . 1+s.CL .Reqn
92 Chapter 5. Circuit Implementation
Vbe1
ΔV = (5.28)
1 + LG
Where LG is the loop gain. From equation 5.18, the loop gain is given by the factor
Aop .gmp .RP T . Hence, the error will be given by:
5.3. The Basic Bandgap Circuit: An overview 93
Figure 5.9: Model for evaluating the eﬀect of ﬁnite Opamp gain
Figure 5.10: Bandgap circuit with Oﬀset voltage representing eﬀect of ﬁnite gain
94 Chapter 5. Circuit Implementation
Vbe1
ΔV = (5.29)
1 + Aop .gmp .RP T
Now that this error has been calculated, it has to be incorporated into the bandgap
circuit so that the value of the bandgap voltage reﬂects this error source. This can be done
by adding an oﬀset voltage source (Vop = 1+AopV.gm
be1
p .RP T
) in series with the positive terminal
of the Opamp as shown in ﬁgure 5.10. The Opamp in ﬁgure 5.10 is an ideal Opamp, and
the oﬀset voltage source Vop accounts for the Opamp’s ﬁnite gain.
With the source Vop present, the voltage V2 can be expressed as:
RCT
Vout ≈ Vbe1 + . (VT . ln (N) − Vop ) (5.32)
RP T
Hence, the eﬀect of the ﬁnite Opamp gain is to subtract a CTAT term ( R CT
RP T
.Vop ≈
RCT Vbe1
.
RP T 1+gmp .Aop .RP T
) from the bandgap voltage. This results in deviation of the bandgap
voltage from the expected value. To see the eﬀect of this error, Vbe1 in the error term will
be decomposed into two components: Vbe avg that represents the average value of Vbe across
temperature, and Vbe T that represents the temperaturedependent portion of Vbe . Two
eﬀects can be observed:
1. Vbe avg will cause an output oﬀset voltage. This oﬀset, however, will have no eﬀect
on temperature compensation as it is temperatureindependent
The constant output oﬀset doesn’t deteriorate the bandgap voltage’s curvature; it just
shifts the whole bandgap characteristics. The most pronounced eﬀect will be due to the
temperaturedependent oﬀset Vbe T . The error term in equation 5.32 is equal to Vbe1 divided
by the loop gain and multiplied by the ratio R CT
RP T
. For the common case of N=8, the ratio
RCT
RP T
amounts to about 10. Hence, the error term is almost equal to Vbe1 divided by one
tenth of the loop gain. To make the error term negligible compared to Vbe1 (and hence make
its temperature eﬀect negligible compared to Vbe1 ), it is necessary to make it less than Vbe1
by a factor of 10 at least. This, in turn, means that one tenth the loop gain should be
equal to 10 i.e. a loop gain of 100 (40 dB) or more would be needed. In fact, simulation
results indicate that a loop gain of about 50 dB or more is needed to achieve the smallest
peaktopeak variation across temperature.
vout
P SR = (5.33)
vdd
Where PSR is short for Power S upply Rejection. Hence improving supply rejection
implies minimizing PSR.
v2 = i.RP T (5.34)
The current i will have two components: the ﬁrst corresponding to the gmp .vsg of the
PMOS transistor and the second corresponding to the current in the PMOS transistor’s
output resistance. Thus, i can be expressed as:
vdd − vout
i = gmp . (vdd − Aop .v2 − Gop .vdd ) + (5.35)
rds
Substituting from equation 5.35 into equation 5.34, v2 can be expressed as:
RP T
v2 = gmp .RP T . (vdd − Aop .v2 − Gop .vdd ) +
. (vdd − vout ) (5.36)
rds
Rearranging equation 5.36, v2 can now be expressed as:
1 RP T
v2 = . gmp .RP T .vdd . (1 − Gop ) + . (vdd − vout ) (5.37)
1 + gmp .RP T .Aop rds
RCT
1+ RP T RP T
vout = . gmp .RP T .vdd . (1 − Gop ) + . (vdd − vout ) (5.39)
1 + gmp .RP T .Aop rds
RP T 1+ R CT
RP T
1+ RCT
RP T RP T
vout 1+ . = . gmp .RP T . (1 − Gop ) + .vdd
rds 1 + gmp .RP T .Aop 1 + gmp .RP T .Aop rds
(5.40)
Hence, the DC value of PSR (P SR0 ) can be expressed as:
98 Chapter 5. Circuit Implementation
⎛ ⎞
⎜ gmp .RP T . (1 − Gop ) +
RCT RP T
vout 1+ RP T rds ⎟
P SR0 = = .⎝ R ⎠ (5.41)
vdd 1 + gmp .RP T .Aop 1+ RCT
1 + RrPdsT . 1+gmp .R PT
P T .Aop
The PSR expression of equation 5.41 is rather complex. Fortunately, some simpliﬁca
tions can be made to obtain a handy expression. The ratio R CT
RP T
is typically much larger
than 1. Similarly, gmp .RP T .Aop represents the loop gain and is thus also much larger than
1. Thus, P SR0 can be approximated to:
⎛ ⎞
⎜ gmp .RP T . (1 − Gop ) +
RCT RP T
RP T rds ⎟
P SR0 = .⎝ RCT ⎠ (5.42)
gmp .RP T .Aop
1 + gmp .Rrds
P T .Aop
Another approximation can be made on the above equation. The ratio RrCT ds
in the
denominator of the term in parentheses is much smaller than one. This is based on the
assumption that rds >> RCT , which is a reasonable assumption in pactice. Besides, the
ratio RrCT
ds
is divided by the loop gain, further reducing its value. Hence, the DC value of
PSR can ﬁnally be represented as:
R
RCT (1 − Gop ) CT
rds
P SR0 = . + (5.43)
RP T Aop gmp .RP T .Aop
For the purpose of discussion, equation 5.43 can be rearranged as:
RCT (1 − Gop ) 1
P SR0 = . + (5.44)
RP T Aop gmp .rds .Aop
To validate the expression reached in equation 5.44, a number of simulations are made
using a behavioral Opamp (the behavioral model is shown in Appendix B). Table 5.2
shows comparison between simulated and calclated values for two diﬀerent Opamp gain
values, and three Opamp PSR values. The simple expression of equation 5.44 predicts
P SR0 within a 2 dB error, which is quite acceptable in practice.
The following notes can be made on the expression of P SR0 in equation 5.44:
Aop (dB) Gop gmp (μS) rds (MΩ) P SR0 sim. (dB) P SR0 calc. (dB)
0.9 35.41 14 58.38 59.65
60
1.0 35.41 14 92 93.73
0.95 35.02 14.48 84.23 85.5
80
1.0 35.02 14.48 111.86 113.93
RCT
(VT . ln (N)) equal to the slope of the Vbe voltage. Thus, RP T
cannot be deliberately
set to adjust the desired P SR0
• The 2nd term of equation 5.44 is inversely proportional to the loop gain, and also
to the output resistance of the PMOS transistor rds . Thus, this term can be easily
minimized by either increasing the loop gain (basically through increasing the gain of
the Opamp Aop ) or by increasing rds (by increasing the length of the PMOS transistor
or by adding a cascode transistor to the current mirror). Thus, through proper choice
of Aop and rds the 2nd term can be made nondominant
• The 1st term of equation 5.44 is inversely proportional to the Opamp’s gain and
directly proportional to (1 − Gop ), where Gop is the PSR of the Opamp. Hence, this
term will be larger than the 2nd term. To minimize the 1st term, Gop should be
as close as possible to one i.e. the Opamp should have a poor PSR. This can be
intuitevly understood by observing ﬁgure 5.11; if the Opamp has a poor PSR, the
supply vdd will couple to the gate of the PMOS transistor minimizing vsg . This, in
turn, will minimize the current component gmp .vsg , hence, decreasing PSR. A similar
result was reached in [Gupta 04] in the context of LDO supply rejection. Towards
this end, it is better to use Opamps with PMOS currentmirror loads which achieve
a nearunity PSR (as opposed to Opamps with NMOS mirror loads that achieve a
near zero PSR) [Gupta 04]
• It can be seen from equation 5.44 that a zero value for P SR0 can be obtained if the
1st and 2nd terms cancel each other. The 2nd term of equation 5.44 is always positive.
The 1st term, however, can be made negative if Gop is made slightly larger than unity.
100 Chapter 5. Circuit Implementation
It can be seen that P SR0 is equal to A1op multiplied by a factor. This factor has two
1
coeﬃcients: R CT
RP T
and (1 − G op ) + gmp .rds
. The ﬁrst coeﬃcient is always greater
than one (for N=8 the factor R CT
RP T
is around 10). The 2nd coeﬃcient will be greater
than zero if Gop is less than one, which is the most common case. Tweaking the value
of Gop can make it slightly larger than one, eﬀectively reducing the 2nd coeﬃcient
and eventually decreasing the overall value of P SR0 . For Gop = 1 + gmp1.rds , P SR0
will be equal to zero.
Figure 5.12: P SR0 versus Gop0 illustrating the possibility of a zero P SR0
To verify the above conclusion, a simulation is made with a behavioral Opamp (the
behavioral model is shown in Appendix B). To get a zero PSR, the Opamp’s Gop0
must be set with a very high precision (since the value of gmp1.rds is very small). For
5.3. The Basic Bandgap Circuit: An overview 101
this speciﬁc simulation, gmp is equal to 35μS and rds is equal to 14.48 MΩ. Hence,
the Gop0 value required for a zero P SR0 is approximately equal to 1.002. To avoid
the precision pitfall, Gop0 is swept from 1 to 1.004. The result, shown in ﬁgure 5.12,
shows that P SR0 decreases to very low values in the vicinity of Gop =1.002, thus
verifying the conclusion and further validating the P SR0 expression of equation 5.44
Now that the value of PSR at DC (P SR0 ) has been evaluated and veriﬁed by simulation,
it’s important to evaluate the frequency charachteristics of PSR. This will be done on two
steps: ﬁrst the frequency response of the Opamp gain (Aop ) will be included, followed by
the frequency response of the Opamps PSR (Gop ). For this purpose, a simpliﬁed version of
equation 5.41 will be used. Two simpliﬁcations are made: R CT
RP T
is taken to be much larger
than one and the denominator of the term in brackets is approximated to 1. Hence, the
starting equation for frequency reponse evaluation will be:
RCT
RP T RP T
P SR = . gmp .RP T . (1 − Gop ) + (5.46)
1 + gmp .RP T .Aop rds
This equation can be further simpliﬁed to:
RCT 1
P SR = . gmp . (1 − Gop ) + (5.47)
1 + gmp .RP T .Aop rds
To include the Opamp’s frequency response in the PSR equation, Aop will be replaced
by a frequencydependent Aop (s). To obtain a simple expression that can give design
insight, it will be assumed that the Opamp’s frequency response has a single pole. This
is a reasonable assumption if the Opamp has a high enough phase margin. Hence, Aop (s)
can be expressed by:
Aop0
Aop (s) = (5.48)
1 + ps0
Where:
Aop0 is the DC gain of the Opamp
p0 is the Opamp’s dominant pole
102 Chapter 5. Circuit Implementation
Hence, substituting by the expression of Aop (s) from equation 5.48 into equation 5.47
the frequency dependent P SR(s) can be expressed as:
1
P SR (s) = RCT
gmp .RP T .Aop0 . gmp . (1 − Gop ) + rds
1+ 1+ ps
“0 ”
RCT . 1+ ps
(5.49)
1
= 0
1+gmp .RP T .Aop0 + ps
. gmp . (1 − Gop ) + rds
0
RCT . 1 + ps0
1
P SR (s) = . gmp . (1 − Gop ) + (5.50)
s
(1 + gmp .RP T .Aop0 ) . 1 + p0 (1+gmp .RP T .Aop0 ) rds
gmp .RP T .Aop0 represents the DC loop gain and is, thus, much larger than 1. This allows
P SR (s) to be approximated as:
“ ”
1+ ps
1 1
P SR (s) ≈ . RCT
Aop0 RP T
. (1 − Gop ) + gmp .rds
. 0 !
1+ s
“ ” (
p0 1+gmp .RP T .Aop0 )
(5.51)
1+ ps
0 !
= P SR0 .
1+ s
(
p0 1+gmp .RP T .Aop0 )
To obtain the complete frequency dependence for P SR(s), the frequency dependence
of the Opamps’s PSR Gop (s) must be incorporated into equation 5.51. To do so, a single
pole model will be assumed for Gop (s) (in the same manner that was done for the gain
Aop (s)). Hence, Gop (s) will be expressed as:
Gop0
Gop (s) = (5.52)
1 + pss
Where:
Gop0 is the DC value of the Opamp’s PSR
ps is the dominant pole of Gop (s)
1
Modifying Gop (s) will only change the factor (1 − Gop ) + gmp .rds
in equation 5.51. The
term (1 − Gop ) + gmp1.rds will be named K. Hence:
5.3. The Basic Bandgap Circuit: An overview 103
Gop0 1
K = 1− 1+ ps
+
s gmp .rds
1 s.gmp .rds
s
= gm .r . 1+ s . 1 + ps + gmp .rds + ps − Gop0 .gmp .rds (5.53)
p ds ( ps )
1
= gm .r . 1+ s . 1 + gmp .rds . (1 − Gop0 ) + ps . (1 + gmp .rds )
s
p ds ( ps )
s
Since the term gmp .rds is much larger than one, the term ps
. (1 + gmp .rds ) will be
approximated to pss .gmp .rds . Thus, K can be approximated as:
1
K≈ . 1 + gmp .rds . (1 − Gop0 ) + ps .gmp .rds
gmp .rds .(1+ ps
s
s
)
1+gmp .rds .(1−Gop0 ) s.gmp .rds
= gm .r . 1+ s . 1 + ps.(1+gmp .rds .(1−Gop0 )) (5.54)
p ds ( ps )
1+gmp .rds .(1−Gop0 ) s
= gm .r . 1+ s . 1 + “ 1 ”
p ds ( ps ) ps . gm .r +(1−Gop0 )
p ds
1+ “
1
s ”
1 ps . +(1−Gop0 )
K= + (1 − Gop0 ) . gmp .rds
(5.55)
gmp .rds 1+ s
ps
1
Replacing the term gmp .rds
+ (1 − Gop0 ) by K0 , K can ﬁnally be written as:
s
1 + ps .K
K = K0 . 0 (5.56)
s
1 + ps
By observing the expression of P SR0 of equation 5.45, it can also be expressed in terms
of K0 as:
1 RCT
P SR0 = K0 . . (5.57)
Aop RP T
By combining equations 5.57, 5.56 and 5.51 the complete expression for P SR(s) can
be ﬁnally expressed as:
s s
1 RCT . 1 + 1+ p0
K0 .ps
P SR(s) = K0 . . . (5.58)
Aop0 RP T 1 + s . 1 + s
ps p0 .(1+LG)
104 Chapter 5. Circuit Implementation
Where:
K0 is equal to gmp1.rds + (1 − Gop0 )
Gop0 is the DC value of the Opamp’s supply rejection
Aop0 is the Opamp’s open loop DC gain
LG is the loop gain of the CMOScompatible bandgap and is equal to gmp .RP T .Aop0
p0 is the dominant pole of the Opamp (which is also the dominant pole of the loop)
ps is the dominant pole of the Opamp’s PSR
To validate the expression of equation 5.58, a number of simulations are made with a
behavioral Opamp (the behavioral model is shown in Appendix B). The following obser
vations and conclusions can be made:
• When the Opamp’s compensation capacitor (Cc ) is connected to ground, the dom
inant pole of both the Opamp’s gain Aop (s) and the Opamp’s PSR Gop (s) will be
identical. Hence, p0 and ps will be equal in equation 5.58. Thus, the P SR(s) equation
will have a single pole and a single zero and will be given by:
s
1 RCT 1 + K0 .ps
P SR(s) = K0 . . . s (5.59)
Aop0 RP T 1 + p0 (1+LG)
The zero is at a frequency ps .K0 . Since K0 is a quantity much smaller than one, the
zero of P SR(s) is at a frequency much lower than the Opamp’s dominant pole. The
pole is at a frequency given by p0 (1 + LG) which is equal to the loop’s unitygain
frequency. The simulation result of this case is shown in ﬁgure 5.13. The DC value of
PSR starts to increase by 20 dB/decade after the 1st zero. The zero, as expected, is at
a much lower frequency than the Loop Gain’s dominant pole. A pole appears in the
PSR response at the Loop Gain’s unity gain frequency (the frequency at which the
Loop Gain is zero dB). Figure 5.13 shows two poles at the unity gain frequency. The
additional pole can be attributed to the capacitance loading the bandgap’s output
(whose eﬀect was ignored in our analysis).
• For the same case where Cc is connected to ground, we can observe from equation
5.59 that improving P SR0 (by decreasing K0 ) will simultaneously cause a reduction
5.3. The Basic Bandgap Circuit: An overview 105
of PSR bandwidth (as the zero frequency is equal to K0 .ps ). In fact, the product of
1
P SR0
and the PSR bandwidth (i.e. ps .K0 ) is constant and is given by:
1 1 RP T
.ps .K0 = .p0 .K0 = p0 .Aop0 . (5.60)
P SR0 P SR0 RCT
This suggests that there is a constant supplyrejection gainbandwidth product in
the same manner that an Opamp would have a constant gainbandwidth product.
Hence, improving P SR0 by varying Gop0 would inevitably result in a reduction in the
PSR bandwidth and viceversa. Figure 5.14 shows a veriﬁcation of this result: P SR0
is changed by varying Gop0 with a reduction in PSR bandwidth as P SR0 improves.
• In reaching equation 5.58, it was assumed that the Opamp’s Gop (s) has a single
pole and no zeroes. This will be true if the compensation capacitor (Opamp’s load
5.3. The Basic Bandgap Circuit: An overview 107
Where gmvdd .vdd .Ro was replaced with Gop0 . Rearranging the equation, Gop (s) can
be found to be:
s.Cc .Ro
1+ Gop0
Gop (s) = Gop0 . (5.62)
(1 + s.Cc .Ro )
Connecting Cc to Vdd will thus create a zero and a pole. The polezero pair will
be very close in frequency if Gop0 is close to one (which is the case for singlestage
Opamps with PMOS currentmirror loads [Gupta 04]). Consider the following cases:
– If Gop0 is equal to one, the zero and pole will perfectly cancel each other. In this
case, Gop (s) will be frequency independent (i.e. Gop (s)=Gop0 ). Hence, equation
5.51 will represent P SR(s) i.e.:
1 RCT 1 + ps0
P SR(s) = K0 . . . s (5.63)
Aop0 RP T 1 + p0 (1+LG)
Hence, the zero in P SR(s) is now located at the Opamp’s dominant pole p0 .
Recall that for the case where Cc is connected to ground, the P SR(s) zero is
located at a frequency much lower than p0 (ps .K0 , K0 <<1). This means that
connecting Cc to Vdd eﬀectively increases the P SR(s) bandwidth by the factor K10
without compromising P SR0 . This agrees with circuit intuition, since connecting
Cc to Vdd enhances the coupling of vdd to the gate of the PMOS transistor at
higher frequencies. This, in turn, reduces the gmp .vsg current component at
higher frequencies leading to a wider bandwidth. Figure 5.15 shows simulation
results for the case where Gop0 is equal to one, with Cc connected once to ground
and once to Vdd
108 Chapter 5. Circuit Implementation
Figure 5.15: PSR and Loop Gain for Cc connected to Vdd and to ground
– For the case where Gop0 is not equal to one (i.e. less than 0.9), Gop (s) will contain
a zero and a pole. To obtain the complete P SR(s) expression, equation 5.51 has
to be evaluated by substituting the correct Gop (s) expression. Doing so is rather
complex and will yield an equally complex result. Alternatively, we can build on
the intuition of constant supplyrejection gainbandwidth product to conclude
that Gop0 <1 will result in an increase in P SR(s) bandwidth. Simulation results,
shown in ﬁgure 5.16, conﬁrm this conclusion
To further validate the conclusions in this section, simulation is made with a real
Opamp. The simple currentmirror Opamp, shown in ﬁgure 5.17, is used for this purpose.
Simulations are made with Cc connected to ground and to Vdd . Simulation result for both
cases are shown in ﬁgure 5.18. The results show that conclusions and observations made
using the behavioral Opamp model are valid for the real Opamp case.
5.3. The Basic Bandgap Circuit: An overview 109
Figure 5.18: PSR for Cc connected to Vdd and ground for real Opamp
5.3. The Basic Bandgap Circuit: An overview 111
The AC model used to evaluate the eﬀect of the Opamp noise is shown in ﬁgure 5.20. The
small siganl current iout can thus be given by:
vnop
iout ≈ (5.66)
RP T
Thus, the output noise vout can be expressed as:
5.3. The Basic Bandgap Circuit: An overview 113
1 vnop 1
vout = iout . RP T + RCT + = . RP T + RCT + (5.67)
gmQ RP T gmQ
Finally, vout can be approximated as:
RCT
vout ≈ vnop . 1 + (5.68)
RP T
As seen from equation 5.68, the Opamp’s input noisevoltage is multiplied by the ra
tio RCT
RP T
. This, in eﬀect, ampliﬁes the Opamp’s noise. Since the Opamp is the noisiest
component in the circuit, special care has to be given to its noise spec.
The AC model used to evaluate the eﬀect of the RP T noise is shown in ﬁgure 5.21. The
small siganl current iout can thus be given by:
114 Chapter 5. Circuit Implementation
The AC model used to evaluate the eﬀect of the RCT noise (vnrct1 )is shown in ﬁgure 5.22.
The small siganl current iout can thus be given by:
The AC model used to evaluate the eﬀect of the noise of the PMOS transistor Mp1 is shown
in ﬁgure 5.23. The small siganl voltage vg can thus be given by:
vout = (inmp1 − gmp .vg ) RP T + RCT + gm1 Q
gmp .Aop .inmp1 1 1
= inmp1 − 1+gmp .RP T .Aop . RP T + gmQ RP T + RCT + gmQ
gmp .Aop 1 1 (5.79)
= inmp1 . 1 − 1+gm . RP T + R P T + RCT +
gmp .Aop
p .RP T .Aop gmQ
gmQ
1− gm
= inmp1 . 1+gmp .RPQT .Aop RP T + RCT + gm1 Q
The AC model used to evaluate the eﬀect of the noise of the PMOS transistor Mp2 is shown
in ﬁgure 5.24. The small siganl voltages v1 and v2 can thus be given by:
2 − v1 )
vg = Aop . (v (5.82)
= −Aop . gmp .vg .RP T + inmp2 . gm1 Q
From which vg can be ﬁnally expressed in the form:
The AC model used to evaluate the eﬀect of the noise of the BJT Q2 is shown in ﬁgure
5.25. The small siganl current iout can thus be given by:
5.3. The Basic Bandgap Circuit: An overview 119
v1 = iout . gm1 Q
(5.88)
v2 = vx + iout .RP T
Thus, the diﬀerence (v1 − v2 ) can be expressed as:
1
v1 − v2 = iout . − RP T − vx (5.89)
gmQ
120 Chapter 5. Circuit Implementation
inq2
iout = (5.92)
gmQ .RP T
Now, vout can be written as:
The AC model used to evaluate the eﬀect of the noise of the BJT Q1 is shown in ﬁgure
5.26. The small siganl current iout can thus be given by:
1
v2 = iout . + RP T (5.97)
gmQ
inq1
iout = (5.100)
gmQ .RP T
122 Chapter 5. Circuit Implementation
2
Component Noise contribution to the output (Vrms /Hz)
2
2
Opamp vnop . 1+ RR
CT
PT 2
RCT
RP T 4.kB .T.RP T . 1 + RP T
RCT 4.kB .T.RCT
2
Mp1 i2nmp1 . gm1 2 . 1 + R CT
RP T
+ 1
gmQ .RP T
Q
2
Mp2 i2nmp2 . gm1 2 . 1 + R CT
RP T
+ 1
gmQ .RP T
Q
2
Q1 i2nq1 . gm1 2 . 1 + R R
CT
+ 1
gmQ .RP T
Q
PT 2
Q2 i2nq2 . gm1 2 . gmQ1.RP T + R CT
RP T
Q
Table 5.3: Noise Contribution of bandgap circuit components to the output noise
1 1 RCT 1
vout = iout + RP T + RCT = inq1 . . 1+ + (5.101)
gmQ gmQ RP T gmQ .RP T
Table 5.3 summarizes the noise contributions of the components of the bandgap circuit to
the output noise. It is to be noted that the expressions shown are valid for both thermal
and ﬂicker noise.
With the noise contributions of all the components identiﬁed, the following observations
can be made:
2
• The Opamp noise is multiplied by the gain factor 1 + R CT
RP T
. Hence, the Opamp
can easily become the major noise source in the bandgap circuit  in terms of both
ﬂicker and thermal noise
• The noise contribution of the RP T resistor is larger than that of RCT . This can
2
RCT
be observed by approximating the contribution of RP T to 4.kB .T.RP T . RP T
=
4.kB .T.RCT . RCT
RP T
. Hence, the RP T noise is larger by the factor RCT
RP T
5.3. The Basic Bandgap Circuit: An overview 123
• The PMOS transistor noise and the bipolar transistor noise see roughly the same
transfer function to the output. Moreover, their noise currents are multiplied by
the fairly lowimpedance gm1 Q reducing their eﬀect in comparison to the other terms.
Since gmQ = VITc , increasing current would reduce gm1 Q and, hence, reduce the eﬀect
of the PMOS and bipolar transistors on output noise. It is to be noted, however,
that for thermal noise increasing current would reduce the PMOS noise by a greater
√
factor than the bipolar noise (i2nqT hermal ∝ Ic whereas i2nmpT hermal ∝ Ic )
• A possible thermal noise optimization strategy (for reaching a speciﬁc noise power
spectral density) is:
Each of these sources adds an error to the output bandgap voltage. In the following
sections, the errors caused by each source will be analyzed
124 Chapter 5. Circuit Implementation
Consider an Opamp which has an inputoﬀset voltage Vos . The eﬀect of this oﬀset on the
bandgap output can be found by replacing Vop by Vos in ﬁgure 5.10 [Razavi 01]. Doing so,
and following the same procedure used in section 5.3.4 the output bandgap voltage can be
expressed as:
RCT
Vout = Vbe1 + . (VT . ln (N) + Vos ) (5.102)
RP T
As can be seen from equation 5.102, the Opamp’s input oﬀset voltage is ampliﬁed at the
output by the factor R CT
RP T
(a factor of almost 10 for N=8). Hence, the Opamp’s inputoﬀset
voltage is a major source of error in bandgap reference. While Vos in equation 5.102 is
5.3. The Basic Bandgap Circuit: An overview 125
assumed constant, it will be temperature and time dependent in practice. This means that
it can contribute signiﬁcant error  not only to the bandgap’s absolute value  but also to
its temperature curvature and longterm drift. It is to be noted that Opamp’s with bipolar
input pairs will have smaller oﬀset voltages than their CMOS counterparts [Sansen 06].
Besides, the oﬀset of a bipolar pair has a morepredictable (PTAT) temperature behavior
[Sansen 06].
To minimize the eﬀect of the Opamp’s oﬀset, chopping can be performed around the
Opamp as shown in ﬁgure 5.27 [Sanduleanu 98] [Lianxi 05] [Jiang 05] [Fruett 03]. This
has the added advantage of reducing the eﬀect of the Opamp’s ﬂicker noise at the bandgap
output.
With mismatch in the PMOS current sources, the two branches of the bandgap circuit
will have unequal currents as shown in ﬁgure 5.28. With a current I ﬂowing in Mp2 and a
current I+ΔI ﬂowing in Mp1 , the voltages Vbe1 and Vbe2 can be expressed as:
I+ΔI
Vbe1 = VT . ln
Is1
(5.103)
I
Vbe2 = VT . ln Is2
Where Is1 and Is2 are the reversesaturation currents of transistors Q1 and Q2, respec
tively. Hence, the PTAT voltage ΔVbe can now be expressed as:
Hence, the bandgap output voltage with PMOS mismatch can now be expressed as:
RCT RCT ΔI
Vout = Vbe1 + .VT . ln (N) + .VT . ln 1 + (5.105)
RP T RP T I
Hence, the mismatch ΔI between the PMOS current mirrors adds a PTAT error term
I
that is proportional to ln 1 + ΔI
I
. Note that ln (1 + y) ≈ y for small y. Hence, the error
126 Chapter 5. Circuit Implementation
RCT RCT ΔI
Vout ≈ Vbe1 + .VT . ln (N) + .VT . (5.106)
RP T RP T I
With typical 3σ values of 1% for ΔI I
[Gupta 07], the error term due to mismatch will
RCT VT
be equal to around RP T . 100 . This is a hundred times smaller than the PTAT term and,
hence, will contribute negligible error to the output.
Hence, to improve the matching accuracy the two terms of equation 5.107 need to be
minimized. The 2nd term can be minimized by increasing the transistor’s overdrive
voltage.
Δβ
The ﬁrst term, on the other hand, can be minimized by reducing the σ β . This can be
done by increasing the transistor’s area (σ Δββ
1
∝ √W.L ) [Hastings 00] [Sansen 06].
It is to be noted that random mismatch is not the only source of the current mis
match ΔI. Systematic mismatch in the Vds voltage of the two PMOS mirror devices can
contribute to current mismatch, due to the ﬁnite output impedance of MOS current mir
rors [Sansen 06]. For this very reason, the resistor RCT was placed in each of the two
branches of the bandgap circuit. This is not essential for the operation of the circuit. Nev
ertheless, it helps decrease the systematic mismatch between the Vds ’s of the two PMOS
current mirrors. However, even with RCT present in both branches there will still be sys
tematic mismatch since nodes 1 and 2 do not possess the same voltage (as a consequence
of the ﬁnite Opamp gain).
BJT mismatch will result from mismatch in the saturation current Is [Gupta 07]. Hence,
if Q1 has a saturation current Is and Q2 has a mismatched saturation current Is + ΔIs ,
then Vbe1 and Vbe2 (refer to ﬁgure 5.29)can be expressed as:
I
Vbe1 = VT ln
Is (5.108)
I
Vbe2 = VT ln N.(Is +ΔIs )
Following the same analysis performed in section 5.3.7.2, the output bandgap voltage
with BJT mismatch can be expressed as:
RCT RCT ΔIs
Vout = Vbe1 + .VT . ln (N) + .VT . ln 1 + (5.109)
RP T RP T Is
This equation takes the same form as equation 5.105 and the same conclusions made
on equation 5.105 can be drawn. Furthermore, the term ΔI
Is
s
of the BJT is typically smaller
ΔI
then the I of PMOS transistor [Sansen 06]. Hence, it will have a less pronounced eﬀect.
If the resistor RP T is made up of a unit resistor Runit , the resistor RCT should, ideally,
be made up of the same unit resistor Runit . Hence, if the desired R CT
RP T
ratio is X then ,
ideally, RCT = X.Runit . However, due to mismatch the resistor RCT will be made up of
the mismatched unit resistor Runit + ΔRunit . The output bandgap voltage with resistor
mismatch will, thus, be given by:
ΔRunit
Vout = Vbe1 + X.VT . ln (N) + X. .VT . ln (N) (5.110)
Runit
Where the ideal bandgap voltage is given by:
Vertical (substrate) PNP transistors are used for the reasons discussed in section 5.3.1.
The ratio N = 8 is used to allow a symmetric commoncentroid layout of the Bipolars as
shown in ﬁgure 5.32 [Mok 04]. Moreover, increasing N doesn’t help much in increasing the
slope of the PTAT voltage since it appears inside the argument of a logarithmic function.
Thus, N has to be increased by a very large amount to achieve a signiﬁcant change. This
makes N = 8 a favorable choice
To achieve a high loop gain without compromising noise, the noise (and power) eﬃcient
telescopic Opamp is used. It is a singlestage Opamp that can be easily compensated by its
load capacitance [Razavi 01]. To have the Opamp’s PSR close to one (which is required for
high overall rejection), the input pair uses NMOS transistors with a PMOS currentmirror
load (refer to section 5.3.5).
131
5.4. Bandgap Reference Voltage Implementation
Figure 5.31: Schematic for circuit 1 (startup not shown)
132 Chapter 5. Circuit Implementation
2 8 kT 8 kT.gmM pt1,2
vnop th ≈ . ∗2+ . ∗2 (5.112)
3 gmM nt1,2 3 gm2M nt1,2
And the total inputreferred ﬂicker noise power spectral density can be given as [Sansen 06]:
2 K K gm2M pt1,2
vnop f ≈ ∗2+ . ∗2 (5.113)
(W.L)M nt1,2 .Cox .f (W.L)M pt1,2 .Cox .f gm2M nt1,2
To decrease the Opamp’s noise, the following measures are taken:
• A large current is allocated to the Opamp (large enough to make the Opamp a non
dominant noise source). This allows achieving a high transconductance in the input
pair (gmM nt1,2 ). This, in turn, reduces the overall inputreferred noise voltage of the
5.4. Bandgap Reference Voltage Implementation 133
Opamp. For thermal noise, a high gmM nt1,2 will reduce the contribution of both the
NMOS and the PMOS transistors to the opamp’s inputreferred noise. For ﬂicker
noise, however, it only reduces the contribution of the PMOS transistors
• The W L
ration of the input pair is increased to increase gmM nt1,2 . To achieve the
maximum possible gm for a ﬁxed current, the transistors should be operated in the
subthreshold (weakinversion) region [Vittoz 03]). However, doing so at the chosen
current level would result in large sizing for the NMOS pair, which would,in turn,
result in large gate capacitance. This would cause stability problems when chopping
is used (refer to section 5.4.1.9.4). Hence, the transistors are sized to operate on the
verge of the weakinversion region (i.e. still operating in saturation but with very
small overdrive voltage Vef f )
• The transconductance of the PMOS currentmirror transistors (Mpt1 & Mpt2 ) was
minimized to reduce their contribution to the Opamp’s inputreferred noise. This
has two other advantages: it reduces their contribution to the Opamp’s inputoﬀset
voltage and it decreases the mismatch between them [Sansen 06]
• The W.L product of the PMOS transistors (Mpt1 & Mpt2 ) and the NMOS transistors
(Mnt1 & Mnt2 ) is increased to lower ﬂicker noise. This has the added advantage of
reducing the mismatch [Hastings 00] and, hence, the Opamp’s inputoﬀset voltage
5.4.1.2.2 SelfBias Loop for the Opamp To obtain the Opamp’s tail current, vari
ous techniques can be used. Two reasonable techniques are:
process variations of the NMOS transistor and the resistor as well as to the supply
(Vdd ) variations
Large variations in the Opamp’s tail current can be troublesome as they may disrupt
the designed DC operating points of the Opamp transistors, with some transistors going
into the linear region. This, in turn, causes a large reduction in the Opamp’s gain.
Another possible option  which provides a more controlled currrent  is to use the
current generated by the bandgap core itself. An illustration of this idea is shown in ﬁgure
5.34. The current in transistors Mp1 &Mp2 is mirrored by the PMOS transistor Mpsb . This
current is mirrored back to the Opamp’s tail current source providing the necessary tail
current. Noting that the bandgap core’s current is PTAT (≈ VT R. lnP T(N ) ), the Opamp’s bias
current will also be PTAT.
While this solution is attractive  saving area and reducing susceptibility to process
variations  it might impose a stability issue. This can be observed by refering to ﬁgure
5.34. It can be seen that the selfbias loop is actually a positive feedback loop. To avoid
instability, the loop gain of the selfbias loop should be well below unity over all the
frequency range. To gain understanding of the selfbias loop, qualitative analysis of the
loop is performed at DC and at very high frequencies (based on the discussion in [Perry 07]):
5.4. Bandgap Reference Voltage Implementation 135
• At DC, the small signal current imnt0 is divided evenly between the two input tran
sistors (Mnt1 & Mnt2 ). The PMOS load mirrors the current in Mnt1 , so that the total
small signal current in the Opamp’s output branch sums to zero. This makes the
gain from the Opamp stage zero and, hence, the overall positive feedback gain will
be very small (ideally zero)
Simulation of the selfbias loop gain is shown in ﬁgure 5.35. The loop gain is well below
unity over the whole frequency range, which ensures that the loop is stable.
136 Chapter 5. Circuit Implementation
5.4.1.2.3 Bias of the cascode transistors The circuit shown in ﬁgure 5.36 is used
to bias the PMOS cascode transistors [Gray 01]. Transistor Mpct is matched to transistors
Mpt3 &Mpt4 . Thus, transistors Mpct , Mpt3 and Mpt4 have the same current density (i.e. the
same I ratio) and, hence, the same overdrive voltage Vef f . The sourcedrain voltage
W/
L
Vsd lin of Mplin is given by:
To bias the NMOS cascode transistor, the circuit shown in ﬁgure 5.37 is used. Transistor
Mnct is matched to transistors Mnt3 &Mnt4 and has the same current density, and hence the
same overdrive voltage Vef f . With the arrangement shown in ﬁgure 5.37, the voltage at
the drain of the input NMOS transistor will be equal to VbeB (the Vbe of the bipolar used
for cascode biasing). Hence, the drain and gate voltage of input NMOS transistor will be
very close ensuring that it does not enter thr linear region with process variations.
It is worth noting that the bias bipolar transistor can be selected from the dummy
transistors that surround the bipolar transistor area Q1 and Q2 (for best matching per
formance, dummy devices are used in layout to assure that all transistors ”see” the same
surroundings [Hastings 00]). This is illustrated in ﬁgure 5.38.
Since minimum supply voltage is 2.4 V and the bandgap voltage is in the range of 1.2 V,
the Vsd on each of the PMOS current mirrors will be more than 1.2 V. This is a fairly large
value which always cascodes to be used comfortably. While troublesome in their biasing,
cascodes provide the advantage of decreasing the systematic current mismatch between the
two transistors (Mp1 &Mp2 ) as it equalizes the Vsd of both transistors. Besides, cascoding
improves the current mirror output impedance which helps in improving the circuit’s supply
138 Chapter 5. Circuit Implementation
rejection. The additional RCT resistor in the Mp2 transistor’s current branch ensures an
even better matching of Vsd ’s. The cascode transistors are biased by the same technique
that was used for the Opamp’s cascodes.
The resistors used are base poly resistors, which have the smallest process variation
and temperature drift in the used technology [aus 04b]. To achieve best matching, RP T
and RCT are made up of the same unit resistance [Hastings 00].
Bandgap circuits require startup circuitry to ensure they will operate as expected [Razavi 01].
The startup circuit used for circuit 1 is shown in ﬁgure 5.39. This startup circuit is adopted
from [Khan 03], with some modiﬁcation. The operation of the circuit can be explained as
follows:
• When the supply is powered on, the output voltage Vbg is initially zero. Hence,
transistor Mst1 is turned oﬀ and its output is pulled to Vdd by the pullup resistor
Rst . This, in turn, means that transistor Mst2 is turned on, pulling the gates of the
PMOS transistors Mp1 and Mp2 to ground. This ensures that there will be current
ﬂowing through the circuit in the startup phase, avoiding the zero solution
• When Vbg reaches its steady state value, Mst1 is turned on and its output is zero.
Thus, Mst2 is oﬀ, allowing the voltage at the gates of Mp1 and Mp2 to take its correct
value. In this case, the current dissipated by the startup circuit is that ﬂowing in Rst .
Hence, Rst is made large to dissipate a small current. For this speciﬁc implementation,
the steady state current in Rst is around 10μA
Figure 5.40 shows the output bandgap voltage Vbg versus temperature. With a 1st
5.4. Bandgap Reference Voltage Implementation 141
order compensation, the circuit achieves a total variation across temperature of 3.9mV,
corresponding to a temperature coeﬃcient (tempco) of approximately 20ppm/◦ C.
Circuit 1 achieves a phase margin of 77◦ and a gain margin of 16dB. To achieve this
performance, a compensation capacitor of 40pF is inserted between the Opamp’s output
node and Vdd . The capacitor is implemented by using a PMOS transistor as a capacitor.
It is to be noted that the added RC ﬁlter doesn’t degrade stability. In fact, it can help
improve stability. To illustrate this, consider ﬁgure 5.42 which shows the small signal model
of the output branch. The voltage vbg can be expressed as:
1
Req Rf + sCf
vbg = iout . 1 (5.116)
Req + Rf + sCf
Where Req is the equivalent AC resistance seen into the drain of the PMOS transistor.
(1 + sCf Rf )
vbg = iout .Req (5.117)
1 + sCf (Rf + Req )
5.4. Bandgap Reference Voltage Implementation 143
Hence, the ﬁlter adds a zero and a pole. If Rf >> Req , the zero and pole frequency will
be close and hence cancel each other. Noting that any load capacitance would be added
in parallel to Cf , it can be seen that the ﬁlter can help improve the circuit’s stability
performance in the presence of capacitive loading. The gain and phase response of the
circuit are shown in ﬁgure 5.43.
Figure 5.44 shows the output noise power spectral density of output bandgap voltage. It
can be noted that:
√
• The circuit achieves a noise power spectral density of 2.5nV / Hz at 400 KHz (after
the output ﬁlter).
• The noise power spectral density in the low frequency range (1mHz  100Hz) is much
higher. The total integrated noise in the 1mHz  100Hz range is 6μV approximately,
which is about 6 times the higher than the required value of 0.9μV
Table 5.4 shows the major noise contributors in the 1mHz  100Hz range (obtained
using Spectre
R circuit simulator). Clearly, the ﬂicker noise of the Opamp transistors is
the major contributor to noise in this range of interest. Hence, it is of great value if the
Opamp’s ﬂicker noise can be reduced, which will be discussed in the following sections.
(a) Gain
(b) Phase
As shown in the previous section, the Opamp’s ﬂicker noise is the major source of noise in
the low frequency range of interest. One possible solution to reduce the Opamp’s ﬂicker
noise is to use chopping around the Opamp. This has the added advantage of reducing the
eﬀect of the Opamp’s inputoﬀset voltage [Sanduleanu 98] [Lianxi 05] [Jiang 05].
To understand the eﬀect of chopping, consider ﬁgure 5.45. The ampliﬁer’s input signal
is multiplied by a square wave with frequency fchop , modulating the input signal into
a higher frequency. Hence, the ampliﬁer eﬀectively ”sees” the input signal modulated
on a carrier. On the other hand, the ampliﬁer’s ﬂicker noise (& oﬀset) reside in lower
frequencies. This can be regarded as a form of frequencydivision multiplexing between
the input signal and the ampliﬁer’s low frequency noise components. At the ampliﬁer’s
output, the ampliﬁed input signal is dechopped (i.e. demodulated ) by the same square
wave, whereas the ampliﬁed low frequency noise is modulated into a higher frequency. A
ﬁlter can then be used to get rid of the unwanted noise in the higher frequency band.
5.4.1.9.1 Choosing the chopping frequency To choose the proper chopping fre
quency, two factors have to be taken into consideration:
1. The input signal is modulated onto the chopper frequency before getting ampliﬁca
tion. Hence, the input signal is eﬀectively present at the chopping frequency. Thus,
5.4. Bandgap Reference Voltage Implementation 147
care must be taken that the chopping frequency lies within the system’s ﬂatgain
region. Two cases can be diﬀerentiated in this regard:
(a) If the Opamp is operated in openloop (which is not our case), the chopping
frequency must be less than the Opamp’s dominant pole frequency (if the max
imum Opamp gain is to be exploited)
(b) If the Opamp is operated in a closedloop (which is our case), the chopping
frequency must lie within the bandwidth of the closed loop or, alternatively,
within the unity gain frequency of the system’s open loop gain
2. The ﬂicker noise is modulated onto the chopper frequency. Hence, if the ﬂicker noise
is to be totally eliminated, the chopping frequency must be high enough to ensure
that the ﬂicker noise tail doesn’t appear in the bandwidth of interest(as shown in
ﬁgure 5.46). This can be formally expressed as:
Where:
fchop is the chopping frequency
fcorner is the ﬂicker noise corner
fBW is the desired bandwidth
148 Chapter 5. Circuit Implementation
Since the system’s clock is 409.6kHz, using a chopping frequency of 409.6kHz or its
dividends is possible. This is further discussed in the following section (section 5.4.1.9.2).
5.4.1.9.2 Eﬀect of Chopped Oﬀset on SNR The Opamp’s input oﬀset will cause
the generation of a square wave at the chopping
frequency.
The amplitude of this square
wave can be shown to be equal to Vos ∗ 1 + RP T . MonteCarlo simulations show that
RCT
the 3σ equivalent oﬀset at the Opamp’s input is about 0.6mV (ﬁgure 5.47).Thus, the
reference voltage to the ΣΔ ForceFeedback loop will be a constant DC voltage with a
superimposed square wave (representing the chopped oﬀset voltage). Since the feedback
voltage is the multiplication of the reference voltage and the ΣΔ output bitstream, the
presence of a square wave component may cause the ΣΔ outofband noise to fold into the
inband region. To assess the eﬀect of this ”spur” on the system’s performance, two cases
are considered: fchop = 409.6kHz (i.e. fchop = ΣΔ Clock frequency) and fchop = 204.8kHz
(i.e. fchop = 12 ΣΔ Clock frequency)
The output of the bandgap with a chopping clock is shown in ﬁgure 5.48. As expected,
the output is the dc bandgap value (1.2V ) with a squarewave superimposed with an
5.4. Bandgap Reference Voltage Implementation 149
CT 3
amplitude of 20mVpp (corresponding to Vos ∗ R RP T
) . Simulations are made on the ΣΔ
Forcre Feedback system using an ideal reference (i.e. with no chopping) and the reference
chopped at 409.6kHz, and 204.8kHz (and not ﬁltered). The output spectra for the three
cases are shown in ﬁgure 5.49
Choosing a chopping frequency equal to the ΣΔ clock frequency has no eﬀect on the
output SNR. This can be qualtitatively explained by the fact that, for each ΣΔ clock
cycle, the chopped bandgap alternates between Vbg + Δv and Vbg − Δv , averaging to Vbg
over each cycle. Hence, the ΣΔ loop eﬀectively ”sees” a DC voltage and is insensitive
to the superimposed square wave. On the other hand, choosing a chopping frequency
equal to half of the ΣΔ clock frequency leads to a severe degradation in SNR (as can
be observed in ﬁgure 5.49). With a frequency equal to half the ΣΔ clock frequency, the
chopping square wave will have a spur in the frequency domain at f2s , coinciding with
the point that has the highest outofband noise in the ΣΔ output spectrum. Since the
reference voltage is eﬀectively multiplied by the output bitstream to form the feedback
force, the presence of this spur leads to downconversion of large outofband noise back
to DC causing severe SNR degradation. Following the same line of reasoning, choosing a
smaller chopping frequency might cause a similar noise folding eﬀect, as the outofband
3
Vos is set to 1mV in this simulation
150 Chapter 5. Circuit Implementation
noise is high over a relatively wide frequency range. Using a very low chopping frequency
will violate the condition of equation 5.118, making it ineﬀective in reducing ﬂicker noise.
Hence, choosing fchop = fs is the best choice for preserving the SNR.
The above simulations are performed using NRZ pulse shape. For a 50% RZ pulse
shape, the chopping frequency should be increased to 2 × fs i.e. 819.2kHz.
• The conﬁguration shown in ﬁgure 5.50(a) [Sanduleanu 98] has a set of switches at
the input of the Opamp that chop the input signal to the chopping frequency fchop .
The dechopping (demodulation) is performed by switches in series with the Opamp’s
cascode transistors. The dechopping eﬀectively inverts the Opamp’s output polarity
whenever the input is inverted, so that the feedback remains negative throughout the
chopping operation. It is to be noted that the dechopping switches are connected
1
to the sources of the cascode transistors. Hence, they see a low impedance ( gm )
5.4. Bandgap Reference Voltage Implementation 151
(a) Conﬁguration of [Sanduleanu 98] (b) Conﬁguration of [Lianxi 05] [Jiang 05]
with a welldeﬁned potential. This is an advantage for the switch. On the other
hand, having the switch in series with the Opamp’s cascode transistors may impose
a limitation specially if a large current is used in the Opamp. The switch’s IR drop
must be low enough in order not to aﬀect the DC operating point of the Opamp’s
transistors
• The conﬁguration shown in ﬁgure 5.50(b) [Lianxi 05] [Jiang 05] is similar to the ﬁrst
one when it comes to the input chopping switches. However, the output chopping
switched are not placed in series with the Opamp’s transistor. Hence, they do not
aﬀect the Opamp’s DC operating point
Due to the low noise, and large current used in the Opamp, the second conﬁguration
(ﬁgure 5.50(b)) is used.
the Opamp’s input pair has a large size (for oﬀset and ﬂicker noise reduction), the input
pair’s gate capacitance is high. The switch and the gate capacitance represent a series RC
section and, hence, add a pole to the open loop gain. If the switch resistance is high, this
pole can be low enough to harm the stability (i.e. reduce phase and gain margins) of the
loop. Hence, care has to be taken in switch sizing.
5.4.1.9.5 Filtering the Chopped reference The oﬀset and ﬂicker noise are mod
ulated onto the high frequency chopping signal. The eﬀect of oﬀset is more pronounced
as it is a larger signal. A ﬁlter is, thus, needed to remove this high frequency noise. An
important thing to consider is where to place this ﬁlter. Two options are viable:
1. The ﬁlter can be placed at the Opamp’s output (directly after dechopping) as shown
in ﬁgure 5.51(a). This is a common practice. However, for the choppedbandgap it
will impose a problem. The Opamp in the choppedbandgap circuit is placed inside
a feedback loop. In absence of the ﬁlter, the feedback adjusts the amplitude of the
5.4. Bandgap Reference Voltage Implementation 153
modulated oﬀset such that, after it is demodulated by the Opamp’s input choppers,
it cancels the Opamp’s input oﬀset (the input to the Opamp has to be very small
or othersiwse the Opamp will saturate). The ﬁlter at the Opamp’s output opens
the feedack path, preventing this cancellation. The Opamp’s input oﬀset may, thus,
cause saturation of the Opamp’s output
2. The ﬁlter can be placed at the output of the feedback loop as shown in ﬁgure 5.51(b).
This overcomes the problem of opening the feedback path of the oﬀset signal and,
hence, allows better performance. This option is adopted in this work
5.4.1.9.6 Noise Performance of the Chopped bandgap Figure 5.52 shows the
output noise of the bandgap reference with and without chopped Opamp (simulations per
formed using SpectreRF R
). The lowfrequency noise power spectral density has decreased
signiﬁcantly from the unchopped case. The total integrated noise voltage in the 1mHz 
154 Chapter 5. Circuit Implementation
100 Hz region is 0.97μV . The dominant noise source in this region is the bipolar transistor.
It is to be noted that after chopping the Opamp, the dominant ﬂicker noise sources will
be the PMOS mirrors and the Bipolars. By design, the PMOS current mirrors are made
nondominant. Hence, the dominant ﬂicker noise source will be the bipolar transistors
(which is the minimum limit that this circuit can reach)
Process variations will change the parabolic characteristics of the bandgap voltage from the
one designed at typical conditions. Hence, provisions must be made to enable the trimming
of the reference back to the ideal characteristics to achieve the minimum possible variation
of bandgap voltage across temperature. If 1st order temperature compensation is used,
there will be a single voltage value that achieves the best performance across temepera
ture (the socalled ”magic voltage” Vmagic ) [RinconMora 06] [Gupta 07] [Pease 90]. The
trimming process can, thus, be simply done by a singlepoint trimming for the value of the
bandgap voltage to reach Vmagic . A detailed method for obtaining the value of Vmagic for a
1st order compensated bandgap reference can be found in [RinconMora 06].
Trimming can be done by changing the PTAT voltage. This, in turn, can be done by
several methods:
1. Changing the value of RCT using a digital word [Gupta 07]. In this case, RCT would
be composed of a ﬁxed part and a trimmable part as shown in ﬁgure 5.53. The
trimmable part can be implemented as shown in ﬁgure 5.53; the digital word controls
MOS switches that shunt the resistors. This approach will impose a problem if a
relatively high trimming resolution is needed. A high trimming resoluton translates
to a small value for the trim resistor. This, in turn, means that an even smaller
resistance is needed for the MOS switch. For lownoise operation, RCT would be
small and a high resolution would translate to a prohibitively small value for the
MOS onresistance
2. Changing the value of RCT using lasertrimming. Laser trimming can be used to
change the dimensions of the resistor RCT and, hence, its value. High accuracy can
5.4. Bandgap Reference Voltage Implementation 155
be achieved by this method. The problem with lasertrimming, however, is its high
cost [Gupta 07]
3. Changing the currentmirroring ratio of the PMOS mirror. Instead of a 1:1 ratio, a
ratio of 1:1+ΔM can be used. This can be done by dividing transistors Mp1 and Mp2
into a number of ﬁngers (Nf ing ). With no trimming, the number of ﬁngers of Mp1 is
equal to that of Mp2 and both are equal to Nf ing (i.e. Nmp1 = Nmp2 = Nf ing ). To
trim, extra ﬁngers Ntrim are connected in parallel to either Mp1 or Mp2 . Fingers added
to Mp2 will increase the PTAT voltage, whereas adding ﬁngers to Mp1 decreases the
PTAT voltage. The voltage Vout in ﬁgure 5.54 can be expressed as:
RCT Nmp2
Vout = Vbe1 + .VT . ln N. (5.119)
RP T Nmp1
Nmp2
This is basically the same as equation 5.14 but replacing M by Nmp1
. The above
equation can be further expanded into:
RCT Nmp2
Vout = Vbe1 + .VT . ln (N) + ln (5.120)
RP T Nmp1
Hence, if ﬁngers are added to Mp2 then Nmp2 = Nf ing + Ntrim . Hence, Vout can be
expressed as:
RCT N +Ntrim
Vout = Vbe1 + .VT . ln (N) + ln f ing
RP T
Nf ing
(5.121)
RCT Ntrim
= Vbe1 + RP T .VT . ln (N) + ln 1 + Nf ing
Ntrim Ntrim
Since Nf ing
will be typically smaller than one, ln 1 + Nf ing
can be approximated to
Ntrim 4
Nf ing
. With this approximation, Vout would be expressed as :
RCT Ntrim
Vout = Vbe1 + .VT . ln (N) + (5.122)
RP T Nf ing
4
based on the assumption that: Nmp2 = Nf ing + Ntrim and Nmp1 = Nf ing . If Nmp1 = Nf ing + Ntrim
and Nmp2 = Nf ing , a negative sign should be added to N trim
Nf ing
5.4. Bandgap Reference Voltage Implementation 157
1
To see why this can achieve a high resolution, consider the case of N trim
Nf ing
= 10 . If
N = 8, ln (N) will be almost equal to 2. Hence, the relative increase in the PTAT
voltage will be approximately 5%. If RCT trimming is used, then with an RCT of
5KΩ, achieving a 5% change in PTAT voltage would require adding a resistance of
250Ω in series. This, in turn, means that the on resistance of all the switches in series
with the 250Ω must be signiﬁcantly less than 250Ω e.g. 25Ω which is an impractical
value
Based on the above discussion, the 3rd option was chosen. With Nf ing = 40, simulations
show that the maximum required value for Ntrim is 16. A similar technique was adopted for
trimming in [Perry 07]. Figure 5.55 shows the trimmed and untrimmed bandgap voltage
for the corner with worst variation across temperature (fastest CMOS, smallest resistors,
lowestβ BJT). The untrimmed bandgap voltages varies by 52mV in this corner; this
variation decreases to 2.74mV after trimming.
A direct approach for using bipolar input pairs is to simply replace the NMOS transistor
with npn transistors in the circuit of ﬁgure 5.31. This, however, is not a viable solution due
to headroom limitations. To understand this limitation consider ﬁgure 5.57 which shows
the suggested connection. An npn bipolar input pair is used with an NMOS current source.
This connection will clearly limit the headroom available for the NMOS current source.
The input to each of the npn transistors is the Vbe voltage of the pnp transistor which
would be in the order of 0.6V0.7V. Similarly, the Vbe of the npn input pair is in the same
order. This means that the tail NMOS current source will have a very limited (nearzero)
headroom which would not be suﬃcient for operating it in the saturation region (which is
the most favorable region for operation of MOS current sources [Sansen 06]).
To overcome this headroom limitation, two bipolar transistors are connected in series
as shown in ﬁgure 5.56 [Razavi 01]. This would allow the tail NMOS current source a
headroom of one Vbe . As an added advantage, the shown connection allows one to obtain an
output voltage equal to double the bandgap voltage (i.e. 2.4V instead of the 1.2V of circuit
1). The 2.4V output can be taken from the Vbg2 terminal. Furthermore, the conventional
5.4. Bandgap Reference Voltage Implementation 159
1.2V bandgap can also be obtained from the same circuit by taking the output from Vbg1 .
Refering to the circuit of ﬁgure 5.56, the voltage V1 can be expressed as:
I = VR2 −V x
PT
(5.125)
= (Vbe1 +Vbe3R)−(V
PT
be2 +Vbe4 )
If transistor Q1 and Q2 are matched with an area ratio of N and equal currents I, and
transistor Q3 and Q4 are matched with an area ratio of N and equal currents I , then:
RCT
Vbg2 = Vbe1 + Vbe3 + 2.VT . . ln (N) (5.127)
RP T
Due to the exponential Ic − Vbe characteristics of bipolar transistors, Vbe1 and Vbe3 will
be almost equal even for diﬀerent currents I and I . Hence, the approximation Vbe1 ≈
Vbe3 = Vbe can be used allowing equation 5.127 to be expressed as:
RCT RCT
Vbg2 ≈ 2.Vbe + 2.VT . . ln (N) = 2. Vbe + VT . . ln (N) = 2.Vbg (5.128)
RP T RP T
Where Vbg is the conventional 1.2V bandgap voltage.
On the other hand, the voltage Vbg1 can be expressed as:
RCT 2
Vbg1 = Vbe4 + 2.VT . . ln (N) (5.129)
RP T
Thus, Vbg1 is no more than the conventional bandgap voltage. The factor 2 in the above
equation means that the ratio RRCT
PT
2
will be half the conventional value (which reduces the
eﬀect of the Opamp’s input oﬀset on Vbg1 [Razavi 01])
The use of a bipolar input pair in circuit 2 leads to the achievement of a high gain, even
without the use of cascode transistors. This can be attributed to the large transconductance
of bipolar transistors compared to their MOS counterparts. Hence, the Opamp used for
circuit 2 consists of a simple bipolar input pair with a PMOS currentmirror load. This
simple circuit allows achieving a loop gain of 67dB without cascoding.
arbitrarily low or otherwise the bipolar input pair would get out of the active region. With
a base voltage of roughly 1.4V, the collector voltage of the bipolar pair should not decrease
below 1.4V. This limits the ﬂexibility of adjusting the Vef f of the PMOS mirrors. Likewise,
the PMOS load of the Opamp has to have a relatively small overdrive Vef f in order not to
get the bipolar pair out of the forwardactive region. This requirement is against the noise
considerations which favors decreasing the overdrive of the PMOS loads.
5.4.2.3.2 Opamp tail current The current needed by the Opamp is determined by
noise considerations. At low currents, the transconductance of the input pair is low. As
a result, the ﬂicker noise of the PMOS mirror load will dominate the inputreferred ﬂicker
noise of the Opamp. At large current, the ﬂicker noise of the bipolar input pair increases
(the inputreferred ﬂicker noise of the bipolar transistor is proportional to its base current
[aus 04a]). Hence, an optimum value exists for the bias current that achieves the minimum
input referred ﬂicker noise. Figure 5.58, shows the output noise on Vbg2 versus the Opamp’s
5.4. Bandgap Reference Voltage Implementation 163
5.4.2.4 Choosing I
Another important noise consideration is the choice of the current I . The current I is
used to bias transistors Q3 and Q4. From a DC point of view, it is tempting to decrease
the current I as Vbe is a relatively weak function of I . This, however, is not favored from
the noise point of view. Decreasing I leads to increasing the resistance seen into Q3 and
Q4 ( gm1Q3,4 ). This, in turn, increases the output noise voltage on the collectors of Q3 and
Q4, leading to an increase in the output noise voltage on Vbg2 . Hence, if the current I
is decreased transistors Q3 and Q4 can easily become the dominant ﬂicker noise sources.
Simulations show that setting I = I is a good choice to avoid this situation and decrease
the overall ﬂicker noise.
Figure 5.59 shows the output bandgap voltage Vbg2 . The peaktopeak variation in volt
age across the 40◦C125◦ C temperature range is 7mV , corresponding to a temperature
coeﬃcient of approximately 18ppm/◦ C.
Figure 5.60 shows PSR of circuit 2 (on the 2.4V reference). An output ﬁlter is used to
improve the high frequency rejection as was done in circuit 1.
Figure 5.61 shows the output noise psd of the reference voltage Vbg2 . The use of bipolars
in the Opamp allows the achievement of low ﬂickernoise without resorting to chopping.
The circuit achieves a total integrated noise voltage of 1μV in the frequency range 1mHz
 100Hz.
164 Chapter 5. Circuit Implementation
The temperature dependent equation of the Bipolar’s Vbe voltage can be expressed as
[Meijer 82]:
k.Tr k T
Vbe (T ) = Vg0 + (η − m) . − λ.T + (η − m) . . T − Tr − T. ln (5.130)
q q Tr
Where:
Vg0 is the extrapolated bandgap voltage of Silicon at 0 Kelvin
λ is a constant that represents the slope of the linear component of Vbe (T )
Tr is the reference temperature
η is a process constant
m is the temperature exponent of the collector current Ic 5
A ﬁrst order temperature compensation scheme cancels the linear term only (λ.T ),
leaving the higher order nonlinearities. It is to be noted that, for ﬁrst order compensation,
the nonlinear terms vanish at T = Tr . This explains why the parabolic curve (of a 1st
order compensated reference)is
ﬂat at T = Tr . The curve is parabolic because the non
linear term (η − m) . q . T − Tr − T. ln Tr
k T
can be approximated by Taylor expansion
2
r (T −Tr )
as − 12 . (η − m) . k.T
q
. Tr
To cancel the higher order nonlinear term totally, two approaches are possible [Hol
man 94]:
5
It is assumed that Ic ∝ T m . For a PTAT Ic , m=1. For a constant Ic , m=0
5.4. Bandgap Reference Voltage Implementation 167
1. Setting m = η i.e. biasing the bipolar transistor (responsible for generating Vbe ) with
a current Ic ∝ T η . Since η is a process constant whose value is around 4, this means
that a P T AT 4 current would be needed. Such a current is very hard to generate in
practice, making this approach impractical.
2. Using the scaled diﬀerence of two Vbe voltages, one biased with a constant current
and one biased with a PTAT current, to generate a more linear voltage Vbe lin . To
illustrate how this can be done, consider the Vbe of a bipolar transistor biased with a
PTAT current. Substituting into equation 5.130 with m=1, the Vbe of this transistor
(Vbem1 ) can be expressed as:
kTr k T
Vbem1 (T ) = Vg0 + (η − 1) . −λ.T +(η − 1) . . T − Tr − T ln (5.131)
q q Tr
Similarly the Vbe of a bipolar transistor biased biased with a constant current Vbem0
can be expressed as:
kTr k T
Vbem0 (T ) = Vg0 + η. − λ.T + η. . T − Tr − T ln (5.132)
q q Tr
A linear Vbe can now be obtained that is free of the higher order nonlinearity. This
can be done by setting:
This is a very interesting result as it allows the total elimination of the nonlinear
terms unlike the other temperature compensation techniques that just minimize this
term [Gunawan 93] [Malcovati 01] [Song 83] [Lee 94] [RinconMora 98] [Leung 03].
The linear temperature variation of Vbe lin can easily be compensated by a PTAT
voltage (in the same manner used for 1st order compensated bandgaps) to obtain a
bandgap voltage with very low temeprature variation.
The 2nd approach in the above discussion will be dubbed ”The ZeroTC technique”
hereafter.
168 Chapter 5. Circuit Implementation
R1
Vx = I1 .R1 + 4.Vbem1 = VP T AT . + 4.Vbem1 (5.134)
R0
The Vbe of the transistors carrying the current I1 is named Vbem1 because these tran
V
sistors are biased by the PTAT current I1 . The current I2 is simply equal to Rref 2
. Since
Vref is the temperatureindependent voltage, the current I2 will be similarly constant with
temperature i.e. the bipolars biased with I2 have Vbe = Vbem0 . Hence, the voltage Vref can
be expressed as:
R1
Vref = Vx − 3Vbem0 = VP T AT . + 4.Vbem1 − 3Vbem0 (5.135)
R0
5.4. Bandgap Reference Voltage Implementation 169
With η = 4, the voltage 4.Vbem1 − 3Vbem0 is actually the the linearized Vbe voltage
(Vbe lin ) i.e. 4.Vbem1 − 3Vbem0 = η.Vbem1 − (η − 1) .Vbem0 = Vbe lin = Vg0 − λ.T . This allows
equation 5.135 to be reexpressed as:
R1
Vref = Vg0 −λ.T+VP T AT . (5.136)
R0
By adjusting VP T AT . R1
R0
to cancel the linear term −λ.T, a very high performance (very
low temperature drift) reference can be obtained.
While this circuit is compact and elegant, it has three major drawbacks:
1. It needs a high supply voltage. With 4 bipolar transistors in series, a supply voltage
of at least 2.8V would be needed for the bipolars only. An even higher supply would
be needed to accomodate the PTAT current source biasing those bipolars, as well as
the PTAT voltage V1 (refer to ﬁgure 5.62)
2. It relies on npn transistors that are not normally available as a standard option in
today’s CMOS technologies
3. The factors η and η − 1 are obtained by the cascading of Vbe ’s. This means that if η
is non integer  as is the practical case [Holman 94]  the perfect cancellation point
cannot be achieved (not even conceptually)
These drawbacks suggest that a diﬀerent implementation is needed for the same com
pensation technique if it is to be implemented in current CMOS technologies.
Vbe lin
Ivbe lin = (5.137)
Rvbe
170 Chapter 5. Circuit Implementation
This current is dumped in the resistor Rref to generate the desired Vbe s  which is a
scaled version of the ideally compensated Vbe lin . Hence:
Rref
Vbe s = .Vbe lin (5.138)
Rvbe
To cancel the linear term of the scaled voltage Vbe s , a PTAT current IP T can be dumped
into the same resistor Rref as shown in ﬁgure 5.63(b). If the current IP T = VR P T AT
PT
, then
the reference voltage Vref in ﬁgure 5.63(b) can be expressed as:
R
adjusted to cancel the linear temperature variation term (−λ.T ) of Vbe lin and Rref
vbe
can be
used to scale the reference as desired. This form would allow a lowsupply operation, if the
R
generation of Ivbe lin does not mandate a high supply voltage. Note that even for Rref
vbe
= 1,
lower supply can be used as there is no need for cascading of Vbe ’s.
Generation of Ivbe lin can be conceptually done as shown in ﬁgure 5.64. A current
Ivbem0 = (η−1).Vbem0
Rvbe
is subtracted from a current Ivbem1 = η.VRbem1
vbe
. Hence, Ivbe lin can be
expressed as:
Hence, the problem of generating the current Ivbe lin translates into the problem of
generating the two currents Ivbem1 and Ivbem0 . The circuits shown in ﬁgures 5.65(a) and
5.65(b) can be used for this purpose. Feedback in both circuits ensures that the positive
and negative Opamp terminals track each other. Hence, the input voltage (either Vbem0
V
or Vbem1 ) is applied  through feedback  to the resistor Rvbe generating a current bem0,1
Rvbe
.
Ivbem1 is a ”source” current. Hence, Ivbem1 is generated by simply mirroring the current
in the PMOS transistor with a ratio of 1 : η. This allows η to take any arbitrary value,
that can also be a fraction. On the other hand, Ivbem0 is a ”sink” current. Hence, Ivbem0 is
implemented by mirroring VRbem0
vbe
and dumping it into a diode connected NMOS transistor.
172 Chapter 5. Circuit Implementation
The current in the NMOS is then mirrored by a ratio of 1 : (η − 1), hence forming the
”sink” current source. Again, 1 : (η − 1) is a mirroring ratio that can take any arbitrary
value, in principle.
Now, it remains to implement the voltages Vbem0 and Vbem1 . This can be easily imple
mented by the circuit shown in ﬁgure 5.66. This circuit is a modiﬁed version of the circuit
in [Banba 99] and [Malcovati 01]. The current IP T i in transistors Q1 and Q2 is a PTAT
current given by:
VT . ln (N)
IP T i = (5.142)
RP T i
Hence, each of Q1 and Q2 is biased with a PTAT current. Any of them can be used
as the source of Vbem1 . To get Vbem0 , the current Iconst is dumped into the diodeconnected
transistor Q3 . Iconst is given by:
Vbem1 VT . ln (N)
Iconst = + (5.143)
RCT i RP T i
Hence, an Iconst with a 1st order temperature compensated behavior can be obtained
by adjusting the RCT i to RP T i ratio. Hence, the Vbem0 voltage can be obtained from Q3 .
Finally, the compensating current IP T (which is a PTAT current) can be easily imple
mented by the circuit of ﬁgure 5.67.
5.4. Bandgap Reference Voltage Implementation 173
Based on the above discussion, the full circuit implementation of the suggested reference
is shown in ﬁgure 5.68. The PTAT compensation circuit that generates IP T is shown
separately in ﬁgure 5.69. The Opamp used is shown in ﬁgure 5.70. The bias current i ota
for all Opamps is mirrored from the constantcurrent Iconst generation circuit. The ratio
Rref
Rvbe
is chosen to be unity. All current mirrors are cascoded for best performance. To
summarize, the circuit blocks used for implementing the reference are:
1. The constant current Iconst generating circuit shown in ﬁgure 5.66. This circuit
provides both Vbem0 and Vbem1
To achieve the best temperature coeﬃcient, simulations show that a very high reso
lution is needed for the resistor RP T (the resistor that controls the slope of the PTAT
compensation current IP T ). The resolution needed is impractically high. To solve this
problem, a value was chosen for RP T that allows it to be matched to Rvbe . To get the
desired resolution, the technique described in section 5.4.1.10 is used, where Nf ing = 400
and Ntrim = 10. The circuit dissipates 1.8mA from a 3V supply. The circuit’s estimated
area is 1200μm × 1200μm.
5.4. Bandgap Reference Voltage Implementation 175
Figure 5.68: Schematic for circuit 3
176 Chapter 5. Circuit Implementation
Figure 5.71(a) shows the output DC voltage of circuit 3 versus temperature. The circuit
is optimized for smallest variation across temperature with η = 6.4. Furthermore, the
PTAT compensation strategy discussed in the previous section was used. The circuit
achieves a peaktopeak variation of 100μV across the temperature range 40◦ C125◦C,
which corresponds to a temperature coeﬃcient of 0.55ppm/◦ C. This is a 30 times smaller
variation than the previous two circuits. For comparison, the bandgap voltages of circuits
1 and 3 are shown on the same graph in ﬁgure 5.71(b) (both voltages scaled to have almost
equal values at the middle of the temperature range).
(a) HigherOrder compensation output (b) Higherorder versus 1st order compensation
To further assess the performance of this circuit, it is simulated at two corners (corre
sponding to maximum and minimum resistance value) and its dc performance is compared
to that of the 1st order compensated circuit (circuit 1). With no trimming, the higherorder
compensated circuit (circuit 3) has better performance in both corners than its correspond
ing 1st order compensated counterpart (circuit 1).
Figure 5.72 shows the DC performance of circuit 1 and circuit 3 for the corner corre
sponding to the minimum resistor value. Both circuits deviate from their performance in
5.4. Bandgap Reference Voltage Implementation 179
the typical resistor corner. Nevertheless, the higher order compensated circuit achieves a
smaller variation across temperature: its peaktopeak variation is only 7mV (correspond
ing to a tempco of 38ppm/◦ C), as opposed to a 36mV peaktopeak variation for 1st order
compensation (corresponding to a tempco of 188ppm/◦ C)).
Figure 5.72: Higherorder and ﬁrstorder compensation for smallest resistance corner
Figure 5.73 shows the DC performance of circuit 1 and circuit 3 for the corner corre
sponding to the maximum resistance value. The higher order compensated circuit achieves
a peaktopeak variation of only 6mV (corresponding to a tempco of 33ppm/◦ C), as op
posed to a 48mV peaktopeak variation for 1st order compensation (corresponding to a
tempco of 256ppm/◦ C)).
Figure 5.74 shows the PSR of circuit 3. The use of cascoded current mirrors together with
the relatively small value used for Rref (which was done for noise considerations) allow
achieving large rejection. A ﬁlter is also added following the reference voltage to ﬁlterout
high frequency supply variations, allowing high rejection at higher frequencies.
180 Chapter 5. Circuit Implementation
Figure 5.73: Higherorder and ﬁrstorder compensation for largest resistance corner
Figure 5.75 shows the output noise PSD for circuit 3. Circuit 3 has signiﬁcantly higher
noise than circuits 1 and 2. The major noise contributors are the current mirrors that
constitute the η and η − 1 ratios. This can be attributed to their large currents and, hence,
large gm which increases both thermal and ﬂicker noise components. The circuit achieves
a total integrated noise voltage of 11μV in the frequency range 1mHz100Hz. Decreasing
the resistance Rref , in general, decreases the output noise.
This can be explained by writing the expressions of the output thermal and ﬂicker noise
voltages due to the η and η − 1 currenr mirrors. These can be given by:
2
vthermal = 83 .k.T.gm.Rref 2
K.gm2 (5.144)
vf2licker = W.L.C ox .f
2
.Rref
It is to be noted that the transconductance gm is proportional to the square root of
the dc current ﬂowing in the transistor. If this transistor represents the η or η − 1 current
182 Chapter 5. Circuit Implementation
1
mirrors, then the current ﬂowing in it would be proportional to Rvbe . The ratio of Rref to
Rvbe is constant for a speciﬁc reference value. For this speciﬁc implementation, Rref = Rvbe .
2 1.5
It can, thus, be concluded that: vthermal ∝ Rref and vf2licker ∝ Rref . This, in turn, means
that decreasing the resistance Rref results in an improvement in the noise performance.
The higher noise associated with circuit 3 means that it wouldn’t achieve the same SNR
as the previous two circuits. It would achieve an SNR worse by about 20dB than circuit
1 and by about 26dB than circuit 2. Nevertheless, this is still a high performance (high
SNR) and is further complemented by the smaller temeprature drift.
Circuit 1 is a pure CMOS circuit that achieves the required SNR performance. Although
Circuit 2 (which is BiCMOS) outperforms it in terms of noise, Circuit 2 is 70% larger in
area than Circuit 1. Thus, the use of chopping in pure CMOS circuits can allow for low
noise performance at relatively smaller areas than the BiCMOS counterparts.
Circuit 3 achieves the minimum temperature drift of the 3 circuits, thanks to higher
order temperature compensation. However, circuit 3 suﬀers from an order of magnitude
higher noise than circuits 1 and 2, as well as a signiﬁcantly larger area (343% larger than
circuit 1 and 162% larger than circuit 2). The much lower temperature drift, however,
complements the larger noise and area.
Conclusions
In this work, analysis has been made to the eﬀect of Jitter on ΣΔ ForceFeedback systems.
Analytical relations were derived for the eﬀect of white jitter on SNR. Analytical relations
were veriﬁed versus simulation. It is shown that for high performance systems, jitter can
become a major performance limiter.
Analysis was also made to the eﬀect of the reference noise on SNR. It was shown that
the reference, and reference noise, is eﬀectively multiplied by the output bitstream to form
the feedback force. As a consequence of this multiplication, the SNR for large input signals
will be independent on the input signal; it will only depende on the reference voltage  to
 reference voltage noise ratio. Hence, reference voltage noise can be challenging if high
performance is needed, speciﬁcally the low frequency 1/f noise.
After reviewing the various reference voltage technologies, bandgap technology is chosen
for its inherent compatibility with CMOS technology. Three bandgap circuit designs are
presented aiming at achieving lownoise and lowdrift.
The 1st design is a conventional design that uses chopping to reduce the eﬀect of Opamp
noise. Trimming of the bandgap for lowest temperature drift across corners is also pre
sented.
The 2nd presented design uses npnBJT’s to achieve lowﬂicker noise for the Opamp.
The circuit is capable of generating 2.4V and 1.2V references simultaneously.
In the 3rd design, a new higherorder temperature compensation scheme is presented;
it is a currentmode implementation of a previously reported circuit. This new implemen
tation, however, allows greater ﬂexibility in the design, giving room for optimization and
allowing lower supplies.
184
Future Work
• Performing the layout of the proposed circuits, and fabrication to test their real
performance on Silicon
185
Appendix A
The DAIC model of the MEMS acceleration sensing system is shown in ﬁgure 3.13. The
MEMS element is modeled as a second order system with a voltagetoforce conversion
block that converts the input voltage to force (recall that the force is proportional to
the square of the input voltage). The output of the MEMS element is a displacement
that is converted to capacitance using a displacement to capacitance conversion block
(capacitaance is inversely proportional to displacement). Figure A.1 shows the block di
agram of the second order system and the associated voltagetoforce and displacement
tocapacitance conversion blocks. Figure A.2 shows the block diagram of the second order
system.
The electronic ﬁlter is implemented by the spice function ”FNZ”, as shown below
186
MEMS acceleration system DAIC model 187
Figure A.2: DAIC model of the second order system (forcetodisplacement conversion)
Appendix B
The Opamp model is shown in ﬁgure B.1. The Opamp has its gain (Aop ) and PSR (Gop ) as
variable parameters. It consists of a voltagecontrolled current source that represents the
transconductance gm of the Opamp’s input pair and a load resistor Ro that represents the
Opamp’s output impedance. Hence, the Opamp’s gain is gm.Ro . To represent the Opamp’s
Gop , another voltage controlled current source is added in parallel (and its control voltage is
the supply Vdd ). This current source is active only in AC analysis and is implemented using
VerilogA behavioral modeling language. The Opamp’s Gop0 is, thus, given by gmvdd .Ro
(where gmvdd is the transconductance of the supply’s voltagecontrolled current source).
188
Opamp Behavioral model 189
‘include "constants.vams"
‘include "disciplines.vams"
analog
begin
if ( analysis("ac") )
k = 1.0;
else
k = 0.0;
end
endmodule
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