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SoC Derivatives Made Easy

Arbind Kumar Rohilla

Simon Rance


Atrenta, Inc.
2077 Gateway Place
Suite 300
San Jose, California 95110
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Todays system-on-a-chip (SoC) designs are creating more challenges than ever
challenges that demand bringing the product to market faster, before the
competition does. The electronics industry and growing competition require that
SoCs achieve a short time to market (TTM) while design complexity continues to grow
at a rapid rate. Another challenge is to keep the SoC design and overall product
costs as low as possible.
How can design companies meet such challenges as TTM, design complexity and
competitive differentiation while keeping costs down? With ever-shortening TTM, one
way is through IP reuse. This implies building a solid, extensible architectural platform
and deriving newer platforms from it as per the application needs, which reduces
design time and increases success rate. There is a need to address the difficulties that
design companies are facing today to create derivative designs. As we are in the
era of highly complex giga-scale products, the error margin or the tolerance guard
band is getting tighter and tighter with respect to previous design approaches.
Conventional chip assembly processes are largely manual, or home grown
script-based, which takes a lot of man hours (even months) and still are not error free.
So what we need is an automated, reliable and flexible solution to accomplish the
necessary tasks in the shortest possible time. An ideal solution will contain hooks to
capture and modify the existing design to drive new functionality. The solution will
enable the designer to increase the abstraction level of connectivity, manipulate the
design hierarchy and perform IP selection. Furthermore, the solution should make use
of a standard database to improve interoperability and ease design handoff.
As the popularity of reusing existing designs or intellectual property (IP) blocks
continues to grow, design challenges escalate. As time to market pressures and
product complexities increase, the pressure to reuse complex building blocks
increases significantly. The solution to the productivity problem is increasing the
abstraction level in design technology and introducing tools to support re-use of
components and system parts. Apart from existing methodologies, one new
approach is to create derivative designs on top of existing ones, which is called
derivative design methodology.
A modern SoC may contain 500 or more IPs (including integration logic), many of
which may have 100 or more ports. Designers have already realized that creating,
reviewing and maintaining 50,000 connections in HDL through a text editor is
exceptionally painful. The experimental results on real applications show that the
proposed approach is effective in making derivative design on the top of an existing
one. Here, we are considering the inputs to be expressed at the register transfer level
(RTL) or in IP-XACT format, which form the reference specification for design
modifications. We will cover each step of a derivative design flow one-by-one.
The migration from an existing design to a derivative design requires smoothly cruising
along many milestones. Success of the previous milestone becomes a prerequisite to
enter the next one. These milestones typically revolve around careful IP selection,
mapping IP ports to interfaces, glue logic management, hierarchy manipulation and
finally archiving and exporting all the modifications as a new-born design. Another
dimension of the problem that makes these milestones even more complex is the
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meaningful integration of elements, which could be part RTL, part IP-XACT, part XML
or some other format that do not easily gel well with the others.

Figure 1: A derivative design flow

Since the migration initiates from pure RTL, behavioral RTL code also needs to be
elegantly handled. Typically, the users design contains all types of intricate RTL
constructs, like complex port types, layered packages, dependent parameters,
functions, live formulae, etc. Also, RTL designs can contain a large proportion of
instances distributed over several levels of hierarchy containing an abundance of
hierarchical connections. At the RTL level, the connections are defined in terms of
ports rather than interfaces and that makes connection management a daunting

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After successfully reading an existing design, the new challenge is to map a
collection of ports to interfaces, enabling a higher level of abstraction from ad-hoc
connectivity to interface-based connectivity. An interface can contain any number
of logical ports and their attributes. The next step is to perform the necessary
mapping between the actual ports to the interface logical port for each defined
interface. Typically this is a highly error-prone and complex task. The complexity
includes handling a selection of interface configurations, such as the type of
interface defined (e.g., master, slave, interface, monitor, mirror/non-mirrored type,
interface naming convention, mapping of logical with actual ports). The mapping
could be of a typical one-to-one type relationship called ad-hoc mapping. However,
when applicable, a more optimal name-based mapping technique can be used to
improve productivity, simplify the task and reduce the possibility of errors. Such a
technique is based on recognizing a common pattern and then utilizing a rule-based
mapping strategy to complete the job with less effort.
In the process of converting an existing design to a derivative design, a lot of new
functionality will get enhanced and added which requires existing IPs to be updated,
deleted, and new IPs to be added. The process of updating existing IPs with the new
version is very challenging where the functionality of the older version needs to be
preserved. A non-disruptive approach to updating existing IPs is required to maintain
the behavior while updating parameters in the IP, incorporating port name changes,
parameter name changes, additional ports, interface name changes and so forth.
The process of IP deletion requires removal of all its association in the design (i.e. the
corresponding IP connectivity should also get removed without affecting other IP
functionality). Similarly, the addition of new IPs must be handled in an error-free and
time-efficient manner.
With existing IPs already arranged in the design, the most important and difficult part
is connectivity modification. A modern SoC can have more than 50,000 connections.
Any significant change to the design will generally lead to erroneous connectivity
(i.e., functional error in the design). The process of modification in design connectivity
requires a number of iterations, along with design knowledge, which is again a very
time consuming task. Such modifications could be traversing existing connections,
deleting connections or adding new connections. For these types of modifications
on a reasonable size design, the existence of an automated way to handle
connectivity for modification in an interactive fashion will significantly improve
productivity in the RTL integration domain.

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Performing hierarchy manipulation without an automated tool is a very tedious and
error-prone task. Even though it often seems like it may be a simple movement of an
instance across a hierarchy, it can often consume several hours or even days when
done manually. One challenge here is to preserve connectivity across hierarchies as
well as the creation of new ports and interfaces at intermediate hierarchies after the
movement. Another challenge is to preserve attributes and the type of connectivity
model while creating or dissolving a hierarchy. The change in an existing hierarchy is
again a very highly error-prone task and requires a lot of human dedication to avoid
a mistake. The process of debugging any problems introduced accidentally after
hierarchy manipulation is again a very time consuming activity for the designer.
Automation for performing hierarchy manipulation is the only solution to handle the
complexity around making such changes in hierarchy while ensuring errors are not
being introduced.
Databases are designed to offer an organized mechanism for storing, managing
and retrieving information. The main aim here is to improve the flow of information
between IP vendors and between EDA tools by defining the interfaces provided by
that IP in a standardized form such as IP-XACT, Tcl, etc. An automated mechanism is
required to convert the design into a standard database accurately and efficiently.
Atrentas GenSys Assembly solution automatically reads in an existing design in the
form of RTL or a standard database like IP-XACT to derive newer functionality as
shown in the detailed derivative design flow in Figure 2.
The GenSys Assembly RTL import utility helps to bring the design database into a new
structured object model, which is more flexible, reliable, and user-friendly to make
changes according to derivative design specification in a very interactive way.
The RTL import feature will extract the top-level abstraction (peripheral part) and
populate the GenSys database while maintaining the low level abstraction
(behavioral part) in terms of glue logic at the same location. Glue logic needs to be
retained throughout the flow for later usage.
During this RTL read process, one block will be created for all assignment/tie-off
statements. For each process/concurrent statement in the RTL, there will be a
separate block at each level of hierarchy in the design.

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Figure 2: Detailed derivative design flow

In the imported design, it is very easy and simple to infer interfaces into the
hierarchical design and automatically conceive the design with the interface
connectivity out of ad-hoc connections. It is based on the mapping (physical port
from the RTL and the logical port of an interface) provided. This mapping can be
specified by the user (i.e., ad-hoc as well as rule-based mapping) or existing
algorithms in GenSys Assembly, such as best fit or greedy approach, can be used.
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Once the interfaces are inferred, only a generator run is required to quickly infer
interface connections throughout the design. At any point in time, the user can
generate the interface summary report to review the higher level of abstraction

Figure 3: Higher level abstraction view and Interface summary report

The next requirement in the flow could be to add, delete and update the existing IPs
as well as interfaces. In GenSys Assembly, it is very easy to add or delete IPs. Only a
few mouse clicks are required to update the old IP with the new IP in the design
along with the mapping facility for ports, interfaces and parameters if added or
deleted for the newer version. Based on the mapping provided at the time of
updating the IP, the old characteristics will be updated with an error-free and very
fast approach. Remember, performing this manually is typically very error-prone and
a time consuming process.
GenSys Assembly also provides a very interactive way to build connections, which
can be used to add, delete, traverse, modify, and filter existing connections. GenSys
even guides the user if a wrong connection is made. These operations through the
connection builder inspire confidence while working on the connectivity part of the
design with full transparency.
In the connection builder window, the user just needs to select the source and
destination IP and perform connectivity across IPs. At any point in time, the user can
see the existing connection or traverse the existing connection through the
connection builder. Finally, the user can also generate a connection statistics report
to check the connectivity distribution in the design (i.e., percentage of ad-hoc,
tie-off, interface, splice, open, and exported connections).
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Figure 4: Connection builder and debug environment

GenSys Assembly and GenSys RTL contain a variety of hierarchy movement and
modification features. The user can create a new hierarchy for any number of
instances using the group feature. Likewise, the user can easily dissolve any hierarchy
using the ungroup feature. For design partitioning, the user can create multiple
hierarchical views of a single design without affecting the original view. The GenSys
family makes moving any instance from one hierarchy to another seamless by
allowing the user to simply drag and drop the IP across the hierarchy in the same way
one moves files across folders in the Microsoft Windows environment.

Figure 5: Hierarchy manipulation

Interoperability is a key aspect of a design database. Apart from supporting
standard formats for design databases such as IP-XACT, GenSys Assembly also
supports its own format for database management called MRS (Machine Readable
Specification) as well as support for Tcl. GenSys Assembly supports all current versions
of the IP-XACT standard.
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GenSys by Atrenta is a framework for creating a derivative design while boosting
productivity in terms of quick iterative cycles while eliminating errors in the design.
A derivative design flow requires an assembly framework with the following attributes:

Ease of data entry

Ultra-fast design build time

Ability to accept large modern designs with thousands of connections

Support for last-minute ECO changes

Automated generation of RTL netlist, design reports & documentation

Customizable to support in-house methodologies

Standard database backend that allows API-based access for custom


Atrentas GenSys solution covers all the above attributes and more. It has been
successfully used to tape out many chips at leading semiconductor companies. It
ensures a valid and well-managed derivative design approach.
Atrentas SpyGlass Predictive Analysis software platform significantly improves
design efficiency for the worlds leading semiconductor and consumer
electronics companies. Patented solutions provide early design insight into
the demanding performance, power and area requirements of the complex
system on chips (SoCs) fueling todays consumer electronics revolution. More
than two hundred companies and thousands of design engineers worldwide rely
on SpyGlass to reduce risk and cost before traditional EDA tools are deployed.
SpyGlass functions like an interactive guidance system for design engineers and
managers, finding the fastest and least expensive path to implementation for
complex SoCs.
SpyGlass from Atrenta: Insight. Efficiency. Confidence.

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