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Desiree Ibon

861125598
EE 120A Section 24
Lab 3-- Programming Combinational Logic
on Basys FPGA Board
Lab Partner: Claire Yang

Overview
This lab was intended to provide better familiarity with Xlinx ISE
Design, Synthesis, and Basys Board FPGA Programming. This is
accomplished with the design and implementation of a simple
AND gate and a BCD-to-7seg decoder. The design of these circuits
was done using Xlinx software and then a test bench was created
with the ModelSim software. Once our circuits were verified, a
user constraint file was created that was loaded into Adept to be
programmed onto our Basys-2 FPGA board.
New Concepts
7 segment display: 7 LEDS that are placed in a way to create a
number 8 layout which can be turned on and off to create
numbers and some letters
anode: an electrode through which positive electric charge flows
cathode: electrode from which a conventional current leaves a
polarized electrical device
Analysis
Experiment 1:
INPUT
S1
0
0
1
1

S0
0
1
0
1

OUTPUT
Q
0
0
0
1

Boolean Equation:
Q = S1S0
The task in experiment one was to design and test a
combinational logic AND gate and to verify it using our Basys-2

FPGA board. First, a truth table and a resulting Boolean equation


were created. The only time that the output is 1 is when both
inputs are set to 1, otherwise all outputs are 0. The AND gate was
then designed using the Xlinx software and a .vhd file was then
created to create a test bench for the schematic. As seen in Figure
2, our design was able to be verified in the ModelSim program
due to how the output is only 1 when both input values are 1. A
user constraint file was then created and we had selected 2
switches and 1 LED to serve as our two inputs and one output for
the AND gate. The .ucf file was then loaded into the Adept
program. Our Basys-2 board were then able to verify our AND
gate with the LED only turning on when the two switches were on.
Experiment 2:
K-Map
K-Map A
00
00 10
01 1
11 0
10 1
X
K-Map B
00
00 10
01 1
11 1
10 1
X
K-Map C
00
00 10
01 1
11 1
1

01
0
1
1
X

11
1
1
X
X

01
1
0
1
X

11
1
1
X
X

01
1
1
1

1
1
X
x

1
0
X
X
11

1
1
X

0
1
X

10 X
K-Map D
00
00 10
01 1
11 0
10 1
X
K-Map E
00
00 10
01 1
11 0
10 1
X
K-Map F
00
00 10
01 1
11 1
10 1
X
K-Map G
00
00 10
01 0
11 1
10 1
X

01

x
11

0
1
1
X

1
0
X
X

01

1
1
X
X
11

0
0
0
X

0
0
X
X

01

1
1
X
X
11

0
1
1
X

0
0
X
X

01

0
1
X
X
11

0
1
1
X

1
0
X
X

1
1
X
X

Truth Table:
S3
0
0
0

INPUTS
S2 S1
0
0
0
0
0
1

S0
0
1
0

A
1
0
1

B
1
1
1

C
1
1
0

OUTPUTS
D
E
1
1
0
0
1
1

F
1
0
0

G
0
0
1

0
0
0
1
1

0
1
1
0
0

1
0
1
0
0

1
0
1
0
1

1
0
1
1
1

1
1
1
1
1

1
1
1
1
1

1
0
0
1
0

0
0
0
1
0

0
1
0
1
1

1
1
0
1
1

Boolean Equations:
a = S2'S1'S0' + S3'+S2S0 + S3'S1 + S3S2'S1'S0
b = S3'S2' + S3'S1S0 + S3'S1'S0' + S2'S1'S0' + S3S2'S1'S0
c = S3'S2 + S3'S1' + S3'S0 + S2'S1'S0' + S3S2'S1'S0
d = S2'S1'S0' + S3'S2S1'S0 + S3'S2'S1 + S3'S1S0'+S +
S3S2'S1'S0
e = S2'S1'S0' + S3'S1S0'
f = S2'S1'S0' + S3'S1'S0' + S3'S2S1' + S3'S2S0' + S3S2'S1'S0
g = S3'S2'S1 + S3'S1S0' + S3'S2S1' + S3S2S1S0 + S3S2'S1'S0' +
S3S2'S1'S0
The task in this experiment was to create a 7 seg decoder which
displays numbers 0 to 9 with the use of 4 switches and the
rightmost LED display. A truth table, K-maps, and Boolean
equations were first created to be able to draft a design on Xlinx.
Using Xlinx, a schematic was designed as seen in Figure 3. Similar
to the first part of the experiment, a .vhd and .ucf file were
created to verify that the design was correct using ModelSim and
Adept software.

Records
Experiment 1:
Schematic:

Figure 1: And Gate

Testbench:

Figure 2: AND gate testbench

Experiment 2:
Schematic:

Figure 3: 7 seg schematic

Testbench:

Figure 4: 7-seg testbench

Discussion
In part 1 of this lab, our schematic, test bench, and
implementation on our Basys-2 FPGA Board worked as per the
specifications provided in the lab manual. For part 2, we ran into
the problem where when we simulated our design using the
Basys-2 FPGA board, our numbers were not displaying properly
and all out outputs were the opposite of what they should have
been. To fix this problem, we added an inverter after every OR
gate so that all outputs would be inverted. Afterwards, our design
had worked according to the specifications.
Conclusion
Through this lab, we have gotten more familiar with Xilinx ISE Design,
Synthesis, and Basys Board FPGA Programming. This was
accomplished with the design of a 7-seg decoder which outputted
numbers zero through 9 and a simple AND gate.
Questions
1. Can there be a difference in logical behavior between
the intended logic entered and simulated and, the logic
actually synthesized for FPGA? Why?
There can be a difference in logical behavior between the
intended logic entered and simulated and the logic synthesized

for FPGA. Despite a test bench showing proper results, the FPGA
board may not work as per the specifications due to the initial
schematic design.
2. Why do we need a configuration file?
A configuration file is needed to setup the initial conditions for our
Basys-2 FPGA boards so that when the board has been
programmed, it works as per the specifications.
3. What must be done in order to use switches SW3 and
SW7 instead of SW0 and SW1? How about using LED5
instead of LED0?
In order to use SW3 and SW7 and LED 5, in the user constraint
file, the locations of SW3, SW7, and LED5 need to be programmed
into the user constraint file to use those to be used on the Basys2 FPGA board.