ECE315 Project 2: A Simple Differential Amplifier

Erin McClure James Yu Steve Keller May 1, 2003

0.1

Design

For our final project design, we started off with the circuit used in Lab 7: a folded-cascode differential amplifier, as seen in Figure A. However, we did not use the same CD4007 chips that we used for Lab 7, since they were not particularly well-matched. We tested a variety of chips and only selected ones that contained nMOS and pMOS transistors that were particularly well-matched (VT 0 matched to 3-4 decimal spaces). Using the Lab 7 setup and well-matched transistors, we were able to meet all of the project specifications except for the unity gain crossover frequency requirement. The value we initially obtained was significantly lower than the specified 50 kHz requirement ( 5-10 kHz), so we proceeded to adjust our circuit to raise the value of Ib . In order to do this, we changed the resistance value R in the biasing circuit from 100 kΩ to 10 kΩ. Since Ohms law states that I = V /R, a decrease in R resulted in an increase in Ib . Raising Ib brought us very close to meeting the unity gain crossover frequency requirement but also lowered the gain of our circuit. Consequently, we proceeded to double the effective width of the differential pair (transistors M1 & M2 ) by adding a transistor in parallel with each of them, as seen in Figure B. By adding these parallel transistors the current difference generated by the differential pair is magnified, thus this increased both the bandwidth and the gain. With these modifications, our circuit successfully met and/or exceeded all of the project specifications. For the folded-cascode differential amplifier circuit, the value of the output voltage Vout is based on a number of different factors. First, the input voltages V1 and V2 are the gate voltages for the M1 /M2 differential nMOS transistor pair that is connected to the source of the M3 /M4 cascoded pMOS transistor pair and the drain of the M5 /M6 cascoded pMOS transistor pair. Due to the bias transistor Mb , which fixes the source current Ib for the M1 /M2 differential pair, a positive difference between the value of V1 and V2 (V1 > V2 ) results in an increase in the current allowed to pass through M1 and a decrease in the current allowed to pass through M2 (since I1 + I2 = Ib ). Upon examination of the current division that Ib goes through in between the pair M3 /M4 and the cascode pair M5 /M6 , this decrease in the current allowed through M2 results in more current to pass through transistor M6 . Moreover, the increase in current through M1 causes less current to go through M5 , and thus less current mirrored by the nMOS mirror M7 and M8 . In the end, more current flows in the output node than out, and increases the output voltage Vout . The exact opposite happens for V1 < V2 , thus V1 is called the non-inverting input and V2 the inverting input. Another factor that influences the value of Vout is the relationship between the bias voltage for the M3 /M4 cascoded pair, Vbp , and the cascode voltage for the M5 /M6 cascoded pair. Since the M3 /M4 & M5 /M6 cascoded transistor pairs are pMOS pairs, their gate voltages must be fixed far enough below VDD for a significant amount of current to be allowed to pass through them.

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0.2

Experiments

All of the following experiments were done using a cascode bias voltage of Vc = 2.8V . Also, this bias voltage was generated using a simple voltage divider with two resistors so as to adhere to the criteria that our amplifier must operate from a single 5 V DC power supply.

0.2.1

Output Characteristics

First we swept Vcm from rail to rail while measuring Vout to find the allowable common mode voltage range. As seen in Figure 1, this range is from about 2V to 5V. To ensure that our amplifier provides a rail to rail output swing we swept Vdm from rail to rail while measuring Vout for different values of V2 . As seen in Figure 2, our amplifier does exhibit rail to rail outputs. Figure 3 provides a much closer view of one of the curves.

0.2.2

Differential Mode Gain

In order to find our differential mode gain we used the relation Adm = ∂Vout ∂Vout ∂Iout = · = Rout · Gm ∂Vin ∂Iout ∂Vin (1)

First, we calculated Rout , the output resistance, by sweeping Vout from rail to rail while measuring Iout , as seen in Figure 4. After graphing the data, we obtained a slope of the best fit line, which corresponds to ∂Iout /∂Vout . Taking the inverse we obtain Rout = ∂Vout = 8.7489 × 105 ∂Iout (2)

Secondly, we calculated Gm , the incremental transconductance gain, by sweeping Vdm while measuring Iout , as seen in Figure 5. After plotting the data we obtained Gm through the slope of the best fit line ∂Iout Gm = = 3.1878 × 10−4 (3) ∂Vin Now we multiply these two values to obtain the differential mode gain Adm = (8.7489 × 105 )(3.1878 × 10−4 ) = 278.0992 = 48.884dB which is sufficient for the given specification of at least 40dB. (4)

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0.2.3

Common Mode Gain and CMRR

In order to find the CMRR (common-mode rejection ratio) we use the relation CM RR = Adm Rout · Gm,dif f Gm,dif f = = Acm Rout · Gm,common Gm,common (5)

So we merely need to find the common mode incremental transconductance gain to obtain CMRR. In order to do this we swept Vcm from 2.5V to 2.7V, the same interval as when we swept Vdm to find Gm,dm , as we measured Iout . After graphing the data as shown in Figure 6, we obtained the slope of the best fit line and obtained Gm,cm = 5.1022 × 10−7 3.1878 × 10−4 ⇒ CM RR = = 623.002 = 55.8898dB 5.1022 × 10−7 which is sufficient in regards to the 50dB specification. (6) (7)

0.2.4

Unity-Gain Characteristics

To obtain the unity-gain characteristics, we made a feedback connection from the amplifier output to the inverting input, and loaded the output with a 1 nF capacitor. Then we used the AFG to provide a sinusoidal input to the non-inverting input, and used the scope to observe the output. In order to ensure that our crossover frequency was at least 50 kHz, we placed as input a 50 kHz sine wave and observed the resulting output signal. Since our system is a single pole system, we √ should expect an approximate 3 dB output at the crossover frequency (or multiplied by 1/ 2). As seen in √ Figure C, the resulting output is phase shifted less than 180◦ and is a little higher than 1/ 2 of the input, which means that it is sufficient to meet the 50 kHz crossover frequency specification. Of course, our circuit is also unity-gain stable when loaded with a 1 nF capacitor.

0.2.5

Offset Voltage

To obtain the offset voltage we first made a connection from the output to the inverting input to make the circuit exhibit unity-gain. We then measured the voltage across Vin and Vout while sweeping Vin from rail to rail to see how much our circuit strays from unity gain. As seen in Figure 7, the offset voltage is within 50 mV over the entire range of the allowed common-mode input, except at the very end where it tapers down.

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0.2.6

Power Characteristics

We measured the total quiescent current drawn from Vdd as 0.276 mA. This was done by using the Keithley 2400 to supply 5V and measure the current going into the circuit when the amplifier was connected as a unity-gain follower with Vin centered in the amplifiers common-mode input range. The total power was calculated to be P = V I = (5V )(0.27600mA) = 0.00138W. (8)

0.2.7

Bandwidth

The bandwidth per unit static power consumed is B= 50000 ωcrossover Idraw = 0.000276 = 2.76 Vdd 5 (9)

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Vcm sweep from rail to rail measuring Vout 0.24

0.22

0.2

0.18

V

out

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0.14

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0.08

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0.5

1

1.5

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2.5 Vcm

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3.5

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4.5

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Figure 1: A sweep of the common-mode voltage while measuring the output voltage shows that the amplifier does indeed work properly near the power rail.

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V 5 V2 = 2.5V V2 = 3.5V V2 = 4.5V

out

vs. V

dm

for different values of V2

4.5

4

3.5

3 Vout

2.5

2

1.5

1

0.5

0

0

0.5

1

1.5

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2.5 Vdm

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3.5

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4.5

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Figure 2: A sweep of the differential mode voltage while measuring the output voltage shows that the amplifier exhibit rail to rail behavior in the allowed input range.

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Close up of V 5

dm

vs. Vout sweep for V2 = 3.5V

4.5

4

3.5

3 Vout

2.5

2

1.5

1

0.5

0 −0.2

−0.15

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−0.05

0 Vdm

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Figure 3: A finer plot of the differential mode voltage versus the output voltage at V2 = 3.5V .

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x 10 7

−5

Vout vs. Iout at V1=V2=2.6V Data Fit

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5

4

3 Iout 2 1 0 −1 −2 0 0.5 1 1.5 2 2.5 Vout 3 3.5 4 4.5 5

Figure 4: A plot of the output current versus resistance curve. The inverse of the slope of the fitted line is the output resistance.

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8

x 10

−5

Vdm vs. Iout at V2=2.6V Data Fit

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4

2 Iout 0 −2 −4 −6 −1 −0.8 −0.6 −0.4 −0.2 0 Vdm 0.2 0.4 0.6 0.8 1

Figure 5: A plot of the output current versus the differential mode input voltage. The slope of the fitted line is the incremental transconductance gain Gm .

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x 10 1.16

−5

Vcm vs. Iout Data Fit

1.15

1.14

1.13
out

I

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1.1

1.09 1.6 1.8 2 2.2 2.4 2.6 Vcm 2.8 3 3.2 3.4 3.6

Figure 6: The output current versus the common-mode input voltage. The slope is the incremental transconductance gain for the common-mode input.

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Offset Voltage 0.2

0.15

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0.05 Vout − Vin

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0.5

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1.5

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2.5 Vin

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Figure 7: A measurement of the offset voltage was made by measuring the voltage across the input and output while the circuit is unity gain connected.

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