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CIRCUIT DESCRIPTION OF EXCITER

DISPLAY BOARD ( 1& 2 )


See circuit diagram 674.0516 & 674.0539
Display Board 1 consists of all the front panel switches on the left side of 10 W-heat sink. The
switches on right side of heat sink are on display board 3.
Display Board 2 includes the following circuitry :

Logic circuit for coding the input attenuators according to the inputs on the front panel.
Storage relays for the commands entered on the front panel.
Amplifier for the modulation signal.

The BCD code entered on the front panel with the coding switches is converted in B1, B2 and
B3 to a binary-coded signal for driving the input attenuators on the input board. If a setting of
more than 15 (decimal) is entered, B2 holds the binary code for 15 and the AF level does not
change any more. At the time, LED GL 14 AF too low is activated through the AND gate
formed by GL9 to GL12 via B3. The transfer contact for the 0.5 dB position leads directly to
the input board.
Relays RS1 and RS2 and flip-flop B4 store the switching commands entered on the display
board 1 with S1 to S6.
i)

Operation without Coder


In this case, only the keys S1, S2 Pre-emphasis on/off are operational. The entered
command is stored, power-failure-proof, in RS1. with link BR5 in position OC (without
coder), the pre-emphasis and low pass filter in the transmitter section are switched. If
links BR1 and BR2 are inserted, RS1 can be remotely controlled. The selected state
is indicated by LEDs GL31 and GL32.

ii) Operation with Coder


Link BR5 is in position MC (with coder) ; links BR1 and BR2 are removed. Relay
RS1 controls only the pre-emphasis circuit in the coder. The mono/stereo command
entered with keys S3/S4 is stored in RS2 power-failure-proof, and determines the
operating mode of the coder.
LEDs GL33/GL34 indicate the selected state mono/stereo.
controllable.

RS2 is remotely

Flip-flop B4 stores the pilot on/off command entered with S5/S6 and passes it on to
the coder. The command is indicated by LED GL35/GL36.
The switching state of RS2 is signalled via C45 and C46 to flip-flop B4, so that in mono
operation the pilot tone is switched off and in stereo operation is automatically
switched on.

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T20IV/V constitute a NAND gate and activate the mono/stereo signal relay on the input
board if stereo operation is selected and the pilot tone is switched on.
The modulation signal is amplified in B5; the gain can be adjusted +0.5 dB with R22.
With nominal deviation, the output level is + dBm. Link BR3 is inserted MC or OC
depending on the origin of the modulation signal (i.e. with or without coder).

INPUT BOARD
See circuit diagram 674.0316 S.
The input board includes the following circuitry :

Input transformers for the R/L signals.


Switch-selectable attenuators for the R/L signals.
Signal relays for mono/stereo, fault, RF present signals.

The modulation signals L/R are fed via ST 3.0 abc, ST 3.9 abc to the input board. In
operation without coder, the L input is the modulation-signal input. In case of balanced inputs,
the inner lines can be interchanged by means of links BR 11 to BR 18. (The factory setting of
the links is BR 11, BR 12, BR 13, BR 14). The inputs can be converted for unbalanced
signals by inserting links BR 2 and BR3.

Fig. 1 AND/OR Select gates (CD 4019)


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Depending on the input resistance, resistors R1, R2, R3 and R35, R36, R37 as well as
components of the external circuitry of B11 and B44 must be selected as follows :
Ri
>2k
600

R1, R2,
R35, R37
1
150

R3, R36

R11, R44

R12, R45

C11, C44

328

121 k
243 k

7.87 k
16.2 k

56 pF *)
22 pF *)

*) Trimming value

After transformation in TR3, TR36, the first level adjustment is made. The levels can be
attenuated up to 0.5 dB by means of transistors T11, T44, which are controlled by the coding
switch the front panel.
The subsequent attenuation elements attenuate the signals by 1, 2, 4, 8 dB respectively. B33
and B34 convert the level of the binary code (0/+12 V) to + 12 V/-12 V for driving the MOS
switches B1 to B4. B31 and B32 serve for the remote control of the attenuation elements.
B31 is an AND/OR select gates assembly (CD4019) as shown in figure 1. B32 is a NOT gate.
The local/remote switch must in this case be set to remote and link BR4 inserted across 2-3.
The L/R signals are fed to the coder via ST6. In operation without coder, the modualtion
signal is amplified to 6 dBm in B66 and fed via ST6 to display board 2.
Relays RS1, RS2 and RS3 provide the messages RF present, mono/stereo, and fault
respectively. These relays are controlled from the power-supply motherboard or display board
2. Resistor R4 can if necessary (carrier enable of transmitter with voltages > 12 V) be
replaced by a diode.
When the transmitter SU 115 is connected to the 100 W Amplifier VU 125, link BR1 must be
inserted.
MPX Loop-through Socket
Using this loop-through socket, an external coder (f.e. ARI-coder) can be connected, to add
an additional signal to the MPX signal. The MPX signal is fed from the loop-through socket to
the attenuator R27, R28 and R29 via cable K25. The attenuator matches the level and
determines the input resistance of the loop-through socket.
|
___________ |_R27
Ri = 600 | 866
Ri = 2 k
| k
|

R28
357
499

R29____
1,54 k
2,21 k factory version

STEREO CODER
See Circuit diagram 674.0216 S.
The L/R signals are fed via ST 11 into two identical circuits (channels). The L channel will be
described below.
The input amplifier B1 brings the signal to a level of about 6 dBm. The pre-emphasis network
R6, C5, C6 is switched in or out by push buttons on the front panel of the transmitter. The 50
s or 75 s pre-emphasis is selected by positioning the link BR5 1-2 or 2-3 respectively.
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The following low pass filter suppresses the undesired frequency components above 15 kHz.
Following B25, the signal goes to the resistance chain of the coder. The desired channel in
mono operation is selected with link BR27.
In mono operation, relay RS 61 shorts out the stereo signal generation (coder) and feeds the
signal to the output amplifier BR11.
i)

Stereo Encoding Process


(Please refer figure 2, 3 & 4)
The coder functions in accordance with a switching technique. The hard switch over
with 38 kHz is replaced by a stepwise transition in 14 steps. With this procedure,
undesired sidebands only appear from the 13th harmonic onwards, and these can be
filtered out with simple circuitry.
This soft switching is realized by means of resistance chain R71 to R103 between
the L-signal (BR26) and the R-signal line (BR 56) which is switched through
sequentially with the FETs T75 to T103. The correction signals -L and -R (through
C82, C87) improve the coding at the instant of subcarrier zero crossing. The
switching pulses for the FETs are generated in the shift registrar B140/B145 and
output in the correct timing sequence by means of the OR gates B130/B135. The
switching sequence within a cycle of the 38-kHz subcarrier signal begins in T86 in
direction T75 and then back via T86 to T103 and ends with T96.

Fig. 2 Theory of Stereo Coding


L = A Sin Lt
R= B Sin WRt

V3

R at t = K/2 + K/2 SinWst


S = Sub Carrier Freq. (38 kHz)

V1 V2 K
(1 + SinWst ) =
K
2

V2 +

V1 + V2 V1 V2
+
SinW s t
2
2

V2 +

V1 V2 V1 V2

SinW s t
2
2

L +R L R
+
SinWst *
2
2

This term represents subcarrier ( 38kHz) amplitude modulated


subcarrier suppressed.

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-12 V

-12V

T76

T79

T86

T88

T96

T98

T103

11

10

11

10

3
(B135)

(B130)

14

CD
4071

CD
4071

B150 IV

12 13 8

-12 V

-12 V

T75

12 13 8

-12V

14

-12 V

38kHz
38kHz

CLK-A

RESET

8
-12V

12 5

11

12 5

13 4

10 3

15

QA1

QA1

QA2

QA2

QA3

QA3

QA4

QA4

14

RESET

4 STAGE

CLK-B

16
(B140)

CLK-A

RESET

6
8
-12V

DATA-B

DATA-B

DATA-A
4 STAGE

DATA-A

13 4

QB1

QB1

QB2

QB2

QB3
QB4

QB3
2

QB4
(B145)

CD 4015

4 STAGE

4 STAGE

15 10 3

CLK-B 1
14
16

CD 4015

532 KHZ

Fig. 3 Stereo Encoding Process (Pilot Tone Method)

Fig. 4 MPX Signal Generation


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ii) Pilot Tone Generation

The crystal oscillator G1/B150III furnishes over inverters B150II/I the basic frequency
of 4.256 MHz (= 2 x 7 x 8 x 38). With 8:1 division in B155I, the 532-kHz clock
frequency is obtained for use with the shift register. From this frequency, the
monostable T221/T224 generates the somewhat delayed clock pulse for the sampleand-hold circuit T196 of the summing amplifier.
In the 16-bit shift register B140/B145, flip-flops 1 to 14 are switched via the line B145.
12-GL 132-B 140.7 to form a ring. A bit is stepped around the ring by the clock and
places a High on one output for one clock period, all the other outputs of the ring being
Low. If no bit is circulating, a bit is fed through GL75 to GL103 via B150 IV and GL
131. The reset line B145.13 (flip-flop 13) to B140.6/14 and B145.6 clears flip-flops 1 to
12 before transfer of the shifted bit into flip-flop 1 and thereby prevents that two or
more bits circulate.
The pilot tone is generated in one of two ways, depending on the pilot operating mode
(link BR 135), in which the shift register functions as a 14:1 divider.
For the pilot tone with fixed phase the signal of flip-flop 8 of the shift register (B140.2)
is used. In the 2:1 divider B155II, this is converted to a symmetric 19-kHz square
wave.
If the phase is adjustable, the signal of flip-flop 6 of the shift register (B140.12) triggers
the monostable B160. The on-time of the monoflop can be adjusted to a value
between approx. 2 and 4 # S with R158 pilot phase, this corresponding to a phase
shift of approx. 14o (>10 ), referred to the pilot tone. Frequency divider B155II in this
case also generates the 19-kHz square wave.
Via B170, the pilot tone can be switched off on the front panel.
The square wave output of B155II has a number of functions. Via C252, this signal
synchronizes the phase control loop in the SCA modulator (option: see separate
description). After being limited in GL 241/GL242, the signal is fed through emitter
follower T242 to the pilot-tone output connector on the rear panel of the transmitter.
After passing through difference amplifier T243/T244, the 19-kHz bandpass filter
(L245, L246) and emitter follower T248, the sinusoidal pilot tone is applied to the
summing amplifier. The amplitude of the pilot tone is determined, dependent on the
pilot-tone mode (BR261), by the current through T243/T244, this being of fixed value
as set with R261 for Pilot On, with R263 adjustable for variable pilot, and zero current
for Pilot Off.
iii) Summing Amplifier, MPX Lowpass Filter, and Output Amplifier.

The summing amplifier consists of an input stage in the form of a difference amplifier
with T181 and T182 and a driving stage T184. The load resistance of this circuit is
provided by a constant-current source T192 to increase the open-loop gain. The
operating point of the complementary output stage T185/T195 is determined by the
emitter resistors R187 and R194 together with diodes GL184 and GL185. The
negative feedback can be adjusted with R186. At the amplifier input, the following
signals are summed in the correct level relationship :

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a) The sum signal M =

L+R
LR
and the difference signal, S =
on the 38-kHz
2
2

subcarrier from the coder.


b) The pilot tone P (19 kHz) from the pilot generator.
c) Correction signal for reducing the cross talk over R173/C171 and R174/C172.
The sample-and-hold circuit T196/C196 eliminates interfering switch over peaks (532
kHz) from the coder. The emitter-follower T202, whose emitter resistance is
configured as a constant current source with T201, feeds the MPX law pass filter.
The MPX low pass filter with L111 and L112 is a Cauer filter with an attenuation pole
at 768 kHz and at 498 kHz. The theoretically possible harmonics of the sub-carrier are
adequately suppressed without degrading the phase and amplitude responses up to
53 kHz.
With relay RS61, either the MPX signal or the mono signal (via BR27) is selected.
The output amplifier B211 sums the following signals in the correct level relationship :
a) The MPX signal (coded signal, including pilot tone).
b) The SCA signal with the SCA-modulator option incorporated. This frequencymodulated signal has a subcarrier in the range 60 to 74 kHz which is coupled with
the pilot tone.
c) The traffic-radio signal.
The MPX signal is amplified +6 dB in this stage (R206:R213) : the other signals are
not amplified.
iv) Display Facility

The test-point selector switch on the front panel provides with the settings L and R for
the display of the AF input signal to the coder and with the setting PILOT for the
separate display of the pilot-tone component of the multiplex signal.
The one-way peak detector T114 to T117 weights the negative half-waves relative to
the input signal L or R. The difference amplifier T116/T117 furnishes the signal for
transistor T115, which functions as rectifier. Capacitor C115 is charged to the peak
value. The FET impedance converter T114 delivers the indication voltage for the
analog meter ; its loading of the charging current circuit is negligible. The feedback
over R114 determines the operating point of the difference amplifier, so that the
capacitor is efficiently kept charged with short-duration peaks in excess of the set
level. The discharge time constant is determined by R115 and R120 and has a value
of roughly 10 seconds.
POWER SUPPLY AND AF SECTION

See circuit diagram 674.0574S


In addition to the DC power supply, the power-supply motherboard also contains the AF
section for signal generation and the peak detector for deviation indication of the output signal.
The board further more contains the automatic power reduction circuit in case of mistuning as
well as a portion of the transmitter output circuit for the desired output power.

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i)

Power Supply

The AC power is applied via the line filter, fuse ASII, and voltage selector to the
toroidal transformer. The monitoring transformer TR2 signals a blown fuse via ST1.1
to LED GL202 on the front panel.
The four secondary voltages of the power transformer, after being rectified and filtered,
are stabilized with the IC voltage regulators B1, B2, B3 and B4. For better heat
dissipation, these regulators are mounted on the rear panel. The regulators for the
positive supplies of +5 V, +12 V and +24 V are not isolated, the regulator for the -12 V
supply is isolated. A non-regulated operating voltage of about +11 to +14 V is taken
off ahead of the +5V regulator and distributed through fuse SI2, mainly for the
operation of relays.
The blown-fuse-indicating LED GL201 for SI2 is also located on the front panel.
The operating voltages of the power supply on the motherboard go via ST3 and K9 to
the input board and from there via ST6 and K31 to the stereocoder and via ST13 and
K33 to display boards 1 and 2. In addition, the voltages from the motherboard go via
ST4 and K10 to the synthesiser.
ii) AF Section

The MPX signal is fed to amplifier B151. In operation with coder, relays RS71 and
RS72 are in the non-energized state. The MPX signal from the output of amplifier
B151 goes via ST8 to the synthesizer.
In operation without coder and in the mono code, relay RS71 is activated through
transistor T71 and the pre-emphasis thereby switched on.
At the same time, the 15-kHz filter is switched into the signal path through relay RS72.
In mono operation, this filter suppresses the 19-kHz pilot tone and the L-R signal.
Switch-in of this filter and of pre-emphasis is only possible in operation without coder,
since in transmitters with coder incorporated the signal is already provided with the
corresponding pre-emphasis.
iii) Frequency-deviation indication

The AF signal sent from the power-supply motherboard to the synthesizer for FM
modulation is also sampled, and the sample applied to a peak detector and processed
for display on the analog meter.
The modulation signal without DC component is applied, after amplification by a factor
of about 2 (2.66) in B166, to peak detector B176/GL176/GL177. During the negative
halfwave of the input voltage, C183 is charged via GL 177 to the peak value. The noninverting impedance converter B186 has a high input impedance and is incorporated
into the rectifying circuit through feed-back resistor R177. During the positive halfwave
of the signal, diode GL176 blocks, and the full negative feedback is effective. Relative
to the AF input signal only the negative deviation peaks contribute to the indication, the
indication time constant being <200 s during charging and about 2 seconds during
discharge.
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iv) Regulation of VHF Output Power

The switch connections for the three transmitter operating modes are as follows :
Power
30 mW
1W
10 W

B114
Any
7-3, 4
6-3,4

B115
7-3,4
6-3,4
6-3,4

B113
7-3,4
6-3,4
7-3,4

B111
7-3,4
6-3,4
6-3,4

B101
7-3,4
6-3,4
6-3,4

B112
6-3,4
6-3,4
7-3,4

a) 10-W Output power

If the level adjuster on the front panel is turned to the right (for greater RF power),
voltage is applied via B92 to the control circuit with B55. The second input to B55 is
the actual voltage from B108. If the output power is too low, B55.7 goes positive and
B55.1 negative. For powers up to about 5 W, the control power for the output stage is
increased via B125 and B112, B113, ST 4.3. For powers greater than 5 W, the output
voltage of the switching regulator is increased via B51.
When the output power exceeds the threshold value set with R67, the units B65 and
T65 send out the message signal RF presents. For the 30-mW output, link BR61
must be set B-C.
b) 1-W Output Power

The adjustment of the range (0.5 to 1.3 W) settable with the output level adjuster is
made with R102. The output from B 95.7 is the variable reference and is connected
via B101 with the positive input of B125I. The test voltage of the directional coupler
amplified in B108I is fed via B111.6-3, 4 and R123 to the negative input of control
amplifier B125 I. This latter varies, via B113 and ST4.3, the PIN-diode regulator B150
and with its the VHF output, until B125.2 and .3 are at the same potential. The DC
voltage at the B108I output is proportional to the output power and is fed to the analog
meter via R113, R114, B114.7-3,4 and B115.
c) 30-mW Output power

The voltage from the output level adjuster is brought to the correct level (1 V = 30 mW)
with R 86 and then applied via B101.7-3, 4 to the positive input of control amplifier
B125I. The test voltage obtained from the test diode GL3 on the filter board is
amplified in B108 II and applied via B111.7-3, 4 and R123 to the negative input of the
B125I. This latter controls via B113 and ST4.3 the PIN-diode regulator B150 in the
synthesizer and with it adjusts the output voltage until the inputs to B125 I are equal.
The amplified test voltage on the output of B108 II is proportional to the output voltage
and is applied via R111, R112, B115.7-3, 4 to the analog meter.
d) Power reduction in case of mismatch

The voltage on B31.5, which is proportional to the reflected power, is amplified and is
applied to B31.2. If this voltage exceeds the threshold set by R34, the output on B31.1
is applied via GL41 to the summing point R57/R56 and thus takes part in the level
control. The result is that the output of the transmitter is reduced to the point where
the reflected power no longer exceeds the permitted value.
A corresponding external control voltage can be applied, via GL42, from the outside (external
regulation of output power).
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SYNTHESIZER
See circuit diagram 594.2059 S.
i)

VCO, PIN-Regulator

The processed AF signal from the power-supply motherboard is fed to B100. 220 mV
corresponds to a deviation of about +40 kHz. Diodes GL111 and GL112 limit the
deviation. With maximum setting of the deviation potentiometer and an AF input of
1.55 V, a maximum transmitter deviation of + 100 kHz can be set with R104.
The AF signal is fed to the capacitance diode GL116, whose basic capacitance with
GL117 is changed within Band II to correspond to the carrier frequency value. A
constant deviation is thereby achieved in the 87.5 to 108 MHz range and thus
determines the accuracy of the deviation indicated on the meter.
L119 forms the circuit inductance. It is adjusted with zero control voltage (BR113 set
A-C) to approximately 96.5 MHz. The control voltage for tuning the VCO, which
covers a range from approx. 3.8 V (87.5 MHz) to +6 V (108 MHz), is applied to the
diodes GL118 (main tuning diode) and GL117 (pull-in-diode- deviation constant over
the range). The de-coupling amplifier, formed from the cascaded stage T130, T135
plus T140, isolates the VCO from the PIN-diode regulator B150. the latter serves both
for switching off the carrier and for RF-level regulation (for 30-mW and 1-W transmitter
output). B157 amplifies the signal to the level (approx. 2 V) required for driving the 1W output stage.
ii) Divider

The oscillator frequency is fed via buffer T160/170 to the 10/11 frequency divider
(modulus divider) B200. The buffer prevents any feedback from the modulus divider
and thus of the 10-kHz noise spectrum about the carrier. The programmable
frequency divider with division ratios of 8750 to 10800 in integral steps consists of the
dividers B200, B204, B208, B216, B217, B224 plus the logic components B222, B212,
B214, B206 and B210. The block diagram of programmable divider is shown in figure
5(a) & (b).
The pre-divider, formed by the connection of B200 (10/11 divider) and B204 (10
divider), is programmable and with its control logic can generate the following three
division ratios on pins 2 and 3 of B200 :
P
=
P + Q2 =
P + Q1 =

100
110, where Q2 corresponds to the factor 10
101, where Q1 corresponds to the factor 1

The control logic is switched so that the pre-divider divides its input pulse sequence by
101 as often as specified by the contents of B216 )=A1, down-counter programmable
from 0 to 9). If this counter has counted down to 0, the content of B217 (=A2 downcounter programmable from 0 to 9) is enabled and the pre-divider divides by 110.

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Fig. 5(a) Programmable Divider (Schematic)


The down-counting of the counter contents is accomplished by having the clock inputs
of all programmable counters (dividers) connected with the output of the pre-divider
(see clock C). If the A2 counter has likewise been counted down to zero, the predivider, corresponding to the residual counter content of B224 (N divider
programmable from 87 to 108), will divide its input pulse sequence by 100.
Example :
F

88.35 MHz

Fref

10 kHz

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Overall division factor =

53

88.35 x 106
= 8835
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Programming :

Pre-divider
divides by
101
110
100

N divider to 88
A2 divider to 3
A1 divider to 5
Factor A

Input

Counter

5
3
88 5 3 = 80

505
330
+ 8000
8835

A1 (B 216)
A2 (B 217)
N (B 224)

Thus, after 8835 input pulses, one pulse is output by the N divider (see clock D).
R is therefore obtained with the following expression :
R = N x P +
R = 88 x 100 +
R = 8835

A2
3

x Q2 + A1 x Q1
x 10 + 5
x 1

The input signal divided in this way is fed to the phase/frequency comparator B310
and compared with the 10-MHz reference frequency divided by 1000.
The 10-MHz reference frequency is generated in the temperature-compensated crystal
unit B300. It can be tuned to its rated frequency with C300.
C

D
F, I

=
=

Output of predivider, clock input for the programmable down counters


A1, A2 and N.
Output of divider (goes to phase comparator)
activate the predivider through the control logic to divided by 101 or
110. If F and I are not activated, the predivider divides by 100.

Fig. 5(b) Programmable Divider (Process)

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iii) Coding Remote Control

The A1, A2 and N dividers are programmed with the BCD-coding switches S220,
S230, S240, S250 and S260. The components B230, B240, B250 and B260 are
selector elements that transmit the internally or externally frequency coding to the
dividers (counters).
iv) Lowpass Filter

The output of the phase/frequency comparator B310 is a 10kHz signal whose duty
cycle is proportional to the phase of the two 10-kHz signals being compared. In case
of unequal frequencies, the output contains a superimposed signal with the difference
frequency.
In the following control amplifier B315, the signal is first integrated and then fed into an
active 4th order Bessel filter with a cutoff frequency of 1 kHz (B325, B332). A
multisection lowpass filter (R333, C335 and R336, C113) with phase correction (R335
and R113) suppresses remnants of the frequency modulation demodulated in the
phase/frequency comparator, so that feedback of the modulation to the VCO,
particularly of the low modulation frequencies, is avoided.
v) Loop-failure Detection

When the frequency control loop is not in lock, a signal with the difference frequency
between the divided oscillator frequency and the reference frequency is output from
B325. this difference frequency serves as criterion for synchronization failure. The
signal is fed to the loop-failure detection circuit (B340, B345). If a difference frequency
is generated, T345 becomes conducting and switches off the carrier through the PINregulator B150. Since low-frequency remnants of the frequency demodulation are also
present in this case at the output of B325 and reach the loop-failure detection circuit,
the modulation signal is fed to this circuit via B345 to compensate for this effect.

FILTER BOARD
See circuit diagram 674.0597S
The filter board contains the 1-W RF output stage, the switching facilities for the three
transmitters operating modes, the output filter and directional coupler.
The maximum output power of the 1-W output stage is approx. 1.3 W. The input network
consists of several matching pads to achieve a wideband transformation. The output coupling
is over the resonant circuit C8, L7, C10. The output level is regulated by adjusting the input
voltage.
The criterion for this output voltage is generated through the directional coupler. The control
facilities B92, B95, B108 and B125 are located on the power-supply mother board and the
PIN-diode regulator (B150) on the synthesizer board.
T1 serves in 10-W operation as driver ; with small output powers, it works in the A mode to
prevent any tendency toward oscillation (T2, T3). T2, in response to collector current, controls
the constant current source T3 for the generation of the base bias voltage.
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The 11-member low pass filter consists of five printed coils and hard-wired disk capacitors. In
the adjustment of the filter, maximum input return loss (ST4) in the 87.5-to-108-MHz range
can be set with C13 and C22.
DIRECTIONAL COUPLER

The two terminated directional coupler loops are capacitively and inductively coupled to the
transmitter output line for measurement of the incident and reflected power. Voltages
proportional to the current and voltage are coupled out. These voltages add up in the loop
terminated with R14 and R15 when the output voltage and current are in phase, i.e. when the
termination impedance at the transmitter output (BU4.1) is real.
The voltage rectified by GL2 is a measure of the incident power, which with a resistive 500-
termination is identical with the true power output by the transmitter and which can be read on
the analog meter on the front panel of the transmitter.
The second directional-coupler loop is directional in the opposite sense from the first, so that
the capacitive and inductive components cancel when current and voltage are in phase.
Therefore, in the case of a resistive termination, no voltage appears across GL1.
If the load impedance is not resistive (50 ), the incident power is greater than the true
power, so that power is reflected. In this case we have :
PT = PI - PR where

PT is the true power


PI is the incident power
PR is the reflected power

The standing wave ratio on the feed line is then :


S

1+ r
1 r

with r =

PR
PI

The generated test voltage is approximately 455 mV for an incident power of 10 W and 120
mV for 1 W. GL1 and GL2 are positively temperature dependence of the diodes.
In 30-mW operation, a separate voltage source is used because of the low voltage level on
GL2. GL3 furnishes the test voltage. The diode is loosely coupled through C32 (3 pF) to the
output in order to prevent feedback of the harmonics generated by the diode. GL3 is
positively biased over R25. The level outputs E, F, A have the following voltages for the three
operating modes :
Operating Mode
30 mw
1w
10 w

STI(T) Publication

Level E
+ 12 V
0
0

Level F
Any
0
+ 12 V

56

Level A
Any
+12 V
0V

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Ckt. Description of Exciter

10 W OUTPUT STAGE
See circuit diagram 674.0468S
The frequency-modulated RF signal is fed to the 10-W output stage with a power of approx.
1.3 W. The transformer circuit preceding T20 provides a broadband matching of the lowimpedance T20 base circuit to approx. 50 . The T20 collector is coupled through the
following lowpass filter to the 50- output. The filter transforms the output impedance of T20
to the resistive load at the transmitter output. The combination C31/R31 eliminate a tendency
of the output stage to low-frequency oscillation. With C24 and L20, the output circuit can be
adjusted to an optimum frequency response over the entire Band II.
To achieve the highest possible efficiency of the 10-W output stage, or equivalently the lowest
possible power consumption of the transmitter as a whole, the power regulation and
adjustment for powers greater than approx. 3 W are made over the operating voltage. For
powers below 3 W, the input power is reduced.

REGULATOR BOARD
See circuit diagram 674.0468S
The regulator is designed as an AGC ; it performs the load-regulation and the power
adjustment of the output stage by changing the operating voltage. The regulator IC B50
controls on-time of the transistor T50 as a function of the output voltage and the control
voltage.
The oscillator frequency is determined by R62, R63, C62 (F) to B50.7, 8 and is set to 19 kHz.
The voltage to be adjusted at B50.6 using R68 determines the maximum duty cycle and thus
the maximum power.
The resistors R76, R77 are used to perform current measurements. With increasing load
current, the voltage drop also increases on R76, R77. If it reaches the threshold voltage of
T75, R74 is switched parallel to R68 and thus the maximum duty cycle is reduced, such that
the output current is limited to the given value. A ripple voltage from the regulator board input
is applied to the input of the regulator IC B50 via BR53, BR54 which produces a negative
ripple feedback at the regulator board output. The minimum or maximum output voltage
(about 13 V to 26 V) is determined using R85.

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FM Transmitter
FAULT DIAGNOSIS

EXCITER SU 115

1.

INPUT BOARD
Feed input at ST3 a, b (0,9) + 6 dBm
CHECK FOR + 6 dBm at 5, 17 of Input Board
CHECK FOR 0 dBm at B 11/6 and B44/6
CHECK FOR 18 dBm at BR 5 (L&R) points
CHECK FOR + 6 dBm at P66 Test Point

2.

STEREO CODER
CHECK FOR + 6 dBm at P5 and P35
CHECK FOR + 6 dBm at BR 26 and BR 56
CHECK FOR + 6 dBm at P211 on MINO/STEREO SELECTION
CHECK FOR + 6 dBm at P248 (MPX SIGNAL)
CHECK FOR 4.256 MHz at BR 153
CHECK FOR 532 KHz at BR 155/6 (155/5)
CHECK FOR 38 KHz at BR 135 283

3.

AF & PSU BOARD


CHECK FOR + 6 dBm at BR 151
CHECK FOR BR-14 FOR CARRIER ON/OFF
CHECK TRANSISTORS T 15, T 75 FOR CARRIER ON/OFF
CHECK FOR LOOP FAILURE T 25

4.

SYNTHESISTER

CHECK AF LEVEL AT

ST 100
OF SYNTH 220 MV
B 100
3

CHECK LOOP FAILURE VOLTAGE AT T 345 EMITTER ZERO


(10.5 volts in case of Loop Failure)
CHECK VOLTAGE VARIATION AT MP 113
FROM 6 V TO + 6 V FOR FREQ. VARIATION OF 88 108 MHz
CHECK FOR 10 MHz at pin 5 of B-300
CHECK FOR 10 KC at pin 1 of B-310
CONNECT BR 113 TO AC CHECK FOR FREQ. 96.5 MHz
TUNE L 118 IF NECESSARY CHECK FREQ. ON B200/16
CONNECT BR 115 TO AB
CHECK FOR SET FREQ. ON T120 COLLECTOR/EMITTER
CHECK FOR SET FREQ. ON BR-156 POINT
CHECK OUTPUT AT ST 157 FINAL O/P 2 VMAX
CHECK FOR 10 KC/S ON B 310 PIN 3
CHECK FOR COMPARATOR O/P AT B 310 PIN 10
5.

FILTER BOARD 110 W STAGE


CHECK RF VOLTAGE AT ST 157 (SYN) 2V MAX
CHECK RF VOLTAGE AT ST 1 ON FILTER PLATE
CHECK RF OUTPUT AT ST 3 FILTER PLATE
CHECK RF OUTPUT AT 20 W AMP OUTPUT

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Ckt. Description of Exciter

MONO
L
-18dBm

L
L

A
U
D
I
O

BR5
R

2
3

INPUT BOARD

AF
+6dBm

-18dBm
R

FOR CHANGEOVER TO RIGHT CHANNEL


1. CHANGE LINKS BR5 AND/OR BR27
2. CHANGE BR3 FOR WORKING WITHOUT
STEREO CODER

M/S
+6dBm

1
B
R
27

STEREO
CODER

2
3

MPX

STEREO

+6dBm
STEREO
CODER
BOARD

BR3
OC
(WITHOUT
CODER)

MC

(WITH CODER)
MPX/AF

DISPLAY BOARD 2

Fig. 6 Emergency arrangement if left channel fails

Fig.7(a) Fault Diagnosis-Exciter SU115 Symptom No Modulation


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FM Transmitter

Fig.7(b) Fault Diagnosis Exciter SU 115 Symptom No Modulation

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Ckt. Description of Exciter

Fig. 7(c) Fault Diagnosis Exciter SU 115 Symptom No Modulation

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FM Transmitter

Fig. 7(d) SU 115 Exciter Trouble Shooting Chart Symptom No output power

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Ckt. Description of Exciter

Fig. 7(e) Symptom Syn- Unlock (Fault Diagnosis Exciter SU 115)

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