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Microprocessor Systems

Unit 2:
The Intel 8086 Architecture and
Programming Model


1. Registers and internal architecture (Ch 2)
2. Address generation (Ch 2)



Microprocessor Systems

data.execution of program instructions – BIU Bus Interface Unit . handles instruction fetch and data read/write functions SYSC3601 3 Microprocessor Systems .8086 Registers and Internal Architecture • There are two main functional logic blocks in the 8086/88 processors: – EU Execution Unit .provides interface to memory and I/O 1. controls the address. 2. and control busses.

EDI.8086 Registers and Internal Architecture EAX.etc A B SYSC3601 4 Microprocessor Systems .EBX.

A Execution Unit – Multipurpose Registers SYSC3601 5 Microprocessor Systems .

• EBX Base Index: Typically used to hold offset addresses. remainder). MOV CX.. LOOP HERE . SYSC3601 6 Microprocessor Systems . LOOP/LOOPD. JNZ to label ‘HERE’ • EDX Data: temporary data storage for part of a result from a multiplication (Most significant result) or division (dividend.Execution Unit – Multipurpose Registers • EAX Accumulator: used for arithmetic and logic operations. .080H HERE . Decrement CX. Shift/rotate). Destination for MUL and DIV.. • ECX Count: Typically used to hold a count value for various instructions (repeated strings.

Execution Unit – Multipurpose Registers • ESP Stack Pointer: Used to offset into the stack segment to address the stack. SYSC3601 7 Microprocessor Systems . EBP. EDI and ESI will become clearer when addressing modes are covered. ESP. PUSH/POP. • EDI Destination Index: Typically used as an offset for the destination memory location for string/byte transfers. • The use of the base and offset registers EBX. JSR • EBP Base Pointer: Used to store a base memory location for data transfers. • ESI Source Index: Typically used as an offset for the source memory location for string/byte transfers.

• Z Zero: ‘1’ if the result of an arithmetic or logic operation is zero. • A Auxiliary carry: Holds the “half-carry/borrow” after addition/subtraction.A. or the borrow after subtraction.Z. ‘1’ .odd parity.even parity.P & C are changed by most arithmetic and logic instructions but are unchanged by data transfers. • P Parity: ‘0’ .B Execution Unit – Flag Register • Note: O. (BCD operations on nibbles). • C Carry: Holds the carry after addition. SYSC3601 8 Microprocessor Systems .

If ‘1’. This is the value of the sign bit of the result of the operation. • D Direction: Selects either increment or decrement for the SI and/or DI registers during string and loop functions. If ‘1’. SYSC3601 9 Microprocessor Systems . • O Overflow: Indicates that a result has exceeded the capacity of a register during signed operations. Program flow is interrupted based on the values of the control and debug registers.Execution Unit – Flag Register • S Sign: holds the sign of the result after a arithmetic or logical operation. • I Interrupt: Controls the operation of the INTR (interrupt request) pin. the registers are decremented. interrupts from INTR are enabled. • T Trap: enables trapping if ‘1’.

• NT (80286+) Nested task: Set when a task is nested within another task. • VM (80386+) Virtual Mode: Virtual mode execution (multiple 8086s running in protected mode). 11 is the lowest. • VIF (Pentium+) Virtual Interrupt Flag: A copy of the interrupt flag. SYSC3601 10 Microprocessor Systems . 00 is the highest. • VIP (Pentium+) Virtual Interrupt Pending: • ID (Pentium+) ID: The CPUID instruction is supported. • AC (80486SX+) Alignment Check: Non-aligned address (for co-processor).Execution Unit – Extended Flag Register • IOP (80286+) I/O Privilege level: Two bits correspond to privilege level for I/O operation. • RF (80386+) Resume Flag: Used during debugging.

Bus Interface Unit B C A SYSC3601 11 Microprocessor Systems .

the BIU fetches the next instruction and places it in the instruction queue. the 8088 is limited to 4. JMP) • We will be spending more time later in the course on bus control. • The instruction queue is now replaced by L1/L2 cache. – The instruction queue must be flushed for some instructions (change of program flow.g..The Bus Interface Unit (BIU) A • The BIU can operate in parallel with the EU • The instruction queue – One task of the BIU is instruction “pre-fetch” • Whenever the external busses are idle. • BIU computes the Physical Address (explained later) SYSC3601 12 Microprocessor Systems . – The 8086 can have up to 6 bytes of information in the instruction queue. e.

Intel x86 cores CPU1 CPU2 CPU3 Copro 16K L1 Cache 256K L2 Cache Pentium II. Pentium Pro SYSC3601 13 Microprocessor Systems . III. 4 same as Pentium Pro with increased L1 & L2 cache sizes.

– EIP (32 bits) in 80386 and up • IP contains the offset of the next instruction to be fetched from the beginning of the code segment. • Can be modified with a JMP or CALL instruction. • Whenever the instruction pointer is saved on the stack. it is automatically adjusted to point to the next instruction to be executed (as opposed to fetched).B Bus Interface Unit – Instruction Pointer • The Instruction Pointer (IP) is updated by the BIU. • Used with CS (see next few slides…) – Physical address of next instruction = CS:IP SYSC3601 14 Microprocessor Systems .

C Bus Interface Unit– Segment Registers • Segment registers are combined with other registers to generate 20-bit addresses. 15 SYSC3601 15 Microprocessor Systems .

SYSC3601 16 Microprocessor Systems . • ES Extra Segment: Additional data segment used by some string instructions.Bus Interface Unit – Segment Registers • CS Code Segment: Used to compute the starting address of the section of memory holding code (restricted to 64K in REAL mode). • FS&GS Additional segment registers in the 80386 (and up) for program use. • DS Data Segment: Used to compute the starting address of the section of memory holding data (restricted to 64K in REAL mode). • SS Stack Segment: Used to compute the starting address of the section of memory holding the stack (restricted to 64K in REAL mode).

The first Mbyte of memory is called real or conventional memory. Real Mode (the 8086/8088/186 can only operate in this mode) • • Allows the µP to address the first 1Mbyte of memory only. 17 Microprocessor Systems . Protected mode (80286. length and access rights. 2.) • • SYSC3601 This mode uses the segment register contents (called a selector) to access a descriptor from a descriptor table. The descriptor describes the memory segment’s location..Address Generation • Two types of address generation: 1..

– The offset address selects a location within the 64K memory segment. – Memory locations are often written as: segment:offset C000:04BA SYSC3601 18 Microprocessor Systems . – The segment address defines the start of a 64K block of memory.Real Mode Address Generation • Memory addresses consist of a segment address plus and offset address.

Real Mode Address Generation Ex. If IP=1200H and CS=1400H then next instruction will be fetched from: 1400:1200 or 14000H +1200H -----15200H SYSC3601 19 Microprocessor Systems .

Segment Offset Special Purpose CS IP Instruction address SS SP or BP Stack address DS BX. which define the segment and offset register combination used by certain addressing modes.SI.DI. 8bit # or 16bit # Data address ES SYSC3601 DI (for string instruction) String destination 20 Microprocessor Systems .Real Mode Address Generation – Funky Rules… • The µP has a set of rules that apply whenever memory is addressed.

2. – Move the existing contents to the new physical location. SYSC3601 21 Microprocessor Systems . Memory segments (i.Real Mode Address Generation • Notes: 1.e. The segment-offset scheme allows programs to be relocated in memory (on 16 byte boundaries). the 64K blocks) may overlap if full 64K are not needed. then update the segment register.

FE000H ← FE00:0000 . . . . 16 bytes resolution FDFF0H SYSC3601 ← FDFF:0000 22 Microprocessor Systems . .Segment Resolution FE010H ← FE00:0010 ≡ FE01:0000 . . . FE005H ← FE00:0005 .

Examples • Ex 1: MOV DL.[BP] Uses an absolute (i.e. physical) source address of: SS x 16 + BP • Ex 2 (overlap): FE00:0005 FE000H +0005H -----FE005H FDFF:0015 FDFF0H +0015H -----FE005H Same location in memory! SYSC3601 23 Microprocessor Systems .Real Mode Address Generation .

Real Address Mode Generation SYSC3601 Start of segment Start of segment Start of segment 24 Microprocessor Systems .

• The stack grows down in memory (i. initialize SP to 0H. • Typically.. • POP CS is NOT allowed. Will decrement to 0FFFFH on first PUSH to point to top of segment. towards 0).e. • Only words (8086-80286) and double words (80386.. SYSC3601 25 Microprocessor Systems . First Out (LIFO) queue.) can be pushed/popped on/off the stack.Stack Operation • The stack is a Last-In..

BX AX ← ← ← ← ← ← 26 ← 1234H 1234H from stack High byte transferred first so that value is LITTLE ENDIAN in memory. AX 2a SS x 10H + SP . PUSH 1234H onto stack 3 POP .1 2b SS x 10H + SP .2 SS x 10H + SP (34H) SS x 10H + SP + 1 (12H) SP + 2 Microprocessor Systems . 12H High order 34H Low order SP .Stack Operation Example ← 1 MOV 2 PUSH BX .1234H .2 2c SP 3a AL 3b AH 3c SP SYSC3601 BX.