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CONTINUOUS-TIME

ANALOG CIRCUIT OPERATION

New Mexico State University, Las

Cruces, NM

continuous-time analog CMOS circuits

The drastic reduction in the supply voltages of CMOS VLSI systems driven by technological as

well as power reduction constraints has forced analog designers to divert from conventional

analog circuit architectures which become non functional in a reduced supply environment and

look for new techniques for low voltage, high performance operation of analog CMOS circuits.

In this presentation a family of high performance low-voltage analog CMOS circuits is

introduced. These are based on the utilization of static, dynamic and switched floating voltage

sources. These circuits operate in all cases with a single supply voltage close to a transistor's

threshold voltage.Among the circuits discussed in this presentation we include: one and two

stage class AB op-amps, rectifiers, filters, transconductors, analog multipliers, etc.

Presented by Jaime Ramirez-Angulo, professor of Electrical Engineering , IEEE fellow and director of the

VLSI lab at the Klipsch School of Electrical and Computer Engineering at New Mexico State University in

Las Cruces, New Mexico (USA). He received a degree in Communications and Electronic Engineering

(Professional degree), a M.S.E.E from the National Polytechnic Institute in Mexico City (1973 and 1976

respectively) and a Dr.-Ing. degree from the University of Stuttgart in Germany in 1982. His research is

related to following areas of analog and mixed signal VLSI design: low-voltage CMOS circuit design, test

techniques for mixed-signal VSLI systems, continuous-time filters and analog array processors.

OUTLINE

I.

II.

Introduction

Basic techniques for continuous-time lowvoltage operation

III. Continuous-time low-voltage amplifier schemes

IV. Low-voltage op-amp architectures with rail-torail input and output swings

V. Low-voltage circuits based on floating gates

VI. Conclusions

Within the next few years most mixed-signal systems will

require operation with sub-volt supply voltages (VDD<1V)

Why?

a) power dissipation reduction (digital circuits

Power VDD2)

b) Technology down scaling (lower oxide

breakdown voltages, no voltage doublers

allowed!)

c) Volume, weight reduction and extended battery

life (wireless applications)

I. INTRODUCTION: Definition

Low-Voltage circuit

Operation with single supply VDD less

than the sum of the threshold voltages of a

PMOS and an NMOS transistor

VDD<VTHn+|VTHp|

VDD<1V for current CMOS technology

with VTH=0.45V

CHALLENGES

require high performance analog front end circuits.

(VDSsat) go against performance: bandwidth, accuracy, power

consumption, silicon area, offsets,..

switched capacitor circuits but their effective signal bandwidths are orders

of magnitude below technology limits

drops (plus signal swing) supplies

I. INTRODUCTION

Example : Two stage OP-AMP with class AB

output stage

+

VDS

VGS

_

+

VSG

MoutP

Vbat

MoutN

VGS

Vdd>Vth+2VDSsat+Vinswing

Vdd>2Vth+VDSsat+Vbat

must operate close to lower rail at

approximately constant voltage

(Vinswing=0)

REDUCTION IN

CONTINUOUS-TIME ANALOG CIRCUITS

IIa. Floating voltage sources:

1) Static (DC level shifters)

2) Dynamic (signal dependent shifters)

3) Switched

IIb. Multiple Input Floating gate transistors

1) Conventional

2) Quasi-floating-gate

IIc. Flipped voltage followers

using DC level shifters

+

Vb

+

A

Vin

Vout

Vin

Vb

Vout

(a)

Vb

B

I1

(b)

(c)

I1+I2

(d)

mirror with reduced supply requirements (c ) Implementations of

floating unipolar DC level shifters (d) implementation of floating

bipolar DC Level shifter

can be used to reduce the effective threshold voltage of MOS

transistors [1]

a) Conventional Cascode mirror:

Vin=2VGS= 2Vth+2VDSsat;

Vout=VGS+VDSsat=Vth+2VDSsat

Vtotal=Vin+Vout=3Vth+4Vdsat

b) Cascode mirror with DC level shifters

Vin=2VTH+2VDSsat-2Vb;

Vout=Vth+2VDSsat-Vb

Vtotal=3Vth+4VDSsat-3Vb=3VTH+4VDSsat

Where:

If

Vth=Vth-Vb

Vb=Vth then Vth= 0 Then Vtotal= 4VDSsat (<1V)

voltage to a value close to zero!

[1] "Current mirrors with low input voltage requirements for built in current sensors," J.

Ramrez-Angulo, 1994 IEEE International Symposium on Circuits and Systems, pp. 529- 532, London, England,

May 30- June 2, 1994

level shifters

a) and b) Resistor/Current source, c) Voltage follower

d) Differential amplifier, e) Low speed Switched capacitor

Remarks:

One of the terminals of the floating voltage source requires to be

connected to a circuits high impedance node, the other terminal to

a low impedance node.

Above circuits can be used to implement both static and dynamic

floating sources

Examples: Class AB CMOS inverters with

Vdd<VthN+|VthP|

sources (b)Resistor-current source implementation (c)

switched implementation

Input Floating Gate Transistors

Multiple Input Floating Gate Transistor: (a) Layout (b) symbol (c)

equivalent circuit model.

Low voltage operation using multiple input

floating gate transistors

Floating gate voltage in a MIFG transistor is a linear

weighted addition of control input voltages V1, V2, Vn

Basic principle for low voltage operation [2]:

Use one terminal for biasing purposes (to set VGQ close to one of

the supply rails) and the remaining terminals for signal injection

[2] "Low-Voltage OTA architectures Using Multiple Input Floating gate Transistors," J. Ramrez-Angulo, S.C. Choi, G. GonzalezAltamirano, IEEE Transactions on Circuitsand Systems, vol. 42, No. 12, pp.971-974, November 1995

Differential voltage in floating gate differential pair:

VGd = VG1-VG2,

Vdi=Vi1-Vi2,

ai=Ci/(C1+C2+..+Cn)

Reduced threshold voltage + Linear combination of differential

control voltages allows for great design flexibility [2]

[2] "MITE Circuits: The Continuous time counterpart to switched capacitor circuits," Jaime Ramirez-Angulo and Antonio Lopez,

IEEE Transactions on Circuits and Systems, special issue on applications of floating gate transistors, vol. 48, No. 1, February 2001

Single ended two input case

C1

C2

VG = VBIAS

+ Vin

C1 + C 2

C1 + C 2

Effective threshold voltage

C1

Vth' = Vth VBIAS

C1 + C 2

Low voltage CMOS inverter

uisng FG transistors

"Modeling Multiple-Input Floating Gate Transistors for Analog Signal Processing," J. Ramrez-Angulo, G. GonzalezAltamirano and S.C. Choi, IEEE International Symposium on Circuits and Systems, Hong Kong, June 9-12, 1997

Drawback:

Charge trapped in floating gate

can lead to large (temperature

dependent) DC offsets

Clarge forms voltage divider with

feedback elements CF=Ctotal-Clarge

Effective gain-bandwidth product

Of floating gate circuit is reduced by relatively large factor

K= Clarge/(Ctotal-Clarge)

floating gate circuits

Quasi floating gate transistor:

Gate capacitively coupled

to signals V1,V2,Vn

Gate connected to supply rail

using a very large valued resistor

Rlarge sets quiescent gate voltage

to the supply rail voltage and minimizes

supply requirement

Rlarge implemented using reverse

biased PN junction

QFG PMOS transistor

c) Layout

d) Equivalent circuit

Advantages

No charge trapped as in true floating gate transistors

Well defined gate quiescent voltage at supply rail minimizes circuits supply

requirements

Input signals can have arbitrary DC components

Drawbacks

Rlarge forms high pass circuit with signal coupling capacitors

swing at junction implementing Rlarge must be limited to avoid forward

biasing the junction

PN junction nonlinear can introduce distortion for gate swings

voltage follower

Flipped voltage Follower: Cascode amplifier with

feedback

Rz HIGH!

Ibias

Very low input Rx=(1/gm)(1/gmro)

High ouput impedance Rz=ro(gmro)

Very low voltage requirements at node x: VDSsat

Signal variations at node Vz (not in the signal

path)

Flipped follower implements an Active DC

level shift

Vz

Ry

VERY

HIGH!

Iin

Vy

LOW!

Rx

Ibias

Ibias

Iout

z

y

Iin

Vbias

x

+

Vin

Low voltage mirror with very low input impedance and low input

voltage requirements

Low Voltage High Performance CMOS Current Mirrors," J. Ramrez-Angulo,

R.G. Carvajal and A. Torralba, IEEE 43drd Midwest Symposium on Circuits and

Systems. Lansing, MI, August 8-11, 2000.

M3

VS

VSGQ-Vd/2

V1

VSGQ

V1

M2

VCM

M1

ID1

ID2

VSGQ

MCM

M1

VCM

VSGQ+Vd/2

M2

V2

ID2

V2

Ib

Vd

common mode

sensor

(a)

( c )

( b)

implementation using flipped voltage follower c) Transconductance

characteristic

"A new Class AB differential Input stage for implementation of low voltage high slew rate op-amps and linear

transconductors," J. Ramirez-Angulo, R. Gonzalez-Carvajal, A. Torralba and Carlos Nieva, IEEE International Symposium on

Circuits an Systems, May 6-9, Sidney Australia

Voltage Sources

Applications:

Low-voltage continuous-time amplifiers based on inverting opamp configuration (Assume single

supply voltage VDDand signal Vin=Vs(t)+VDD/2)

Approach:

Keep both input terminals of op-amp closte to one of the supply rails by Inserting a floating DC

source with value Vbat=VDD/2 in series with negative op-amp input.

"A simple technique for low-voltage op-amp operation in continuous-time," J. Ramrez-Angulo, A Torralba, R.G.

Carvajal and J.Tombs, IEE Electronics Letters, vol. 35, No. 4, February 18th, 1999, pp. 263-264

R2

Vin

R1

VDD/2

_

+

RF

Vin

R1

Vout

I

VDD/2

R1

_

Vout

(b)

Vbat

+ _

_+

Vout

R1

(a)

+

Vin

_

R2

RF

(c)

Low voltage amplifier based on DC floating sources (a) Standard inverting configuration (b) wideband

constant bandwidth configuration based on current sensing c) Fully differential version of circuit of Fig. a

dynamic floating voltage sources

Principle:

Rearrange non-inverting configuration by inserting a source Vs in series

between output and negative op-amp input terminals and connecting the

positive terminal to one of the supply rails

"Low-voltage CMOS amplifiers with wide input-output swing based on a novel scheme, J. Ramrez-Angulo, A Torralba,

R.G. Carvajal and J.Tombs, IEEE Transactions on Circuits and Systems-I, vol. 47, No. 5, May 2000, pp. 772-774.

Ib

+

_ Vs

OA

Vo

OA

OA

Vo

Vo

Vs

_+

(a)

(b)

Ib

Ib=Vs/R

(c)

Dynamic FVCVS technique. a) Op-amp in voltage follower configuration. b) Grounding the op-amp input and

inserting a FVCVS in the feedback path c) implementation of FVCVS with resistor and current sources

Ib

Vref

Vref

+

_ DA

V's

R

Ib

_OA

Vcn

(a)

R

Ib

Vout

Ib

(b)

with an auxiliary opamp DA. b) STEP 2: Current-to-voltage conversion inserting the

FVCVS in the feedback path of the main operational amplifier OA.

Vref

OA

A'

(A-1)*I bQ

R

A*I b

B

Vout

A*I b

(A-1)*I bQ

B'

A using the FVCVS technique. This

circuit replaces the circuit in figure b

above. Ib and Ib Q are obtained using

two copies of the circuit in figure 2a,

with inputs Vs and Vs Q, respectively.

amplifier architectures with rail-to-rail

input and output swings

Basic scheme of low voltage

two stage class A/AB op-amp

based on inverted battery

technique: (a) Single ended

scheme, (b) two possible

implementations of the floating

battery, (c) fully differential

scheme.

"Class AB output stage for low voltage CMOS opamps with accurate quiescent current control," A.

Torralba, R.G. Carvajal, J. Martinez-Heredia and J.

Ramirez-Angulo, Electronics Letters, vol. 36, No. 21,

12th October 2000, pp. 1753-1754.

differential op-amp

RF

VcntCMP

Icnt

Vbias

M17

M5

Rb

Vi-

Vi+

RCM4

RCM3

Va

R1

Vb

M3

M4

VcntCMN

Vb

VcntCMN

M18

VcntCMP

MBCMFN

Vo+

M9

M10

M15

Ro

Vo-

Icnt

RCM

RCM

M11

M12

(b)

_+

Vout

RF

M6

(c)

M16

Ro

+_

Icnt

M20

Vbias

Vbat

Rbp

(a)

VrefCM

+

Vin

_

M8

Vo+

Rbat

Va

Icnt

M19

M2

M1

Vo-

M7

MBINPST

R1

Icnt

VcntCMP

M14

VcntCMN

(a) Implementation uisng input stage with

local common mode feedback and class

AB output stage with inverted battery (b)

low-voltage common mode feedback

network c) Low-voltage test setup

Simple technique using Local CMFB to enhance Slew Rate and bandwidth of one-Stage cmos op-amps, Jaime

Ramirez-Angulo and Michael Holmes. Electronics Letters, vol. 38, No 23, pp. 1409-1411, November 7th 2002,

class AB/AB fully differential op-amp

VbatP

Icnt

VbatP

MBINPst

M17

M5

M1P

Va

M1

Vi-

Vsh

MFVF

MBFVF

Rbat

Vb

Rbat

Vbias

Vi-

M1

M2

Va

Icnt

M3

VbatN

M4

VbatN

Cc

Vb

M6

M3

M7

M3P

Rc

M4

M6

VcntCM

Icnt

M18

Vo+

Vi+

Vo+

Cc Rc

M7

M8

M8

VoVa

MBinpst

M5

Vb

M2P

Vi+

Ibat

M2

Ibat

Vo-

VbiasP

Icnt

M19

M4P

(a)

(a)

Vbias

VbiasN

MBCMFN

MB

VbatP

M13

M9P

Vo-

M10P

M9

Ro

M10

VbatN

Ro

Va

M11

Vb

M12

Ibat

Ibat

Vo+

Ro

M10

M9

Ro

VrefCM

VoRbat

RCM

VrefCM

M20B

RCM

RCM

IQ

VbatP

(b)

M15

IQ

Vo+

RCM

M19B

MBCMFN

M16

VbatN

M11

VcntCM

M12

M14

(c)

stage using pseudo class AB differential amplifier

output stage using inverted battery (b) Common mode

Feedback network c) IQ control circuit

(b)

stage op-amp (b) Low voltage

common mode feedback

network

transient response comparison

*conventional classA/class A two stage fully differential op-

**************************************************************

800

750

V(VO)

V(VO)

500

TRANSIENT

RESPONSES (mV)

250

V(VI)

0

-250

V(VI)

V(VO)

400

V(VI)

0

-400

-500

-800

0

-750

0

0.4

0.8

1.2

TIME (us)

1.6

0.4

1.2

1.6

2.0

TIME (us)

V(VI)

V(VO)

TopSPICEw32 5.82b

(a)

0.8

2.0

01-APR-2003 05:27:37

(b)

(a) Transient response of new class AB/AB op-amp (b) Transient response of

conventional class A/A op-amp with same static bias current

A New Power Efficient Fully Differential Low Voltage Two State Op-Amp Architecture , J.

Ramrez-Angulo S. Thoutam G.O. Ducoudray and R.G. Carvajal, VLSI'03: June 23-26, 2003, Las

Vegas, Nevada, USA. pp. 87-02

input floating gate transistors

Options for input swing

reduction with common mode

close to a supply rail

1) Use DC level shifter

VLS=Vdd/2 (discussed

previously)

2) Use dynamic level shifter

(discussed previously)

3) Use capacitive voltage

dividers (shown here):

Low-voltage amplifiers with Capacitive divider: (a) Basic scheme, (b) Voltage

follower (c) Fully differential scheme (d) Gain C1/C2 fully differential amplifier.

microphotograph of fabricated chip, (b) detail of the

single ended amplifier and (c) fully differential version.

transfer characteristic and (b) step

transient response.

"Low-voltage CMOS Op-amp with rail-to-rail signal swing for continuous-time signal processing using multiple-input

floating-gate transistors," J. Ramirez-Angulo, R. G. Carvajal, J. Tombs, and A. Torralba, IEEE Transactions on Circuits

and Systems, special issue on applications of floating gate transistors, vol. 48, No. 1, January 2001, pp. 110-116

gate transistors

Closed loop application I: Low-voltage gain programmable

amplifier

V I+

V I-

SW 4

8C

SW 3

4C

SW 2

2C

SW 1

QFGMOS1

_

+

SW 1

SW 2

2C

SW 3

4C

SW 4

8C

_

+

VO+

V O-

C

QFGMOS2

Jaime Ramirez-Angulo, Antonio J. Lopez-Martin and Ramon G. Carvajal, ISCAS 2003, May

25-28, 2003, Bangkok, Thailand

transistors

Closed loop application II: Low-voltage D-to-A converter

2N-1C

VDDdN-1

4C

1.5

QFGMOS1 (2N-1)C

VDDd2

2C

C

_

+

VDDd0

C

-VDDd0

2C

-VDDd1

VO-

0

-0.5

(2N-1)C

-VDDd2

2N-1C

VO+

-1

4C

-VDDdN-1

0.5

Volta ge (V)

VDDd1

QFGMOS2

-1.5

3

4

Time (ms )

transistors

Closed loop application III: Low-voltage D/A converter

2N-1C

VDDdN-1

4C

QFGMOS1 (2N-1)C

VDDd2

2C

VDDd1

C

_

+

VDDd0

C

-VDDd0

2C

-VDDd1

4C

(2N-1)C

-VDDd2

2N-1C

-VDDdN-1

QFGMOS2

VO+

VO-

transistors

M1

IB

M2

VINVI2VI1-

M4

M3

CN

C2

C1

CN

M1A

M2A

MQ2

MQ1

C2

C1

M5

VIN+

M1B

VI2+

VI1+

VOSW B

CAZ

R1

R1 M

6

CMFB

CC RC

M7

RC CC

M8

M2B

R1

M9 R1

VO+

SW A

CAZ

DC input offset voltage can be amplified by large DC open opamp open loop gain

Closed loop applications require operational amplifier with an

autozeroing circuit

open loop applications

Low-voltage mixer with quasi-floating gate transistors

RL

RL

Rlarge

Rlarge

Vin1a

Vin2a

M1

M2

Ib

Rlarge

Rlarge

Rlarge

Vin1b

Vin1b

Vin2a

Vin2b C

MFVF

Vin1a

M3

M4

Vin2b

Vin2a

Vin1a

Vin2a

Vin1a

Vin2b

C

C

M5

Vcm

C

C

A new Family of Low-Voltage Analog Circuits Based on Quasi Floating Gate Transistors, J. Ramirez-Angulo, C.

Urquidi, R.G. Carvajal, A. Lopez-Martin, IEEE Transactions on Circuits and Systems, II May 2003.

gate transistors

MRlarge1

Vclk

C1

Vin

Vclksh

MRlarge1

MRlarge2

Vclkn

Vclk

MRlarge2

C2

MpassN

Vclkn

MpassP

V clknsh

MpassP

MpassN

Vclk

Vclkn

Vclkn

Vout

Chold

VG

Vin

(a)

Mswitch

Vout

Chold

(c)

MRlargeP

Vclk

Vclk

Vclknsh

MRlargeP1

Vout

Vin

V1

Chold

(b)

MRlargeP2

C1

V2

C2

V2sh

V1sh

M2

M1

R

Q

(d)

Low voltage quasi-floating gate circuits using supply voltage boosting: examples of quasifloating gate supply boosting (a) Rail-to-rail sample and hold using complementary CMOS

switch (b) almost rail-to-rail to-rail sample and hold with NMOS switch, (c) rail-to-rail sample

and hold with bootstrapped switch (d) NAND gate with resistive load.

A New Analogue Switch for Very Low Voltage Applications, F. Muoz1 J. B. Palomo and M.

Kachare, IEE Electronics Letters, MAY 1 2003; v.39, no.9, p.701-702

V. CONCLUSIONS

a) Three basic techniques to reduce supply requirements of

continuous-time analog systems were discussed

b) A new family of low-voltage high performance linear analog

circuits that operate in continuous-time with single supply

voltages close to a transistor thresholds voltage presented

c) Most circuits presented are class AB and have also very low

static power dissipation

d) The circuits presented here will allow implementation of

mixed-mode systems with a single supply voltage Vdd<0.7V

in new CMOS technologies (<0.2um) with transistor

thresholds voltages close to 0.4v

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