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development board
User manual (ordb2a-ep4ce22 board)
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This board is designed by ORSoC AB. The board is available in the OpenCores webshop (http://opencores.org/shop,items)
Copyright 2011 ORSoC
Page 2 / 19
Table of Contents
Resources on the board_____________________________4
FPGA____________________________________________5
Supply________________________________________________________5
Memory_________________________________________ 6
SDRAM_______________________________________________________6
SPI FLASH_____________________________________________________6
SDIO FLASH___________________________________________________6
Fast Ethernet_____________________________________7
RMII timing parameters________________________________________7
MDC/MDIO timing parameters___________________________________7
USB____________________________________________ 8
Expansion________________________________________9
JP1__________________________________________________________9
JP2__________________________________________________________9
This board is designed by ORSoC AB. The board is available in the OpenCores webshop (http://opencores.org/shop,items)
Copyright 2011 ORSoC
Page 3 / 19
FPGA
Memory
SDRAM 32 Mbyte
Fast Ethernet
USB
Expansion
Supply
This board is designed by ORSoC AB. The board is available in the OpenCores webshop (http://opencores.org/shop,items)
Copyright 2011 ORSoC
Page 4 / 19
FPGA
The board is populated with a ALTERA Cyclone IV device. Manufacturers part number is
EP4CE22F17C6N
Resources
EP4CE22F17C6N
22320
594
66
20
153
Configuration of the FPGA is done from SPI FLASH using Active Serial (AS) mode.
Mode select signals connection supporting AS:
Mode
state
MSEL2
GND
MSEL1
2.5V (FPGA_PLL)
MSEL0
GND
Supply
The device uses a number of different supplies:
Supply
Voltage
Source
FPGA_CORE
1.2V
EP5382
FPGA_PLL
2.5V
SP6201, LDO
VCCIO
3.3V
EP5382
Note:
Digital part of PLL is supplied from FPGA_CORE via LC filters.
This board is designed by ORSoC AB. The board is available in the OpenCores webshop (http://opencores.org/shop,items)
Copyright 2011 ORSoC
Page 5 / 19
Memory
SDRAM
The board is populated with an SDR SDRAM from Micron.
Manufacturers part number:
MT48LC16M16A2P6A
Address table
Parameter
16Meg x 16
Configuration
4 Meg x 16 x 4 banks
Refresh count
8K
Row addressing
8K A[12:0]
Bank addressing
4 BA[1:0]
Column addressing
512 A[8:0]
Timing parameters
Speed
grade
-6A
Clock
frequency
167 MHz
Access time
CL=2
-
Setup time
Hold time
CL=3
5.4 ns
1.5 ns
0.8 ns
SPI FLASH
The SPI FLASH has dual uses
1. Configuration storage for FPGA
2. Instruction and data storage for OpenRISC processor
The FPGA is configured for Active Serial, AS, mode and will at powerup configure from SPI
FLASH if a valid FPGA image is stored in memory.
Default population is with U6, W25Q08 1Mbyte. Optional population is U7 W25QG64, 8
Mbyte. U6 is SO16 and U7 S016 wide.
SDIO FLASH
JP4 is a micro SD connector. Board is compatible with both SD and SDHC FLASH card.
This board is designed by ORSoC AB. The board is available in the OpenCores webshop (http://opencores.org/shop,items)
Copyright 2011 ORSoC
Page 6 / 19
Fast Ethernet
Fast Ethernet is implemented with Micrel KSZ8021 PHY. Package is a small QFN 4x4 mm.
Board has an RJ45, JP3, with built-in magnetics and dual LED indicators.
One LED is connected to 3.3V. The other is connected to PHY and has programmable
behavior. Default is On when link is upt and toggling when there is activity on the line.
Ethernet has a programmable interrupt line.
A 25 MHz oscillator is connected to the clock input of the PHY. This clock is internally
frequency doubled and sourced on pin 16 as a reference clock connected to FPGA clock
input. This is a continuous clock and can source an PLL in the FPGA.
The Ethernet PHY has a RMII interface towards the MAC in the FPGA. All interface signals
are synchronous to the reference clock.
RMII timing parameters
Timing parameter
Description
Min
Typ
Max
20
Unit
Tcyc
Clock cycle
T1
Setup time
ns
T2
Hold time
ns
Tod
Output delay
ns
13
ns
Description
Min
Typ
Max
400
Unit
Tp
MDC period
ns
Tmd1
10
ns
Tmd2
ns
This board is designed by ORSoC AB. The board is available in the OpenCores webshop (http://opencores.org/shop,items)
Copyright 2011 ORSoC
Page 7 / 19
USB
The board has an USB level shifter to guarantee USB defined signals.
Board has an USB connector of type micro AB. With different type of cabling the following
scenarios can be supported
1. USB type A
2. USB type B
3. USB micro type A
4. USB micro type B
5. USB on the go
On USB signal there is logic controllable resistors
D+ pulldown, 15K
D- pullup, 1.5K
There is a signal. VSENSE, which monitors the 5V signal in the USB interface.
Signal ENB controls a power switch for the USB supply line.
Note:
There is support for an additional USB port. If used connector JP4, SDHC, is removed and
U21 and JP6 is populated.
JP6 is a USB type A connector.
This board is designed by ORSoC AB. The board is available in the OpenCores webshop (http://opencores.org/shop,items)
Copyright 2011 ORSoC
Page 8 / 19
Expansion
On the solder side there is two 80 pin surface mount expansion connectors.
Connector manufacturer and part number:
SAMTECH
SFM-135-02-S-D-A
JP1
JP1 has 8 general purpose IO and 2 dedicated clock/input signals. Signal level is 3.3V.
Signals connected to FPGA bank 4.
Also present is 10 IO signals shared with USB interface. These can be used as general
purpose IO if U3 is removed.
JP2
JP2 has 54 general purpose IO and 6 2 dedicated clock/input signals. Signal level is 3.3V.
Signals connected to FPGA bank 6,7 and 8.
Intended use for JP2 is
1. PCI
2. LPC, low pin count interface as defined by INTEL
3. AC'97 digital audio interface as defined by INTEL
This board is designed by ORSoC AB. The board is available in the OpenCores webshop (http://opencores.org/shop,items)
Copyright 2011 ORSoC
Page 9 / 19
The FT4232H is FTDIs 5th generation of USB devices. The FT4232H is a USB 2.0 High
Speed (480Mb/s) to UART/MPSSE ICs. The device features 4 UARTs. Two of these have
an option to independently configure an MPSSE engine. This allows the FT4232H to
operate as two UART/Bit- Bang ports plus two MPSSE engines used to emulate JTAG, SPI,
I2C, Bit-bang or other synchronous serial modes.
FT4232H is connected to USB connector of type micro B, JP5.
Usage of FT4232
Channel
Mode
Usage
JTAG
FPGA configuration
JTAG
OpenRISC debug
SPI
UART
Linux console
UART
Linux terminal
This board is designed by ORSoC AB. The board is available in the OpenCores webshop (http://opencores.org/shop,items)
Copyright 2011 ORSoC
Page 10 / 19
Supply
Board need an 5V supply. Depending on population supply can have three sources:
Source
Populate
Comment
R2
R1
R39
Converter
3.3V
EP5382
1.2V
FPGA core
EP5382
2.5V
SP6201
3.3V
SDHC
EP5382
5V
USB
MIC2026
This board is designed by ORSoC AB. The board is available in the OpenCores webshop (http://opencores.org/shop,items)
Copyright 2011 ORSoC
Page 11 / 19
FPGA interconnect
Configuration
JTAG
TDI
U1.H4
U8.16
TMS
U1.J5
U8.17
TCK
U1.H3
U8.18
TDO
U1.J4
U8.19
nSTATUS
U1.F4
CONF_DONE
U1.H14
U8.23
10K pullup, R9
nCONFIG
U1.H5
U8.22
nCE
U1.J3
U8.21
DATA
U1.H2
U6.2
U7.8
DCLK
U1.H1
U6.6
U7.16
nCSO
U1.D2
U6.1
U7.7
ASDO
U1.C1
U6.5
U7.15
HOLDn
U1.G2
U6.7
U7.1
Wn
U1.H14
U6.3
U7.9
10K pullup, R7
Config status
SPI FLASH
AS
Control
JTAG Debug
JTAG
TDI
U1.G5
U8.27
TMS
U1.F2
U8.29
TCK
U1.E1
U8.26
TDO
U1.F1
U8.28
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Copyright 2011 ORSoC
Page 12 / 19
UART
UART0
TX0
U1.D1
U8.38
TX on U8
RX0
U1.F3
U8.39
Rx on U8
TX1
U1.C2
U8.48
TX on U8
RX1
U1.B1
U8.52
RX on U8
DQ15
U1.T6
U2.53
DQ14
U1.P3
U2.51
DQ13
U1.N6
U2.50
DQ12
U1.N3
U2.48
DQ11
U1.R5
U2.47
DQ10
U1.P8
U2.45
DQ9
U1.P1
U2.44
DQ8
U1.T4
U2.42
DQ7
U1.N1
U2.13
DQ6
U1.L3
U2.11
DQ5
U1.L2
U2.10
DQ4
U1.K5
U2.8
DQ3
U1.K1
U2.7
DQ2
U1.K2
U2.5
DQ1
U1.J2
U2.4
DQ0
U1.J1
U2.2
DQMH
U1.R6
U2.39
DQML
U1.L1
U2.15
BA1
U1.N5
U2.21
BA0
U1.R3
U2.20
A12
U1.T5
U2.36
A11
U1.R7
U2.35
A10
U1.M8
U2.22
A9
U1.T7
U2.34
A8
U1.T3
U2.33
A7
U1.T2
U2.32
UART1
SDRAM
SDRAM
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Copyright 2011 ORSoC
Page 13 / 19
U1.P6
U2.31
A5
U1.N8
U2.30
A4
U1.M7
U2.29
A3
U1.L7
U2.26
A2
U1.L8
U2.25
A1
U1.P2
U2.24
A0
U1.M6
U2.23
RAS
U1.R1
U2.18
CAS
U1.N2
U2.17
WE
U1.L4
U2.16
CS
CK
U1.R4
CKE
U2.19
Connected to GND
U2.38
U2.37
Connected to 3.3V
SD connector
SD
DAT3
U1.J14
JP4.2
DAT2
U1.J13
JP4.1
DAT1
U1.K16
JP4.8
DAT0
U1.K15
JP4.7
CMD
U1.J15
JP4.3
CLOCK
U1.J16
JP4.5
JP4.4
3.3v
JP4.6
GND
Ethernet, RMII
MICREL KSZ8021
RXD1
U1.L16
U4.12
RXD0
U1.N14
U4.13
RXER
U1.N16
U4.17
CRS_DV
U1.N15
U4.15
TXD1
U1.R16
U4.21
TXD0
U1.P16
U4.20
TXEN
U1.P15
U4.19
INTRP
U1.M16
U4.18
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Copyright 2011 ORSoC
Page 14 / 19
U1.M15
U4.16
MDIO
U1.L14
U4.10
MDC
U1.L15
U4.11
USB
USB
VMO
U3.13
VPO
U3.12
OE_N
U3.2
U1.N9
VM
U3.5
VP
U3.4
U1.P11
SPEED
U3.9
ACC_DET
JP7.4
V_SENSE
PULL_UP_D+
PULL_DOWN_D+
This board is designed by ORSoC AB. The board is available in the OpenCores webshop (http://opencores.org/shop,items)
Copyright 2011 ORSoC
Page 15 / 19
Expansion
JP1
JP1
CLK0
U1.T9
JP1.15
CLK1
U1.R9
JP1.16
IO0
U1.R11
JP1.7
IO1
U1.T11
JP1.8
IO2
U1.T12
JP1.9
IO3
U1.R10
JP1.10
IO4
U1.R12
JP1.11
IO5
U1.T10
JP1.12
IO6
U1.T13
JP1.13
IO7
U1.P9
JP1.14
IO8
U1.R13
JP1.19
IO9
U1.M10
JP1.20
IO10
U1.T14
JP1.21
IO11
U1.N9
JP1.22
IO12
U1.R14
JP1.23
IO13
U1.P11
JP1.24
IO14
U1.T15
JP1.25
IO15
U1.N11
JP1.26
IO16
U1.P14
JP1.27
IO17
U1.N12
JP1.28
JP1.29
..
JP1.68
Not connected
3.3v
JP1.1
JP1.2
JP1.3
JP1.4
GND
JP1.5
JP1.6
JP1.17
JP1.18
JP1.69
JP1.70
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Copyright 2011 ORSoC
Page 16 / 19
JP2
JP2
CLK0
U1.A8
JP2.5
CLK1
U1.B8
JP2.6
IO0
U1.E6
JP2.7
IO1
U1.B3
JP2.8
IO2
U1.D3
JP2.9
IO3
U1.A2
JP2.10
IO4
U1.E7
JP2.11
IO5
U1.A3
JP2.12
IO6
U1.D5
JP2.13
IO7
U1.C3
JP2.14
IO8
U1.C6
JP2.15
IO9
U1.A4
JP2.16
IO10
U1.E8
JP2.17
IO11
U1.B4
JP2.18
IO12
U1.D6
JP2.19
IO13
U1.A5
JP2.20
IO14
U1.D8
JP2.21
IO15
U1.B5
JP2.22
IO16
U1.C8
JP2.23
IO17
U1.A6
JP2.24
IO18
U1.C9
JP2.25
IO19
U1.B6
JP2.26
IO20
U1.E9
JP2.27
IO21
U1.A7
JP2.28
IO22
U1.D9
JP2.29
IO23
U1.B7
JP2.30
IO24
U1.C11
JP2.31
IO25
U1.A10
JP2.32
IO26
U1.E10
JP2.33
IO27
U1.B10
JP2.34
IO28
U1.D11
JP2.35
IO29
U1.A11
JP2.36
IO30
U1.E11
JP2.37
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Copyright 2011 ORSoC
Page 17 / 19
U1.B11
JP2.38
IO32
U1.D12
JP2.39
IO33
U1.A12
JP2.40
IO34
U1.F8
JP2.41
IO35
U1.B12
JP2.42
IO36
U1.C14
JP2.43
IO37
U1.A13
JP2.44
IO38
U1.D14
JP2.45
IO39
U1.B13
JP2.46
IO40
U1.F14
JP2.47
IO41
U1.A14
JP2.48
IO42
U1.F13
JP2.49
IO43
U1.B14
JP2.50
IO44
U1.F9
JP2.51
IO45
U1.A15
JP2.52
IO46
U1.C15
JP2.53
IO47
U1.B16
JP2.54
IO48
U1.C16
JP2.55
IO49
U1.F15
JP2.56
IO50
U1.D15
JP2.57
IO51
U1.G15
JP2.58
IO52
U1.D16
JP2.59
IO53
U1.G16
JP2.60
CLK2
U1.A9
JP2.61
CLK3
U1.B9
JP2.62
CLK4
U1.E15
JP2.63
CLK5
U1.E16
JP2.64
5.0v
JP2.1
JP2.2
JP2.3
JP2.4
GND
JP2.65
JP2.66
JP2.67
JP2.68
JP2.69
JP2.70
This board is designed by ORSoC AB. The board is available in the OpenCores webshop (http://opencores.org/shop,items)
Copyright 2011 ORSoC
Page 18 / 19
This board is designed by ORSoC AB. The board is available in the OpenCores webshop (http://opencores.org/shop,items)
Copyright 2011 ORSoC
Page 19 / 19