# Transistor Transistor Logic (TTL

)
Popular in discrete components systems.
Not used in modern LSI chips.

Standard TTL IC numbers and functions:
74xdd
0 to 70°C
e.g.

or

54xdd
-55 to 125°C

7400 : Quad 2-i/p NAND basic TTL technology
74LS94: 4bit shift register Low power Schottky TTL technology

Simple TTL Inverter

Simple cct (2 tr., 2 res.)
Small size

5V .7 .2 = 0.0.VCEI(sat) = 0.Simple TTL Inverter VTC ‐ 1 •VIN Lo → QI (BE) forward biased By proper choice of RB → QI sat for VIN=VLO → QO cutoff → VOUT = VOH = VCC •Increasing VIN → VBEO will reach 0.7V (ON) → QO will FA VIL= VBEO(FA) .

0.6V •For VIN > VIH → QIBE reverse VBCI = VCC – IBIRB – VBEO(sat) → QIBC forward QI reverse active! NMH = 5 .6 = 4.8V → QO will sat VOL= VCEO(sat) = 0.2 = 0.4V NML = 0.VCEI(sat) = 0.2V also VIN = VIH = VBEO(sat) .Simple TTL Inverter VTC ‐ 2 •Increasing VIN further → VBEO will reach 0.2 = 0.8 – 0.3V .5 – 0.

9 – 0. .7 = 0.Dynamic Advantage At instant of VI switching Hi to Lo: VEI → VOL = VCEO (sat) ≈ 0.2V but VCI still at VBEO (sat) ≈ 0.1 < 0. Faster switch off.2 + 0.9V Also: VBCI = VBI – VCI = 0.7V QIBC is still in reverse QI FA → current gain Advantage: Large initial current removing charges on Q O base.8 = 0.8V QIBE becomes fwd: VBI = VIN + VBE(FA) = 0.

.Dynamic Advantage Example Calculate the initial QO base current When the i/p to the gate is switched from Hi to Lo.

Simple TTL NAND Gate QI: Multiple Emitter BJT Advantage: Smaller size than 3 BJT’s Case 1: Any i/p Lo QBEI (Fwd) → IBI large → QI (sat) → QO(cutoff) VOUT = VOH Case 2: All i/p Hi QBEI (Rev) → VBI = VCC QBCI (Fwd) → QI (RA) → VBO = VCC .VBCI (Fwd) → QO(sat) VOUT = VOL .

Standard TTL NAND Gate (7400) .

Standard TTL NAND Gate (7400) Active Pull‐Up Drive Splitter Level Shifting Clamping Diodes Totem Pole Totem Pole -Improved speed (Totem pole) -Improved i/p protection (clamping diodes) .

Active Pull-up (QP & RCP): Provides larger current to load gates w/ OH for faster charging of load bases and increased fan-out. Discharge Resistor (RD): Provides a discharge path for the base of QO when switching from sat. Comparing between the simple BJT inverter and the standard TTL gate: (Next slide) 4.7V) between QO and QP to ensure no simultaneous conduction of both. 3. Time constants and initial currents give indication about gate switching speed.TTL Gate Circuit Parts 1. Clamping Diodes (DC): To protect i/p from negative spikes. ( 2nd slide) . 2. Let load be capacitor CEQ. Level Shifting Diode (DL): Provides voltage isolation (0. Faster speed. to cutoff (OL to OH).

.Capacitive Load Comparison Simple BJT Inverter Standard TTL Gate OL → OH >> << Switching speed improved.

to ensure QP & QO will not conduct simultaneously. → QP cannot be conducting → cutoff because of level shifting DL. DL on. Assume QP conducting.Level Shifting Diode For OL. .

Active Elements Status Output Low Output High .

assuming QS cutoff ICI << IBI → QI is sat → QS is truly in cutoff. also QO for: VIN < VBES (FA) – VCEI (sat) → VBP = VCC → VBEP & DL (fwd) VOUT will rise until QP and DL reach edge of conduction •Increasing VIN will raise VBS until VBES is FA .TTL VTC Calculations •VIN Lo → VBEI (ON) ICI ≈ 0.

.TTL VTC Calculations ‐ 2 •Increasing VIN > VIL → VBO (ON) → QO (FA) Slope of VTC changes because current is not going through RD anymore.

TTL VTC Calculations ‐ 3 •Increasing VIN further: QO & QS reach sat .

Standard TTL VTC .

TTL Fan Out ‐ 1 Driving gate Hi → Load gates QI’ (RA) → No load current → Fan-out not a problem .

TTL Fan Out ‐ 2 Driving gate OL → Load gates QI’ (sat) → Hi load current sunk into QO → Fan-out limitation .

TTL Fan Out Derivation ‐ 1 .

TTL Fan Out Derivation – 2   .

TTL Fan Out Example .

TTL Power Dissipation .

Open Collector TTL .

Low Power TTL (74L04) Inverter Increased resistor values. Lower power but also lower speed and lower fan-out. .

Higher speed but also higher power. REP for discharge of QP2 base. . Note: Darlington pair in pull-up section.High Speed TTL (74H04) Inverter Reduced resistor values. further increase in current output.