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INDEX

Exp.
No

Date

Title

01

SYSTEM DESIGN USING PIC 16F877A

02

SYSTEM DESIGN USING MSP430

03

SYSTEM DESIGN USING AT89C51
MICROCONTROLLER

04

SYSTEM DESIGN USING ATMEGA32
MICROCONTROLLER

05

SIMULATION OF QMF USING
SIMULATION PACKAGE

06

DESIGN OF SERIAL IN PARALLEL
OUT SHIFT REGISTER

07

DESIGN OF MOD-4 DOWN COUNTER

08

IMPLEMENTATION OF ADAPTIVE
FILTERS IN DSP PROCESSOR

09

IMPLEMENTATION OF
MULTISTAGE MULTIRATE SYSTEM
IN DSP PROCESSOR

10

DESIGN OF DATA ACQUISITION
AND SIGNAL PROCESSING SYSTEM

11

IMPLEMENTATION OF LED
INTERFACING IN DSP PROCESSOR

12

BUILT-IN SELF TEST AND FAULT
DIAGNOSIS

13

DESIGN & SIMULATON OF
TEMPERATURE SENSOR USING PIC
16F877A

Page
No.

Mark

Signature

W7 PROCEDURE: I. . Creating Project  For Creating C Project. 6.Ex. Type the relevant code. save it. Open MPLAB IDE software 2.c” for C 5. VPUT-01 Universal PIC Embedded Trainer 2. Personal Computer Software: 1. Save the source file as “. VPUT-02 16F877A controller Piggy Back 3. APPARATUS REQUIRED: Hardware: 1. File  New 4. Serial Cable 4. Click project  Project Wizard  Next  Device (16f877A) and click Next  select Active tool suite “CCS C Compiler” and Click Next  Next  Finish 3. Open new source file from. CCS C Compiler tool chain 3. Developing Procedure 1.No: 01 SYSTEM DESIGN USING PIC 16F877A Date: AIM: To design & implement the PIC 16F877A Microcontroller to interfacing of LED using Embedded C program in MPLAB IDE. PIC Boot plus Downloader 4. Operating System Windows Xp. Add the file to the project and build the project. MPLAB IDE workbench for windows platform 2.

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LED interfacing is the stepping stone for microcontroller development. Select hex File : “. Baud rate : 38400 c. 3. The kit supports in system programming (ISP) which is done through USB port.hex” b. one of the best solutions for embedded programming in PIC family. Connect the power card to the development board. a. Make the following settings on the downloader software.II. . Open “PIC Boot plus” GUI for hex file downloading. The program is developed through Micro C compiler. Com Port : User Defined 6. PIC16F/18F Development Kit is proposed to smooth the progress of developing and debugging of various designs encompassing of High speed 8bit Microcontrollers. The kit is designed in such way that all the possible features of the microcontroller will be easily used by the students. suitable for beginners who wish to study basics of embedded microcontroller programming. This is a simple embedded program for PIC 16F877A to interface LEDs. Connect the serial cable between the PC and development board. 4. 5. Switch on the power supply. Microchip’s PIC (PIC16F877A). Click Write button on GUI and Reset the Controller THEORY: The PIC16F Development board is specifically designed to help students to master the required skills in the area of embedded systems. 2. Execution Procedure 1. It is compatible for Windows XP and Windows 7 platforms and comes with internal burning tools.

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} } } . delay_ms(500).PB4 #include<16f877A. delay_ms(500).0x08. while(1) { for(i=0. output_high(PIN_B4). output_low(PIN_B4). output_high(PIN_B4).i++){ output_d(0xff).i.0x10.PROGRAM: //This Program For LED interface //Data Lines . output_low(PIN_B4).0x04.0x20.0x80}. output_d(0x0). delay_ms(500).i++) { output_d(led[i]).0x02.PORTD //Latch Line . void main() { output_b(0xff). rcv=PIN_C7) unsigned int led[]={0x01. output_low(PIN_B4).h> #use delay(clock=20000000) #use rs232(baud=19200.i<5.i<8. output_high(PIN_B4).0x40. xmit=PIN_C6. } for(i=0.

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.OUTPUT: For C Code Alternative LEDs are continuously flashed. RESULT: Thus the PIC 16F877A Microcontroller to interfacing of LED using Embedded C program in MPLAB IDE is designed and implemented.

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Ex.No: 02

SYSTEM DESIGN USING MSP430

Date:

AIM:
To design & implement the MSP430 Microcontroller to interfacing of LED using
Embedded C program
APPARATUS REQUIRED:
Hardware:
1. VPUT-01 Universal PIC Embedded Trainer
2. VPUT-01 MSP430 controller Piggy Back
3. Serial Cable
4. Personal Computer
Software:
1. IAR MSP430
2. MSP FET
3. Operating System Windows Xp,W7
PROCEDURE:
I.

Developing Procedure
i.

For C Project
1. Open IAR MSP430 Software.
2. For creating project “Project  Create New Project  C Main 
then browse the location, gave the name of project and save it.
3. Choose LED-Debug: Options --> General Options:32 Bit
4.

Linker  Output  Others

5. Debugger  Driver  FET Debugger
6. Project  Rebuild All  Led.c

II.

Execution Procedure
1. Connect the power card to the development board.

2. Connect the serial cable between the PC and development board.
3. Switch on the power supply.
4. Open “MSP FET.exe” GUI for hex file downloading.
5. Go to Tools  Setup  select BSL
6. File  Open  Auto  Reset

THEORY:
The Texas Instruments MSP430 family of ultralow power microcontrollers consist of
several devices featuring different sets of peripherals targeted for various applications. The
architecture, combined with five low power modes is optimized to achieve extended battery
life in portable measurement applications. The device features a powerful 16-bit RISC CPU,
16-bit registers, and constant generators that contribute to maximum code efficiency. The
digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode
in less than 6 μs. The MSP430F15x/16x/161x series are microcontroller configurations with
two built-in 16-bit timers, a fast 12-bit A/D converter, dual 12-bit D/A converter, one or two
universal serial synchronous/asynchronous communication interfaces (USART), I 2C, DMA,
and 48 I/O pins. In addition, the MSP430F161x series offers extended RAM addressing for
memory-intensive applications and large C-stack requirements. Typical applications include
sensor systems, industrial control applications, hand-held meters, etc.

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while(1) { P2OUT = 0x55. } } OUTPUT: For C Code Alternative LEDs are continuously flashed.j<600.j++).i<8. P2OUT = 0xAA.i++) for( int j=0.PROGRAM: #include "msp430x16x. P2DIR = 0xff. } void main() { // P2SEL = 0x00. RESULT: Thus the MSP430 Microcontroller to interfacing of LED using Embedded C program is designed and implemented. delay().h" void delay() { for(int i=0. . delay().

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Execution Procedure 1.W7 PROCEDURE: I. Project  Build All. Open the RIDE Software. APPARATUS REQUIRED: Hardware: 1. Step 1: “COM Port: User Defined . Developing Procedure i. 2. Switch on the power supply. VPUT-01 Universal PIC Embedded Trainer 2. Connect the serial cable between the PC and development board. Connect the power card to the development board. 4. RIDE 2. Project  New  Save the File. File  New  C Files  Write Program  Save. II. 2. Personal Computer Software: 1.Ex.No: 03 SYSTEM DESIGN USING AT89C51 Date: MICROCONTROLLER AIM: To design & implement the AT89C51 Microcontroller to interfacing of LED using Embedded C program. Flash Magic 3. Project  Add Node/Source/Applications 5. For C Project 1. VPUT-05 AT89C51 controller Piggy Back 3. 3. 4. Operating System Windows Xp. 3. Serial Cable 4.

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serial port and interrupt system to continue functioning. THEORY: The AT89C51 is a low-power. a full duplex serial port. Step 5: Start  Yes.Hex File. In addition. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset. 7. on-chip oscillator and clock circuitry. timer/counters. 128 bytes of RAM. a five vector two-level interrupt architecture. Step 2: Uncheck “ Erase all Flash + Security” Check “Erase Blocks used by Hex File” 6. Freq: 16 MHz 5. Step 3: Load . the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set and pinout. 8. 32 I/O lines. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip. The AT89C51 provides the following standard features: 4K bytes of Flash. high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). two 16-bit timer/counters. Step 4: Uncheck All.Baud Rate: 9600 Device : 89C51RD2Hxx Interface : None (ISP) Osci. . the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications. The Idle Mode stops the CPU while allowing the RAM.

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void delay(). } . LATCH = 1.i<2500. LATCH = 0. LATCH = 1.i++) for(j=0.j<0xff.h> #include<stdio.h> sbit LATCH =P2^4. P0 = 0Xaa.PROGRAM: #include<reg51. LATCH = 0. void main() { while(1) { P0 = 0X55. int i. delay(). delay().j. } } void delay() { long int i. for(i=0.j++).

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. RESULT: Thus the AT89C51 Microcontroller to interfacing of LED using Embedded C program is designed and implemented.OUTPUT: For C Code alternative LEDs are continuously flashed.

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. then click ok.12 4. Personal Computer Software: 1. click File  New  Source  OK. For creating project File  New  Project  OK  No. Open CodeVision AVR C Compiler.No: 04 Date: AIM: To design & implement the ATMEGA32 Microcontroller to interfacing of LED using Embedded C program. 3. AVR Studio 4 for windows platform 3. Code Vision AVR C Compiler for Windows Platform 2. To create source file. then browse the location. APPARATUS REQUIRED: Hardware: 1. Chip45boot2 GUI V1. Serial Cable 4. Then in the same Configure window select C Compiler tab choose the chip ATMEGA32 and select clock as 16 MHz. 5. 2. 4. gave the name of project and save it. Developing Procedure i. go to Project  Configure  Files  Input Files  click Add and choose the C file to add with project. Operating System Windows Xp. VPUT-07 ATMEGA32 controller Piggy Back 3. VPUT-01 Universal PIC Embedded Trainer 2.SYSTEM DESIGN USING ATMEGA32 MICROCONTROLLER Ex. For C Project 1.W7 PROCEDURE: I. To Configure and select device.

.

II.

Execution Procedure
1. Connect the power card to the development board.
2. Connect the serial cable between the PC and development board.
3. Switch on the power supply.
4. Open “45boot2 GUI V1.12” GUI for hex file downloading.
5. Make the following settings on the downloader software.
a. Select hex File

: “.hex”

b. Baud rate

: 19200

c. Com Port

: User Defined

6. Click Connect to Bootloader, and then wait for status to glow as green.
7. Click Program Flash, wait for some moment.
8. After finishing download click Start application.

THEORY:
The Atmel ® AVR® core combines a rich instruction set with 32 general purpose
working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit
(ALU), allowing two independent registers to be accessed in one single instruction executed in
one clock cycle. The resulting architecture is more code efficient while achieving throughputs
up to ten times faster than conventional CISC microcontrollers. The ATmega32 provides the
following features: 32Kbytes of In-System Programmable Flash Program memory with ReadWhile-Write capabilities, 1024bytes EEPROM, 2Kbyte SRAM, 32 general purpose I/O lines,
32 general purpose working registers, a JTAG interface for Boundary- scan, On-chip
Debugging support and programming, three flexible Timer/Counters with com- pare modes,
Internal and External Interrupts, a serial programmable USART, a byte oriented Two-wire
Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with
programmable gain (TQFP package only), a programmable Watchdog Timer with Internal
Oscillator, an SPI serial port, and six software selectable power saving modes. The Idle mode
stops the CPU while allowing the USART, Two-wire interface, A/D Converter, SRAM,
Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode
saves the register contents but freezes the Oscillator, disabling all other chip functions until the
next External Interrupt or Hardware Reset. In Power-save mode, the Asynchronous Timer
continues to run, allowing the user to maintain a timer base while the rest of the device is
sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except
Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In
Standby mode, the crystal/resonator Oscillator is running while the rest of the device is
sleeping. This allows very fast start-up combined with low-power consumption. In Extended
Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. The
device is manufactured using Atmel’s high density nonvolatile memory technology. The Onchip ISP Flash allows the program memory to be reprogrammed in-system through an SPI
serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot
program running on the AVR core.

PROGRAM:
#include<mega32.h>
#include<delay.h>

#define LED

PORTA

#define LED_LATCH
#define CLR

0

#define SET

1

PORTB.4

void main()
{
DDRA = 0xFF;
DDRB.4 = 1;
while(1)
{
LED ^= 0XFF;
LED_LATCH = CLR;
LED_LATCH = SET;
delay_ms(2000);
}
}

OUTPUT:
For C Code all the LEDs are continuously toggled.

RESULT:
Thus the ATMEGA32 Microcontroller to interfacing of LED using Embedded C
program is designed and implemented.

FREQUENCY RESPONSE OF QMF FILTER .

the output is simulated and verified.Ex.  Write the program in Editor window.  Save the program with MATLAB extension . Editor window is opened.  Then .m  Debug ->save and run. Together these filters are known as the Quadrature Mirror Filter pair.  FILE ->New->M-file.No: 05 SIMULATION OF QMF USING SIMULATION Date: PACKAGE AIM: To simulate QMF design using MATLAB APPARATUS REQUIRED:  Personal computer. a quadrature mirror filter is a filter whose magnitude response is mirror image about of that of another filter.0 PROCEDURE:  Open the MATLAB. A filter will be quadrature mirror filter of The filter responses are symmetric about if .  MATLAB 7. THEORY: In digital signal processing.

IMPULSE RESPONSE .

ylabel('constant'). 2H(z) g1 = -2*h1. subplot(2. xlabel('n').5 0. the power sum of the highpass and low-pass filters is equal to 1. stem(h0). In other words.^(0:N). title('Impulse Response. CODING: QUADRATURE MIRROR FILTER (QMF) DESIGN clc.2). This is known as power complementary property. H(z) % H(-z) % impulse response plot for analysis filter figure.1). % QMF synthesis filter. a quadrature mirror filter pair is often used to implement a filter bank that splits an input signal into two bands. H_0(Z)'). % define filter cut-off frequency m = [1 1 0 0].* h0.2.hanning(N+1)). % number of co-efficients f = [0 0. stem(h1). and the sampling rate is normalized to .552 1]. title('Impulse Response. The resulting high-pass and low-pass signals are often reduced by a factor of 2. xlabel('n').2. % define filter structure h0 = fir2(N. The analysis filters are often related by the following formulae in addition to quadrate mirror property: where is the frequency.m. % clear command & workspace N = 32. subplot(2. H_1(Z)').In audio/voice codecs. giving a critically sampled two-channel representation of the original signal. ylabel('constant'). % -2H(-z) . clear. h1 = (-1).f. % For Standard QMF Bank g0 = 2*h0. % FIR filter design using hanning window.

FILTER ERROR .

% impulse response plot for synthesis filter hold on. -10. text(0.2. . -10. G_1(Z)').815.1. xlabel('n'). [H1. text(0. '|{\itH}_1(\omega)|^2'.'fontsize'. ylabel('Error (dB)'). '|{\itH}_0(\omega)|^2'. title('Impulse Response.error).2. % Plotting radian Vs gain hold on.W] = freqz(g0/2. % Determine Frequency Response plot(W/pi. % error in 'dB' figure. stem(g0).^2 + (abs(H1)). stem(g1). subplot(2. % Determine Frequency Response plot(W/pi.^2. subplot(2.Frequency Response'). ylabel('constant').1. ylabel('constant').512). title('Filter Error').'demi'). G_0(Z)').'demi'). grid xlabel('\omega/\pi (rad)'). title('Impulse Response.'fontsize'.512). plot(W/pi. RESULT: Thus the QMF is simulated using MATLAB and output is verified successfully. % Determine Filter Error sum = (abs(H)).'fontweight'. [H. ylabel('Gain (dB)').'fontweight'.4).20*log10(abs(H1))).13]).15 0.W] = freqz(g1/2.12.grid. % Plotting radian Vs gain xlabel('\omega/\pi (rad)').12.3). xlabel('n'). % QMF filter's frequency response plot figure.20*log10(abs(H))).115. axis([0 1 -0. title('QMF Filter . % find-out filter error error = 10*log10(sum).

OUT PUT .

pin.  Xilinx software. Therefore. PROCEDURE:  Fileopen new projectgive project namenew source  Enter the program  Filesave with . data-out. If four data bits are shifted in by four clock pulses via a single wire at data-in. the data becomes available simultaneously on the four Outputs QA to QD after the fourth clock pulse. a serialin/parallel-out shift register converts data from serial format to parallel format.Ex.No: 06 Date: DESIGN OF SERIAL IN PARALLEL OUT SHIFT REGISTER AIM: To design a sequential circuit serial in parallel out shift register using VHDL. below.vhd extension  Processsynthesischeck syntax  If the program verified successfully then click on simulation  Processbehavioral checkingsimulate wave form  Verify the operation of designed system with obtained test bench wave form THEORY: A serial-in/parallel-out shift register is similar to the serial-in/ serial-out shift register in that it shifts data into internal storage elements and shifts data out at the serial-out. . It is different in that it makes all the internal stages available as outputs. APPRATUS REQUIRED:  Personal Computer.

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Parallel Out Shift Register . Design of Serial In . Perhaps.Parallel Out Shift Register using Behavior Modeling Style: Output Waveform : Serial In .The practical application of the serial-in/parallel-out shift register is to convert data from serial format on a single wire to parallel format on multiple wires. we will illuminate four LEDs (Light Emitting Diodes) with the four outputs (QA QB QC QD).

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s[1] <= s[2]. s[0] <= s[1]. wire din . endmodule RESULT Thus the sequential circuit for serial in parallel out shift register is designed and output verified successfully. else begin s[3] <= din. input clk . wire reset .dout ). always @ (posedge (clk)) begin if (reset) s <= 0. input reset . . wire clk .clk . reg [3:0]s. s[2] <= s[3]. end end assign dout = s.reset . input din . wire [3:0] dout . output [3:0] dout .PROGRAM: VERILOG CODE: module SIPO ( din .

OUTPUT: .

APPRATUS REQUIRED:  Personal Computer. 10.00.3(n-1).  Xilinx software.01.. Counter has two output lines.Ex. PROCEDURE:  Fileopen new projectgive project namenew source  Enter the program  Filesave with .01.1. For example mod-4 counter capable of counting states 0. Hence the states 00.vhd extension  Processsynthesischeck syntax  If the program verified successfully then click on simulation  Processbehavioral checkingsimulate wave form  Verify the operation of designed system with obtained test bench wave form THEORY: Counter has a clock input (CLK) and a RESET input.2.….1.2. and 11 on subsequent clock cycles. 01.10. Thus mod-n counter capable of counting states 0.…. Are counted when the rising edge of clock is detected . which take on values of 00.n-1.11.No: 07 DESIGN OF MOD-4 DOWN COUNTER Date: AIM: To design a sequential circuit mod-4 down counter using VHDL.

` .

-.std_logic_1164. begin SYN_COUNT:process (CLK. CD <= '1' after 20 ns when (U_D = '0' and QINT = 0) else '0' after 20 ns. -.PROGRAM: library IEEE. end if.subtraction of integer end if. elsif CLK='1' and CLK'event then if U_D = '1' then QINT <= QINT + "01" after 20 ns. QOUT <= TO_BITVECTOR(QINT).all.clock and asynchronous inputs begin if pon = '1' then QINT <= "00" after 20 ns. architecture COUNTER of MOD4CTR is signal QINT: STD_LOGIC_VECTOR(1 downto 0). use IEEE. -.std_logic_unsigned. end COUNTER.supports addition/subtraction of vectors entity MOD4CTR is port (U_D. QOUT: out BIT_VECTOR(1 downto 0). CU.carry bits end MOD4CTR .1 after 20 ns. -. end process SYN_COUNT. CD: out BIT). .PON.type conversion: casting CU <= '1' after 20 ns when (U_D = '1' and QINT = 3) else '0' after 20 ns. -. PON) -. RESULT Thus the sequential circuit for mod-3 down counter is designed and output verified successfully.all.supports the data type std_logic use IEEE. --addition of bits else QINT <= QINT .CLK : in BIT.

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Ex. Auto initialization model < No auto initialization>.  STEP-9: Go to project  rebuild all  STEP-10: select “out file”  STEP-11: convert out file to asc file. .cmd> to project  STEP-7: Go to Build option < linker> . heap and stack Size<400>  STEP-8: include library rts 6700.No: 08 IMPLEMENTATION OF ADAPTIVE FILTERS IN DSP Date: PROCESSOR AIM: To implement the adaptive filters in DSP processor TMS320C6713.lib  ok. APPARATUS REQUIRED:  TI .TMS320C6713 kit  Code Composer Studio software  CRO -1  FG -2 PROCEDURE:  STEP-1: Setup configuration of DSP processor in Code composer Studio  STEP-2: Select C67XX and Platfom< simulator> and C6713 device cycle  ADD Save  quit.  STEP-3: open Code composer Studio  STEP-4: GO to new type Project name “adaptive”  select location  finish.  STEP-6:Go to project  add files < CSK6713.  STEP-5: Go to new  select Source file  Type program  save as “ adaptive.c”.

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THEORY: An adaptive filter is a filter that self-adjusts its transfer function according to an optimization algorithm driven by an error signal. typedef short Int16. The adaptive filter uses feedback in the form of an error signal to refine its transfer function to match the changing parameters. Int32 outValue. Int16 outCh2. Because of the complexity of the optimization algorithms. PROGRAM: Adaptive Filter Signal: typedef unsigned int Uint32. adaptive filters have become much more common and are now routinely used in devices such as mobile phones and other communication devices. most adaptive filters are filters. typedefint Int32. camcorders and digital cameras. int main(void) { Int16 outCh1. double *kern. Int16 *noiseSig. A digital signal processor (DSP) is a specialized microprocessor with an architecture optimized for the operational needs of digital signal processing. . Int16 alteredSig. Int16 errorSig. Int16 *origSig. and medical monitoring equipment. typedef unsigned short Uint16. Int16 noiseEst. As the power of digital signal processors has increased.

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Uint32 socRead. noiseSig = (Int16 *)0x00014000. adcOut = *adcValue. origSig = (Int16 *)0x00013000. for(filtCount = 0. *(kern + filtCount) = 0x00000000. Uint16 *dacCh2. adcOut = *adcValue. socValue = (Uint32 *)0x9004000c. //adcOut ^= 0x0800. Uint32 *adcValue. dacCh1 = (Uint32 *)0x90040008. kern = (double *)0x00016000. .Int32 filtCount. filtCount++) { *(noiseSig + filtCount) = 0x00000000. Uint16 adcOut. filtCount< 32. adcValue = (Uint32 *)0x90040008. } while(1) { socRead = *socValue. Uint32 *socValue. adcOut&= 0x0fff. Uint32 *dacCh1. *origSig = adcOut. dacCh2 = (Uint16 *)0x9004000a.

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*dacCh1 = outCh1. *noiseSig = adcOut. outValue = 0.noiseEst. filtCount--) { *(kern + filtCount) = *(kern + filtCount) + (2 * 0. alteredSig = *origSig + *noiseSig. *dacCh2 = outCh2. adcOut ^= 0x0800. filtCount++) outValue += *(noiseSig + filtCount) * *(kern + filtCount). for(filtCount = 0. } outCh1 = alteredSig.0000001 * errorSig) * *(noiseSig + filtCount). } RESULT Thus the adaptive filter is implemented in DSP processor and output is verified on CRO. //*dacCh2 = adcOut. .adcOut&= 0x0fff. filtCount< 32. noiseEst =outValue>> 12. } return 0. outCh2 = errorSig. *(noiseSig + filtCount + 1) = *(noiseSig + filtCount). filtCount>= 0. errorSig = alteredSig . //*dacCh1 = adcOut. for(filtCount = 31.

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lib  ok.  STEP-6:Go to project  add files < CSK6713.No: 09 IMPLEMENTATION OF MULTISTAGE MULTIRATE Date: SYSTEM IN DSP PROCESSOR AIM: To implement the multistage multi rate system in DSP processor TMS320C6713. Auto initialization model < No auto initialization>. .  STEP-9: Go to project  rebuild all  STEP-10: select “out file”  STEP-11: convert out file to asc file.cmd> to project  STEP-7: Go to Build option < linker> . heap and stack Size<400>  STEP-8: include library rts 6700.  STEP-3: open Code composer Studio  STEP-4: GO to new type Project name “multirate”  select location  finish.Ex. APPARATUS REQUIRED:  TI .  STEP-5: Go to new  select Source file  Type program  save as “ multirate.c”.TMS320C6713 kit  Code composer Studio software  CRO -1  FG -2 PROCEDURE:  STEP-1: setup configuration of DSP processor in Code composer Studio  STEP-2: select C67XX and Platform< simulator> and C6713 device cycle  ADD Save  quit.

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L/M. A digital signal processor (DSP) is a specialized microprocessor with an architecture optimized for the operational needs of digital signal processing. N1 = 8. N2 = 37. fs1 = 3000 Hz. fs2 = 1000 Hz. A common use of multirate signal processing is for sampling-rate conversion.h> /* Specifications for the filters used: fs = 8 KHz. sample 2: 28 us. and transform analysis to name but a few. Suppose a digital signal x[n] is sampled at an interval T1. sample 4: 0. communications systems. and we wish to obtain a signal y[n] sampled at an interval T2. which involves both decimation and interpolation. providing the ratio T1/T2 is a rational number i. The two basic operations in a multirate system are decreasing (decimation) and increasing (interpolation) the sampling-rate of a signal. PROGRAM: Multistage Multirate Processing Signal #include "deci3. Sampling-rate conversion can be accomplished by L-fold expansion.1 ms sample 1 = indexSamp 1 sample 2 = indexSamp 2 sample 3 = indexSamp 3 sample 4 = indexSamp 0 This means that without using additional delays the samples are not read at the 8 Khz rate.005.h" #include "deci4. dp1 = dp2 = 0.001. For every 4 samples read from the adc the following approximate times apply without using any additional delays: samples 1 and 3: 16 us. Then the techniques of decimation and interpolation enable this operation. ds1 = ds2 = 0. fp1 = fp2 = 700 Hz.THEORY: Multirate systems have gained popularity since the early 1980s and they are commonly used for audio and video processing.e. or for increased computational efficiency. Multirate systems are sometimes used for sampling-rate conversion. In most applications multirate systems are used to improve the performance. M1 = M2 = L2 = L1 = 2. followed by low-pass filtering and then M-fold decimation.h" #include <stdio. .

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Uint32 valueL1. 2. */ typedef unsigned int Uint32. UcharindexInit. int interpL2(void). Int16 *fInterpL2. Uint32 *outL1.125 ms). typedef unsigned char Uchar. 3 and 4 so that each sample would be read at a rate close to 8 KHz (0. Uchar indexL2. typedef unsigned short Uint16. int deciM1(void). int interpL1(void). Uchar indexL1. Uint32 *inInterpL2. typedef short Int16. typedefint Int32. Uint32 *inDeciM1. int main(void) . Uint32 *inDeciM2. Uint32 *inInterpL1. UcharindexSamp. Int16 *fInterpL1. int deciM2(void).Therefore appropriate delays are added for samples 1. Int32 filtCount. Uint16 adcOut. Int32 outValue. Uint32 *storeL1.

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inDeciM2 = (Uint32 *)0x00012000. fInterpL2 = (Int16 *)0x0000a000. Uint32 countM1.{ Uint32 *socValue. Uint32 *adcValue. filtCount++) *(inTest + filtCount) = filtCount + 0x300. Uint32 socRead. Uint32 countL1. filtCount< 50. Uint32 *dacValue. for(filtCount = 0. outL1 = (Uint32 *)0x00017000. inInterpL1 = (Uint32 *)0x00014000. . inInterpL2 = (Uint32 *)0x00013000. storeL1= (Uint32 *)0x00016000. inTest = (Uint32 *)0x00015000. Int32 tCount. Uint32 countL2. inDeciM1 = (Uint32 *)0x00011000. Uchar *led. led = (Uchar *)0x90040016. adcValue = (Uint32 *)0x90040008. Uint32 countM2. fInterpL1 = (Int16 *)0x0000b000. Uint32 *inTest. socValue = (Uint32 *)0x9004000c. dacValue = (Uint32 *)0x90040008.

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filtCount< 200. for(filtCount = 0. else if (indexSamp == 2) for(tCount = 0. *(inInterpL2 + filtCount) = 0.for(filtCount = 0. indexL1 = 1. tCount++). tCount++). else if ((indexSamp == 1) || (indexSamp == 3)) for(tCount = 0. countL2 = 0. filtCount++) { *(inDeciM1 + filtCount) = 0. indexSamp = 1. countM2 = 0. . while(1) { if(indexSamp == 0) for(tCount = 0. tCount++). filtCount++) *(fInterpL1 + filtCount) = *(fDeciM1 + filtCount) * 2. tCount< 200. adcOut ^= 0x0800. countM1 = 1. *(inDeciM2 + filtCount) = 0. for(filtCount = 0. filtCount++) *(fInterpL2 + filtCount) = *(fDeciM2 + filtCount) * 2. } indexL2 = 1. adcOut = *adcValue. adcOut&= 0x0fff. filtCount< 8. socRead = *socValue. countL1 = 0. *(inInterpL1 + filtCount) = 0. tCount< 700. filtCount< 37. tCount< 900.

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filtCount--) *(inInterpL2 + filtCount + 1) = *(inInterpL2 + filtCount). countM1 = 0. } if((countM1 == 0) && (countM2 == 0)) { while(countL2 < 2) { interpL2(). } if(countM2 == 2) { deciM2(). } } storeL1= (Uint32 *)0x00016000. indexInit = 1. if(countM1 == 2) { deciM1(). if((countM1 == 0) && (countM2 == 0) && (countL2 == 2)) { while(countL1 < 4) { if(countL1 == 0) { valueL1 = *storeL1. countM2 = 0. for(filtCount = 36. countM2++. countL2++.*inDeciM1 = adcOut. . filtCount>= 0.

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*inInterpL1 = valueL1. } } outL1 = (Uint32 *)0x00017000. filtCount--) *(inDeciM1 + filtCount + 1) = *(inDeciM1 + filtCount). filtCount>= 0. countL1 = 0. *dacValue = outValue.*inInterpL1 = valueL1. int deciM1(void) { . } return 0. countL2 = 0. countL1++. countM1++. filtCount>= 0. filtCount--) *(inInterpL1 + filtCount + 1) = *(inInterpL1 + filtCount). } else if(countL1 == 2) { valueL1 = *(storeL1 + 1). else outValue = *(outL1 + indexSamp). for(filtCount = 7. if(indexInit == 0) outValue = 0x800. } interpL1(). indexSamp++. for(filtCount = 7. if(indexSamp == 4) indexSamp = 0.

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return 0. . outValue = 0. *inInterpL2 = outValue. if(indexL2 == 0) filtCount = 0. for(filtCount = 0. filtCount += 2. for(filtCount = 0. } int deciM2(void) { outValue = 0. filtCount>= 0. filtCount++) outValue += *(inDeciM2 + filtCount) * *(fDeciM2 + filtCount). outValue>>= 14. *inDeciM2 = outValue. } outValue>>= 16. filtCount< 8.for(filtCount = 36. return 0. filtCount--) *(inDeciM2 + filtCount + 1) = *(inDeciM2 + filtCount). *storeL1++ = outValue. outValue>>= 14. outValue = 0. return 0. filtCount++) outValue += *(inDeciM1 + filtCount) * *(fDeciM1 + filtCount). filtCount< 37. while(filtCount< 37) { outValue += *(inInterpL2 + filtCount) * *(fInterpL2 + filtCount). } int interpL2(void) { indexL2 ^= 0x01. else filtCount = 1.

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outValue = 0. } RESULT: Thus the multistage multirate system is implemented in DSP processor and output is verified on CRO. if(indexL1 == 0) filtCount = 0. return 0.} int interpL1(void) { indexL1 ^= 0x01. } outValue>>= 16. *outL1++ = outValue. while(filtCount< 8) { outValue += *(inInterpL1 + filtCount) * *(fInterpL1 + filtCount). else filtCount = 1. . filtCount += 2.

SIGNAL PROCESSING DESIGN: .

APPRATUS REQUIRED:  Personal Computer  MATLAB Tool PROCEDURE:  Open MATLAB tool  Click Simulink icon in the MATLAB command window  create a new model by filenewmodel in the Simulink library browser .Ex.No: 10 Date: DESIGN OF DATA ACQUISITION AND SIGNAL PROCESSING SYSTEM AIM: To design a model for data acquisition and signal processing using MATLAB Simulink.

OUTPUT: .

and sensor readings. electrical engineering and applied mathematics that deals with operations on or analysis of analog as well as digitized signals.  Analog-to-digital converters. images. select the sources required and track it in to the new model created and join the blocks  click start simulation icon  double click the scope and output is obtained THEORY: Data acquisition is the process of sampling signals that measure real world physical conditions and converting the resulting samples into digital numeric values that can be manipulated by a computer. telecommunication transmission signals. control system signals. and many others.  Signal conditioning circuitry to convert sensor signals into a form that can be converted to digital values. for example biological measurements such as electrocardiograms. representing time-varying or spatially varying physical quantities. Signal processing is an area of systems engineering. which convert conditioned sensor signals to digital values. . Signals of interest can include sound. The components of data acquisition systems include:  Sensors that convert physical parameters to electrical signals. electromagnetic radiation. Data acquisition systems (abbreviated with the acronym DAS or DAQ) typically convert analog waveforms into digital values for processing.

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RESULT: Thus the model for data acquisition and signal processing using MATLAB Simulink is designed and output was verified. .

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 STEP-3: open Code composer Studio  STEP-4: GO to new type Project name “led”  select location  finish.c”. .  STEP-9: Go to project  rebuild all  STEP-10: select “out file”  STEP-11: convert out file to asc file.  STEP-6:Go to project  add files < CSK6713.cmd> to project  STEP-7: Go to Build option < linker> .  STEP-5: Go to new  select Source file  Type program  save as “led.lib  ok.No: 11 IMPLEMENTATION OF LED INTERFACING IN DSP PROCESSOR Date: AIM: To implement the LED interfacing in DSP processor TMS320C6713.TMS320C6713 kit  Code composer Studio software PROCEDURE:  STEP-1: setup configuration of DSP processor in Code composer Studio  STEP-2: select C67XX and Platform< simulator> and C6713 device cycle  ADD Save  quit. heap and stack Size<400>  STEP-8: include library rts 6700.Ex. APPARATUS REQUIRED:  TI . Auto initialization model < No auto initialization>.

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//Some delay data=0xf0.i<0x5ff.i++) //Some delay for(j=0. while(1) //infinite loop start heare { data=0x0f. //Data send to LED for(i=0.j<0xff.i. //Variable declaration //int *port0A. } } RESULT: Thus the LED Interfacing using DSP Kit is designed and implemented. //Led address decleration void main() { int data. //data to be LED port0A=data. //Data send to LED for(i=0.i<0x5ff. //port0A=(int *)0xa000.PROGRAM: //LED OUT PROGRAM //=============== ioport int port0A.i++) for(j=0. .j.j++). //data to be LED port0A=data.j++).j<0xff.

Tool on Built-in Self -Test and Fault Diagnosis: Step 1: .

6. Unlike other similar systems. THEORY: BUILT-IN SELF TEST: Linear Feedback Shift Registers (LFSR) and other Pseudo-Random Pattern Generators (PRPG) have become one of the central elements used in test and self test of contemporary complex electronic systems like processors. Set the Register Length as 60. and research environment that supports both analytic and synthetic way of learning. The BISTA represents an integrated simulation.No: 12 BUILT-IN SELF TEST AND FAULT DIAGNOSIS Date: AIM: To develop & test the built-in self-test and fault diagnosis. controllers. training. this tool facilitates study of various test optimization problems. APPARATUS REQUIRED: 1. Open the Software BISTAD 2. Windows XP PROCEDURE: 1. Verify the Output in Charts & Diagnozer. We have developed a training and research tool BIST Analyzer (BISTA) for learning basic and advanced issues related to PRPG-based test pattern generation. Set the Clock cycles to run as 10000 5. To Generate & Load the TST and AGM files. and high-performance integrated circuits. 4. The multi-platform JAVA runtime environment allows for easy access and usage of the tool both in a classroom and at home. BISTAD 2. The main didactic aim of the tool is presenting complicated concepts in a comprehensive graphical and analytical way. allows fault coverage analysis for different circuits and with different LFSR parameters.Ex. 3. Set the Feedbacks and Seed as Random. .

Step 2: Step 3: .

The software provides easy action and reaction (click and watch). SHORT THEORETICAL BASICS Test Generation Test generation (TG) is a complex problem with many interacting aspects e. fault diagnosis and fault location in digital circuits.vector insertion panel. Vector insertion panel has two sub-panels . and investigate the effect of real physical defects in electronic circuits.FAULT DIAGNOSIS The tool set DIAGNOZER represents a multifunctional remote e-learning environment for teaching research by learning and investigating the problems of fault diagnosis in electronic systems. It is a collection of software tools which allow to simulate a system under diagnosis. It offers a set of tools for understanding the principles of test generation. A big reservoir of simple combinational circuits is given to train on the screen in interactive mode the main important techniques and algorithms. fault model based and fault model free approaches to fault diagnosis as well as cause-effect and effect-cause techniques of fault location are supported in the presented environment. fault tables and waveforms. fault simulation. Both. The work window of this program consists of three parts .one for manually inserting vectors and another one for automated pseudo random test generation. the possibility of distance learning. and view panel for test vectors.g. Also different embedded BIST and self diagnosis architectures are emulated to evaluate the efficiency of diagnosis. The boxes at the lines on schematics are clickable for inserting proper signals directly on the internal lines of the circuits to imitate deterministic test generation procedures. the cost of TG . emulate a pool of different methods and algorithms of fault location and analyze the efficiency of different embedded self-diagnosing architectures. Basics of Test and Diagnostics INTRODUCTION This applet supports action-based learning via Internet the basics of Digital Test. and learning by doing. view panel for design schematics.

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In the case of the fault s-a-1 the value 0 on that line will change to 1. The complexity of TG methods and algorithms depends on the structure of the gate-level circuits. and others. we have to assign 0 either to the line 3 or to the line 8 or to both lines. random TG. Fault Diagnosis A unit under test (UUT) fails when its observed behaviour is different from its expected . There are different methods used in test generation: deterministic methods (fault-oriented TG. combined deterministic/random TG.  To to justify the assigned line values justify the value 0 on the line 9. In the case of the fault s-a-1 on the line 9 the value 0 on the line 11 will change to 1.(complexity of the method. test length) and the quality of generated tests (fault coverage). In general three fundamental steps are used in generating a test for a fault:  to activate the fault To activate a fault stuck-at-1 (s-a-1) on the line 9 of the circuit we have to assign to the line 9 the value 0.  to propagate the resulting error to a primary output (PO) To propagate the error signal of a fault stuck-at-1 (s-a-1) on the line 9 through the OR-gate 11 we have to assign value 0 to the line 10. fault independent TG).

Step 4: .

To locate faults. The database constructed in this step is called a fault table or a fault dictionary. Sequential diagnosis procedure can be graphically represented as diagnostic tree. carried out as a top-down process (with a system operating in the field) or bottom-up process (during the fabrication of the system). Fault Table Example Sequential Fault Diagnosis Methods In sequential fault diagnosis the process of fault location is carried out step by step. where each step depends on the result of the diagnostic experiment at the previous step.behaviour. Diagnosis consists of locating the physical fault(s) in a structural model of the UUT. It uses fault simulation to determine the possible responses to a given test in the presence of faults. Sequential experiments can be carried out either by observing only output responses of the UUT or by pinpointing by a special probe also internal control points of the UUT (guided probing). Such a test experiment is called adaptive testing. Combinational Fault Diagnosis Methods This approach does most of the work before the testing experiment. . The result of the test experiment represents a combination of effects of the fault to each test pattern. one tries to match the actual results of test experiments with one of the pre-computed expected results stored in the database. The diagnosis process is often hierarchical.

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The shortest test contains two patterns the longest four patterns.Example of Fault Location by Edge-Pin Testing The diagnostic tree in the Figure below corresponds to the fault table example. Different faults need for identifying test sequences with different lengths. We can see that most of the faults are uniquely identified. The principle of guided-probe testing is to backtrace an error from the primary output where it has been observed during edge-pin testing to its physical location in the UUT. because T2does not distinguish among these faults. The use of adaptive testing may substantially decrease the average number of tests required to locate a fault. In our example. adaptive testing determines the next vector to be applied based on the results obtained by the preceding vectors. if T1 fails. . At this point applying T2 would be wasteful. Not all test patterns used in the fault table are needed. The next probing depends on the result of the previous step. the possible faults are {F2.F4 remain indistinguishable. In each step an internal signal is probed and compared to the expected value. Probing is carried out step-by-step. Result: Thus the built-in self-test and fault diagnosis is verified successfully. Guided-Probe Testing Guided-probe testing extends edge-pin testing process by monitoring internal signals in the UUT via a probe which is moved (usually by an operator) following the guidance provided by the test equipment. Rather than applying the entire test sequence in a fixed order as in combinational fault diagnosis.F3}. two faults F1.

CIRCUIT DESIGN & OUTPUT: .

x extension file and right click on that and compile it  Click build all and make project icons  Go to Configure Select device  16f877ok  Go to Configureconfiguration bits(disableenable)ok  Open PIC ISP check whether com1 port is selected or not select . APPARATUS REQUIRED:  MPLAB IDE  PROTEUS VSM PROCEDURE: I. Developing Procedure:  Open MPLAB IDEGo to project Wizard next select ICchoose ccs compiler create a folderfinish  Newfiletype the programsave the document with . II.Ex. Simulation Procedure:  Open Proteus ISIS 7 Professional  Library  Pick Device/Symbols…  Connect the Components as per Circuit Diagram.Hex File). .  Double click the Microcontroller  Browse the Program file (.c extension  Right click on source fileadd filesselect .hex fileclick download.  Debug  Execute  Verify the Simulated Output in LCD Display.No: 13 DESIGN & SIMULATON OF TEMPERATURE Date: SENSOR USING PIC 16F877A AIM: To design & simulation of Temperature Sensor interfacing using PIC16F877A.

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UBYTE COUNT=0. b=temp1/10. lcd_data(com+0. ADCON1=0X82. TRISD=0X00. c=b%10. lcd_data(com+2. } void main() { UBYTE b.d.b.h" #define heart_beat RC0 UWORD temp1.'C'). static void hex_ascii(UWORD com) { UBYTE a.c.e. d=b/10. ADCON0=0X00.d. .f. temp1=ADRESH<<8. TRISE=0X00. temp1=(temp1+ADRESL)/2.c+0x30).h> #include "LCD. lcd_data(com+1.a+0x30). i=0.PROGRAM: Program #include<pic. a=temp1%10.c. PORTE=0X00.

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ADON=1. lcd_init(). // SETTING PRESCALAR VALUE AS 8 T1CKPS0=1.i<9. lcd_condis(0x80.3). // TIMER MODE T1CKPS1=1. lcd_condis(0xc8. TMR1CS=0. hex_ascii(0xc5)."Health Indicator". CHS0=0. lcd_condis(0xc0."HB:"..16).5). TMR1H=0x0B. ADCON0=(ADCON0|0X04). TMR1L=0xDB.) { CHS2=0. while(TMR1IF==0) .i++) { TMR1ON=1. TRISC=0Xff.//ADC on delay(200).PORTD=0X00."Temp:". PORTC=0X00.//channel selection CHS1=0. for(. for(i=0.//initialize ADC conversion delay(200).

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. } COUNT=COUNT*6. b=COUNT%10.//UNIT DIGIT c=COUNT/10. } } RESULT: Thus the interfacing Temperature Sensor with PIC using Proteus was designed & simulated. lcd_data(0xcb+1. d=c%10."bpm".3). // tens digit // hundred digit lcd_data(0xcb+0. } } if(TMR1IF)TMR1IF=0.d+0x30).TMR1ON=0. } else { COUNT.b+0x30). COUNT=0.{ if(heart_beat==1) { COUNT=COUNT+1. e=c/10. lcd_condis(0xcd.