## Are you sure?

This action might not be possible to undo. Are you sure you want to continue?

3837-3841

© Research India Publications;

http://www.ripublication.com/ijaer.htm

**Ac Grid Connected Photovoltaic Energy System Using 21-Level Multilevel
**

Cascade H-Bridge Inverter

M.Venkateshkumar1,

Asst Professor (SG), Dept of EnEE,

Saveetha School of Engineering

venkatmme@gmail.com

Abstract-In this paper the operation of multilevel cascade HBridge inverter topology has been studied.. The mathematical

model of multilevel inverter has been evolved. The inverter

operation has been analyzed using this model and the resultant

waveform thoroughly studied.. Based on this analysis a new

hybrid multilevel cascade H- bridge inverter model has been

proposed with reduced number of switches. The proposed

model has been developed using Matlab /Simulink software.

An analysis of the proposed inverter model from its resultant

waveforms has established the better performance of the

inverter. This inverter model is being recommended for

studies of systems with grid connected renewable energy

sources.

Key words: 21 level Cascade inverter, renewable energy,

Matlab Simulink.

Introduction

Recently, the need for increasing the power level in industry

has sustained the continuous development of multilevel

inverters because of their capability of handling voltage rating.

A Cascade multilevel inverter

Numerous industrial applications have begun to require higher

power apparatus in recent years. Some medium voltage motor

drives and utility applications require medium voltage and

megawatt power level. For a medium voltage grid, it is

troublesome to connect only one power semiconductor switch

directly. As a result, a multilevel power converter structure has

been introduced as an alternative in high power and medium

voltage situations. A multilevel converter not only achieves

high power ratings, but also enables the use of renewable

energy sources. Renewable energy sources such as

photovoltaic, wind and fuel cells can be easily interfaced to a

multilevel converter system for a high power application.

The concept of multilevel converters has been introduced

since 1975. The term multilevel began with the three-level

converter. Subsequently, several multilevel converter

topologies have been developed.

However, the elementary concept of a multilevel converter to

achieve higher power is to use a series of power

semiconductor switches with several lower voltage dc sources

to perform the power conversion by synthesizing a staircase

voltage waveform. Capacitors, batteries, and renewable energy

voltage sources can be used as the multiple dc voltage sources.

The commutation of the power switches aggregate these

multiple dc sources in order to achieve high voltage at the

output; however, the rated voltage of the power semiconductor

R.Indhumathi2

Asst Professor, Dept of EEE

Jawahar Engineering College

indhu.success@gmail.com

switches depends only upon the rating of the dc voltage

sources to which they are connected.

A multilevel converter has several advantages over a

conventional two-level converter that uses high switching

frequency pulse width modulation (PWM). The attractive

features of a multilevel converter can be briefly summarized

as follows.

● Staircase waveform quality: Multilevel converters can not

only generate the output voltages with very low distortion, but

also reduce the dv/dt stresses; thereby reducing

electromagnetic compatibility (EMC) problems.

● Common-mode (CM) voltage: Multilevel converters

produce smaller CM voltage; therefore, the stress in the

bearings of a motor connected to a multilevel motor drive can

be reduced. Furthermore, CM voltage can be eliminated by

using advanced modulation strategies such as that proposed

in[8] .

● Input current: Multilevel converters can draw input current

with low distortion.

● Switching frequency: Multilevel converters can operate at

both fundamental switching frequency and high switching

frequency PWM. Unfortunately, multilevel converters do have

some disadvantages. One particular disadvantage is the greater

number of power semiconductor switches needed. Although

lower voltage rated switches can be utilized in a multilevel

converter, each switch requires a related gate drive circuit.

This may cause the overall system to be more expensive and

complex.

Multilevel Power Converter Structures 2

5

**A single-phase structure of an m-level cascaded inverter is
**

illustrated in Figure.1. Each separate dc source (SDCS) is

connected to a single-phase full-bridge, or H-bridge, inverter.

Each inverter level can generate three different voltage

outputs, +Vdc, 0, and –Vdc by connecting the dc source to the

ac output by different combinations of the four switches, S1,

S2, S3, and S4. To obtain +Vdc, switches S1 and S4 are turned

on, whereas –Vdc can be obtained by turning on switches S2

and S3. By turning on S1 and S2 or S3 and S4, the output voltage

is 0. The ac outputs of each of the different full-bridge inverter

levels are connected in series such that the synthesized voltage

waveform is the sum of the inverter outputs. The number of

output phase voltage levels m in a cascade inverter is defined

by m = 2s+1, where s is the number of separate dc sources. An

example phase voltage waveform for an 11-level cascaded Hbridge inverter with 5 SDCSs and 5 full bridges is shown in

Figure 2. The phase voltage van = va1 + va2 + va3 + va4 + va5. For

5.ripublication. . The previous model of cascade multilevel inverter has been analyzed and its performance evaluated. Single –Phase structure of a multilevel cascade Hbridge inverter Figure 2: Output Phase Voltage waveform of a cascade inverter From figure 2 the magnitude of the Fourier coefficients when normalized with respect to Vdc are given by H ( n) 4 n [cos( n 1 ) cos( n 2 ) . http://www. and for battery-based applications. Three-phase cascaded inverters can be connected in wye..4 (2015) © Research India Publications.... 7…….htm a stepped waveform such as the one depicted in Figure 2 with s steps.... ISSN 0973-4562 Vol... or in delta.( 2) Where n=1. V(t) 4Vdc sin(nt) .6. 4. and 13th... θs. .. ... A new cascade multilevel H-bridge inverter has been proposed in this paper. This will enable the manufacturing process to be done more quickly and cheaply. θ1. these angles are chosen so that predominant lower frequency harmonics.. Peng [7] has demonstrated a prototype multilevel cascaded static VAR generator connected in parallel with the electrical system that could supply or draw reactive current from an electrical system..(1) n [cos(n ) cos(n ) .... cos(n )] 1 2 s Multilevel cascaded inverters have been proposed for such applications as static VAR generation.. .....com/ijaer. 11th.. This inverter has been developed by using Matlab simulink soft as shown in figure 3b. The proposed topology results in reduction of installation area and cost maintaining the magnitude of dc voltage source... This structure consists of series connected sub multilevel inverter Figure 1. Advantages: The number of possible output voltage levels is more than twice the number of dc sources (m = 2s + 1)...International Journal of Applied Engineering Research. Matlab Simulation Of Proposed Inverter Model 2......... θ2.. can be chosen such that the total harmonic voltage distortion is minimum. 5.. Generally. 5th... 3838 . 10 No. the Fourier Transform is as in equation 1....... 7th.. The series of H-bridges makes for modularized layout and packaging.... harmonics are eliminated.... an interface with renewable energy sources. cos( n s )]. .... The conducting angles.. 3.

International Journal of Applied Engineering Research. Figure 4: Proposed model 7level inverter output voltage waveform The output voltage of 7 level stepped waveform is illustrated in figure 4. http://www. it will result in reduction of harmonics and pure sinusoidal wave from. ISSN 0973-4562 Vol.htm Figure 6: 21 level cascade multilevel inverter output voltage waveform Figure 3: a) 7 level Cascade Multilevel H-bridge inverter b) New proposed model with ideal diode Figure 7: The gate pulses for first 1 to 5 MOSFET switches. Simulation model of 21 levels Cascade Multilevel Inverter Figure 8 : The gate pulses 6 to 10 MOSFET switches Figure 5: 21 level cascade inverter H-bridge model 3839 .ripublication.4 (2015) © Research India Publications.com/ijaer. Newly developed 21 level inverter model using Matlab is shown in figure 5. 10 No. Whenever the number of levels is increased.

an equivalent circuit model is represented with a switch and a gate-source. voltage and current ratings of the switches in a multilevel inverter play important roles on the cost and realization of the inverter. FSW = Switching Frequency. Each switch in the suggested topology is composed of one MOSFET and one anti-parallel diode. Standing voltage For low and medium frequencies. however. Switching losses: PSW = (EON + EOFF) * FSW -------------------------------. PMOSFET = PSW + PCOND -------------------------(3) Conduction losses: The calculation of conduction losses PCOND = I2 OUT * RON * VOUT / VIN ---------------(4) Where RON is the maximum operating MOSFET junction temperature(T).9. Opto-isolators can work in a wide range of input signal pulse width. the currents of all switches are equal with the rated current of the load. Figure 10: gate driver circuit for the switch A comparison of the power component requirements among the conventional and suggested multilevel inverters for the 3840 . a MOSFET can operate as an ideal switch[1][3]. Symbols Cx and Lx represent an external parasitic capacitance and a leakage inductance of the transformer. Thus. 7 and fig 8. In the proposed model the number of switches are reduced and hence the overall switching losses.htm C Comparison of the suggested conventional cascaded multilevel inverter A Switching loss: structure with Table 1 Comparison of power component requirements among conventional cascaded multilevel inverters. B Simulation Result analysis Cost Gate driver Area Control Conventional Cascade Mlevel inverter Proposed Model Vdc(Nstep -1) Vdc(Nstep -1) 24 14 2Vdc (Nstep 1) High More More Complex 2Vdc (Nstep -1) Low Low Less Easy The main purpose of this paper is reduction of the components of the cascaded multilevel inverters. in which the dashed line represent an intrinsic MOSFET. Triggering pulses of MOFSET switches are shown in fig 7 and fig 8. They all have voltage dependencies. Cds are a gate-source. A power MOSFET has a rather large on-resistance. ISSN 0973-4562 Vol. Fig. Therefore. Output voltage waveform is shown in fig 6. each switch requires one gate pulse as shown in fig. not the case for the voltage. Here Ron is an on-resistance.4 (2015) © Research India Publications. Each switch in the inverter requires an isolated driver circuit. 10 shows the isolator and driver circuit of each switch. where Vswitch j represents the peak inverse voltage of the jth switch PIV Vswitch j j 1 The existing cascade multilevel inverter required more number of switches for getting the desired output voltage waveform. EON = Trun on switching losses in power MOSFET. Description Maximum output voltage Number of switches (MOSFET) Figure 9 : Circuit model of the power MOSFET switch . In other words. a Schmitt trigger and a buffer. This is. a gate-drain and a drain-source capacitance. Cgd. Therefore. This circuit consists of an optoisolator. but a separate isolated power supply is required for each switching device. the MOSFET used in this circuit can be represented as shown in Fig.com/ijaer. Also. 21 level inverter. The peak inverse voltage (PIV) of all switches is represented by the summation Vswitch j. 10 No. The isolation can be provided using either pulse transformers or opto-isolators. http://www. In the proposed topology. gate-drain and drain-source capacitances.ripublication. The power loss in any MOSFET is the combination of the switching losses and MOSFET’s conduction losses. EOFF = Trun off switching losses in power MOSFET. Symbols Cgs.International Journal of Applied Engineering Research. This also leads to reduction in the installation area and the number of the gate driver circuits. Another important problem in inverters is the ratings of switches. the cost of the suggested topology is less than the conventional topology for realizing Nstep voltages for output. respectively.(5) Where PSW = Switching Power Losses.

. Z. Blaabjerg. Reference Papers: [1]. Henry Shu-Hung Chung on A 31-level cascade inverter for power applications on Industrial Electronics. 1416-1423. 1998. VanCoevering.ripublication. Ebrahim Babaei *. T. 1983.66% less for realizing Nstep voltages for output as compared to conventional inverter.. J. Y. Soumia Mouna Lagoun. [3]. Rec.3 [4]. 11301138. C. pp: 613 – 617 [5]. A. S. Farid Khoucha. I. Bai. 3841 . “A New Medium Voltage PWM Inverter Topology for Adjustable Speed Drives. 1996.C “A novel model for MOSFET switching loss calculation”on Power Electronics and Motion Control Conference. “Hybrid Cascaded H-Bridge Multilevel-Inverter Induction-MotorDrive Direct Torque Control for Automotive Applications” on IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS vol 57 . R. IEEE-IAS Annu. Teodorescu. Enjeti. Peng. J. vol.htm same number of the output voltage steps is given in Table 1. F. Lee. 10 No. Woom.Yoshida “Characteristics and improvement of power MOSFET switching loss” Telecommunications Energy Conference. J. The number of switches in the topology recommended in this paper is 41. Feel-Soon Kang. pp.International Journal of Applied Engineering Research.com/ijaer. M. E.” IEEE Transactions on Industry Applications.Okabe. Man Hyung Lee. S. Lai. ISSN 0973-4562 Vol. Meeting. B.. IEEE Transactions on Vol: 49 2002. Ron Hui. no. pp: 1600 – 1606. Lee.. 32. 508 – 513. Y. CheulU Kim “ An Efficient Multilevel-Synthesis Approach and its Application to a 27 –level inverter” on Industrial Electronics.4 (2015) © Research India Publications. The 4th International Vol:3 2004 . S. [8].. F. W. The resultant waveform obtained has been studied and compared with the existing inverter model to prove the effectiveness of the proposed model. Meng. INTELEC '83. pp: 1669 . Issue: 6 2005.” in Conf.K. 2004. http://www. Oct.2010 pp :892-899 [7]. and F.Katsueda. Louis. U. pp. Sung-Jun Park. St. MO. Fifth International 1983. The proposed inverter model is recommended for grid connected renewable energy sources. “A Multilevel Voltage-Source Inverter with Separate DC Sources for Static Var Generation. Seyed Hossein Hosseini “New cascaded multilevel inverter topology with minimum number of switches” on Energy Conversion and Management vol :50 2009 pp2761–2767 [6]. P. O. Sulistijo. pp.1672 Vol.Q. Conclusions In this paper a new 21 level cascade multilevel inverter model developed using Matlab Simulink has been presented. Cengelci. Sept. Huang. [2]. IPEMC 2004. 5.Y. IEEE Transactions on Vol: 52. McKeever.

- 9. High and Medium Voltage.fulluploaded byTJPRC Publications
- Final Documentuploaded bySai Krishna
- Performance Analysis of Asymmetrical Cascaded H-Bridge Nine Level Inverter with Photovoltaic Arraysuploaded byijsret
- International Journal of Engineering Research and Developmentuploaded byIJERD
- Brushless Dc Driver With Brushed Motoruploaded bycyberdog001
- SI9978DWuploaded bymeroka2000
- 002072099102800410uploaded byEnzo Karol Velásquez
- Power Electronics Question Paperuploaded byvagoliyo
- 16-MPS-100uploaded bybehzad
- AMP Si3540 Specsheetuploaded byElectromate
- Monomobile Project Fileuploaded bypbargotra786
- A Novel Single-phase Cascaded H-bridge Inverter With New Cell Configuration and Reduced Power Electronics Components With Low Thduploaded byInternational Journal of Research in Engineering and Technology
- Fronius USA Symo Final Landscape 396273 Snapshotuploaded byvitinrj
- HEM (101)uploaded byRavi Kumar
- Patient Helper Without Viduploaded byparth_singh_6
- AN200907AdvantagesofNPCuploaded byVijai Mogan
- 16213uploaded bybazoka fransiskus
- Robot Project Report Roboticsuploaded bydcrust_amit
- In This Article I Will Offer Driver Circuit for 12 Vuploaded byPriya Jakoon
- Danfoss_VLT5000_Data_Sheet.pdfuploaded byKukuh Widodo
- Effect of short circuited DC link capacitor of an AC–DC–AC inverter on the performance of induction motoruploaded byPrabhupada Satapathy
- Speed Control of an Induction Motor Using Raspberry PIuploaded byJosé De Jesús PC
- Project Reportuploaded byHariprasad KP
- ACM2 TAU Datasheet Enuploaded byvishiwizard
- an9404uploaded byNatalia González Rogget
- Load Performance of PIC Based.pdfuploaded byMuller
- E9Battery Chrgrs & Inverters ETTMuploaded bysulemankhalid
- Instruction SMA Tripoweruploaded byMirea Aurel
- 5-Level Parallel Current Source Inverter for Highuploaded byAnonymous 1aqlkZ
- Thiuploaded byAhmed Janad

- HVDC Question Bankuploaded byBals Bala
- Calculationuploaded byBals Bala
- Regression Anlysisuploaded byBals Bala
- EE2518-POWER ELECTRONICS LAB MANUAL.rtfuploaded byBals Bala
- Introduction power electronoicsuploaded byBals Bala
- HVDC Question Bank.pdfuploaded byBals Bala
- List of Experimentsuploaded byBals Bala
- Introduction of power electronicsuploaded byBals Bala
- Regression Anlysisuploaded byBals Bala
- diac.pptuploaded byBals Bala
- Calculationuploaded byBals Bala
- 10.1.1.8.5044uploaded byBals Bala
- Calculationuploaded byBals Bala
- Calculationuploaded byBals Bala
- Calculationuploaded byBals Bala
- Calculationuploaded byBals Bala
- Calculationuploaded byBals Bala
- Calculationuploaded byBals Bala
- Calculationuploaded byBals Bala
- Calculationuploaded byBals Bala

Close Dialog## Are you sure?

This action might not be possible to undo. Are you sure you want to continue?

Loading