# Overview

Switching-network logic blocks

Last lecture

Timing diagrams
Multilevel logic

 Multilevel NAND/NOR conversion
 AOI and OAI gates

Hazards

"Switching-network" logic blocks

Routes a single input to one of many outputs
Also called a decoder
multiplexer

 Multiplexers/selectors
 Demultiplexers/decoders

Routes one of many inputs to a single output
Also called a selector

Demultiplexer

Today

Multiplexer

demultiplexer

Programmable logic devices (PLDs)
 Regular structures for 2-level logic
control

control
CSE370, Lecture 10

1

Rationale: Sharing complex logic functions

CSE370, Lecture 10

Basic concept

Sa

A1

B0

B1

MUX

MUX

A

B

Sb

multiple inputs

DEMUX
Z0

CSE370, Lecture 10

2n data inputs; n control inputs ("selects"); 1 output
Connects one of 2n inputs to the output
“Selects” decide which input connects to output
Two alternative truth-tables: Functional and Logical

Example: A 2:1 Mux

Functional truth table

Z = SIn1 + S'Ino

Sum
Ss

2

Multiplexers

Share an adder: Select inputs; route sum
A0

We construct these
devices from:
(1) logic gates
(2) networks of transistor switches

multiple output destinations

I0
S
I1

Z1
3

CSE370, Lecture 10

S
0
1
Z

Z
In0
In1

Logical truth table
In1
0
0
0
0
1
1
1
1

In0
0
0
1
1
0
0
1
1

S
0
1
0
1
0
1
0
1

Z
0
0
1
0
0
1
1
1
4

Lecture 10 F 1 0 1 0 0 0 1 1 C' C' 0 1 1 0 1 0 0 0 1 1 0 1 2 3 4 8:1 MUX 5 6 7 S2 S1 S0 A B C F C' C' 0 1 0 1 2 4:1 MUX 3 S1 S0 A F B 8 .Logic-gate implementation of multiplexers 2:1 mux Multiplexers (con't) 4:1 mux I0 I0 Z S  2:1 mux: Z = S'In0 + SIn1  4:1 mux: Z = S0'S1'In0 + S0'S1In1 + S0S1'In2 + S0S1In3  8:1 mux: Z = S0'S1'S2'In0 + S0'S1S2In1 + ... Lecture 10 6 A 2n:1 mux can implement any function of n variables  I0 I1 I2 I3 Z Multiplexers as general-purpose logic Can form large multiplexers from smaller ones  8:1 mux S0 S1 S2 S1 Cascading multiplexers  I0 I1 I2 I3 I4 I5 I6 I7 A lookup table A 2n – 1:1 mux also can implement any function of n variables  Example: F(A. I1 I1 Z I2 I0 S I0 I1 2:1 mux I3 Z Z S0 I0 I1 I2 I3 4:1 mux Z S0 S1 I1 S0 CSE370. Lecture 10 5 CSE370.B.C) = m0 + m2 + m6 + m7 = A'B'C' + A'BC' + ABC' + ABC = A'B'(C') + A'B(C') + AB(0) + AB(1) 4:1 mux Z A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 S1 S2 7 CSE370. Lecture 10  Many implementation options  8:1 mux I4 I5 I6 I7 8:1 mux 4:1 mux 2:1 mux 4:1 mux S 0 S1 S2 Z I0 I1 2:1 mux I2 I3 2:1 mux I4 I5 2:1 mux I6 I7 2:1 mux S0 CSE370.

Lecture 10 B A'B'C' A'B'C A'BC' A'BC AB'C' AB'C ABC' ABC demultiplexer “decodes” appropriate minterms from the control signals C 12 . 1.Multiplexers as general-purpose logic Demultiplexers Implementing a 2n:1 mux as a function of n–1 variables      AB CD 00 C  (n-1) mux control variables S0 – Sn–1 One data variable Sn Four possible values for each data input: 0.B. the input is called an “enable” (G) 1:2 Decoder: Out0 = G • S' Out1 = G • S 0 1 2 F 8:1 3 MUX 4 5 6 7 S2 S1 S0 A Basic concept S1 S0 11 CSE370. Sn' Example: F(A. 2n outputs Single input connects to one of 2n outputs “Selects” decide which output is connected to the input When used as a decoder. Lecture 10  2:4 demux G 2:4 Decoder: Out0 = G • S1' • S0' Out1 = G • S1' • S0 Out2 = G • S1 • S0' Out3 = G • S1 • S0 C F = A’B’C’+A’CD+B’CD+AC’D’+BCD’ 1:2 demux Single data input.D) implemented using an 8:1 mux A 01 11 10 00 1 0 1 1 01 1 0 0 0 11 1 1 0 1 10 0 1 1 0 B CSE370.B. Lecture 10 D 1 D 0 1 D' D D' D' Choose A.C as control variables Choose D as a data variable F=A’B’C’(1)+A’B’C(D)+A’BC’(0)+A’BC(1) +AB’C’(D’)+AB’C(D)+ABC’(D’)+ABC(D’)     B 9 Logic-gate implementation of demultiplexers 10 A n:2n demux can implement any function of n variables  Out0  Use variables as select inputs Tie enable input to logic 1 Sum the appropriate minterms (extra OR gate) Out1 Out0 S Out2 Out1 1 Out3 0 1 2 3:8 3 Demux 4 5 6 7 S2 S1 S0 A CSE370. Lecture 10 3:8 Decoder: = G • S2' • S1' • S0' = G • S2' • S1' • S0 = G • S2' • S1 • S0' = G • S2' • S1 • S0 = G • S2 • S1' • S0' = G • S2 • S1' • S0 = G • S2 • S1 • S0' = G • S2 • S1 • S0 Demultiplexers as general-purpose logic  G Out0 Out1 Out2 Out3 Out4 Out5 Out6 Out7 CSE370.C. n control inputs (“selects”). Sn.

Lecture 10 16 . Lecture 10 15 CSE370. 5-term. 4-function PLA  Programmable block for sum-of-products logic • • • inputs AND array product terms OR array outputs • • • CSE370. Lecture 10 5:32 demux  Actually NAND/NOR gates You program the array by making or breaking connections You "program" the wire connections A 3-input. Lecture 10 B 0 1 2 3:8 3 Demux 4 5 6 7 S2 S1 S0 0 1 2 3:8 3 Demux 4 5 6 7 S2 S1 S0 C D A'B'C'D'E' ABCDE E 0 1 2 3:8 3 Demux 4 5 6 7 S2 S1 S0 0 1 2 3:8 3 Demux 4 5 6 7 S2 S1 S0 C D A'BC'DE' AB'C'D'E' AB'CDE E 14 All two-level logic functions are available Concept: Large array of uncommitted AND/OR gates  0 2:4 1 Demux 2 S1 S0 3 A A B C D CSE370.Demultiplexers as general-purpose logic Cascading demultiplexers  Example F1 = A'BC'D + A'B'CD + ABCD F2 = ABC'D' + ABC F3 = (A'+B'+C'+D') Enable = 1 0 1 2 3 4 5 6 7 4:16 8 Demux 9 10 11 12 13 14 15 A'B'C'D' A'B'C'D A'B'CD' A'B'CD A'BC'D' A'BC'D A'BCD' A'BCD AB'C'D' AB'C'D AB'CD' AB'CD ABC'D' ABC'D ABCD' ABCD F1 F F2 F3 13 Programmable logic (PLAs & PALs )   CSE370.

make wanted connections F0 F1 F2 F3 = = = = A + B'C' AC' + AB B'C' + AB B'C + A B C AB B'C AC' B'C' A Reuse terms 17 CSE370. break unwanted connections Anti-fuse: Comes disconnected.Sharing product terms   Example: Programming the wire connections F0 = A + B'C' F1 = AC' + AB F2 = B'C' + AB F3 = B'C + A Personality matrix: product term AB B'C AC' B'C' A A 1 – 1 – 1 CSE370. Lecture 10 inputs B C 1 – 0 1 – 0 0 0 – – outputs F0 F1 F2 0 1 1 0 0 0 0 1 0 1 0 1 1 0 0  inputs 1 = asserted in term 0 = negated in term – = does not participate  A outputs 1 = term connected to output 0 = no connection to output F3 0 1 0 0 1 Fuse: Comes connected. Lecture 10 F0 F1 F2 F3 18 .