An Optimized Modified Booth Recoder

for Efficient Design of the Add-Multiply
Operator
Complex arithmetic operations are widely used in Digital Signal Processing (DSP)
applications. In this work, we focus on optimizing the design of the fused Add-Multiply (FAM)
operator for increasing performance. We investigate techniques to implement the direct
recoding of the sum of two numbers in its Modified Booth (MB) form. We introduce a
structured and efficient recoding technique and explore three different schemes by
incorporating them in FAM designs. Comparing them with the FAM designs which use
existing recoding schemes, the proposed technique yields considerable reductions in terms
of critical delay, hardware complexity and power consumption of the FAM unit.

Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through

In this brief, a low-power flip-flop (FF) design featuring an explicit type pulse-triggered
structure and a modified true single phase clock latch based on a signal feed-through
scheme is presented. The proposed design successfully solves the long discharging path
problem in conventional explicit type pulse-triggered FF (P-FF) designs and achieves better
speed and power performance. Based on post-layout simulation results using TSMC CMOS
90-nm technology, the proposed design outperforms the conventional P-FF design dataclose-to-output (ep-DCO) by 8.2% in data-to-Q delay. In the mean time, the performance
edges on power and power- delay-product metrics are 22.7% and 29.7%, respectively.

The proposed modified FTL reduces total power consumption up to 13. The comparison analysis has been carried out by simulating the logic circuit by 180 nm technology. Published in: Signal Processing and Integrated Networks (SPIN).1. The proposed circuit achieves a reduction in the average power. Feedthrough logic can improve the performance by partial evaluation in its computational block before getting a valid input. 2015 2nd International Conference on Date of Conference: 19-20 Feb.An efficient design technique for low power dynamic feedthrough logic with enhanced performance for wide fan-in gates  This paper presents a new approach to high performance and low power circuit for wide fan-in gates using a new CMOS logic known as feedthrough logic (FTL).An 8-b 250-Msample/s power optimized pipelined A/D converter in 0. This model works more effectively in the case of NOR gates but creates more delay as compared to other proposed FTL models. 2015 2.18-µm CMOS The optimal pipeline analog to digital converter (ADC) architectures are analysed to determine the optimal partitioning and particular bits per stage for power optimization . The FTL is more suited for those circuits which consists of a critical path of large cascaded inverting gates. FTL based circuits can perform better in both high fan-out and high frequency operations due to both dynamic power consumption and lower delay at the cost of area.25% in wide fan-in NAND gates and 99.9% in wide fan-in NOR gates.

purpose.5-1. 2015 International Symposium on . 60.18 μm CMOS and 8-bit with 2.5 bits per stage resolution.8 V power supply. Compared with sending raw ECG data.52 μW. The optimal partitioning of the 8-bit ADC is realized with 2. we also can use the algorithm based on DWT to observe frequency-domain features in Parkinson's disease (PD).5 bits/stage resolution ADCs achieved 43 dB SINAD. and power consumption is 27 mW from a 1.5-2 cascading stages employed with double sampling sample hold (DSSH) architecture.6 dB SFDR for an input signalfrequency of 1.5-1.7 MHz at 250 MSPS. and then extract R-R intervals from the reconstructed waveform.7 MHz at 250 MSPS. In EEGsignal processing. our design saves as much as 99.5% power while only detecting and sending R-R interval sequences in ECG application. the operating clock frequency is 360 Hz. Hence. Technology and Applications (VLSI-SATA). the operating voltage is 1.5-1.5-1.8 V. It is found in our design that the multi bit partitioning with 2.15 mm2.5 bits per stage for an 8-bit pipeline ADCs circuit.20 dB SINAD.5-2 cascading stages and another topology with 1.A configurable wavelet processor for biomedical applications In ECG signal processing. Architecture. Published in: VLSI Systems. and power consumption is 49 mW from a 1. The total core area is 1. 2015 International Conference on Date of Conference: 8-10 Jan. An 8bit 1. is optimum in terms of power consumption compare to the 1.5-2.52.5 bits/stage resolution ADC with the same technology process achieved 47. 50. we proposed a configurable wavelet processor with feature extraction circuit in the sensor for more efficient biomedical applications.8 V power supply. Published in: VLSI Design. ADCs are implemented in 0. Automation and Test (VLSI-DAT). We have implemented the design with TSMC 0.18 μm technology. and the power consumption is 0.78 dB spurious free dynamic range (SFDR) for an input signal frequency of 1. 2015 3.5-1. we can use discrete wavelet transform (DWT) algorithm to remove unusable features from original signals.

2015 5. they are two kinds of factor form matching. this is particularly attractive for arithmetic circuits. The clock gating logic can be generalized by using a technique called a Wide Spread Adapting (WSA) clock gating technique which is a modified Boolean function technique. Approximate computing reduces accuracy. The strong matching seeks for the matches which are externally present in the factored forms and the weak matching identifies matches that are implicit in the logic and they are hard to discover. such as signal processing and multimedia. but it still provides meaningful and faster results with usually lower power consumption. 2015 2nd International Conference on Date of Conference: 26-27 Feb. The WSA technique does the matchingprocess by using a WSA algorithm. Clock gating logic uses strong and weak matching process. The gating function is theprocess of filtering glitches from a block which is achieved by inserting clock gating cell. Published in: Electronics and Communication Systems (ICECS). gate count and area.Date of Conference: 27-29 April 2015 4. This WSA technique reduces the clocking signal and the gate pattern. Thus the proposed method achieves reduced clock gating which in turn reduces delay.A Design Approach for Compressor Based Approximate Multipliers Approximate computing is best suited for error resilient applications. power. In this paper. a new design approach is .Generalization of clock gating logic using wide spread adapting technique he Clock gating reduces dynamic power dissipation in synchronous circuits.

Several protection schemes have been proposed to detect and correct errors in FFTs. This makes protection against soft errors a requirement for many applications. Published in: VLSI Design (VLSID). 2015 6. an interesting option is to use algorithmic-based fault tolerance (ABFT) techniques that try to exploit the algorithmic properties to detect and correct errors. Issue: 99 ) . 2015 28th International Conference on Date of Conference: 3-7 Jan. Published in: Very Large Scale Integration (VLSI) Systems. In modern communication systems. IEEE Transactions on (Volume:PP . Among those. two improved protection schemes that combine the use of error correction codes and Parseval checks are proposed and evaluated.Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks Soft errors pose a reliability threat to modern electronic circuits. One example is fast Fourier transforms (FFTs) that are a key building block in many systems. probably the use of the Parseval or sum of squares check is the most widely known.Signal processing and communication applications are well suited for ABFT. this technique is first applied to protect FFTs. Extensive simulation results show that the proposed designs achieve significant accuracy improvement together with power and delay reductions compared to previous approximate designs.proposed to exploit the partitions of partial products using recursive multiplication for compressor-based approximate multipliers. For some applications. Communications and signal processing systems are no exceptions to this trend. a technique that exploits this fact to implement fault tolerance on parallel filters has been proposed. it is increasingly common to find several blocks operating in parallel. In this brief. The results show that the proposed schemes can further reduce the implementation cost of protection. An image processing application is also presented to show the efficiency of the proposed designs. Four multiplier designs are proposed using 4:2 approximate compressors. Then. Recently.

dc and ac hysteresis. lock for the loop. Published in: VLSI Design (VLSID). All the above techniques are implemented in TSMC 0. because of high Q (quality factor) resonators. signal levels at start up can be very low. 2015 28th International Conference on Date of Conference: 3-7 Jan. In particular. This paper proposes a novel frequency scan technique to achieve start up and. This paper proposes a new VLSI architecture for . The paper describes a comparator circuit to convert the input sinusoid to a clock with in-built band pass filter. 2015 A VLSI architecture for watermarking of grayscale images using weighted median prediction Watermarking the digital data is a familiar technique to authenticate and resolve the copyright issues of multimedia data.18 micron process for the ADXRS290 gyroscope product and results show a reliable PLL lock with startup time <. hence.5 ms for up to a Q of 2500. Also a scheme is proposed to avoid wrong phase at start up which could arise in a resonator loop using charge pump based PLL. posing challenges to achieve PLL lock or lead to unacceptable lock times.A Frequency Scan Scheme for PLLBased Locking to High-Q MEMS Resonators Making a MEMS resonator to oscillate at its natural frequency is an essential function in vibratory gyroscopes and is done by using a PLL inside the feedback loop.Page(s): Date of Publication : 11 March 2015 7.

The heater delays were analysed as a function of various heater parameters. In addition to the quench onset criterion used for LTS. as this mechanism will have a minimum computation complexity. 2015 Vlsi image processing 1.. heating station lengths (down to 10 mm) and insulation thickness's (up to 150 μm Kapton). In this VLSI based data hiding process the secret digital signature is hidden in the host image and analyzed with the PSNR value and Payload capacity. the time delay between the heater activation and consequent normal zone initiation in the winding. The heater delays. 2015 2nd International Conference on Date of Conference: 26-27 Feb.watermarking grayscale images using weighted median prediction operation. The heater efficiency seriously decreased for Tcs above 20 K when the cable energy margin approached the energy provided by the protection heater. requiring the cable maximum temperature to reach the current sharing temperature (T cs). The simulated delays in the reference YBCO-cable (T op = 4.Modeling Quench Protection Heater Delays in an HTS Coil he purpose of this research was to investigate the efficiency of the state-of-the-art quench protection heater technology applied to a high-temperature superconductor (HTS)-based accelerator type magnet.5 K. were simulated using the 2D thermal modelling tool CoHDA. Tcs = 16. their value ranges were based on the heaters in the recent LTS magnets: heater powers (PPH(t = 0) = 20-200 W/cm2). I = 5 kA. i. Although experiments are needed . Published in: Electronics and Communication Systems (ICECS). which has been successfully used for low-temperature superconductor (LTS) coils.e.5 K) were mainly between 20 and 100 ms. a criterion accounting for the current redistribution within a cable was introduced in the model. B = 20 T (parallel to cable's wide surface).

1 December 2014 . Issue: 3 ) Article#:2014 october 2. IEEE Transactions on (Volume:25 . Published in: Applied Superconductivity. One is a pair of copper shaking coils coaxially located inside and outside the HTS coil to apply an ac magnetic field in the axial direction. It is found that the copper shaking coils yield the allowable amount of power dissipation in liquid helium. it seems clear that heater based quench protection for HTS-based accelerator magnets requires significant technology developments. The other is an HTS shaking coil with notch located only outside the HTS coil to minimize the radial components of local ac fields applied to windings of the HTS coil as small as possible.Designs and Tests of Shaking Coils to Reduce Screening Currents Induced in HTS Insert Coils for NMR Magnet Two types of shaking coils are focused on reducing screening currents induced in solenoid coils wound with high-temperature superconducting (HTS) tapes.to confirm these results. The effectiveness of the HTS shaking coil to reduce screening-current-induced fields generated by another magnetized HTS coil is also experimentally validated in liquid nitrogen using a commercially available coated conductor with narrow width.