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An Interactive Workshop

on

Field Programmable Gate Arrays


(FPGAs)
21st – 23rd July 2009

Prepared by
Shahzad Asif
Lecturer
MS (System on Chip)
Linköping University
Sweden

Department of Electrical Engineering


COMSATS Institute of Information Technology
Chak Shahzad Campus, Islamabad.
An Interactive Workshop on FPGA

Outline
An Interactive Workshop
¾ Introduction to FPGA and HDLs
on
¾ Xilinx Design Flow
Field Programmable Gate Array (FPGA)
¾ How the code is synthesized to hardware
¾ Difference between synthesis and
Speaker: Shahzad Asif implementation
Lecturer (EE Department)
¾ Coding in VHDL
MS(System-
MS(System-on-
on-Chip)
Linkö
Linköping University, Sweden.

Hardware Design Process Why HDLs?


Design Idea
ARCHITECTURE xyz OF comparator IS
BEGIN a 1

Behavioral Design PROCESS(a,b,gt,eq,lt)


PROCESS(a,b,gt,eq,lt) 2
3

BEGIN
Flow Graph, Pseudo Code, .. 1
3
1
2 9
a_gt_b

IF a > b THEN 2 8

a_gt_b <= ‘1’; b


1 2 1
Data Path Design 3

a_eq_b <= ‘0’; gt


2

Bus & Register Structure. a_lt_b <= ‘0’;


ELSIF a < b THEN eq
1
2
8
9

1
a_gt_b <= ‘0’;
a_eq_b
3
Logic Design 1
2

a_eq_b <= ‘0’; lt


2
8
9

Gate Wirelist, Netlist. a_lt_b <= ‘1’; 1


3
2

ELSIF a = b THEN
Physical Design a_gt_b <= ‘0’; 1 2 1
3
1
2 9
a_lt_b

2 8

a_eq_b <= ‘1’;


Transistor List, Layout, ... a_lt_b <= ‘0’; 1
3
2

END IF;
Manufacturing
END PROCESS;
END xyz;
Chip or Board 3 4

Why HDLs? (Continued) HDL Advantages


¾ Itis evident from the previous example ¾ Top-
Top-down design support.
¾ Architecture test at a very early stage.
that how easy it is to specify hardware
¾ Technology independence.
using High-level language constructs. ¾ Design reusability.
¾ HDLs are used to describe the ¾ Synthesis. (EDA support)
architecture/behavior of an electronic ¾ Standard.
systems. ¾ Easy understanding than schematics.
¾ Documentation.
¾ Higher productivity.
¾ Generic Designs

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An Interactive Workshop on FPGA

HDL Disadvantages Levels of design description


¾ No control for gate level
Algorithmic level
¾ Logic implementation are inefficient
Level of description
¾ Quality of synthesis varies from tool to tool Register Transfer Level
most suitable for synthesis
¾ Synthesis not standard
Logic (gate) level

Circuit (transistor) level

Physical (layout) level

7 8

Two competing implementation FPGAs vs. ASICs


approaches
ASICs FPGAs
ASIC FPGA
Application Specific Field Programmable Off-the-shelf
Integrated Circuit Gate Array High performance

Low development costs


• designed all the way • no physical layout design;
from behavioral description design ends with Low power
to physical layout a bitstream used Short time to the market
to configure a device
• designs must be sent Low cost (but only
for expensive and time • bought off the shelf in high volumes) Reconfigurability
and reconfigured by
consuming fabrication
designers themselves
in semiconductor foundry
9 10

Other FPGA Advantages Field-


Field-Programmable Device (FPD)
¾ Manufacturing cycle for ASIC is very ¾ A general term that refers to any type of
costly, lengthy and engages lots of integrated circuit used for implementing
manpower digital hardware, where the chip can be
z Mistakes not detected at design time have configured by end user to realize different
large impact on development time and cost designs.
z FPGAs are perfect for rapid prototyping of ¾ Another name for FPDs is Programmable
digital circuits Logic Devices (PLDs).
¾ Easy upgrades like in case of software
¾ Unique applications
z reconfigurable computing 11 12

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An Interactive Workshop on FPGA

Types of FPD FPGA


¾ Programmable Logic Array (PLA)
z Contains two levels of logic, an AND-
AND-plane and an OR-
OR-plane. Configurable
¾ Programmable Array Logic (PAL) Logic
z Programmable AND-
AND-plane, fixed OR-
OR-plane Blocks
¾ Simple PLD (SPLD)
I/O

Block RAMs

Block RAMs
z usually refers to PLA or PAL.
¾ Complex PLD (CPLD) Blocks
z Consists of an arrangement of multiple SPLD-
SPLD-like blocks on a
single chip.
Field- Block
¾ Field-Programmable Gate Array
z Whereas CPLDs feature logic resources with a wide number of RAMs
inputs (AND planes), FPGAs offer more narrow logic resources.
z Offer a higher ratio of flip-
flip-flops to logic resources compared to
CPLDs.

13 14

FPGA Major FPGA Vendors


¾ Xilinx, Inc.
¾ Building block of an FPGA is a CLB
¾ Altera Corp.
(Configurable Logic Block). ¾ Atmel FPGA Vendors
¾ A typical CLB consist of 4- ¾ Lattice Semiconductor
4-input LUT(Look Xilinx
Up Table), D flip-
flip-flop, and two input
multiplexer.
58%

31% 11%

Altera All Others


15 16

FPGA Nomenclature
Design Implementation in LUT
2-input Lookup Table 2-input Lookup Table

XC3S1500-4FG320 Address Data Address Data


00 0 00 1
01 0 01 1
Spartan 3 1500 k speed 320 pins 10 0 10 1
family = 1.5 M grade 11 1 11 0
equivalent -4
logic gates = standard package type 2-input AND Gate 2-input NAND Gate

performance

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An Interactive Workshop on FPGA

Implementation of FA using LUT Coding in VHDL


3-input Lookup Table 3-input Lookup Table ¾ Basic Syntax
Address Sum Address Cout ¾ Data Types
(A,B,Cin) (A,B,Cin) ¾ Operators
000 0 000 0 ¾ Signals, Constants, Variables
001 1 001 0 ¾ Signals vs. Variables
010 1 010 0 ¾ Combinational Logic
011 0 011 1 ¾ Component Instantiation
100 1 100 0 ¾ Sequential Logic
101 0 101 1 ¾ Test Bench

111 1 111 1 19 20

Basic Syntax Data Types


¾ Entity
z A black box. ¾ Bit (2-
(2-level logic ‘0’, ‘1’)
z Only the input and output ports can be seen here.
¾ Std_Logic (8-
(8-valued logic ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’, ‘-’)
Entity and_gate is
port (a, b : in std_logic;
c : out std_logic);
a
c ¾ Boolean (True, False)
End and_gate; b
¾ Integer (32-
(32-bit integer)
¾ Architecture
z Design within the black box. ¾ Vector and arrays
Architecture behavior of and_gate is
Begin
¾ Record (user-
(user-defined type, just like a structure in C
c <= a and b; language)
End behavior;

21 22

Operators Operators (Contineud)


¾ Relational operators
Equal to ’=’
¾ Assignment operators z

z Not equal to ’/=’


/=’
z <= used to assign a value to a signal z Less than ’<’
z Greater than ’>’
z := used to assign a value to a variable or a constant. z Less than or equal to ’<=’
<=’
Greater than or equal to ’>=’
>=’
¾ Logical opertors ¾
z

Shift operators
z NOT, AND, OR, NAND, NOR, XOR, XNOR z Shift left logic ’sll’
sll’
z Shift right logic ’srl’
srl’
¾ Arithmetic operators z Shift left arithmetic ’sla’
sla’
z Shift right arithmetic ’sra’
sra’
z Addition ’+’
Note: For shift operations, left operand must be of type BIT_VECTOR,
BIT_VECTOR, while the
z Subtraction ’-’ right operand must be an INTEGER.
z Multiplication ’*’ ¾ Concatenation operators
z &
z Division ’/’ (shift operation is used for division) z (, , , )
z Example: z <= x & ”10010”
10010”, z <= (’
(’1’, ’1’, ’0’, ’1’, ’0’, ’1’, ’0’, ’1’)

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An Interactive Workshop on FPGA

Signals, Constants, Variables Signals vs. Variables


¾ CONSTANT
z A CONSTANT can be declared in a PACKAGE, ENTITY, or ARCHITECTURE.
ARCHITECTURE. SIGNAL VARIABLE

• CONSTANT set_bit : BIT := ‘1’;


¾ SIGNAL Assignment <= :=
z SIGNAL represents circuit interconnects (wires).
z SIGNAL can be declared in a PACKAGE, ENTITY, or ARCHITECTURE.
z Its update is not immediate. In other words, its new value is not
not available until the Represents circuit interconnects (wires) Represents local information
conclusion of the corresponding PROCESS, FUNCTION, or PROCEDURE. Utility

• SIGNAL y : std_logic_vector (7 downto 0);


• SIGNAL control : std_logic := ‘1’; Scope Can be global (seen by entire code) Local (visible only inside the
Note: Initial value in the syntax above is not synthesizable. corresponding PROCESS,
¾ VARIABLE FUNCTION, or PROCEDURE)
z It can only be used inside a PROCESS FUNCTION, or PROCEDURE. Update is not immediate in sequential code Updated immediately
z Unlike SIGNAL, its update is immediate, so the new value can be promptly used
Behavior
in the next line of code.

• VARIABLE y : std_logic_vector (7 downto 0) := “10001000”


10001000”; Usage In a PACKAGE, ENTITY, or Only in sequential code, that
ARCHITECTURE. In an ENTITY, all PORTS is, in a PROCESS,
are SIGNALS by default. FUNCTION, or PROCEDURE.
25 26

Concurrent Code 2-1 MUX (Structural)

ENTITY MUX2to1 IS
¾ VHDL code is inherently concurrent (parallel) PORT (a, b : IN STD_LOGIC;
¾ Only statements inside a PROCESS, sel : IN STD_LOGIC;
q : OUT STD_LOGIC);
FUNCTION, or PROCEDURE are sequential. END MUX2to1;
¾ Concurrent code cannot be used to implement
ARCHITECTURE mux1 OF MUX2to1 IS
synchronous circuits. SIGNAL s1, s2 : STD_LOGIC;
BEGIN
a1 <= a and (not sel);
sel);
a2 <= b and sel;
sel;
q<= a1 or a2;
END mux1;

27 28

2-1 MUX using WHEN statement 2-1 MUX using WITH statement

ENTITY MUX2to1 IS ENTITY MUX2to1 IS


PORT (in1, in2 : IN STD_LOGIC; PORT (in1, in2 : IN STD_LOGIC;
sel : IN STD_LOGIC;
sel : IN STD_LOGIC; mux_out : OUT STD_LOGIC);
mux_out : OUT STD_LOGIC); END MUX2to1;
END MUX2to1;
ARCHITECTURE mux3 OF MUX2to1 IS
ARCHITECTURE mux2 OF MUX2to1 IS BEGIN
WITH sel SELECT
BEGIN mux_out <= in1 WHEN ‘0’,
mux_out <= in1 WHEN sel=
sel=‘0’ ELSE in2 WHEN ‘1’,
in2 WHEN sel=
sel=‘1’ ELSE ‘0’ WHEN OTHERS;
‘0’; END mux3;
END mux2;

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An Interactive Workshop on FPGA

Tri-
Tri-state Buffer Half Adder (Structural)

ENTITY tri_state IS ENTITY half_adder IS


PORT (ena
(ena : IN STD_LOGIC;
input : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
PORT (a, b : IN STD_LOGIC;
output : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); sum, cout : OUT STD_LOGIC);
END tri_state;
tri_state; END half_adder;
half_adder;
ARCHITECTURE arch_tri_state OF tri_state IS
BEGIN ARCHITECTURE arch_half_adder OF half_adder IS
output <= input WHEN (ena
(ena=
=‘0’) ELSE BEGIN
(OTHERS => ‘Z’);
sum <= a XOR b;
END arch_tri_state;
arch_tri_state;
cout <= a AND b;
END arch_half_adder;
arch_half_adder;

31 32

Components (Continued)
Components PORT MAP
¾ Allows the construction of hierarchical designs. ¾ Positional mapping (also called in-
in-order mapping)
¾ Used for partitioning a code, code sharing, and code
reuse. COMPONENT inverter
¾ To use (instantiate) a COMPONENT, it must first be PORT (a : IN STD_LOGIC;
declared. b : OUT STD_LOGIC);
END COMPONENT;
COMPONENT component_name
PORT (port_name : signal_mode signal_type; ... -- other code
port_name : signal_mode signal_type;
...); U1: inverter PORT MAP (x, y);
END COMPONENT;

33 34

Components (Continued)
PORT MAP
Full Adder
¾ Nominal mapping (also called out-
out-of-
of-order mapping)
¾ Ports can also be left unconnected by using the keyword ’OPEN’
OPEN’.
¾ Note that you should never leave the input port unconnected.

COMPONENT inverter
PORT (a : IN STD_LOGIC;
b : OUT STD_LOGIC; W1
W2
c : OUT STD_LOGIC);
END COMPONENT;

... -- other code W3

U1: inverter PORT MAP (a=>x


(a=>x,, b=>y, c=>OPEN);

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Full Adder (Structural)


(using component instantiation) Test Bench
ENTITY full_adder IS ¾ Testing of a design is essential before
PORT (a, b, cin : IN STD_LOGIC;
sum, cout : OUT STD_LOGIC); physical fabrication.
END full_adder;
full_adder;
¾ We can write a VHDL program that
ARCHITECTURE arch_full_adder OF full_adder IS
COMPONENT half_adder encapsulates the DUT (Design Under
PORT ( a, b : IN STD_LOGIC;
sum, cout : OUT STD_LOGIC); Test), generates stimulus signals and
END COMPONENT;
BEGIN
captures the response signals. Such an
C1: half_adder PORT MAP(a,b,w1,w3); arrangement is called a Test bench.
C2: half_adder PORT MAP(w1,cin,sum,w2);
cout <= w2 or w3; W1 W2
END arch_full_adder;
arch_full_adder;

W3
37 38

Test Bench Test Bench (Continued)


Test Bench

DEVICE
DEVICE RESPONSE CAPTURE UNDER TEST
STIMULUS (DUT)
UNDER TEST AND
GENERATOR
(DUT) COMPARISON

Test bench architecture

39 40

Test Bench of Full Adder Test Bench of Counter


ENTITY counter_4bit_test IS
ENTITY full_adder_test IS END counter_4bit_test;
ARCHITECTURE arch_counter_4bit_test OF counter_4bit_test IS
END full_adder_test;
full_adder_test; COMPONENT counter_4bit
ARCHITECTURE arch_full_adder_test OF full_adder_test IS PORT (clk
(clk,, rst : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
COMPONENT full_adder END COMPONENT;
PORT (a,b,cin
(a,b,cin : IN STD_LOGIC; SIGNAL clk,
clk, rst : STD_LOGIC := '0';
sum,cout : OUT STD_LOGIC); SIGNAL data_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
END COMPONENT;
clk_gen:
clk_gen: PROCESS
SIGNAL a,b,cin : STD_LOGIC; BEGIN
SIGNAL sum,cout : STD_LOGIC; LOOP
SIGNAL in_vector : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000"; WAIT FOR 5 ns;
BEGIN clk <= NOT clk;clk;
PROCESS END LOOP;
END PROCESS clk_gen;
clk_gen;
BEGIN
rst_gen:
rst_gen: PROCESS
WAIT FOR 20 ns; BEGIN
in_vector <= in_vector + '1'; -- std_logic_unsigned.all is required rst <= '1';
END PROCESS; WAIT FOR 30 ns;
a <= in_vector(0); rst <= '0';
b <= in_vector(1); WAIT;
END PROCESS rst_gen;
rst_gen;
cin <= in_vector(2);
counter1: counter_4bit PORT MAP (clk rst, data_out);
(clk,, rst, data_out);
U1: full_adder PORT MAP (a, b, cin,
cin, sum, cout);
cout); END arch_counter_4bit_test;
END arch_full_adder_test;
arch_full_adder_test;

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Synthesis
Implementation
VHDL description Circuit netlist
ARCHITECTURE MLU_DATAFLOW OF MLU IS

SIGNAL A1:STD_LOGIC;
SIGNAL B1:STD_LOGIC;
SIGNAL Y1:STD_LOGIC;
SIGNAL MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC;

BEGIN
A1<=A WHEN (NEG_A='0') ELSE
NOT A;
B1<=B WHEN (NEG_B='0') ELSE
NOT B;
Y<=Y1 WHEN (NEG_Y='0') ELSE
NOT Y1;

MUX_0<=A1 AND B1;


MUX_1<=A1 OR B1;
MUX_2<=A1 XOR B1;
MUX_3<=A1 XNOR B1;

WITH (L1 & L0) SELECT


Y1<=MUX_0 WHEN "00",
MUX_1 WHEN "01",
MUX_2 WHEN "10",
MUX_3 WHEN OTHERS;

END MLU_DATAFLOW;

43 44

Translation Pin Assignment


Synthesis
FPGA
Circuit netlist Timing Constraints
Constraint Editor
Electronic Design Native
Constraint SEGMENTS(0)
Interchange Format SEGMENTS(1)
File CLOCK
CONTROL(0) SEGMENTS(2)
EDIF NCF UCF CONTROL(1) SEGMENTS(3)
User Constraint File Design SEGMENTS(4)
CONTROL(2)
RESET SEGMENTS(5)
SEGMENTS(6)

Translation

NGD Native Generic Database file

45 46

Circuit Netlist Mapping

LUT0
LUT4

LUT1
FF1
LUT5

LUT2

FF2
LUT3

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Placing Routing
FPGA CLB SLICES
FPGA CLB SLICES
Programmable Connections

49 50

Configuration Signals
¾ Once a design is implemented, you must create SIGNAL a : STD_LOGIC;
STD_LOGIC;
a file that the FPGA can understand
z This file is called a bit stream: a BIT file (.bit a
extension) 1 wire

¾ The BIT file can be downloaded directly to the SIGNAL b : STD_LOGIC_VECTOR(7


STD_LOGIC_VECTOR(7 DOWNTO 0);
FPGA, or can be converted into a PROM file
which stores the programming information b
8 bus

51 52

Merging wires and buses Splitting buses


a a
4 4
10 10
b 5 d d b
5

c c

SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);


SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL b: STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL b: STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNAL c: STD_LOGIC;
SIGNAL c: STD_LOGIC; SIGNAL d: STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL d: STD_LOGIC_VECTOR(9 DOWNTO 0);
a <= d(9 downto 6);
d <= a & b & c; b <= d(5 downto 1);
c <= d(0);

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PROCESS PROCESS (Continued)


¾ A process is a sequence of instructions referred
to as sequential statements. OPTIONAL

• A process can be given a unique name using an


optional LABEL followed by the keyword
PROCESS [label:] PROCESS [(sensitivity list)]
• The keyword BEGIN is used to indicate the start
of the PROCESS
[declaration part]
• All statements within the PROCESS are executed BEGIN
SEQUENTIALLY.
statement part
• A PROCESS must end with the keywords END
PROCESS. END PROCESS [label];

55 56

PROCESS with a Sensitivity List Sequential Code


¾ List of signals to which ¾ PROCESS, FUNCTION, and
the process is sensitive.
¾ Whenever there is an PROCEDURE are executed sequentially.
event on any of the label: process (sensitivity list)
list)
¾ Sequential code can be used to build
signals in the sensitivity declaration part
list, the process fires. begin sequential circuits as well as
¾ Every time the process statement part combinational circuits.
fires, it will run in its
end process;
entirety.
¾ WAIT statements are
NOT ALLOWED in a
processes with
SENSITIVITY LIST.
57 58

DFF with asynchronous reset Multiple Drivers (Race Condition)


ENTITY bad_code1 IS
ENTITY DFF IS PORT (d1, d2, clk,
clk, rst : IN STD_LOGIC;
PORT (d, clk,
clk, rst : IN STD_LOGIC; q : OUT STD_LOGIC);
q : OUT STD_LOGIC); END bad_code1;
END DFF; ARCHITECTURE arch_bad_code1 OF bad_code1 IS
BEGIN
PROCESS (clk
(clk,, rst)
rst)
ARCHITECTURE arch_DFF OF DFF IS BEGIN
BEGIN IF ( rst = ‘1’ ) THEN
PROCESS (clk
(clk,, rst)
rst) q <= ‘0’;
BEGIN ELSIF (clk
(clk’’EVENT AND clk=
clk=‘1’) THEN
IF ( rst = ‘1’ ) THEN q <= d1;
q <= ‘0’; END IF;
END PROCESS;
ELSIF (clk(clk’’EVENT AND clk=
clk=‘1’) THEN
PROCESS (clk
(clk,, rst)
rst)
q <= d; BEGIN
END IF; IF ( rst = ‘1’ ) THEN
END PROCESS; q <= ‘0’;
END arch_DFF;
arch_DFF; ELSIF (clk
(clk’’EVENT AND clk=
clk=‘1’) THEN
q <= d2;
END IF;
END PROCESS;
END arch_bad_code1;
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Shift Register Shift Register (Example 1)


ENTITY shift_register1 IS
PORT (d, clk,
clk, rst : IN STD_LOGIC;
q : OUT STD_LOGIC);
END shift_register1;

ARCHITECTURE arch_shift_register OF shift_register1 IS


SIGNAL q1, q2 : STD_LOGIC;
BEGIN
PROCESS (clk(clk,, rst)
rst)
BEGIN
IF ( rst = ‘1’ ) THEN
q1 <= ‘0’;
q2 <= ‘0’;
q <= ‘0’;
ELSIF (clk(clk’’EVENT AND clk=
clk=‘1’) THEN
q1 <= d;
q2 <= q1;
q <= q2;
END IF;
END PROCESS;
END arch_shift_register;
arch_shift_register;
61 62

Shift Register (Example 2) Shift Register (Example 3)


ARCHITECTURE arch_shift_register OF shift_register2 IS
SIGNAL q1, q2 : STD_LOGIC;
ENTITY shift_register3 IS
BEGIN
PORT (d, clk,
clk, rst : IN STD_LOGIC;
PROCESS (clk(clk,, rst)
rst)
q : OUT STD_LOGIC);
BEGIN
END shift_register3;
IF ( rst = ‘1’ ) THEN q1 <= ‘0’;
ELSIF (clk(clk’’EVENT AND clk=
clk=‘1’) THEN q1 <= d;
ARCHITECTURE arch_shift_register OF shift_register3 IS
END IF;
CONSTANT n : INTEGER := 4;
END PROCESS;
SIGNAL internal_sig : STD_LOGIC_VECTOR(n-
STD_LOGIC_VECTOR(n-1 DOWNTO 0);
PROCESS (clk(clk,, rst)
rst)
BEGIN
BEGIN
PROCESS (clk(clk,, rst)
rst)
IF ( rst = ‘1’ ) THEN q2 <= ‘0’;
BEGIN
ELSIF (clk(clk’’EVENT AND clk=
clk=‘1’) THEN q2 <= q1;
IF ( rst = ‘1’ ) THEN
END IF;
internal_sig <= (OTHERS => ‘0’);
END PROCESS;
ELSIF (clk(clk’’EVENT AND clk=
clk=‘1’) THEN
PROCESS (clk(clk,, rst)
rst)
internal_sig <= d & internal_sig(n-
internal_sig(n-1 DOWNTO 1);
BEGIN
END IF;
IF ( rst = ‘1’ ) THEN q <= ‘0’;
END PROCESS;
ELSIF (clk(clk’’EVENT AND clk=
clk=‘1’) THEN q <= q2;
q <= internal_sig(0);
END IF;
END arch_shift_register;
arch_shift_register;
END PROCESS;
END arch_shift_register;
arch_shift_register; 63 64

Shift Register (Example 4) Counter


ENTITY shift_register4 IS
GENERIC (n : INTEGER := 4);
PORT (d, clk,
clk, rst : IN STD_LOGIC;
q : OUT STD_LOGIC);
END shift_register4;

ARCHITECTURE arch_shift_register OF shift_register4 IS


SIGNAL internal_sig : STD_LOGIC_VECTOR(n-
STD_LOGIC_VECTOR(n-1 DOWNTO 0);
BEGIN
PROCESS (clk(clk,, rst)
rst)
BEGIN
IF ( rst = ‘1’ ) THEN
internal_sig <= (OTHERS => ‘0’);
ELSIF (clk(clk’’EVENT and clk=
clk=‘1’) THEN
internal_sig <= d & internal_sig(n-
internal_sig(n-1 DOWNTO 1);
END IF;
END PROCESS;
q <= internal_sig(0);
END arch_shift_register;
arch_shift_register;

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Frequency Division 2-1 MUX using CASE statement

Entity freq_division is Entity MUX2to1 is


PORT (clk
(clk,, rst : in std_logic;
std_logic; PORT (in1, in2 : in std_logic;
std_logic;
clk_out : out std_logic);
std_logic); sel : in std_logic;
std_logic;
End freq_division;
freq_division; mux_out : out std_logic);
std_logic);
End MUX2to1;
Architecture arch_freq_division of freq_division is
SIGNAL count : STD_LOGIC_VECTOR(7 DOWNTO 0); Architecture mux4 of MUX2to1 is
begin begin
PROCESS (clk (clk,, rst)
rst) PROCESS(in1, in2, sel)
begin BEGIN
if ( rst = ‘1’ ) then CASE sel IS
count <= (OTHERS => ‘0’); WHEN ‘0’ => mux_out <= in1;
elsif (clk’
clk’event and clk=
clk=‘1’) then WHEN ‘1’ => mux_out <= in2;
counter <= counter + 1; WHEN OTHERS => mux_out <= ‘0’;
end if;
end process; END CASE;
clk_out <= count(7); END PROCESS;
end arch_freq_division;
arch_freq_division; end mux4;
67 68

2-1 MUX using IF/ELSE statement Generic Adder using LOOP


ENTITY adder IS
Entity MUX2to1 is GENERIC (length : INTEGER := 8);
PORT (in1, in2 : in std_logic;
std_logic; PORT (a, b : IN STD_LOGIC_VECTOR (length-
(length-1 DOWNTO 0);
sel : in std_logic;
std_logic; cin : IN STD_LOGIC;
mux_out : out std_logic);
std_logic); sum : OUT STD_LOGIC_VECTOR (length-
(length-1 DOWNTO 0);
End MUX2to1; cout : OUT STD_LOGIC);
END adder;
Architecture mux5 of MUX2to1 is
begin ARCHITECTURE arch_adder OF adder IS
PROCESS(in1, in2, sel) BEGIN
BEGIN PROCESS (a, b, cin)
cin)
IF sel = ‘0’ then VARIABLE carry : STD_LOGIC_VECTOR (length DOWNTO 0);
mux_out <= in1; BEGIN
ELSIF sel = ‘1’ then carry(0) := cin;
cin;
mux_out <= in2; FOR i IN 0 TO length-
length-1 LOOP
ELSE sum(i)
sum(i) <= a(i)
a(i) XOR b(i)
b(i) XOR carry(i);
carry(i);
mux_out <= ‘0’; carry(i+1) := (a(i
(a(i)) AND b(i))
b(i)) OR (a(i
(a(i)) AND carry(i))
carry(i)) OR (b(i
(b(i)) AND carry(i));
carry(i));
END IF; END LOOP;
END PROCESS; cout <= carry(length);
carry(length);
end mux5; END PROCESS;
END arch_adder;
arch_adder;
69 70

Binary to BCD Converter


Shift and Add-
Add-3 Algorithm
Combinational Multiplier
¾ Code implemented in C Blocks is as follows:
PROCESS(binary_in)
PROCESS(binary_in)
BEGIN
CASE binary_in IS
WHEN "0000" => BCD_out <= "0000";
WHEN "0001" => BCD_out <= "0001";
WHEN "0010" => BCD_out <= "0010";
WHEN "0011" => BCD_out <= "0011";
WHEN "0100" => BCD_out <= "0100";
WHEN "0101" => BCD_out <= "1000";
WHEN "0110" => BCD_out <= "1001";
WHEN "0111" => BCD_out <= "1010";
WHEN "1000" => BCD_out <= "1011";
WHEN "1001" => BCD_out <= "1100";
WHEN OTHERS => BCD_out <= "0000";
END CASE;
END PROCESS;
71 72

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Booth Multiplier Bad Program


Process(clk)
Process(clk)
BEGIN
IF (clk’
(clk’EVENT AND clk=’clk=’1’) THEN
small<=list (i);
pos<=i;
IF (small >list (j)) THEN
small<=list (j);
pos<=j;
END IF;
list (pos)<=list (i);
list (i)<=small;
i<=i+1;
END IF;
END PROCESS;

73 74

Shift Operation using FOR Loop


¾ Left shifting a signal which is defined as
’SIGNAL x : STD_LOGIC_VECTOR(6 DOWNTO 0);’
0);’

PROCESS(clk)
BEGIN
PROCESS(clk)
x(6) <= x(5);
BEGIN Equavalent Code x(5) <= x(4);
FOR i IN 0 TO 5 LOOP
x(4) <= x(3);
x(i+1) <= x(i);
x(3) <= x(2);
END LOOP;
x(2) <= x(1);
x(0) <= ’0’;
x(1) <= x(0);
END PROCESS;
x(0) <= ’0’;
END PROCESS;

75

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Introduction to Modelsim

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Step 1: Launch the ModelSim 5.7f Simulator.

• Open the ModelSim 5.7f software: Go to Start Menu Æ Programs Æ


ModelSim SE 5.7f Æ ModelSim

• Go to File Æ New Æ Project (the following dialogue box will appear)

Figure 1: Starting New Project

• Write the project name and click OK.


• After clicking OK, the following small window will appear

Figure 2: Adding a new/existing file to project

After selecting Create New File another window will appear

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Figure 3: Create a new project file

• Give the name of the VHDL File and select OK.

Step 2: Right click on the name of the file, and select Edit.

Figure 4: Editing the file

Write the following code

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;

ENTITY half_adder IS
PORT (a,b : IN STD_LOGIC;
sum, cout : OUT STD_LOGIC);
END half_adder;

ARCHITECTURE arch_half_adder OF half_adder IS


BEGIN

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sum <= a XOR b;


cout <= a AND b;
END arch_half_adder;

• Save the Code

Step 3: Simulate your VHDL code to verify that it is functioning correctly. If after
simulating the design you find an error, you can go back and make changes, recompile
the code, and re-simulate

• Right Click on workspace Æ Add To Project Æ New File


• Write the Stimulus code, which as follows

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;

ENTITY half_adder_test IS
END half_adder_test;

ARCHITECTURE arch_half_adder_test OF half_adder_test IS

COMPONENT half_adder
PORT (a,b : IN STD_LOGIC;
sum,cout : OUT STD_LOGIC);
END COMPONENT;

SIGNAL in1,in2 : STD_LOGIC;


SIGNAL sum,cout : STD_LOGIC;

BEGIN

PROCESS
BEGIN
in1 <= '0';
in2 <= '0';
WAIT FOR 20 ns;

in1 <= '1';


in2 <= '0';
WAIT FOR 20 ns;

in1 <= '0';


in2 <= '1';
WAIT FOR 20 ns;

in1 <= '1';


in2 <= '1';

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WAIT FOR 20 ns;


END PROCESS;

U1: half_adder PORT MAP (in1, in2, sum, cout);

END arch_half_adder_test;

• Compile all the files(if an error occurs edit that particular file)
• Now click on menu Simulate ÆSimulate, following window will appear

Figure 5: Simulate

• Select the work and the test file. Then click OK.
• The design will be loaded.
• Now Select the Simulation Æ Run Æ Run All
• The results will be displayed in the text form.
• To, view the wave forms click on View Æ Signal, and View ÆWave.
• The following windows will appear.

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Figure 6: Signal and Wave Window

• Select the signals, right click and add them to waveform.


• Select restart

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Figure 7: Restarting the simulation

• Then Select Run All

Figure 8: Waveform

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SPARTAN XCS 10 TUTORIAL


Using
Xilinx 4.1i

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Step 1: First of all we need to start a new project. Do this by clicking FileÆ New Project.
The following window will appear.

Figure 1: Starting New Project

Here you can set the project name, and other information.

Step 2: Now, we have to add a .VHDL file to the project. Click on, Project Æ New
Source. The following window will appear.

Figure 2: Adding a new file to project

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Step 3: Continue to next steps. We do not need to write any information during this.

Figure 3: Xilinx window after adding a new source file

Step 4: Now write the VHDL code as shown in the figure. After this select the “Edit
Implementation Constraints Editor”. We have to run the Editor for locking the pins. By
only double clicking this option we can run the Editor.

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Figrue 4: Edit Implementation Constraints

A new window will be opened. We have to lock the pins according to the Spartan I/Os.
The following are the pin numbers which we have assigned to our modules inputs and
output. All the inputs are connected to the switches on the Board and the we assign the
output to an LED.

The format for writing the pin number is e.g,


A Í p28.

You have to save this file and the close the Editor and return to the XILINX main
window.

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Figure 5: Pin Assignments

Step 5: After giving the pin configuration run the synthesize command by simply double
clicking it or by selecting the synthesize option and then using the run command. The
green TICK on the ‘Synthesize’ button will indicate correct syntheses.

Step 6: After this double click the ‘Implement Design’ option. Green TICK on the
Implement button will indicate correct Implementation.

Step 7: The next step is to generate a bit file which can be downloaded in the FPGA.
This can be easily done by simply double clicking the ‘Generate Programming File’
option. If the bit file is generated successfully you will see the same green TICK on it.

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Figure 6: Xilinx window after “Generate Programming File”

Step 5: For the downloading of the bit file we have to use the utility of “Configure
Device iMPACT”.

Figure 7: Configure Device (iMPACT)

By running it we will see another window.

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Figure 8: iMPACT window after configuring device

This window tells us that the device connected is a valid device and it is ready to be
loaded with the bit file.

Figure 9: Assigning new configuration file

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By right clicking on the device icon we get two options:


1 Program
2 Assign New Configuration File…

If no configuration file is assigned or if you want to assign a new configuration file then
select the 2nd option. A browser window will be opened and from here you can select the
bit file which you want to down load in the FPGA. In this example the bit file Name is
“and_gate.bit”.

After selecting the bit file you have to Program the device. After the successful
downloading has been done you will be given a success message.

Figure 10: iMPACT window after successful program download

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THE VHDL CODE:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY and_gate IS
PORT (a,b : IN STD_LOGIC;
output : OUT STD_LOGIC);
END and_gate;

ARCHITECTURE Behavioral OF and_gate IS

BEGIN

output <= a AND b;

END Behavioral;

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XSA BOARD PINS CONFIGURATIONS:

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LAB # 01

In this lab, we will design some small circuits in VHDL using the ModelSim tool. You
will use a typical HDL flow, write the HDL code, and run a functional HDL simulation.

• Half Adder
• Full Adder
• 4-bit Ripple Carry Adder (Structural)
• 4-to-1 Multiplexer

After completing this lab, you will be able to:

• Perform the basic design flow for writing VHDL code using concurrent statements.
• Understand the basic design for a testbench.
• Simulate a VHDL file using Modelsim.
• Analyze the simulation Results.

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Half Adder
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;

ENTITY half_adder IS
PORT (a,b : IN STD_LOGIC;
sum, cout : OUT STD_LOGIC);
END half_adder;

ARCHITECTURE arch_half_adder OF half_adder IS


BEGIN
sum <= a XOR b;
cout <= a AND b;
END arch_half_adder;

Half Adder Testbench


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;

ENTITY half_adder_test IS
END half_adder_test;

ARCHITECTURE arch_half_adder_test OF half_adder_test IS

COMPONENT half_adder
PORT (a,b : IN STD_LOGIC;
sum,cout : OUT STD_LOGIC);
END COMPONENT;

SIGNAL in1,in2 : STD_LOGIC;


SIGNAL sum,cout : STD_LOGIC;

BEGIN

PROCESS
BEGIN
in1 <= '0';
in2 <= '0';
WAIT FOR 20 ns;

in1 <= '1';


in2 <= '0';
WAIT FOR 20 ns;

in1 <= '0';


in2 <= '1';
WAIT FOR 20 ns;

in1 <= '1';


in2 <= '1';
WAIT FOR 20 ns;
END PROCESS;

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U1: half_adder PORT MAP (in1, in2, sum, cout);

END arch_half_adder_test;

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Full Adder
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;

ENTITY full_adder IS
PORT (a,b,cin : IN STD_LOGIC;
sum, cout : OUT STD_LOGIC);
END full_adder;

ARCHITECTURE arch_full_adder OF full_adder IS


BEGIN
sum <= a XOR b XOR cin;
cout <= (a AND b) or (a AND cin) or (b AND cin);
END arch_full_adder;

Full Adder Testbench


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY full_adder_test IS
END full_adder_test;

ARCHITECTURE arch_full_adder_test OF full_adder_test IS

COMPONENT full_adder
PORT (a,b,cin : IN STD_LOGIC;
sum,cout : OUT STD_LOGIC);
END COMPONENT;

SIGNAL a,b,cin : STD_LOGIC;


SIGNAL sum,cout : STD_LOGIC;
SIGNAL in_vector : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";

BEGIN

PROCESS
BEGIN
WAIT FOR 20 ns;
in_vector <= in_vector + '1'; -- std_logic_unsigned.all is
required
END PROCESS;

a <= in_vector(0);
b <= in_vector(1);
cin <= in_vector(2);

U1: full_adder PORT MAP (a, b, cin, sum, cout);

END arch_full_adder_test;

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4-bit RCA (Structural)


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;

ENTITY RCA_4bit IS
PORT (a,b : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cin : IN STD_LOGIC;
sum : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
cout : OUT STD_LOGIC);
END RCA_4bit;

ARCHITECTURE arch_RCA_4bit OF RCA_4bit IS

COMPONENT full_adder2
PORT (a,b,cin : IN STD_LOGIC;
sum,cout : OUT STD_LOGIC);
END COMPONENT;

SIGNAL c1, c2, c3 : STD_LOGIC;

BEGIN

f_adder1: full_adder2 PORT MAP (a(0), b(0), cin, sum(0), c1);


f_adder2: full_adder2 PORT MAP (a(1), b(1), c1, sum(1), c2);
f_adder3: full_adder2 PORT MAP (a(2), b(2), c2, sum(2), c3);
f_adder4: full_adder2 PORT MAP (a(3), b(3), c3, sum(3), cout);

END arch_RCA_4bit;

4-bit RCA Testbench


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY RCA_4bit_test IS
END RCA_4bit_test;

ARCHITECTURE arch_RCA_4bit_test OF RCA_4bit_test IS

COMPONENT RCA_4bit
PORT (a,b : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cin : IN STD_LOGIC;
sum : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
cout : OUT STD_LOGIC);
END COMPONENT;

SIGNAL a,b : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";


SIGNAL cin : STD_LOGIC;
SIGNAL sum : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL cout : STD_LOGIC;

BEGIN

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input_a: PROCESS
BEGIN
WAIT FOR 20 ns;
a <= a + '1'; -- std_logic_unsigned.all is required
END PROCESS input_a;

input_b: PROCESS
BEGIN
WAIT FOR 20 ns;
b <= b + "0010"; -- std_logic_unsigned.all is required
END PROCESS input_b;

cin <= '0';

RCA_1: RCA_4bit PORT MAP (a, b, cin, sum, cout);

END arch_RCA_4bit_test;

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4 to 1 Multiplexer
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;

ENTITY MUX_4to1 IS
PORT (in1, in2, in3, in4 : IN STD_LOGIC;
sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
mux_out : OUT STD_LOGIC);
END MUX_4to1;

ARCHITECTURE arch_MUX_4to1 OF MUX_4to1 IS


BEGIN
mux_out <= in1 WHEN sel="00" ELSE
in2 WHEN sel="01" ELSE
in3 WHEN sel="10" ELSE
in4 WHEN sel="11" ELSE
'0';
END arch_MUX_4to1;

4 to 1 Multiplexer Testbench
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_unsigned.all;

ENTITY MUX_4to1_test IS
END MUX_4to1_test;

ARCHITECTURE arch_MUX_4to1_test OF MUX_4to1_test IS

COMPONENT MUX_4to1
PORT (in1, in2, in3, in4 : IN STD_LOGIC;
sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
mux_out : OUT STD_LOGIC);
END COMPONENT;

SIGNAL in1,in2,in3,in4 : STD_LOGIC;


SIGNAL sel : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
SIGNAL mux_out : STD_LOGIC;
SIGNAL in_vector : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";

BEGIN

PROCESS
BEGIN
WAIT FOR 100 ns;
in_vector <= in_vector + '1';
END PROCESS;

PROCESS
BEGIN
WAIT FOR 10 ns;
sel <= sel + '1';

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END PROCESS;

(in1,in2,in3,in4) <= in_vector;

mux1: MUX_4to1 PORT MAP (in1, in2, in3, in4, sel, mux_out);

END arch_MUX_4to1_test;

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LAB # 02
In this lab, we will design some small circuits in VHDL using the Xilinx 4.1. You will
use a typical HDL flow, write the HDL code, and run a functional HDL simulation
(Modelsim is integrated with the Xilinx for simulation purpose). After simulation, you
will synthesize the HDL code and implement it on Spartan-I FPGA.

• Full Adder
• 4-bit Ripple Carry Adder (Using loop)
• 7-Segment Decoder
• 4-bit Ripple Carry Adder with 7-Segment decoder for observing output

After completing this lab, you will be able to:

• Perform the basic design flow for writing VHDL code using concurrent statements.
• Perform the hierarchical design, using component instantiation.
• Simulate a VHDL file using Modelsim (from Xilinx environment).
• Synthesize the VHDL code, and implement it on FPGA.

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Full Adder (Structural)


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;

ENTITY full_adder2 IS
PORT (a,b,cin : IN STD_LOGIC;
sum, cout : OUT STD_LOGIC);
END full_adder2;

ARCHITECTURE arch_full_adder2 OF full_adder2 IS

COMPONENT half_adder
PORT (a,b : IN STD_LOGIC;
sum,cout : OUT STD_LOGIC);
END COMPONENT;

SIGNAL w1, w2, w3 : STD_LOGIC;

BEGIN

h_adder1: half_adder PORT MAP (a, b, w1, w3);


h_adder2: half_adder PORT MAP (w1, cin, sum, w2);

cout <= w2 OR w3;

END arch_full_adder2;

Pin Configuration (UCF)


NET "a" LOC = "P28";
NET "b" LOC = "P27";
NET "cin" LOC = "P26";
NET "cout" LOC = "P69";
NET "sum" LOC = "P68";

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4-bit RCA (using loop)


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;

ENTITY RCA_4bit_2 IS
GENERIC (length : INTEGER := 4);
PORT (a,b : IN STD_LOGIC_VECTOR(length-1 DOWNTO 0);
cin : IN STD_LOGIC;
sum : OUT STD_LOGIC_VECTOR(length-1 DOWNTO 0);
cout : OUT STD_LOGIC);
END RCA_4bit_2;

ARCHITECTURE arch_RCA_4bit_2 OF RCA_4bit_2 IS


BEGIN

PROCESS (a, b, cin)


VARIABLE carry : STD_LOGIC_VECTOR (length DOWNTO 0);
BEGIN
carry(0) := cin;
FOR i IN 0 TO length-1 LOOP
sum(i) <= a(i) XOR b(i) XOR carry(i);
carry(i+1) := (a(i) AND b(i)) OR (a(i) AND carry(i)) OR
(b(i) AND carry(i));
END LOOP;
cout <= carry(length);
END PROCESS;

END arch_RCA_4bit_2;

Pin Configuration (UCF)


NET "a<0>" LOC = "P25";
NET "a<1>" LOC = "P26";
NET "a<2>" LOC = "P27";
NET "a<3>" LOC = "P28";
NET "b<0>" LOC = "P19";
NET "b<1>" LOC = "P20";
NET "b<2>" LOC = "P23";
NET "b<3>" LOC = "P24";
NET "cin" LOC = "P59";
NET "cout" LOC = "P66";
NET "sum<0>" LOC = "P60";
NET "sum<1>" LOC = "P61";
NET "sum<2>" LOC = "P62";
NET "sum<3>" LOC = "P65";

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7-Segment Decoder
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;

ENTITY seven_segment_decoder IS
PORT (data_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
data_out : OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END seven_segment_decoder;

ARCHITECTURE arch_seven_segment_decoder OF seven_segment_decoder IS

SIGNAL data_decoded : STD_LOGIC_VECTOR(6 DOWNTO 0);

BEGIN

-- data_out(6,5,4,3,2,1,0) --> a, b, c, d, e, f, g
WITH data_in SELECT
data_decoded <= ('1','1','1','1','1','1','0') WHEN "0000",
('0','1','1','0','0','0','0') WHEN "0001",
('1','1','0','1','1','0','1') WHEN "0010",
('1','1','1','1','0','0','1') WHEN "0011",
('0','1','1','0','0','1','1') WHEN "0100",
('1','0','1','1','0','1','1') WHEN "0101",
('1','0','1','1','1','1','1') WHEN "0110",
('1','1','1','0','0','0','0') WHEN "0111",
('1','1','1','1','1','1','1') WHEN "1000",
('1','1','1','1','0','1','1') WHEN "1001",
('1','1','1','0','1','1','1') WHEN "1010",
('0','0','1','1','1','1','1') WHEN "1011",
('1','0','0','1','1','1','0') WHEN "1100",
('0','1','1','1','1','0','1') WHEN "1101",
('1','0','0','1','1','1','1') WHEN "1110",
('1','0','0','0','1','1','1') WHEN "1111",
(OTHERS=>'0') WHEN OTHERS;

data_out <= NOT (data_decoded); -- for common-cathode 7-segment

END arch_seven_segment_decoder;

7-Segment Decoder Testbench


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_unsigned.all;

ENTITY seven_segment_decoder_test IS
END seven_segment_decoder_test;

ARCHITECTURE arch_seven_segment_decoder_test OF
seven_segment_decoder_test IS

COMPONENT seven_segment_decoder
PORT (data_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

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data_out : OUT STD_LOGIC_VECTOR(6 DOWNTO 0));


END COMPONENT;

SIGNAL data_in : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";


SIGNAL data_out : STD_LOGIC_VECTOR(6 DOWNTO 0);

BEGIN

PROCESS
BEGIN
WAIT FOR 10 ns;
data_in <= data_in + '1';
END PROCESS;

seven_seg1: seven_segment_decoder PORT MAP (data_in, data_out);

END arch_seven_segment_decoder_test;

Pin Configuration (UCF)


NET "data_in<0>" LOC = "P25";
NET "data_in<1>" LOC = "P26";
NET "data_in<2>" LOC = "P27";
NET "data_in<3>" LOC = "P28";
NET "data_out<0>" LOC = "P45";
NET "data_out<1>" LOC = "P46";
NET "data_out<2>" LOC = "P47";
NET "data_out<3>" LOC = "P48";
NET "data_out<4>" LOC = "P49";
NET "data_out<5>" LOC = "P50";
NET "data_out<6>" LOC = "P51";

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4-Bit RCA with 7-Segment Decoder


In this lab, you are given the black box (entity) and you have to design the architecture
yourself using the blocks of RCA and 7-segment decoder which have been designed in
the previous lab.

ENTITY RCA_7_segment IS
PORT (a,b : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Seven_segment_out : OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END RCA_7_segment;

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LAB # 03
In this lab, we will design sequential circuits in VHDL using the Xilinx 4.1. You will use
a typical HDL flow, write the HDL code, and run a functional HDL simulation
(Modelsim is integrated with the Xilinx for simulation purpose). After simulation, you
will synthesize the HDL code and implement it on Spartan-I FPGA.

• Frequency Divider (LED Flasher)


• 4-bit Counter
• 4-bit Combinational Multiplier

After completing this lab, you will be able to:

• Perform the basic design flow for writing VHDL code using concurrent and
sequential statements (Inside a Process).
• Understand of how to design a positive-edge or negative-edge flip-flop.
• Understand the working of a Process.
• Synthesize the VHDL code, and implement it on FPGA.

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Frequency Divisor (LED Flasher)


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;

ENTITY freq_division IS
PORT (clk_in, rst : IN STD_LOGIC;
clk_out : OUT STD_LOGIC);
END freq_division;

ARCHITECTURE arch_freq_division OF freq_division IS

SIGNAL counter : STD_LOGIC_VECTOR(25 DOWNTO 0);


SIGNAL clk2 : STD_LOGIC;

BEGIN

PROCESS (clk_in,rst)
BEGIN
IF(rst='1') THEN
counter <= (OTHERS=>'0');
clk2 <= '0';
ELSIF (clk_in'EVENT AND clk_in='1') THEN
IF(counter=12500000) THEN
counter <= (OTHERS=>'0');
clk2 <= NOT clk2;
ELSE
counter <= counter + '1';
END IF;
END IF;
END PROCESS;

clk_out <= clk2;

END arch_freq_division;

Frequency Divisor Testbench


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_unsigned.all;

ENTITY freq_division_test IS
END freq_division_test;

ARCHITECTURE arch_freq_division_test OF freq_division_test IS

COMPONENT freq_division
PORT (clk_in, rst : IN STD_LOGIC;
clk_out : OUT STD_LOGIC);
END COMPONENT;

SIGNAL clk_in, rst : STD_LOGIC := '0';

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SIGNAL clk_out : STD_LOGIC;

BEGIN

clk_gen: PROCESS
BEGIN
LOOP
WAIT FOR 20 ns;
clk_in <= NOT clk_in;
END LOOP;
END PROCESS clk_gen;

rst_gen: PROCESS
BEGIN
rst <= '1';
WAIT FOR 30 ns;
rst <= '0';
WAIT;
END PROCESS rst_gen;

freq_div: freq_division PORT MAP (clk_in, rst, clk_out);

END arch_freq_division_test;

Pin Configuration (UCF)


Since no system reset is available on the board, so we will use a push
button as reset.

NET "clk_in" LOC = "P13";


NET "clk_out" LOC = "P69";
NET "rst" LOC = "P59";

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4-bit Counter
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;

ENTITY counter_4bit IS
PORT (clk, rst : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END counter_4bit;

ARCHITECTURE arch_counter_4bit OF counter_4bit IS

COMPONENT freq_division
PORT (clk_in, rst : IN STD_LOGIC;
clk_out : OUT STD_LOGIC);
END COMPONENT;

SIGNAL counter : STD_LOGIC_VECTOR(3 DOWNTO 0);


SIGNAL clk_divided : STD_LOGIC;

BEGIN

PROCESS (clk_divided,rst)
BEGIN
IF(rst='1') THEN
counter <= "0000";
ELSIF (clk_divided'EVENT AND clk_divided='1') THEN
counter <= counter + '1';
END IF;
END PROCESS;

data_out <= counter;

freq1: freq_division PORT MAP (clk, rst, clk_divided);

END arch_counter_4bit;

4-bit Counter Testbench


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_unsigned.all;

ENTITY counter_4bit_test IS
END counter_4bit_test;

ARCHITECTURE arch_counter_4bit_test OF counter_4bit_test IS

COMPONENT counter_4bit
PORT (clk, rst : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;

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SIGNAL clk, rst : STD_LOGIC := '0';


SIGNAL data_out : STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

clk_gen: PROCESS
BEGIN
LOOP
WAIT FOR 5 ns;
clk <= NOT clk;
END LOOP;
END PROCESS clk_gen;

rst_gen: PROCESS
BEGIN
rst <= '1';
WAIT FOR 30 ns;
rst <= '0';
WAIT;
END PROCESS rst_gen;

counter1: counter_4bit PORT MAP (clk, rst, data_out);

END arch_counter_4bit_test;

Pin Configuration (UCF)


NET "clk" LOC = "P13";
NET "data_out<0>" LOC = "P66";
NET "data_out<1>" LOC = "P67";
NET "data_out<2>" LOC = "P68";
NET "data_out<3>" LOC = "P69";
NET "rst" LOC = "P59";

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4-bit Multiplier (Combinational)


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY comb_multiplier4bit IS
PORT ( A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
P : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END comb_multiplier4bit;

ARCHITECTURE arch_comb_multiplier4bit OF comb_multiplier4bit IS

COMPONENT full_adder
PORT (a,b,cin : IN STD_LOGIC;
sum, cout : OUT STD_LOGIC);
END COMPONENT;

COMPONENT half_adder
PORT (a,b : IN STD_LOGIC;
sum, cout : OUT STD_LOGIC);
END COMPONENT;

SIGNAL A0B0, A1B0, A2B0, A3B0 : STD_LOGIC;


SIGNAL A0B1, A1B1, A2B1, A3B1 : STD_LOGIC;
SIGNAL A0B2, A1B2, A2B2, A3B2 : STD_LOGIC;
SIGNAL A0B3, A1B3, A2B3, A3B3 : STD_LOGIC;

SIGNAL C10, C11, C12, C13, C20, C21, C22, C23, C30, C31, C32, C33 :
STD_LOGIC;
SIGNAL S10, S11, S12, S13, S20, S21, S22, S23, S30, S31, S32, S33 :
STD_LOGIC;

BEGIN

A0B0 <= A(0) AND B(0);


A1B0 <= A(1) AND B(0);
A2B0 <= A(2) AND B(0);
A3B0 <= A(3) AND B(0);

A0B1 <= A(0) AND B(1);


A1B1 <= A(1) AND B(1);
A2B1 <= A(2) AND B(1);
A3B1 <= A(3) AND B(1);

A0B2 <= A(0) AND B(2);


A1B2 <= A(1) AND B(2);
A2B2 <= A(2) AND B(2);
A3B2 <= A(3) AND B(2);

A0B3 <= A(0) AND B(3);


A1B3 <= A(1) AND B(3);
A2B3 <= A(2) AND B(3);

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A3B3 <= A(3) AND B(3);

half_add1: half_adder PORT MAP (A0B1, A1B0, S10, C10);


half_add2: half_adder PORT MAP (A0B2, S11, S20, C20);
half_add3: half_adder PORT MAP (A0B3, S21, S30, C30);
half_add4: half_adder PORT MAP (A3B1, C12, S13, C13);

full_add1: full_adder PORT MAP (A1B1, A2B0, C10, S11, C11);


full_add2: full_adder PORT MAP (A2B1, A3B0, C11, S12, C12);
full_add3: full_adder PORT MAP (A1B2, S12, C20, S21, C21);
full_add4: full_adder PORT MAP (A2B2, S13, C21, S22, C22);
full_add5: full_adder PORT MAP (A3B2, C13, C22, S23, C23);
full_add6: full_adder PORT MAP (A1B3, S22, C30, S31, C31);
full_add7: full_adder PORT MAP (A2B3, S23, C31, S32, C32);
full_add8: full_adder PORT MAP (A3B3, C23, C32, S33, C33);

P <= C33 & S33 & S32 & S31 & S30 & S20 & S10 & A0B0;

END arch_comb_multiplier4bit;

4-bit Multiplier Testbench


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY comb_multiplier4bit_test IS
END comb_multiplier4bit_test;

ARCHITECTURE arch_comb_multiplier4bit_test OF comb_multiplier4bit_test


IS

COMPONENT comb_multiplier4bit
PORT ( A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
P : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;

SIGNAL A, B : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";


SIGNAL P : STD_LOGIC_VECTOR(7 DOWNTO 0);

BEGIN

input_1: PROCESS
BEGIN
WAIT FOR 40 ns;
A <= A + '1'; -- std_logic_unsigned.all is required
END PROCESS input_1;

input_2: PROCESS
BEGIN
WAIT FOR 20 ns;
B <= B + "0010"; -- std_logic_unsigned.all is required
END PROCESS input_2;

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comb_mul1: comb_multiplier4bit PORT MAP (A, B, P);

END arch_comb_multiplier4bit_test;

Pin Configuration (UCF)


NET "A<0>" LOC = "P25";
NET "A<1>" LOC = "P26";
NET "A<2>" LOC = "P27";
NET "A<3>" LOC = "P28";
NET "B<0>" LOC = "P19";
NET "B<1>" LOC = "P20";
NET "B<2>" LOC = "P23";
NET "B<3>" LOC = "P24";
NET "P<0>" LOC = "P60";
NET "P<1>" LOC = "P61";
NET "P<2>" LOC = "P62";
NET "P<3>" LOC = "P65";
NET "P<4>" LOC = "P66";
NET "P<5>" LOC = "P67";
NET "P<6>" LOC = "P68";
NET "P<7>" LOC = "P69";

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LAB # 04
In this lab, we will design sequential circuits in VHDL using the Xilinx 4.1. You will use
a typical HDL flow, write the HDL code, and run a functional HDL simulation
(Modelsim is integrated with the Xilinx for simulation purpose). After simulation, you
will synthesize the HDL code and implement it on Spartan-I FPGA.

• 4-bit Sequential Multiplier


• 8-bit Binary to BCD Converter (Combinational)
• 4-bit Counter with 7-Segment Display

After completing this lab, you will be able to:

• Perform the basic design flow for writing VHDL code for an iterative algorithm.
• Perform the design flow for a circuit having combinational and sequential blocks.
• Synthesize the VHDL code, and implement it on FPGA.

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4-bit Multiplier (Sequential)


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY Booth_Multiplier4bit IS
PORT ( multiplier : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
multiplicand : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
product : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
valid_out : OUT STD_LOGIC);
END Booth_Multiplier4bit;

ARCHITECTURE arch_Booth_Multiplier4bit OF Booth_Multiplier4bit IS

SIGNAL M,Q,A : std_logic_vector(3 DOWNTO 0);


SIGNAL C : std_logic;

SIGNAL t5bits_1 : std_logic_vector(4 DOWNTO 0);

SIGNAL Q2 : std_logic_vector(3 DOWNTO 0);

BEGIN

PROCESS(clk,rst)
VARIABLE state : integer;
VARIABLE count : integer;
BEGIN
IF rst='1' THEN
M <= "0000";
Q <= "0000";
Q2 <= "0000";
A <= "0000";
count := 4;
C <= '0';
valid_out <= '0';
state := 0;
t5bits_1 <= "00000";
ELSIF clk='1' AND clk'EVENT THEN
CASE state IS
WHEN 0 => state := state + 1;
M <= multiplicand;
Q <= multiplier;
Q2 <= multiplier;
t5bits_1 <= "00000";
C <= '0';
A <= "0000";
valid_out <= '0';
count := 4;
WHEN 1 =>
IF Q(0)='1' THEN
state := 2;

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t5bits_1 <= ('0' & A)+('0' & M);


ELSE
state := 3;
END IF;
WHEN 2 => state := 3;
C <= t5bits_1(4);
A <= t5bits_1(3 DOWNTO 0);
WHEN 3 => state := state + 1;
FOR i IN 0 to 2 LOOP
Q(i) <= Q(i+1);
END LOOP;
Q(3) <= A(0);
FOR i IN 0 to 2 LOOP
A(i) <= A(i+1);
END LOOP;
A(3) <= C;
C <= '0';
count := count - 1;
WHEN 4 =>
IF count=0 THEN
state := state + 1;
valid_out <= '1';
ELSE
state := 1;
END IF;
WHEN 5 =>
IF(M=multiplicand) THEN
IF(Q2=multiplier) THEN
state := 5;
valid_out <= '1';
ELSE
state := 0;
valid_out <= '0';
END IF;
ELSE
state := 0;
valid_out <= '0';
END IF;
WHEN OTHERS => state := 0;
END CASE;
END IF;
END PROCESS;

Product <= A & Q;

END arch_Booth_Multiplier4bit;

4-bit Multiplier Testbench


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY Booth_Multiplier4bit_test IS
END Booth_Multiplier4bit_test;

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ARCHITECTURE arch_Booth_Multiplier4bit_test OF
Booth_Multiplier4bit_test IS

COMPONENT Booth_Multiplier4bit
PORT ( multiplier : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
multiplicand : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
product : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
valid_out : OUT STD_LOGIC);
END COMPONENT;

SIGNAL multiplier, multiplicand : STD_LOGIC_VECTOR(3 DOWNTO 0) :=


"0000";
SIGNAL clk, rst : STD_LOGIC := '0';
SIGNAL product : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL valid_out : STD_LOGIC;

BEGIN

input_1: PROCESS
BEGIN
-- WAIT FOR 600 ns;
WAIT UNTIL valid_out='1';
multiplier <= multiplier + '1'; -- std_logic_unsigned.all is
required
END PROCESS input_1;

input_2: PROCESS
BEGIN
-- WAIT FOR 600 ns;
WAIT UNTIL valid_out='1';
multiplicand <= multiplicand + "0010"; -- std_logic_unsigned.all
is required
END PROCESS input_2;

clk_gen: PROCESS
BEGIN
LOOP
WAIT FOR 20 ns;
clk <= NOT clk;
END LOOP;
END PROCESS clk_gen;

rst_gen: PROCESS
BEGIN
rst <= '1';
WAIT FOR 30 ns;
rst <= '0';
WAIT;
END PROCESS rst_gen;

Booth_Mul1: Booth_Multiplier4bit PORT MAP (multiplier, multiplicand,


clk, rst, product, valid_out);

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END arch_Booth_Multiplier4bit_test;

Pin Configuration (UCF)


NET "multiplier<0>" LOC = "P25";
NET "multiplier<1>" LOC = "P26";
NET "multiplier<2>" LOC = "P27";
NET "multiplier<3>" LOC = "P28";
NET "multiplicand<0>" LOC = "P19";
NET "multiplicand<1>" LOC = "P20";
NET "multiplicand<2>" LOC = "P23";
NET "multiplicand<3>" LOC = "P24";
NET "product<0>" LOC = "P60";
NET "product<1>" LOC = "P61";
NET "product<2>" LOC = "P62";
NET "product<3>" LOC = "P65";
NET "product<4>" LOC = "P66";
NET "product<5>" LOC = "P67";
NET "product<6>" LOC = "P68";
NET "product<7>" LOC = "P69";
NET "clk" LOC = "P13";
NET "rst" LOC = "P59";
NET "valid_out" LOC = "P51";

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8-bit Binary to BCD Converter


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY binary_BCD_converter IS
PORT(binary: IN std_logic_vector(7 DOWNTO 0);
unit_out,ten_out: OUT std_logic_vector(3 DOWNTO 0);
hundred_out: OUT std_logic_vector(1 DOWNTO 0));
END binary_BCD_converter;

ARCHITECTURE arch_binary_BCD_converter OF binary_BCD_converter IS

COMPONENT add3
PORT(binary_in: IN std_logic_vector(3 DOWNTO 0);
BCD_out: OUT std_logic_vector(3 DOWNTO 0));
END COMPONENT;

SIGNAL add_in1,add_in2,add_in3,add_in4,add_in5,
add_in6,add_in7:std_logic_vector(3 DOWNTO 0);

SIGNAL add_out1,add_out2,add_out3,add_out4,add_out5,
add_out6,add_out7:std_logic_vector(3 DOWNTO 0);

BEGIN

c1: add3 PORT MAP (add_in1,add_out1);


c2: add3 PORT MAP (add_in2,add_out2);
c3: add3 PORT MAP (add_in3,add_out3);
c4: add3 PORT MAP (add_in4,add_out4);
c5: add3 PORT MAP (add_in5,add_out5);
c6: add3 PORT MAP (add_in6,add_out6);
c7: add3 PORT MAP (add_in7,add_out7);

add_in1 <= '0' & binary(7 DOWNTO 5);


add_in2 <= add_out1(2 DOWNTO 0) & binary(4);
add_in3 <= add_out2(2 DOWNTO 0) & binary(3);
add_in4 <= add_out3(2 DOWNTO 0) & binary(2);
add_in5 <= add_out4(2 DOWNTO 0) & binary(1);
add_in6 <= '0' & add_out1(3) & add_out2(3) & add_out3(3);
add_in7 <= add_out6(2 DOWNTO 0) & add_out4(3);

unit_out <= add_out5(2 DOWNTO 0) & binary(0);


ten_out <= add_out7(2 DOWNTO 0) & add_out5(3);
hundred_out <= add_out6(3) & add_out7(3);

END arch_binary_BCD_converter;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY add3 IS
PORT(binary_in: IN std_logic_vector(3 DOWNTO 0);

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BCD_out: OUT std_logic_vector(3 DOWNTO 0));


END add3;

ARCHITECTURE arch_add3 OF add3 IS

BEGIN
PROCESS(binary_in)
BEGIN
CASE binary_in IS
WHEN "0000" => BCD_out <= "0000";
WHEN "0001" => BCD_out <= "0001";
WHEN "0010" => BCD_out <= "0010";
WHEN "0011" => BCD_out <= "0011";
WHEN "0100" => BCD_out <= "0100";
WHEN "0101" => BCD_out <= "1000";
WHEN "0110" => BCD_out <= "1001";
WHEN "0111" => BCD_out <= "1010";
WHEN "1000" => BCD_out <= "1011";
WHEN "1001" => BCD_out <= "1100";
WHEN OTHERS => BCD_out <= "0000";
END CASE;
END PROCESS;

END arch_add3;

8-bit Binary to BCD Converter


Testbench
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY binary_BCD_converter_test IS
END binary_BCD_converter_test;

ARCHITECTURE arch_binary_BCD_converter_test OF
binary_BCD_converter_test IS

COMPONENT binary_BCD_converter
PORT(binary: IN std_logic_vector(7 DOWNTO 0);
unit_out,ten_out: OUT std_logic_vector(3 DOWNTO 0);
hundred_out: OUT std_logic_vector(1 DOWNTO 0));
END COMPONENT;

SIGNAL binary : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS=>'0');


SIGNAL unit_out, ten_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL hundred_out : STD_LOGIC_VECTOR(1 DOWNTO 0);

BEGIN

input: PROCESS
BEGIN
WAIT FOR 20 ns;
binary <= binary + '1'; -- std_logic_unsigned.all is required
END PROCESS input;

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bin_BCD1: binary_BCD_converter PORT MAP (binary, unit_out, ten_out,


hundred_out);

END arch_binary_BCD_converter_test;

Pin Configuration (UCF)


NET "binary<0>" LOC = "P19";
NET "binary<1>" LOC = "P20";
NET "binary<2>" LOC = "P23";
NET "binary<3>" LOC = "P24";
NET "binary<4>" LOC = "P25";
NET "binary<5>" LOC = "P26";
NET "binary<6>" LOC = "P27";
NET "binary<7>" LOC = "P28";
NET "unit_out<0>" LOC = "P60";
NET "unit_out<1>" LOC = "P61";
NET "unit_out<2>" LOC = "P62";
NET "unit_out<3>" LOC = "P65";
NET "ten_out<0>" LOC = "P66";
NET "ten_out<1>" LOC = "P67";
NET "ten_out<2>" LOC = "P68";
NET "ten_out<3>" LOC = "P69";
NET "hundred_out<0>" LOC = "P50";
NET "hundred_out<1>" LOC = "P46";

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4-bit Counter with 7-Segment


In this lab, you will combine the 4-bit counter with the 7-segment decoder so that we can
see the result on 7-segment display.

ENTITY counter_4bit_7_segment IS
PORT (clk, rst : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END counter_4bit_7_segment;

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LAB # 05
In this lab, we will design a circuit of Ripple Carry Adder and Multiplier. At one time
only one operation can be performed and user can select the desired operation. The
output of the addition will be displayed on 7-segment display in hexadecimal format
(carry out will be discarded). The output of the multiplier will be displayed on 7-segment
in BCD format.

The block diagram of the circuit, and pin configuration is given, and you will write the
VHDL code yourself using whatever style you like. Some of the blocks in this design
have been implemented in previous labs, so it would be wise to use those blocks
wherever possible.

Note: To make the debugging easier, use the same wire names as given in block
diagram.

After completing this lab, you will be able to:

• Write the synthesizable VHDL code for any given block diagram.

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RCA_Multiplier_Combined

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RCA_Multiplier_Combined Testbench
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY RCA_Multiplier_combined_test IS
END RCA_Multiplier_combined_test;

ARCHITECTURE arch_RCA_Multiplier_combined_test OF
RCA_Multiplier_combined_test IS

COMPONENT RCA_Multiplier_combined
PORT (clk, rst : STD_LOGIC;
a,b : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
sel : STD_LOGIC;
seven_seg_out : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
seven_seg_Anode : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;

SIGNAL clk, rst : STD_LOGIC := '0';


SIGNAL a,b : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS=>'0');
SIGNAL sel : STD_LOGIC;
SIGNAL seven_seg_out : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL seven_seg_Anode : STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

clk_gen: PROCESS
BEGIN
WAIT FOR 20 ns;
clk <= NOT clk;
END PROCESS clk_gen;

rst_gen: PROCESS
BEGIN
rst <= '1';
WAIT FOR 30 ns;
rst <= '0';
WAIT;
END PROCESS rst_gen;

input_a: PROCESS
BEGIN
WAIT FOR 400 ns;
a <= a + '1'; -- std_logic_unsigned.all is required
END PROCESS input_a;

input_b: PROCESS
BEGIN
WAIT FOR 400 ns;
b <= b + "0010"; -- std_logic_unsigned.all is required
END PROCESS input_b;

sel_signal: PROCESS

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BEGIN
sel <= '0';
WAIT FOR 2000 ns;
sel <= '1';
WAIT FOR 2000 ns;
END PROCESS sel_signal;

RCA_mult: RCA_Multiplier_combined PORT MAP(clk, rst, a, b, sel,


seven_seg_out, seven_seg_Anode);

END arch_RCA_Multiplier_combined_test;

Pin Configuration (UCF)


NET "a<0>" LOC = "P25";
NET "a<1>" LOC = "P26";
NET "a<2>" LOC = "P27";
NET "a<3>" LOC = "P28";
NET "b<0>" LOC = "P19";
NET "b<1>" LOC = "P20";
NET "b<2>" LOC = "P23";
NET "b<3>" LOC = "P24";
NET "clk" LOC = "P13";
NET "rst" LOC = "P59";
NET "sel" LOC = "P58";
NET "seven_seg_Anode<0>" LOC = "P44";
NET "seven_seg_Anode<1>" LOC = "P40";
NET "seven_seg_Anode<2>" LOC = "P39";
NET "seven_seg_Anode<3>" LOC = "P38";
NET "seven_seg_out<0>" LOC = "P45";
NET "seven_seg_out<1>" LOC = "P46";
NET "seven_seg_out<2>" LOC = "P47";
NET "seven_seg_out<3>" LOC = "P48";
NET "seven_seg_out<4>" LOC = "P49";
NET "seven_seg_out<5>" LOC = "P50";
NET "seven_seg_out<6>" LOC = "P51";

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Digilab XLA Reference Manual


Revision: April 15, 2002

Overview
Power 25MHz Prototype/expansion
The Digilab XLA circuit board provides an 5VDC SPROM
jack CLK connector
regulator
ideal platform for experimenting with digital 5-9VDC

circuit designs and modern CAD tools. The Serial


Serial Port

converter
board features a Xilinx Spartan XCS10 FPGA,
RS-232
Port BNC
a large collection of I/O devices and ports, and
1/8"
an integral breadboard, so a wide array of audio
circuits can be implemented without the need EPP or SPP
parallel port Spartan(XL)
Parallel Port

for any additional hardware. XLA board PS2


XCS10 port
features include: JTAG
Buffer

Port
VGA
port
• A Xilinx XCS10 or XCS10XL FPGA;
• On-board 1.5A regulator (5.0V or 3.3V); Port/prog
• A socketed 25MHz oscillator; switch
• An EPP-capable parallel port for serial-slave
FPGA programming and user data transfers; Integral 630
• tie- point
Eight LEDs, eight slide switches, four breadboard 4 7-seg. 8 LEDs 8 switches 4 buttons
pushbuttons, and a four-digit seven-segment displays
display provide circuit I/O’s;
• PS/2 mouse/keyboard, serial, and 3-bit color XLA circuit board block diagram
VGA ports;
Spartan XL devices can be accommodated (the
• An integral 630 tie-point breadboard;
board also supports the XC4010 5V FPGA). The
• A large prototyping/expansion connector
XLA board works seamlessly with the Xilinx
provides easy access to FPGA and I/O CAD tools, including the Foundation Student
signals;
Edition tool (but not WebPack at this time). The
• BNC and audio connectors for support of large integral breadboard allows accessory
bread-boarding applications; circuits (like A/D and D/A converters) to be
• An SPROM socket for non-volatile easy constructed. The XLA board ships with a
applications. power supply and programming cable, so
designs can be implemented immediately
A simple resistor change generates a 5V or without the need for any additional supplies.
3.3V power supply, so both Spartan and

Copyright Digilent, Inc. All rights reserved Document: 502-002


Copyright Digilent, Inc. Digilab XLA Reference Manual 2/12

Functional Description

The XLA board provides a self-contained digital circuit design environment that offers an ideal
platform for experimenting with digital circuit designs and/or modern CAD tools. A large-capacity
gate array, provide allow a wide array of designs to be implemented without the need for any
additional hardware.

Signals
Signal Definition Connections
The Digilab board has been A1 - A4 Seven-segment Anodes SSDs, FPGA, J1
designed to allow rapid circuit CA - CG Seven-segment Cathodes SSDs, FPGA, J1
construction and convenient DP Seven-segment Decimal Point SSDs, J1
test lead attachment. Most BTN1 - 4 Push Button connections Buttons, FPGA, J1
signals are routed to the SW1 - SW8 Slide switch connections Switches, FPGA, J1
prototyping connector (J1), to LD1 - LD8 LED connections LEDs, FPGA, J1
the gate array, and to a test LDG Gate connection on 74HC373 74HC373, FPGA, J1
lead connector. Depending on ASFT Audio connector shaft Audio connector, J1
function, the signals arise from ATIP Audio connector tip Audio connector, J1
devices or connectors on the CLK1 CLK1 connected to PGCK1 CLK1, FPGA
board, or they drive devices or CLK2 CLK2 connected to PGCK2 CLK2, FPGA, J1
connectors on the board. The O1 - O5 Unassigned FPGA pins FPGA, J1, J2
table defines all Digilab PD0 - PD7 Parallel port data pins J7 (par. port), FPGA, J1, J3
signals and shows all their PWE Parallel port Write Enable (EPP) J7 (par. port), FPGA, J1, J3
connections. PAS Parallel port Address Strobe (EPP) J7 (par. port), FPGA, J1, J3
PDS Parallel port Data Strobe (EPP) J7 (par. port), FPGA, J1, J3
Circuit board PINT Parallel port Interrupt (EPP) J7 (par. port), FPGA, J1, J3
PRS Parallel port Reset (EPP) J7 (par. port), FPGA, J1, J3
The FR-4 fiberglass circuit PWT Parallel port Wait/Busy (EPP) J7 (par. port), FPGA, J3
board uses a 1oz. copper, two BNCS BNC connector shield BNC connector, J1
layer, plated through-hole
BNCP BNC connector center post BNC connector, J1
process with 6mil minimum
R, G, B VGA Red, Green, and Blue signals J6 (vga), FPGA, J2
trace size and .039” through-
HS VGA Horizontal Sync J6 (vga), FPGA, J2
holes. Solder mask is provided
VS VGA Vertical Sync J6 (vga), FPGA, J2
on both sides, a silk-screen is
RXD, TXD RS-232 receive and send signals J4 (serial), FPGA, J2
provided on the component
PS2D, PS2C PS2 port data and clock signals J5 (PS/2), FPGA, J1, J2
side, and all connectors can
accommodate mechanical
stays. Four 6/32”-sized corner holes are provided for stand-offs (to keep the board from contacting the
work surface).
U6
Power Supply Vin LM317T
J8 Power Vout Vdd
The circuits and components R5 R4
connector Adj
C24 240 240
on the Digilab XL board 1.5uF
require a 5VDC or 3.3VDC C23 R6
power supply. The board is 10uF LD9
750
equipped with a LM317T GND

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Copyright Digilent, Inc. Digilab XLA Reference Manual 3/12

adjustable LDO voltage regulator (U6) that can produce either 5V or 3.3V depending on the R6
resistor value (750 ohms for 5V; 390 ohms for 3.3V). The regulator will produce the selected voltage
whenever a 6V-12VDC wall-plug transformer is attached at the power jack J8. Any 6-12VDC wall-
plug transformer can be used, provided it has a coaxial 2.1mm center positive connector. The power
circuit uses several bulk decoupling capacitors (C20, C23, C24) to produce a stable Vdd supply that
typically has less than 50mV of ripple, even under heavy loads. An LED (LD9) in series with a 240-
ohm resistor illuminates whenever power is present. With all IC’s loaded in their sockets, including a
25MHz oscillator, the board consumes between 300 and 400 milliamps (depending on the size of
FPGA-based circuits). Breadboard circuits or connected devices can markedly increase current
consumption. For loads greater than about 500mA or power supply voltages greater than about 10V,
the LM317T can be attached to the metalized pad on the circuit board with a 6/32 nut and screw to
increase its heat-sinking capacity.

Push Buttons

Outputs from the four momentary-contact push Vdd


buttons are normally low, and are driven high only
while the button is actively pressed. The buttons To J1 and
nominally have a worst-case bounce time of about FPGA
RP6
1ms. The buttons drive the FPGA and J1 circuit RP7 4.7KOhm
nodes via a 4.7K resistor. The decoupling resistor is 4.7KOhm
included so that the FPGA can use the button-
connected pins as outputs if needed, without risking GND
damage from the button state.

Slide switches
The eight slide switches can be used to connect either Vdd or Vdd
GND to eight pins on the FPGA as well as to connections on RP4 & 5
4.7 KOhm
J1. The switches exhibit about 2ms of bounce, and no active To J1 and
debouncing circuit is employed. As shown on the right, a 4.7K- FPGA
ohm series resistor is used to provide nominal input protection,
and to allow the switch-connected inputs to the FPGA to be GND
used as outputs if necessary.

LEDs
Vdd
U1
Eight red LEDs are provided R1
74HC373
for circuit outputs. The LED 10K Ohms
LD signals From
cathodes are tied to ground via FPGA and J1 D Q
270-ohm resistors (in resistor LD1- LD8
LDG signal From G
pack RP9). The anodes are FPGA and J1
driven by U1, a 74HC373 RP9
RP8
CMOS D-register with 24mA 10K Ohm 270 Ohm
per pin output current. Inputs to
the 74HC373, each of which
GND GND
have a 10K pull-down resistor

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Copyright Digilent, Inc. Digilab XLA Reference Manual 4/12

(RP8), arise from a common circuit node tied to both the FPGA and connections on J1. Thus, care
should be taken not to drive the LED inputs from both the J1 connector and from the FPGA
simultaneously. A 74HC373 is used so that the LED drive signals can be decoupled from the FPGA,
allowing the LED pins on the FPGA to serve a dual purpose if needed. The 74HC373 gate signal,
which has a 10K pull-up (R1), can be driven from the FPGA or from a connection on J1.

BNC connector

The BNC connector is provided to allow easy


connection to test and measurement equipment. Sheild To BNCP
Both the shield and the center post are connected connection on J1
only to pins on the J1 connector to allow
To BNCS
maximum flexibility. In a typical use, the BNC Post connection on J1
shield will be connected to GND using a jumper
Side view Front view
wire in the J1 connector, and the center post will
be connected to the desired circuit node (again
using a jumper wire).

Audio connector

The two signals on the 1/8" audio connector are


connected to pins on the J1 connector in order to allow
easy connection of audio devices (e.g., speakers or 1/8" Stereo
1/8" Stereo
microphones). Although the audio connector is a audio plug audio jack
asft
stereo connector, both channels have been tied into a
common node. In typical use, the ASFT and ATIP
signals will be connected to appropriate breadboard
circuit nodes with jumper wire. To drive a speaker, both channels connected
these nodes can be tied to a dual-ended amplifier; to to asft signal atip
receive a microphone, they can be tied to a differential
amplifier.

PS2 connector

The pin definitions for the PS2 PS2 Pin Definitions


Pin 1
connector are shown on the right. Pin Function
The clock and data signals (PS2C 2 1 1 Data
and PS2D) are connected to J2 4 3 2 Reserved
6 5
(for easy connection of test and Pin 6 Pin 5 3 GND
measurement equipment), and to 4 Vdd
Bottom-up 5 Clock
the Xilinx FPGA. The PS2
PS2 Connector front view hole pattern 6 Reserved
signals are not routed to J1.

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Copyright Digilent, Inc. Digilab XLA Reference Manual 5/12

Serial Port

Serial port signal definitions and connector and circuit details are shown below. The Digilab serial port
is compatible with RS232 two-wire communication protocols; that is, only the RXD and TXD signals
from the serial port are routed to the FPGA. When using the serial port to communicate with a
computer, a two-wire protocol such as XON/XOFF must be used. Specified RS232 voltages are +12V
to +3V for a logic “0” and –12V to –3V for a logic “1” (the "dead area" between -3v and +3v is
designed to absorb line noise). The Digilab board uses a MAX202 RS232 voltage converter to convert
these signals to 5VDC for a logic “1” and GND for a logic “0”.

The two devices connected to either end of a serial cable are known as the Data Terminal Equipment
(DTE) and the Data Communications Equipment (DCE). The DCE was originally conceived to be a
modem, but now many devices connect to a computer as a DCE. A DTE device uses a male DB-9
connector, and a DCE device uses a female DB-9 connector. The DTE is considered the source of data,
and the DCE the peripheral device. Two DTE devices can be connected via a serial cable only if lines
two and three are crossed – this is known as a null modem cable. A DTE and DCE device can be
connected with a straight-through cable. The XLA board is configured as a DCE device.

Serial Port Pin Definitions


Pin # Name Function Direction Connected
Pin 5 Pin 1
Pin 9 Pin 1
1 DCD Data carrier detect DCE DTE N
2 RXD Received data DCE DTE Y
3 TXD Transmitted data DCE DTE Y
DB9 top-down Pin 9 Pin 6 4 DTR Data terminal ready DCE DTE N
hole pattern 5 SG Signal ground Y
DB9 serial port connector
6 DSR Data set ready DCE DTE N
Front view
7 RTS Request to send DCE DTE N
8 CTS Clear to send DCE DTE N
9 RI Ring Indicator DCE DTE N

1
6
2 RXD_12V 12 13 To RXD on FPGA and J6
7 RTS 10 14 To TXD on FPGA and J6
3 TXD_12V 11 7
8 CTS 9 8
4 RTS and CTS not routed from
MAX202
9
5

GND Maxim MAX202


DB9 Connector RS232 VoltageConverter

VGA connector

The five standard VGA signals (Red, Green, Blue, Horizontal Sync, and Vertical Sync) are routed
from the FPGA to the VGA connector and to the J2 header (the J6 header allows for easy connection
of test and measurement equipment). Standard VGA R, G, and B signals are terminated with a 75-ohm

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Copyright Digilent, Inc. Digilab XLA Reference Manual 6/12

pull-down resistor. As shown below, a 470-ohm series resistor drives the R, G, and B signals, and the
resistor-divider that is formed ensures the video signals never exceed the VGA-specified maximum of
0.7VDC. Note that each color is either on or off, which allows for eight different colors.

Pin 5 Pin 1 Pin 1


Pin 10 Pin 6
Pin 15
Pin 15 Pin 11

DB15 VGA connector DB15 through-hole pattern as


Front view seen from the top

470 Ohm
1 RP11
To R on FPGA and J2
6
11 470 Ohm
2 RP11
To G on FPGA and J2
7
12 470 Ohm
3 RP11
To B on FPGA and J2
8
13 To HS on FPGA and J2
4
9
14 To VS on FPGA and J2
5
10
15
GND
DB15
Connector

Parallel Port

All parallel port signals except pin 15 (SPP


Pin EPP signal EPP Function
Error), pin 12 (SPP paper out), and pin 13
(SPP Select) are routed. Although the signal 1 Write Enable (O) Low for read, High for write
names reflect the Enhanced Parallel Port 2-9 Data bus (B) Bidirectional data lines
(EPP) mode, any protocol can be used for 10 Interrupt (I) Interrupt/acknowledge input
data transfer. Note that the full ECP 11 Wait (I) Bus handshake; low to ack
protocol (including pin15) can be used if 12 Spare NOT CONNECTED
DB25 pin 15 is connected to one of the 13 Spare NOT CONNECTED
“open” signals on the FPGA (O1 – O5). All 14 Data Strobe (O) Low when data valid
signals are also available at the J3 header for 15 Spare NOT CONNECTED
easy test and measurement equipment 16 Reset (O) Low to reset
connection. All signals use 220 ohm series 17 Address strobe (O) Low when address valid
resistors to dampen possible line reflections 18-25 GND System ground
and decouple the 5VDC port lines from the

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Copyright Digilent, Inc. Digilab XLA Reference Manual 7/12

possible 3.3VDC Digilab Vdd voltage. The Xilinx programming circuit, discussed in the following
section, also uses the parallel port connector. Refer to that discussion for more information regarding
the parallel port circuit.

Pin 13 Pin 1
Pin 1

Pin 25 Pin 14 Pin 25

DB25 parallel port connector


Front view

Xilinx Programming Circuit

The programming circuit (below) has been designed to accommodate a standard parallel cable and the
Xilinx xchecker configuration protocol. The parallel cable will be auto-detected from with the Xilinx
project manager, so that no external programming software is required. If the cable is not automatically
detected the first time the Xilinx software is run with the board, it may be necessary to manually set the
cable type in the Xilinx Design Manager “communications” pull-down menu.

The xchecker interface uses the DB25 connector and a standard parallel cable to connect to the FPGA
programming port (readback functions are not supported). 4.7K pull-ups are provided on the PROG,
INIT, and DONE signals. The parallel port interface serves both programming and functional needs. A
circuit has been designed that allows the port to be manually switched from programming mode to port
mode. Slide-switch SW9, located near the parallel port connector, can be placed in the “PROG” mode
for programming and “PORT” mode to use the parallel port as a parallel port. Note that to program the
FPGA and then use the parallel port, care must be taken in the application circuit design to not drive
the port data signals until after the switch is moved to the “PORT” position. See the parallel port demo
project at the Digilent website for more details.

The Digilab board can also accommodate a Xilinx SPROM in the 8-pin socket labeled ROM. To
program from the ROM, load the ROM into the socket, place SW9 in the “PORT” position, and apply
power to the board.

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Copyright Digilent, Inc. Digilab XLA Reference Manual 8/12

Vdd

1 Write Enable (PWE)


14 Data Strobe (PDS) DONE
2 Data 0 (PD0)
15 CCLK
3 Data 1 (PD1) Xilinx
16 Reset (PRST) Spartan DATA IN
4 Data 2 (PD2)
Address Strobe (PAS) XCS05, PROG
17
5 Data 3 (PD3) XCS10,
18 XCS05XL
6 Data 4 (PD4)
XCS10XL,
19
7 Data 5 (PD5) or
20 XC4005,
8 Data 6 (PD6)
XC4010
21
9 Data 7 (PD7) FPGA
22
10 Interrupt (PINT)
23
11 Wait (PWT)
24
12
25
13 VDD SENSE
CABLE DET1
CABLE DET2
DONE1
DB25
connector
GND

PORT
Programming
Vdd "decoupling"
Circuit

Program enable
GND switch (SW9) GND

PROG

Clocks and Resets

Two half-size (i.e., 8-pin DIP) sockets designated CLK1 and CLK2 have been provided near the FPGA
for system clocks. Two clocks have been provided to accommodate peripherals that demand particular
clocks (e.g., the VGA and serial devices), while still allowing a general system clock. CLK1, attached
to the Spartan PGCK1 input, is considered the primary clock (pin 13), and CLK2 has been routed to
the PGCK2 input (pin 35). No special system reset circuits have been provided – typically, one of the
buttons is used as a functional system reset.

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Copyright Digilent, Inc. Digilab XLA Reference Manual 9/12

Data access connectors (J1, J2, J3)

J1 is a 72-pin socket connector that allows easy access to all Digilab signals for breadboarding
purposes. All J1 pin definitions are provided in silk-screen labels immediately adjacent to the
connector. In its intended use, individual wire-jumpers can be inserted into socket pins on J1 and into
the breadboard area, thereby connecting breadboard circuit devices to the Digilab circuits. Note that J1
has seven pins providing GND connections and seven providing Vdd connections – these provide
breadboard circuit with easy access to Vdd and GND.

J2 and J3 are single-row header connectors intended to allow easy connection of test and measurement
equipment. Both J2 and J3 have GND pins that can serve as references for test and measurement
equipment. All pins definitions are provided in silk-screen labels immediately adjacent to the
connectors.

Schematic representations of the J1, J2, and J3 header connectors follow. Refer to the table of signal
definitions provided earlier in this section.

VDD VDD
GND GND
DP SW1
CA SW2
CB SW3
CC SW4
CD SW5
CE SW6
CF SW7
CG SW8
A1 LD1
A2 LD2
A3 LD3
A4 LD4
RXD LD5
TXD LD6
O4 LD7
O5 LD8
CLK2 LDG
BTN3 BTN1
BTN4 BTN2
VDD VDD GND PWE
GND GND O1 PD0
O3 O2 O2 PD1
PINT O1 O3 PD2
PAS PD0 O4 PD3
PDS PD1 O5 PD4
PWE PD2 R PD5
VDD PD3 G PD6
VDD PD4 B PD7
VDD PD5 HS PAS
GND PD6 VS PINT
GND PD7 RXD PRS
GND GND TXD PWT
BNCS ASFT PS2C PDS
BNCP ATIP PS2D GND

J1 J2 J3
Breadboarding Test lead Test lead
connector connector connector

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Copyright Digilent, Inc. Digilab XLA Reference Manual 10/12

FPGA

The Digilab board can accommodate a Xilinx Spartan XCS05, XCS10, XCS05XL, and XCS10XL
FPGA in the 84-pin PLCC socket (the XL parts require a 390 ohm R6 for 3.3V operation). Any of
these SRAM-based FPGA’s may be programmed using a parallel cable or an SPROM (see above). The
parallel cable provides an inexpensive programming solution that is compatible with the Xilinx CAD-
tool cable detection software, so that the FPGA can be programmed without leaving the Xilinx
environment. Refer to the Xilinx Spartan data sheet (http://www.xilinx.com/partinfo/spartan.pdf) for
technical data regarding the FPGA’s.

The table on the right shows all Pin # Function Pin # Function Pin # Function
FPGA pin connections. In this
pin-list, gray boxes indicate 1 GND 29 O1 57 BTN3
dedicated pins that are not 2 Vdd 30 M1_NC 58 BTN2
available for use. Italicized 3 PWE 31 GND 59 BTN1
names indicate dual-purpose
pins; for these pins, the Xilinx 4 PD0 32 MODE 60 LD8
function is shown first followed 5 PD1 33 Vdd 61 LD7
by Digilab’s assignment in 6 PD2 34 M2_NC 62 LD6
parenthesis. 7 PD3 35 CLK2 63 Vdd
8 PD4 36 O2 64 GND
Some FPGA signals, including
9 PAS 37 O3 65 LD5
the LED drive signals and the
unassigned (or open) signals are 10 PRS 38 A4 66 LD4
available on the J1 prototyping 11 Vdd 39 A3 67 LD3
connector. Care should be taken 12 GND 40 A2 68 LD2
to ensure that these signals are 13 CLK1 41 INIT (O4) 69 LD1
not simultaneously driven by
14 PDS 42 Vdd 70 LDG
both the FPGA and by other
drivers. If the FPGA is loaded 15 PWT 43 GND 71 DIN (O5)
in the U3 socket and external 16 PD5 44 A1 72 DOUT (RXD)
circuits must drive these signals, 17 PD7 45 CG 73 CCLK
it would be best to tri-state the 18 PD6 46 CF 74 Vdd
FPGA signals. 19 SW8 47 CE 75 TXD (PINT)
The parallel port connector can 20 SW7 48 CD 76 GND

be used as the FPGA 21 GND 49 CC 77 R


programming port or as a 22 Vdd 50 CB 78 G
parallel port. When 23 SW6 51 CA 79 B
downloading a circuit that 24 SW5 52 GND 80 HS
drives the parallel port data
25 SW4 53 DONE 81 VS
signals, ensure that the signals
are not driven until SW9 has 26 SW3 54 Vdd 82 PS2C
been moved to the PORT 27 SW2 55 PROG 83 PS2D
position. See the parallel port 28 SW1 56 BTN4 84 PINT
demo project on the Digilent
web site.

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Copyright Digilent, Inc. Digilab XLA Reference Manual 11/12

Any CAD-tool-designed circuit that requires fewer than about 5K – 10K gates can be programmed into
the Xilinx FPGA. However, the circuit description must first be transformed into the format required
by the FPGA. This transformation proceeds in several steps, typically beginning with an EDIF, VHDL,
or Verilog file format and ending with a Xilinx “bit” file format. Xilinx (of course) produces a tool that
accomplishes this transformation, which is available in the Xilinx Alliance and Foundation products
(see the Xilinx web site). Although other methods of transforming files may be available, only the
Xilinx solution has been used with the Digilab board. Although the use of the Xilinx tools is beyond
the scope of this document, Xilinx has several good tutorials and helpful documentation available at
their web site.

All signals on the Digilab board that connect the buttons, switches, and LEDs to the J1 connector are
connected to the Xilinx FPGA chip as well. Any circuit implemented in the FPGA can use the buttons
and switches as inputs and the LEDs as outputs. When the Digilab board was fabricated, the buttons,
switches, and LEDs were connected to particular pins on the FPGA (see the table in the previous
section for all FPGA pin definitions). To connect an FPGA-based circuit to these devices, you must
include information in your schematic to “map” circuit inputs and outputs to particular FPGA pins.
Mapping is accomplished by including special components in your schematic called IPADs, IBUFs,
OPADs and OBUFs. These components exist solely to allow you to define physical pin connections,
and so they only need be used in circuit schematics that you intend to download.

Once you have a complete and error-free schematic, you may add IBUFs and IPADs to all inputs, and
OBUFs and OPADs to all outputs. Then, the IPADs and OPADs can be connected to particular pins
by double-clicking the pads and entering the “LOC” parameter and pin number in the appropriate
fields (Name and Description, respectively). In the example circuit below, two switches (SW1 on pin
P28 and SW2 on pin P27) are connected via an AND gate to LED1 (LD1 on pin P69). If this circuit
were downloaded to the FPGA, then LD1 would illuminate whenever SW1 and SW2 were asserted.

For simulation purposes, labes can be added to wires between the IBUF's and the circuit.
Labels are added by doule-clicking the wire and entering the name in the dialog box.

LOC=P28 IPAD
IBUF OPAD LOC=P69
OBUF
LOC=P27 IPAD
AND2
IBUF

"LOC" parameters are added by double-clicking the pad symbol and entering LOC in the Parameters
Name feild and Pnn in the Parameters Description feild, and then pressing Add and OK.

Once all IPADs, IBUFs, OPADs, and OBUFs have been added and edited with pin locations, you can
begin the implementation process by choosing the “Implementation” button from the Xilinx main
screen. In the first dialog box that appears, choose Yes to update the netlist from the schematic editor.
In the second dialog box, make sure the device is S10PC84 and speed is 3 before proceeding; the
version and revision names can use the defaults. Press the Run button, and then wait for the status
window showing Translate, Map, Place & Route, Timing, and Configure processes to terminate.
Before proceeding, make sure that the Digilab board is powered on and connected to the PC via the
parallel cable, and that SW9 is in the PROG position. Then select the Programming option from the
Xilinx main window, and “hardware debugger” from the subsequent dialog box. The cable should be

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Copyright Digilent, Inc. Digilab XLA Reference Manual 12/12

auto-detected; if not, manually choose the parallel cable in the Cable à communications dialog box.
Once the cable has been detected, you can download your design simply by double-clicking on the
appropriate file name in the hardware debugger window.

Two 8-pin DIP clock sockets have been provided for use with the FPGA. Labeled CLK1 and CLK2,
they connect to pin 13 (Xilinx primary clock buffer #1) and pin 35 (Xilinx primary clock buffer #2).
Clock sources up to 80MHz have been successfully used with the board.

The FPGA programming circuit has been designed to accommodate a standard parallel cable or an
SPROM. When programming the FPGA from within the Xilinx CAD tool, the parallel cable will be
automatically detected (so no external programming software is required). If a cable is not
automatically detected the first time the Xilinx software is run with the board, it may be necessary to
manually set the cable type in the Xilinx Design Manager “communications” pull-down menu.

The parallel port interface serves both programming and functional needs. A circuit has been designed
that allows the port to be manually switched from programming mode to port mode. Slide-switch
SW9, located near the parallel port connector, must be placed in the “PROG” mode for programming
from a host PC and “PORT” mode to use the parallel port as a parallel port or to program from an
onboard ROM at power-up. Note that to program the FPGA and then use the parallel port, care must be
taken in the application circuit design to not drive the port data signals until after the switch is moved
to the “PORT” position.

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