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Simulation of a communication system using
Verilog Language
Saran M.L. 1, Dr. T.C. Manjunath 2 and Harsha Karamchandani 3
Abstract—MIMO systems are widely used in baseband communications and also play a major role in 4G technology. FPGA
based implementations of MIMO systems provide an environment for testing and development of MIMO based communication
systems. The proposed FPGA based MIMO system aims at developing a transmitter system consisting of source, encoder,
interleaver, modulator and a receiver system consisting of ML detector, de-interleaver, decoder system and a noisy wireless
channel which is represented by a wired channel to which error bits are given to mimic the noise. The above modules are going
to be developed using Xilinx, simulated and integrated in to the FPGA kit. As a scope of future work the FPGA based MIMO
communication system can also be modified and extended to calculate Bit error rate, SNR etc.
Index Terms—Bit error, SNR, MIMO, Tx, Rx.

—————————— u ——————————



he paper is organized as follows…. A brief introduction about the related work is presented in the introductory section. Lot of works done in the relevant
field by various researchers is shown in the form of literature survey in the section 2. The objective of the paper is
presented in the section 3 followed by the basics of a
MIMO communication system in section 4. Section 5 presents the overview of the block diagram of a communication system followed by the concepts of spatial multiplexing in section 6. Spatial diversity is discussed in section 7
followed by the applications & use of smart antennas in
section 8. The section 9 depicts the description of a 2×2
MIMO Systems followed by the applications of MIMO
system in section 10. The drawbacks of MIMO system is
discussed in section 11 followed by the proposed work in
section 12. The transmitter design is explained in section
14 followed by the convolution encoder, puncturing, interleaver in section 15, 16 & 17 respectively. QAM Modulation is explained in section 18 followed by the receiver,
depuncuring, deinterleaver in section 19, 20 & 21 respectively. This is followed by the implementation requirements such the hardware & software in section 25. The
paper is concluded with the conclusions in section 34 followed by the references.
Multiple Input Multiple Output (MIMO) Communication System is a new and emerging technology and is expected to play a very important role in 4G wireless systems. FPGA prototyping of MIMO provides an accelerated and repeatable test environment in a laboratory setting
[1]. MIMO systems have evolved rapidly as a generic

technology of communication in 4G wireless systems [2].
MIMO technology makes use of multiple antennas both
at the transmitter section and at the receiver section to
make excellent utilization of the available bandwidth and
to reduce the effects of fading and signal loss. This technique also helps to increase the number of bits transmitted i.e. bitrate. Most recently MIMO systems are also used
in wired power line communications for 3-wire installations.
The prototyping of MIMO systems by using FPGA’s or
ASIC’s provides an alternative testing environment for
MIMO systems [3] as the practical realization and testing
of MIMO technology is complex and costly. MIMOOFDM is used in LTE [4]. Field Programmable Gate Arrays (FPGA) are integrated circuits which can be configured by the user or developer by using any hardware
description languages (HDL) such as VHDL or Verilog.
FPGA’s provide a hardware testbed using which the testing and evaluation of many logic networks or circuits or
systems can be done [1, 3]. FPGA’s consists of large number of logic gates and memory blocks (RAM blocks) to
implement complex digital computations [1].
An important challenge for the MIMO technology
would be the design of the transmitter and receiver sections which involves complex algorithms at both sections
[5, 7]. The design and testing part can be simplified by
designing the circuits using hardware description languages (HDL) and Integrated Software Environment (ISE)
which provides accurate simulations of the design. In
order to provide a hardware testbed for the MIMO systems, the designs can be synthesized into FPGA’s. This
type of prototyping of the MIMO system will provide an
• F.A. Mr. Saran ML is with the ECE Dept. of HKBKCE, B’lore & is a PG
excellent testbed under which testing of MIMO can be
done and also important parameters such as delay in
• S.B. Dr. T.C.Manjunath is the Principal of HKBK College of Engg, Bangalore, Karnataka, India & is a Ph.D. from IIT Bombay and a Sr. IEEE Mem- communication, bit error rate, SNR etc., can be determined [2].
• T.C. Mrs. Harsha Karamchandani is a Asst. Prof. in ECE Dept. of
Thus this type of prototyping of MIMO on an FPGA is
HKBKCE & is a Ph.D. research scholar.
also a convenient method to check the suitability of alternate algorithms and evaluating hardware tradeoff’s. This


prototyping provides verification of physical layer design
ideas and makes the designing more economical [6].
FPGA’s can also be used to implement a communication
system directly as the complexity of baseband communications are high and there is always a need to do reprogramming due to changes in evolving standards [3].

FPGA based prototyping of MIMO systems provide
excellent testbed for testing and evaluation of transmitter
and receiver algorithms. Research in the field of MIMO
and also on prototyping of MIMO on FPGA’s are being
carried out from many years. A brief survey of some of
the important literatures in this field has been presented
in the subsequent section [4].

2.1 Reference Paper 1
Amirhossein Alimohammad and Saeed Fouladi Fard,
“FPGA-Based Bit Error Rate Performance Measurement
of Wireless Systems”,IEEE Transactions On Very Large
Integration (VLSI) systems, ISSN No: 10638210,volume 22, Issue: July 2014, Pages:1583-1592,
Publication: 21 August 2013. In this paper the development
and testing of an FPGA based bit error rate tester for digital baseband communication systems have been developed. The bit error rate tester is developed for both multiple input multiple output (MIMO) and single input and
single out put (SISO) digital communication systems. The
paper demonstrates the techniques to develop a complete
transmitter and receiver section for a 2×2 MIMO and SISO system. The transmitter system uses Golay coding
technique for channel encoding, followed by a pseudorandom interleaver section and a 16-QAM modulation
technique. The receiver section consists of ML detector,
pseudorandom de-interleaver and decoder. The paper
also discusses the issues of noisy channels and ways of
data reception through noisy channels [5].
2.2 Reference Paper 2
Numan, M.W, Islam, M.T., Misran.N., “An efficient
FPGA-based hardware implementation of MIMO wireless
systems” Communication Systems Networks and Digital
Signal Processing conference, ISBN: 978-1-4244-8858-2,
pages: 152-156 Conference date: 21-23 July 2010. This paper presents an efficient hardware realization of a 2×2
MIMO system which is designed and implemented on a
Xilinx Virtex -4 XC4VLX60 field programmable gate array
(FPGA). In this paper the design of MIMO involves a
transmitter section consisting of Alamouti encoding and
Inphase –Quadrature (I-Q) modulation schemes. The paper discusses the use of a new and completely different
decoding technique for the MIMO system. The paper discusses the use of Matlab and VHDL for the development
of the system where both matlab and VHDL simulations
are done and both are compared to check for the similarities. The synthesis is done using VHDL [6].
2.3 Reference Paper 3
A. Alimohammad, S. F. Fard, and B. F. Cockburn,

“FPGA-accelerated baseband design and verification of
broadband MIMO wireless systems,” in Proc. IEEE 1st
Int. Conf. Adv. Syst. Testing Validation, Sep. 2009, pp.
135–140. This paper discusses the prototyping of the
physical layer of a 2×2 MIMO system on a Xilinx Virtex–E
XCV2000E FPGA. The paper discusses the complete implementation of the baseband layer of a 2×2 MIMO with
the transmitter section consisting of channel coding, interleaving and modulation. The receiver part consisting of
ML detector, De-interleaving and channel decoding are
also discussed. The paper finally discusses the design of a
Bit error rate tester for the MIMO by comparing the received bits with a copy of the transmitted bits from the
source [7].

2.4 Reference Paper 4
Yu Heejung, Kyon Ghee song, Kwhanghuyn Ryn “Design and FPGA implementation of MIMO-OFDM based
WLAN system” Vehicular technology conference VTC2006 spring IEEE 63, volume 3, pages 1333-1338, publication year: 2006. This paper discusses the design of a
transmission architecture based on dual band and MIMOOFDM schemes and media access control (MAC) layer
using the enhanced distributed channel access (EDCA)
including a block acknowledgement method (ACK). The
complete system is synthesized in an FPGA and verified.
This paper discusses the development of a 2×2 MIMO
system with convolution coding at the transmitter and
Viterbi decoding technique at the receiver [8].
2.5 Reference Paper 5
Paulraj.A.J, Gore.D.A, Nabar.R.U, Bolcskei.H, “An
overview of MIMO communications-a key to gigabit
wireless”, Proceedings of the IEEE, ISSN:0018-9219, volume:92, pages: 198-218,publication:08 November 2004. In
this paper the methodology of MIMO is discussed in detail, the advantages, disadvantages of MIMO are briefed.
The paper also demonstrates the use of MIMO in wireless
technology and shows that high data transfer rates in
GB/s can be achieved. The paper proves the high capacity of MIMO system over single antenna systems by applying the Shannon’s channel capacity formula [9].
2.6 Reference Paper 6
Murphy.P, Lou.F, Sabharwal.A, Frantz.J.P , “An FPGA
based rapid prototyping platform for MIMO system”,
Signal Systems and Computer Conference 2004, Record of
the 37 Asilomar conference, volume 1, pages:900-904,
publication: 2003. In this paper the design of an MIMO
testbed in a Virtex-II FPGA is discussed. Rapid prototyping of MIMO transceivers for wideband channel is discussed. The testbed allows for real time operation of
baseband processing and RF up/down conversion. Here
the testbed is designed to allow maximum flexibility for
research and design purposes [10].

The prime objective of the proposed dissertation work
is to realize a (2×2) MIMO system on a Field Programmable Gate Array. The dissertation aims in developing an


efficient software simulation of transceiver system and a
noisy channel. The transmitter section would consist of
two transmitters each consisting of individual encoders,
interleavers and modulators. The receiver section will
consist of two individual receivers each having individual
detectors, demodulators and decoders. After the simulation, the MIMO system is implemented on an FPGA
where input in the form of binary values would be given
to the system through switches or push buttons and output will be viewed on the LED display present on the
FPGA kit. The work also aims at evaluating the delay
involved in the communication and also the number of
bits involved during the delay time [12].

with many multipath transmissions. The receiver will
receive the signal and it decodes the signal accordingly,
i.e, the first receive antenna will receive multiple signals
through the multipath but it must detect only the signal
sent from first transmitter, the same applies to another
receivers [15].

5.1 Features of MIMO
Some   of   the   important   features   of   the   MIMO   are   listed  
below  and  it  is  these  features  that  enable  the  MIMO  with  
excellent  spectral  efficiency  and  higher  bit  rates  [16].  

Multiple-input multiple-output (MIMO), is a radio frequency wireless communication technology that uses
multiple antennas at the transmitter and receiver, is being
used in many of the new and upcoming wireless techniques such as LTE, HSPA+ etc. MIMO is used in these
technologies as this technique can provide excellent spectral efficiency and an improved link capacity over conventional single antenna techniques. MIMO performs
three main functions of spatial multiplexing, spatial diversity and smart antennas. MIMO development began
many years ago. It started with the use of Spatial diversity of antennas in 1990’s and was followed by using spatial
multiplexing also in 1993 as proposed by researchers
Arogyaswami Paulraj and Thomas Kailath. Bell Labs
demonstrated the first laboratory prototype of spatial
multiplexing MIMO in 1998.Recently MIMO techniques
also makes use of smart antenna technology also [13].

The figure below shows general MIMO scenarios with
M transmit antennas and N receiver antennas. The transmitter section and receiver section can be seen along with
a multipath channel [14].

Spatial   multiplexing   is   a   technique   where   different  
transmitters   transmit   different   information   signals  
through  different  antennas.  Thus  when  multiple  antennas  
are  used  at  the  transmitting  side,  the  bit  rate  is  increased  
with   an   order   equal   to   the   number   of   transmit   antennas  
over   a   single   antenna   system.   This   increases   the   spectral  
efficiency   as   the   multiple   transmissions   happen   over   a  
bandwidth   that   was   dedicated   for   a   single   antenna  
transceiver  system.  Thus  higher  bit  rate  communication  is  
guaranteed  by  spatial  multiplexing  of  MIMO  [17].    

Space  diversity  or  antenna  diversity  is  the  use  of  multiple  
spatially   separated   antennas   to   send   and   receive  
redundant   information   so   that   the   fading   effects   of  
channel   can   be   mitigated.   MIMO   can   achieve   exactly   the  
same   by   transmitting   redundant   data   through   different  
antennas  and  receiving  the  same  across  the  receivers  thus  
reducing   the   error   rates   of   the   system   as   well   as   solving  
the  problem  of  fading  in  a  practical  wireless  environment  

In   addition   to   the   above   mentioned   properties   MIMO  
systems   can   make   use   of   smart   antennas   with   beam  
forming   techniques   to   improve   the   signal   to   noise   ratios  
of   the   communication   systems.   By   careful   use   of   smart  
antenna   technology   the   co   channel   effects   can   also   be  
mitigated  [19].  
Figure 1: General Outline of MIMO system

As shown in the figure 1 an MIMO system can have M
transmit and N receive antennas where the N transmitting antennas might send same signal or different signal
to the receiver. Generally N and M are equal and sometimes different. The channel is generally wireless. As can
be seen from the figure there are direct path transmission
existing between the transmitters and receivers along

The   figure   shows   a   2×2   MIMO   communication   system  
which  is  a  simplified  version  of  the  generic  system  shown  
in  figure1.  This  system  has  only  two  inputs  and  two  out-­‐‑
put   antennas   .There   is   a   direct   path   and   a   multipath   be-­‐‑
tween  the  transmitters  and  receivers.  This  type  of  system  
is   common   in   some   of   the   wireless   communication   sys-­‐‑


tems.   This   type   of   configuration   is   generally   selected   for  
the   study   of   MIMO   systems   as   the   prototyping   of   these  
systems   are   easier   and   simple.     This   dissertation   work  
also   aims   at   developing   a   prototype   of   a   2×2   MIMO   sys-­‐‑
tem   along   with   its   complete   transmitter   and   receiver  
components.   The   advantage   of   this   system   is   that   it   pro-­‐‑
vides  a  platform  to  evaluate  the  performance  of  an  MIMO  
and  it  can  easily  be  extended  to  a  m×m  system  by  increas-­‐‑
ing  the  transmitters  and  receivers  [20].

shown   in   the   above   figure   the   main   objective   and   inten-­‐‑
tion  of  the  dissertation  work  would  be  a  complete  integra-­‐‑
tion  of  the  2×2    MIMO  system  using  less  number  of  logi-­‐‑
cal   blocks   in   the   FPGA   thus   increasing   its   efficiency   and  
also   reducing   the   delay   time   for   transmission   of   bits   be-­‐‑
tween  the  transmitters  and  the  receivers.  between  with  a  
reduced   delay   between     The   Above   top   level     diagram  
can   be   split   in   to   a   transceiver   level   diagram   that   shows  
the  transmitter  receiver  connections  as  shown  below  [24].  






Figure 2: A 2×2 MIMO communication System representation



Figure 3:Top level view of the integrated 2×2 MIMO communication system










MIMO   is   combined   with   OFDMA   and   is   used   in   IEEE  
802.16e.MIMO-­‐‑OFDM   is   used   in   IEEE   802.11n.   Mobile  
radio  telephone  standards  such  as  3GPP  and  3GPP2  make  
use   of   MIMO.   In   3GPP,   High   Speed   Packet   Access   Plus  
(HSPA+)   and   Long   Term   Evolution   (LTE)   standards   uti-­‐‑
lize   MIMO.   MIMO   technology   is   also   used   in   non-­‐‑
wireless   applications   such   as   home   networking   standard  
ITU-­‐‑T  G.9963.   It   is   a   power   line   communication   system    
which  uses  MIMO  to  transmit  multiple  signals  over  mul-­‐‑
tiple  AC  transmission  wires  [21].  



MIMO  systems  require  multiple  parallel  transmitters  and  
receivers   leading   to   increase   in   hardware   costs.   MIMO  
systems   also   suffers   from   increased   power   usage.   Real  
time   implementations   of   complex   MIMO   systems   are  
challenging  and  time  consuming  [22].    

This   section   will   give   a   detailed   description   of   what   the  
dissertation  work  proposes  and  intents  to  do  starting  with  
a   top   level   conceptual   block   diagram   of   the   completely  
integrated   2×2   MIMO   system   followed   by   a   Transceiver  
level   block   diagram   that   shows   the   transmitters   and   re-­‐‑
ceivers  in  the  system  .  Then  the  transmitters  and  receivers  
are  explained  in  detail  using  individual  block  diagrams  of  
transmitter  and  receiver  [23].    The  above  figure  shows  the  
integrated   top   level   view   of   the   proposed   2×2   MIMO  
communication   system   with   the   basic   input   and   output  
pins.  There  are  two  inputs  Din1  and  Din2  other  than  the  
control  inputs  clock  (Clk)  and  Reset  (Rst)  at  the  input  side  
and  two  outputs  Dout1  and  Dout  2  at  the  output  side.  As  





Figure 4: Generic Transceiver level block diagram of the proposed
2×2 MIMO system

The  proposed  block  diagram  is  explained  as  follows.  The  
block  diagram  of  the  2×2  mimo  system  consisting  of  two  
transmitters   and   two,   receivers   and   a   multipath   channel  
are  shown  in  the  figure.  The  transmitter  section  comprises  
of   a   source   an   encoder   that   performs   encoding   of   the  
source  symbols.  The  encoder  is  followed  by  an  interleaver  
which  is  used  for  error  correction  during  burst  error  sce-­‐‑
narios   in   the   channel.   The   interleaver   is   followed   by   a  
modulator   that   modulates   the   symbols   and   makes   them  
suitable   for   transmission   through   a   noisy   channel.   The  
output  bits  from  the  transmitter  are  added  with  error  bits  
to   corrupt   the   signal   which   normally   happens   in   a   noisy  
channel  [25].      
The   wireless   channel   is   approximated   by   using   a   wired  
channel   to   which   error   bits   are   inserted   that   produces   a  
noise  like  scenario,  thus  mimicking  the  real  world  scenar-­‐‑
io.  Two  2×1  Multiplexers  are  used  at  the  beginning  of  the  


receivers   so   that   the   receivers   can   select   only   the   signal  
associated   for   it   and   reject   the   multipath   signal.   The   re-­‐‑
ceiver   section   consists   of   a   maximum   likelihood   detector  
which   generates   an   optimal   estimate   of   the   transmitted  
symbols.  The  detector  is  followed  by  a  de-­‐‑interleaver  that  
performs   the   inverse   of   interleaver   and   finally   a   decoder  
decodes   the   symbols.   The   decoded   bit   stream   will   repre-­‐‑
sent  the  original  data  transmitted  by  the  transmitter  [26].    














n  =  the  number  of  outputs  or  number  of  code  words  gen-­‐‑
K=  is  the  number  of  input  bits  entering  at  any  time.  
M=  is  the  total  number  of  shift  registers  or  number  of  flip-­‐‑
flops  required  to  realize  the  encoder.  
Encoding   of   convolution   codes   can   be   done   using   differ-­‐‑
ent  approaches  such  as  the  time  domain  approach  where  
the   convolution   codes   are   generated   by   multiplying   the  
data  bits  with  the  impulse  response  bits  which  are  gener-­‐‑
ated   locally.   Alternatively   the   impulse   response   bits   can  
be   selected   in   the   form   of   a   matrix   also.   Convolution  
codes  can  also  be  generated  by  transform  domain  method  
also   where   the   impulse   response   bits   i.e.   the   generator  
bits   are   given   in   the   form   of   polynomials.   Convolutional  
codes   are   used   extensively   in   numerous   applications   in  
order   to   achieve   reliable   data   transfer,   including  digital  
video,   radio,  mobile   communication,   and  satellite   com-­‐‑
munication  [28]  

Figure 5: Detailed Block Diagram of the transmitter section  

The   above   figure   shows   a   detailed   block   diagram   of   the  
transmitters  which  the  dissertation  expects  to  realize.  The  
above   figure   shows   two   transmitter   sections   with   all   the  
individual  blocks  starting  from  the  source  till  the  modula-­‐‑
tor.  The  two  transmitters  are  necessary  for  achieving  two  
inputs   i.e.   multiple   inputs   for   our   2×2   MIMO.       The  
transmitter  section  comprises  of  a  source  an  encoder  that  
performs  encoding  of  the  source  symbols.  The  encoder  is  
followed  by  an  interleaver  which  is  used  for  error  correc-­‐‑
tion  during  burst  error  scenarios  in  the  channel.  The  inter-­‐‑
leaver   is   followed   by   a   modulator   that   modulates   the  
symbols   and   makes   them   suitable   for   transmission  
through   a   noisy   channel.   The   output   bits   from   the   trans-­‐‑
mitter   are   added   with   error   bits   to   corrupt   the   signal  
which   normally   happens   in   a   noisy   channel.   Now   let   us  
consider  the  individual  blocks  in  detail  [26].  

An   encoder   in   a   communication   system   will   generally  
take  the  message  bits  as  the  inputs  and  change  the  input  
bits   by   adding   more   redundant   bits   so   that   error   correc-­‐‑
tion  and  error  detection  can  be  done.  Convolution  encod-­‐‑
er  is  a  forward  error  correction  encoder,  where  the  encod-­‐‑
ed  output  bits  will  not  only  depend  on  the  current  input  
bits  but  also  on  the  preceding  message  bits.  Convolution  
encoders   are   best   known   for   its   error   correcting   proper-­‐‑
ties.   Encoding   of   convolutional   codes   can   be   accom-­‐‑
plished  using  simple  shift  registers.  In  general  a  convolu-­‐‑
tion   encoder   is   represented   using   three   digits   (n,k,m)  
where  [27]  

Puncturing  is  the  process  of  increasing  the  rate  and  reduc-­‐‑
ing   the   redundancy   of   the   coded   bits,   this   is   done   by   re-­‐‑
moving   some   of   the   parity   bits   after   encoding   with   the  
convolutional  encoder.  Puncturing  reduces  the  complexi-­‐‑
ty   of   the   encoder   and   increases   the   flexibility   of   the   sys-­‐‑
tem.  Generally  predefined  codes  are  used  for  puncturing  
at  the  encoder  and  de-­‐‑puncturing  is  done  at  the  decoder.  
Puncturing   is   used   in   Wi-­‐‑Fi,   GPRS   and   EDGE   standards  

Interleaving   is   a   technique   for   making  the   encoding  
schemes  more   robust   to   counter   the   burst   errors.   Inter-­‐‑
leaving  will  perform  the  reordering  of  data  in  such  a  way  
that  consecutive  bytes  of  data  are  distributed  over  a  larger  
sequence  of  data  to  reduce  the  effect  of  burst  errors.  This  
method   thus   equips   the   transmitter   to   correct   errors  
which   can   appear   in   groups,   which   is   generally   not   cor-­‐‑
rectable   by   the   encoders   [30].   Interleaver   will   spread   the  
transmitted   data   over   time   resulting   in   significant   im-­‐‑
provements   in   finding   and   correcting   errors   at   the   error  
correction   decoders.     Interleaver   can   be   implemented   in  
the  form  of  block  interleaver  or  pseudorandom  interleav-­‐‑
er.  The  implementation  of  interleaver  would  require  logic  
blocks   ,control   units,   shift   registers   and   counters   for   its  

Quadrature   amplitude   modulation   (QAM)   is   a   modula-­‐‑


tion  technique  which  can  be  used              for  both  analog  sig-­‐‑
nal   and   digital   bit   streams.   In   this   modulation   technique  
the  two  carrier  waves  used  are  out  of  phase  by  90  degrees  
and   thus   the   name   quadrature.   It   performs   Amplitude  
Shift   Keying(ASK)   for   both   the   carrier   waves   and   sum  
these   waves   thus   the   final   waveform   is   a   combination   of  
phase   shift   keying(PSK)   and   Amplitude   Shift   Key-­‐‑
ing(PSK).QAM   is   used   as   the   modulation   technique   for  
most  of  the  telecommunication  systems.    This  dissertation  
work  aims  in  developing  a  16-­‐‑QAM  for  both  the  transmit-­‐‑
ters.   The   16   QAM   consists   of   a   square   lattice   of   message  
points   where   there   are   four   message   sequences   at   four  
quadrants  of  the  square  lattice.  In  general  a  16  QAM  will  
transmit   16   independent   signals   over   the   same   channel  
bandwidth.  Generally  the  output  of  the  16QAM  will  be  16  
real  bits  and  16  imaginary  bits.  

such  that  the  estimate  is  very  likely  a  replica  of  the  trans-­‐‑
mitted  bits  and  thus  the  name  maximum  likelihood.  

The   modulator   will   perform   the   inverse   operation   of   the  
demodulator   by   removing   the   carrier   bits   which   were  
modulated   by   the   data   bits   and   will   give   an   output   con-­‐‑
sisting  of  only  the  spatially  spread  data  bits  which  are  to  
be  de  interleaved.  

The   de-­‐‑interleaver   will   perform   the   reverse   operation   of  
the  interleaver  .The  de-­‐‑interleaver  can  also  be  realized  by  
using   either   pseudorandom   methods   or   block   de-­‐‑













The   de-­‐‑puncturing   unit   will   perform   the   reverse   opera-­‐‑
tion   of   the   puncturing   and   it   is   generally   used   with   the  
Viterbi  decoder.  




Figure 6: Detailed Block Diagram of the receiver section

The  above  diagram  shows   all   the   blocks   required   for  the  
two   receivers   in   the   2×2   MIMO   communication   system.  
Each   receiver   section   consists   of   a   maximum   likelihood  
detector   which   generates   an   optimal   estimate   of   the  
transmitted   symbols.   The   detector   is   followed   by   a   de-­‐‑
modulator   for   demodulating   and   retrieving   the   original  
data   bits   followed   by   the   de-­‐‑puncturing   unit   whose   out-­‐‑
put   is   fed   to   the   de-­‐‑interleaver   that   performs   the   inverse  
of  interleaver  and  finally  the  Viterbi  decoder  decodes  the  
symbols.  The  decoded  bit  stream  will  represent  the  origi-­‐‑
nal  data  transmitted  by  the  transmitter.  The  final  out  out-­‐‑
put   from   the   receiver   1   and   2   are   Dout   1   and   Dout   2   re-­‐‑
spectively.   In   the   following   sections   the   details   of   indi-­‐‑
vidual  bocks  are  discussed.      

Maximum  Likelihood  (ML)  detector  is  a  scheme  to  detect  
the   received   bits   across   our   noisy   channel.   The   received  
bits  will  consist  of  the  original  data  bit  transmitted  along  
with  the  noisy  components  which  are  added  to  the  signal  
by  our  error  bits  at  the  end  of  the  transmitter  section.  Af-­‐‑
ter   receiving   the   bits   the   ML   detector   will   remove   the  
noise   bits     and   it   will   prepare   an   estimate   of   the   original  
data   bits.   The   estimate   is   prepared   by   the   ML   detector  

The   Viterbi   decoder   uses   the   Viterbi   algorithm   and   it   is  
the   universal   scheme   for   decoding   the   convolutional  
codes.  The  input  to  the  Viterbi  decoder  is  the  coded  bits.  
The  decoder  applies  the  Viterbi  algorithm  which  is  a  max-­‐‑
imum  likelihood  algorithm  which  can  give  optimum  out-­‐‑
puts  especially  where  the  bits  are  corrupted  by  noise.  

25.1    Software  Requirements  
The  following  section  gives  a  brief  description  of  the  vari-­‐‑
ous   software   requirements   such   as   the   editor,   simulator  
and  the  coding  language  used  etc.  
25.2    Verilog  
Verilog   language   is   used   as   the   coding   language   for   the  
dissertation   work.   Verify   Logic   (Verilog)   is   a   Hardware  
Description   Language   a   textual   format   for   describing  
electronic   circuits   and   systems.   Applied   to   electronic   de-­‐‑
sign,   Verilog   is   intended   to   be   used   for   verification  
through   simulation,   for   timing   analysis,   for   test   analysis  
(testability   analysis   and   fault   grading)   and   for   logic   syn-­‐‑
thesis.   The   Verilog   HDL   is   an   IEEE   standard   -­‐‑   number  
1364.   The   first   version   of   the   IEEE   standard   for   Verilog  


was   published   in   1995.   A   revised   version   was   published  
in  2001;  this  is  the  version  used  by  most  Verilog  users.    
The   IEEE   Verilog   standard   document   is   known   as   the  
Language   Reference   Manual,   or   LRM.   This   is   the   com-­‐‑
plete   authoritative   definition   of   the   Verilog   HDL.   A   fur-­‐‑
ther   revision   of   the   Verilog   standard   was   published   in  
2005,   though   it   has   little   extra   compared   to   the   2001  
standard.   System   Verilog   is   a   huge   set   of   extensions   to  
Verilog,   and   was   first   published   as   an   IEEE   standard   in  
2005.  See  the  appropriate  Knowhow  section  for  more  de-­‐‑
tails  about  System  Verilog.  IEEE  Std  1364  also  defines  the  
Programming  Language  Interface,  or  PLI.  This  is  a  collec-­‐‑
tion   of   software   routines   which   permit   a   bidirectional  
interface   between   Verilog   and   other   languages   (usually  
C).   Note   that   VHDL   is   not   an   abbreviation   for   Verilog  
HDL   -­‐‑   Verilog   and   VHDL   are   two   different   HDLs.   They  
have  more  similarities  than  differences,  however.  Verilog  
descriptions   can   span   multiple   levels   of   abstraction   i.e.  
levels  of  detail,  and  can  be  used  for  different  purposes  at  
various  stages  in  the  design  process.  At  the  highest  level,  
Verilog   contains   stochastical   functions   (queues   and   ran-­‐‑
dom   probability   distributions)   to   support   performance  
Verilog  supports  abstract  behavioral  modeling,  so  can  be  
used  to  model  the  functionality  of  a  system  at  a  high  level  
of   abstraction.   This   is   useful   at   the   system   analysis   and  
partitioning   stage.   Verilog   supports   Register   Transfer  
Level  descriptions,  which  are  used  for  the  detailed  design  
of  digital  circuits.  Synthesis  tools  transform  RTL  descrip-­‐‑
tions  to  gate  level.  Verilog  supports  gate  and  switch  level  
descriptions,   used   for   the   verification   of   digital   designs,  
including   gate   and   switch   level   logic   simulation,   static  
and   dynamic   timing   analysis,   testability   analysis   and  
fault  grading.    
Verilog   can   also   be   used   to   describe   simulation   environ-­‐‑
ments;   test   vectors,   expected   results,   results   comparison  
and  analysis.  With  some  tools,  Verilog  can  be  used  to  con-­‐‑
trol   simulation   e.g.   setting   breakpoints,   taking   check-­‐‑
points,   restarting   from   time   0,   and   tracing   waveforms.    
Verilog   is   suitable   for   use   in   the   digital   hardware   design  
process,   from   functional   simulation,   manual   design   and  
logic   synthesis   down   to   gate-­‐‑level   simulation.   Verilog  
tools   provide   an   integrated   design   environment   in   this  
Verilog  is  also  suited  for  specialized  implementation-­‐‑level  
design   verification   tools   such   as   fault   simulation,   switch  
level   simulation   and   worst   case   timing   simulation.   Veri-­‐‑
log   can   be   used   to   simulate   gate   level   fanout   loading   ef-­‐‑
fects  and  routing  delays  through  the  import  of  SDF  files.  

The  RTL  level  of  abstraction  is  used  for  functional  simula-­‐‑
tion  prior  to  synthesis.  The  gate  level  of  abstraction  exists  
post-­‐‑synthesis   but   this   level   of   abstraction   is   not   often  
created  by  the  designer,  it  is  a  level  of  abstraction  adopted  
by   the   EDA   tools   (synthesis   and   timing   analysis,   for   ex-­‐‑
The   diagram   below   summarizes   the   high   level   design  
flow  for  an  ASIC  (i.e.  gate  array,  standard  cell)  or  FPGA.  
In  a  practical  design  situation,  each  step  described  in  the  
following  sections  may  be  split  into  several  smaller  steps,  
and  parts  of  the  design  flow  will  be  iterated  as  errors  are  

Figure 7: Design Flow using Verilog

As   a   first   step,   Verilog   may   be   used   to   model   and   simu-­‐‑
late   aspects   of   the   complete   system   containing   one   or  
more   ASICs   or   FPGAs.   This   may   be   a   fully   functional  
description  of  the  system  allowing  the  specification  to  be  
validated   prior   to   commencing   detailed   design.   Alterna-­‐‑
tively,  this  may  be  a  partial  description  that  abstracts  cer-­‐‑
tain   properties   of   the   system,   such   as   a   performance  
model  to  detect  system  performance  bottle-­‐‑necks.  

Once   the   overall   system   architecture   and   partitioning   is  
stable,   the   detailed   design   of   each   ASIC   or   FPGA   can  
commence.  This  starts  by  capturing  the  design  in  Verilog  
at   the   register   transfer   level,   and   capturing   a   set   of   test  
cases  in  Verilog.  These  two  tasks  are  complementary,  and  
are   sometimes   performed   by   different   design   teams   in  
isolation  to  ensure  that  the  specification  is  correctly  inter-­‐‑
preted.  The  RTL  Verilog  should  be  synthesizable  if  auto-­‐‑
matic  logic  synthesis  is  to  be  used.  Test  case  generation  is  
a   major   task   that   requires   a   disciplined   approach   and  
much  engineering  ingenuity:  the  quality  of  the  final  ASIC  
or  FPGA  depends  on  the  coverage  of  these  test  cases.  


The   RTL   Verilog   is   then   simulated   to   validate   the   func-­‐‑
tionality  against  the  specification.  RTL  simulation  is  usu-­‐‑
ally  one  or  two  orders  of  magnitude  faster  than  gate  level  
simulation,  and  experience  has  shown  that  this  speed-­‐‑up  
is  best  exploited  by  doing  more  simulation,  not  spending  
less  time  on  simulation.  In  practice  it  is  common  to  spend  
70-­‐‑80%  of  the  design  cycle  writing  and  simulating  Verilog  
at  and  above  the  register  transfer  level,  and  20-­‐‑30%  of  the  
time  synthesizing  and  verifying  the  gates.  

Although   some   exploratory   synthesis   will   be   done   early  
on   in   the   design   process,   to   provide   accurate   speed   and  
area   data   to   aid   in   the   evaluation   of   architectural   deci-­‐‑
sions   and   to   check   the   engineer'ʹs   understanding   of   how  
the   Verilog   will   be   synthesized,   the   main   synthesis   pro-­‐‑
duction   run   is   deferred   until   functional   simulation   is  
complete.  It  is  pointless  to  invest  a  lot  of  time  and  effort  in  
synthesis  until  the  functionality  of  the  design  is  validated.  


by  the  designer.  It  also  allows  the  developer  to  synthesize  
the   design   onto   an   FPGA   or   ASIC.   It   also   allows   the   de-­‐‑
signer  to  perform  the  timing  analysis  of  the  designs.  The  
low-­‐‑cost   Spartan   family   of  FPGAs  is   fully   supported   by  
this   edition,   as   well   as   the   family   of  CPLDs,   meaning  
small   developers   and   educational   institutions   have   no  
overheads  from  the  cost  of  development  software.  

As  Xilinx  ISE  is  used  for  design  development  and  imple-­‐‑
mentation  the  OS  requirements  are    
Windows:   Windows   XP,Windows7,   Windows   8,   Win-­‐‑
dows  8.1  
Linux:   Red   hat   enterprise   4,   5,   or   6   and   Suse   enterprise  
ModelSim  :  Modelsim  is  a  hardware  simulation  environ-­‐‑
ment   which   provides   accurate   simulations   of   HDL   de-­‐‑
signs.   It   also   allows   the   developer   to   perform   debugging  
easily.   It   equips   the   developer   to   easily   change   value   of  
signals  during  testing  and  development  phase.  Modelsim  
is   generally   used   along   with   Xilinx   ISE   as   a   simulator.  
Modelsim   can   also   provide   synthesize   of   HDL   designs  
onto  FPGA’s  and  ASIC’s.  

Figure 8: Synthesis using Verilog

Synthesis   is   the   procedure   of   loading   the   simulated   and  
verified   Verilog   code   in   to   a   programmable   logic   struc-­‐‑
ture   such   as   an   FPGA   or   an   ASIC   in   order   to   verify   and  
check  the  system  created.  It  is  not  sufficient  that  the  Veri-­‐‑
log   is   functionally   correct;   it   must   be   written   in   such   a  
way   that   it   directs   the   synthesis   tool   to   generate   good  
hardware.   There   are   currently   three   kinds   of   synthesis  
which  are  possible  such  as  behavioral  synthesis,  high  lev-­‐‑
el  synthesis  and  RTL  synthesis.  

Xilinx  integrated  software  environment  (ISE)  is  a  software  
tool   developed   and   produced   by   Xilinx.   This   ISE   is   used  
for   the   simulation   and   analysis   of   hardware   description  
language  (HDL)  designs.  This  ISE  provides  support  for  a  
variety  of  hardware  description  languages  such  as  VHDL,  
Verilog  etc.  It  provides  RTL  level  diagrams  of  the  designs  
so   that   even   minute   details   of   the   design   can   be   verified  

Artix  Field  Programmable  Gate  Arrays  (FPGA)  are  devel-­‐‑
oped  by  Xilinx.  Artix  FPGA’s  consume  50%  lower  power  
than   the   other   FPGA’s.   The   cost   of   artix   FPGA’s   are   also  
low  compared  to  other  family  of  FPGA’s.  The  Artix  fami-­‐‑
ly   is   designed   to   address   the   small   form   factor   and   low-­‐‑
power   performance   requirements   of   battery-­‐‑powered  
portable   ultrasound   equipment,   commercial   digital   cam-­‐‑
era   lens   control,   and   military   avionics   and   communica-­‐‑
tions  equipment.  

A  Single  input  Single  output  data  transmission  is  realized  
here.  The  implementation  is  carried  out  by  using  the  Xil-­‐‑
inx  ISE  and  Modelsim  tools.  The  Verilog  HDL  language  is  
used   for     programming   the   module.   The   below   figure  
shows  the  block  level  snap  shot  of  the  SISO  module.  


Figure 9:SISO Module Snapshot



The   above   figure   shows   the   top   level   module   of   the   im-­‐‑
plemented   SISO   module.   The   module   has   three   inputs  
comprising   of   clock(clk),reset(rst)   and   data_in(3:0)   which  
is   a   4   bit   digital   input.   The   module   consists   of   a   four   bit  
signal  data_out(3:0).  The  above  snap  shot  shows    the  VLSI  
implementation   of   a   4   bit   digital   data   communication  
system  having  a  single  input  and  output.  

Figure 10: Detailed block diagram of SISO module  


The  SISO  module  internally  comprises  of  a  16-­‐‑Quadrature  
Amplitude  Modulation(QAM)  modulator  as  the  transmit-­‐‑
ter  and  demodulator  as  the  receiver  as  shown  in  figure  10.  
The   modulator   produces   a   two   16   bit   values   as   the   out-­‐‑
puts   which   are   labeled   as   real_part(15:0)   and   imagi-­‐‑
nary(15:0).   These   two   signals   are   fed   as   the   input   for   the  
demodulator   with   new   labels   as   r_in(15:0)   and   i_in(15:0)  
respectively.   The   output   of   the   demodulator   is   pout(3:0)  
which  is  the  output  Dout  of  the  SISO  module.  

The   modulator   adapts   a   digital   16-­‐‑QAM   modulation  
technique  to  modulate  the  input  signals  data_in  fed  as  the  


inputs.   QAM   is   a   modulation   technique   which   can   be  
used  for  both  analog  signal  and  digital  bit  streams.  In  this  
modulation  technique  the  two  carrier  waves  used  are  out  
of  phase  by  90  degrees  and  thus  the  name  quadrature.  It  
performs   Amplitude   Shift   Keying(ASK)   for   both   the   car-­‐‑
rier  waves  and  sum  these  waves  thus  the  final  waveform  
is   a   combination   of   phase   shift   keying(PSK)   and   Ampli-­‐‑
tude  Shift  Keying(PSK).    


Input  Data  

Output  bits  (Real,  

Table1:  Digital  16-­‐‑QAM    output  combinations  

The   demodulator   will   perform   the   inverse   operation   of  
the   modulator   by   removing   the   carrier   bits   which   were  
modulated   by   the   data   bits   and   will   give   an   output   con-­‐‑
sisting  of  only  the  spatially  spread  data  bits  which  are  to  
be  de  interleaved.  In  the  dissertation  work  the  demodula-­‐‑
tor  is  implemented  such  that  it  compares  the  input  signals  
which  are  16  bit  values  of  the  four  grid  values  10,20,30,40  
and  converts  these  values  into  data  symbols.  The  demod-­‐‑
ulator   will   compare   any   one   imaginary   value   with   four  
different  real  values  and  take  a  decision  accordingly.  The  
data  symbols  are  created  in  the  way  such  that  for  a  modu-­‐‑
lated   pair   of   (30,10)   the   output   symbol   is   1111(15)   as  
shown  in  the  table  1.    

Figure 11:16-QAM constellation diagram


The   dissertation   has   implemented   a   digital   16-­‐‑QAM   by  
using  the  constellation  diagram  as  shown  in  the  figure  11.  
The  figure  shows  two  axis  real  and  imaginary  that  signi-­‐‑
fies   the   inphase   and   quadrature   carrier   waves.   The   sym-­‐‑
bols   or   data   bits   are   maked   on   the   four   quadrants   and  
their  binary  values  are  also  shown.  There  are  four  differ-­‐‑
ent   values   10,20,30   and   40   at   both   the   axes   used   to  
uniquely  represent  one  data  symbol.  Thus  any  data  sym-­‐‑
bols   are   uniquely   represented   by   a   pair   of   values,   i.e,  
0001(1)  is  represented  by  (10,40).  The  values  10,20,30  and  
40   are   programmed   as   16   bit   values   ,   thus   the   output   of  
the  modulator  for  any  one  data  symbol  will  be  16  bit  real  
values  and  16  bit  imaginary  values.  The  data  symbols  and  
corresponding   outputs   are   shown   in   the   table   1   as   fol-­‐‑

The   above   snapshot   shows   the   complete   simulation  
waveforms  of  the  SISO  module.The  important  waves  are  
that  of  clk,  rst,  data_in,data_out  and  the  other  waveforms  
are  the  intermediate  values  such  as  inputs  and  outputs  of  
the  modulator  and  demodulator.  

In   the   research   work   considered,   some   important   litera-­‐‑
tures   regarding   MIMO   systems   and   its   implementation  
using   FPGA   kits   have   been   studied   .An   objective   for   the  
work  to  be  done  has  been  framed  and  a  block  diagram  of  
the   proposed   MIMO   system   has   been   realized.   The   soft-­‐‑
ware  tools  required  for  the  work  has  been  identified  and  
installed.   The   hardware   equipment’s   required   for   the  
work   has   also   been   decided.   Xilinx   ISE   tool   is   being  
learned   and     the   work   of   the   convolution   encoder   has  


been   started.   In   the   future,   the   aim   would   be   to   develop  
software  implementation  of  the  encoder  and  the  complete  
transmitter  section.  









Figure 12:The simulation waveforms of the SISO module










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[30] Jan Mietzner, Robert Schober, Lutz Lampe, Senior Wolfgang H.
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Techniques for Wireless Communications – A Comprehensive Literature Survey”, pp. 87-105, 2009.
Dr. T.C. Manjunath was born in Bangalore, Karnataka,
India on Feb. 6, 1967 & received the B.E. Degree (Bachelor of Engg.) from R.V. College of Engg. (Bangalore
Univ., B’lore) in the year 1989, M.E. degree in Automation, Control & Robotics from the prestigious Govt.’s
LD College of Engg., (Gujarat Univ., Ahmadabad) in
the year 1992 and Ph.D. in Systems & Control Engineering from the prestigious Indian Institute of Technology Bombay (IIT Bombay) in the year 2007 respectively. He has got a
teaching (academic), research & administrative experience of more than 26
years in various engineering colleges all over the country (Karnataka, Gujarat, Maharashtra) and is currently working as Principal in HKBK College
of Engg., Bangalore, Karnataka, India. He has worked in the levels of Lecturer, Asst. Prof., Prof., i/c HOD, Prof. & Head, Director-Research, i/c
Principal & as Full time Principal in the various institutions where he has
worked so far. He has also worked as a Project Assistant and as a Research
Engineer in the Systems and Control Engineering (IIT Bombay, India) and
worked on control of space launch vehicles using FOS feedback technique
in IITB. He has published more than 460+ papers in various National,
International journals and Conferences in India & abroad and published
more than a dozen textbooks (18), notable among them being (‘Introduction to robotics’ - 1st edition, ‘Fast Track to Robotics’ - 4th edition, ‘Fundamentals of Robotics’ in 2 volumes, Vol-1 and Vol-2 along with a CD which
contains about 200 C / C++ programs for performing various simulations
on robotics – 5th edition, ‘Examination Security System - Design & Development of Examination Mechanism Using Electronic Box’ from Germany
costing around 49 Euros). He has also published a number of ‘book chapters’ in various edited books from renowned publishers. He has also published a research monograph in the International level from the SpringerVerlag publishers (Europe) based on his Ph.D. thesis topic titled, “Modeling, Control and Implementation of Smart Structures”, Vol. 350, LNCIS,
costing 114.95 Euros. He is a member of 21 professional societies. Some of
them are … He is a member of IEEE for the past 13 years (currently Sr.
Member), Sr. member of IIIE, SPIE student member and IOP student
member for 4 years, life member of ISSS (India), life member of additive
manufacturing society of India (LMAMSI), life member of the ISTE (India),
life member of ISOI (India), life member of SSI (India), life member of the
CSI (India), Life member of IMAPS, Sr. Member of IACST (Singapore) and
life member cum fellow of the IETE (India), AMSI, Chartered Engineer
from IE (I) and Fellow of the Institute of Engineers (FIE). He has given a
number of guest lectures / expert talks and seminars in many institutions
across the country and participated in more than 2 dozen CEP / DEP
courses, seminars, workshops, symposiums, besides conducting a few
courses in the institutions where he worked. He was awarded with the
“Best research scholar award in engineering discipline” for the academic
year 2006-07 for the entire institute from the Research Scholars Forum
(RSF) from Indian Institute of Technology Bombay (IITB). This award was
presented in recognition of the significant contribution to the research
(amongst all the researchers in all disciplines) in IIT Bombay. Also, he was
conferred with the best paper awards in a number of conferences. He was
also conferred with the prestigious Rajiv Gandhi Education Excellence
Award, Rashtriya Vidya Gaurav Gold Medal Award & International educational excellence award (in recognition of sterling merit excellence performance and outstanding contribution for the progress of the nation &
world-wide) from New Delhi in the year 2013 w.r.t. his achievements in
the field of education, academics, administration & research. He was also
instrumental in getting Research centres (12 nos.) along with M.Tech. programmes & new UG programmes in the colleges where he has worked so
far as the administrative head. He was also responsible for getting AICTE
grants under MODROB scheme for the development of the Robotics &
Mechatronics Labs in one of the colleges where he worked. Apart from
which, he has brought a number of grant-in-aids for the conduction of
various events like workshops, conferences, seminars, projects, events, etc.,
wherever he has worked [from VTU, DST, IETE, CSI, IEEE, IE(I), VGST,
KSCST, Vodafone, Uninor, etc.] from different sources. He has visited
Singapore, Russia, United States of America, Malaysia and Australia for
the presentation of his research papers in various international conferences
abroad. His biography was published in 23rd edition of Marquis’s Who’s
Who in the World in the 2006 issue. He has also guided more than 2 dozen
projects (B.E. / B.Tech. / M.E. / M.Tech.) in various engineering colleges
where he has worked, apart from guiding a couple of research scholars
who are doing Ph.D. in various universities under his guidance. Many of
his guided projects, interviews, the events what he had conducted have

appeared in various state & national level newspapers and magazines
(more than 100 times). He has also reviewed many research papers for the
various national & international journals & conferences in India & abroad
(more than 5 dozen times). He has also organized a number of state &
national level sports tournaments like yogasana, chess, cricket, volleyball,
etc. He is also an editorial board / advisory board / reviewer member and
is on the panel of many of the national & international Journals. He has
also served on the advisory / steering / organizing committee member of
a number of national & international conferences. He has given many
keynote / invited talks / plenary lecturers in various national & international conferences and chaired many sessions, was the judge, special invitee, guest of honor & was the chief guest on various occasions. He has
also conducted / organized / convened / coordinated more than 150
courses / workshops / STTP’s / FDP’s / Technical paper fests, Student
level competitions & Symposiums, etc., in various engineering colleges
where he worked so far. He has also taken many administrative initiatives
in the college where he has worked as HOD, Principal & also where he is
currently working as Principal, besides conducting all the semester university exams successfully as chief superintendent, deputy chief superintendent, squad member, etc. Some of the special administrative achievements
as HOD, Principal & Head of the Institution are …. He improved the results of the various branches in East West Inst. of Tech. / New Horizon
College of Engg. / Atria Inst. of Tech. / BTL Inst. of Tech. / HKBK College
of Engg. He gave more importance to the development of in-house projects for the final years. He motivated many of the faculties to take up take
up consultancy works & did it efficiently, so that the college got some good
income. He made the faculties to take up research (Ph.D) work or do
M.Tech. by compelling them constantly to purse for higher studies. As an
administrative head, he made the faculties to publish paper in either national / international journals & conferences at least one in an academic
year. He started the student chapters in all the branches such as IETE,
IEEE, ISTE, CSI, SAE, ISSS, ISOI & also conducted a number of events
under their banners. He brought in power decentralization in the institute
by developing the habit of making coordinator-ships for various works,
getting the work done by monitoring and following it up successively. He
conducted a number of exams from public sectors & private sectors such as
GATE exams, CET / COMED-K, KPSC, Police Exams, Inst. of Civil Engineer exams & conducted a number of state & national level examinations
like Defense, PG entrance exams, Medical, KPTL in the college so that the
college could get some revenue (under the banner of revenue generation
scheme). He started the weekly monitoring of the staff & students. He
developed the counseling of student data booklets & that of the faculty
work-books. All the laboratory manuals were developed in-house, printed
& given to the students (both in the hard as well as in the soft copy). He
used to conduct the academic & governing council meetings regularly
along with the HOD’s meetings time to time. He had looked after the
NBA process in BTLIT & in HKBKCE, Bangalore. He conducted the prestigious 7th IETE ICONRFW & the 28th Karnataka State CSI Student Convention. He introduced the scheme of best lecturer award / best HOD
award / best non-teaching award / service awards concept / Principal cup
/ Departmental cup, etc. in the colleges where he worked as administrative
head. He created a record placement of more than 600 students in Atria
Inst. of Tech. / BTLITM & in HKBKCE with the help of the placement
department. He helped the management to fill up many of the student
admissions in the first year of UG (B.E.) & in PG (M.Tech.) course. He
created a number of hobby-clubs, EDC cells, Innovation & Incubation
centres, centre of excellences in the institute for the staffs & students to
work towards development of prototypes, models, and projects. He started the faculty seminar series in the institute so that every faculty gives a
lecture of 45 mins with 15 mins discussion at least once in a month. He
introduced the concept of coaching class / tutorial classes for the weak
students & remedial class concept for the failed students, which yielded
successful results apart from the training of top 10 students for getting
ranks (9th / 3rd Rank). He made the students to get university ranks in
BTL & HKBKCE in UG stream. He started certificate oriented courses of 3
months & 6 months for the various types of people, especially on Saturdays & Sundays. He made the students to participate in competitions
outside the college & win a number of prizes, brought laurels to the institution. He helped the students to get some financial assistance using sponsors for the cultural events. He brought a grant of nearly Rs. 75 lakhs till
date in the various organizations where he has worked so far. He developed the Innovation & Entrepreneurship Development Cell in HKBKCE &
did a number of programs under its belt. He was responsible for some of
the UG students of HKBKCE to make them establish a start-up company
in the college itself by name ‘pentaP systems’. He made more than one
dozen MOU’s with reputed firms & sectors with the college and utilized all
the advantages of the signed MOUs with the companies. He streamlined
many of the process in the office level & that of the departmental level by
developing new formats for the smooth conduction of various processes


along with excellent documentation. He developed the culture of making
up of small / mini hobby projects by the students. He developed the system documentation of the entire departments & that of the college. Under
industry-institute interaction, he conducted a number of industry oriented
courses like CADD course, ANSYS course, Oracle course, Infosys campus
connect courses (18 batches rolled out in HKBKCE), Software testing, etc.
His special areas of interest are Control systems, DSP, AI, IP, Robotics,
Signals & systems, Smart Intelligent Structures, Vibration control, Instrumentation, Circuits & Networks, Matlab, etc..….