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1.

An invalid condition in the operation of an activeHIGH input S-R latch occurs when ________.
HIGHs are applied
Your Answer: simultaneously to both
inputs S and R

2.

If an S-R latch has a 0 on the S input and a 1 on


the R input and then the R input goes to 0, the
latch will be ________.
RESET
Your Answer:

3.

The symbols on this flip-flop device indicate


________.

triggering takes
Your Answer: place on the
positive-going
edge of the CLK
pulse
triggering takes
Correct Answer: place on the
negative-going
edge of the CLK
pulse

With regard to a D latch, ________.

4.

the Q output is
Your Answer: opposite the D
input when EN
is LOW
the Q output
Correct Answer: follows the D
input when EN

is HIGH

5.

On a positive edge-triggered S-R flip-flop, the


outputs reflect the input condition when ________.
the clock pulse is
Your Answer: HIGH
the clock pulse
Correct Answer: transitions from
LOW to HIGH

6.

A positive edge-triggered D flip-flop will store a 1


when ________.
the D input is HIGH
Your Answer: and the clock
transitions from
LOW to HIGH

7.

A J-K flip-flop is in a "no change" condition when


________.
J = 1, K
Your Answer: = 0
J = 0, K
Correct Answer: = 0

8.

A J-K flip-flop with J = 1 and K = 1 has a 20 kHz


clock input. The Q output is ________.
constantly HIGH
Your Answer:
a 10 kHz square
Correct Answer: wave

9.

Propagation delay time, tPLH, is measured from the


________.
triggering edge
Your Answer: of the clock
pulse to the
HIGH-to-LOW
transition of the
output
triggering edge
Correct Answer: of the clock
pulse to the
LOW-to-HIGH
transition of the
output

10.

Four J-K flip-flops are cascaded with their J-K


inputs tied HIGH. If the input frequency (fin) to the
first flip-flop is 32 kHz, the output frequency (fout)
is ________.
2 kHz
Your Answer:

11.

Two J-K flip-flops with their J-K inputs tied HIGH


are cascaded to be used as counters. After four
input clock pulses, the binary count is ________.
11
Your Answer:
00
Correct Answer:

12.

How many flip-flops are required to produce a


divide-by-128 device?
4
Your Answer:
7
Correct Answer:

13.

The pulse width of a one-shot circuit is determined


by ________.
two resistors
Your Answer:
a resistor and
Correct Answer: capacitor

An RC circuit used in a nonretriggerable 74121

14.

one-shot has an REXT of 49 k


and a CEXT of 0.2 F.
The pulse width (tW) is approximately ________.
6.8 ms
Your Answer:

An RC circuit used in a 74122 retriggerable one-

15.

shot has an REXT of 100 k


and a CEXT of 0.005
The pulse width is ________.

Your Answer:

Correct Answer:

16

160

F.

The output pulse width for a 555 monostable

16.

circuit with R1 = 3.3 k


________.

and C1 = 0.02

Your Answer:

73

F is

A 555 operating as a monostable multivibrator has

17.

a C1 = 0.01

F. Determine R1 for a pulse width of 2

ms.

Your Answer:

181 k

A 555 operating as a monostable multivibrator has

18.

an R1 of 220 k
4 ms.

. Determine C1 for a pulse width of

Your Answer:

19.

0.016

In a 555 timer, three 5 k


resistors provide a
trigger level of ________.
1/3 VCC and a
Your Answer: threshold level
3/4 VCC
1/3 VCC and a
Correct Answer: threshold level
2/3 VCC

The output pulse width of a 555 monostable circuit

20.

with R1 = 4.7 k

and C1 = 47

F is ________.
24 ms

Your Answer:
243 ms
Correct Answer:

A 555 operating as a monostable multivibrator has

21.

a C1 = 100
500 ms.

F. Determine R1 for a pulse width of

Your Answer:

455

Correct Answer:

4.5 k

A 555 operating as a monostable multivibrator has

22.

an R1 of 1 M
s.

. Determine C1 for a pulse width of 2

18 F
Your Answer:

Correct Answer:

23.

1.8

To form the timing network that sets the output


frequency of a 555 configured as an astable circuit,
________.
two external
Your Answer: resistors and an
external capacitor
are used