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E&CE 327: Digital Systems Engineering

Lecture Slides

2015t1 (Winter)
Instructor: Rodolfo Pellizzoni
Notes by: Mark Aagaard

University of Waterloo
Dept of Electrical and Computer Engineering

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ECE-327: 2015t1 (Winter)0 1

CONTENTS

1.3.2 Library Units . . . . . . . . . . . . . . . . .


1.3.3 Entities and Architecture . . . . . . . . . .
1.3.4 Concurrent Statements . . . . . . . . . . .
1.3.5 Component Declaration and Instantiations
1.3.6 Processes . . . . . . . . . . . . . . . . . .
1.3.7 Sequential Statements . . . . . . . . . . .
1.3.8 A Few More Miscellaneous VHDL Features
1.4 Concurrent vs Sequential Statements . . . . . . .
1.4.1 Concurrent Assignment vs Process . . . .
1.4.2 Conditional Assignment vs If Statements .
1.4.3 Selected Assignment vs Case Statement .
1.4.4 Coding Style . . . . . . . . . . . . . . . . .
1.5 Overview of Processes . . . . . . . . . . . . . . .
1.5.1 Combinational Process vs Clocked Process
1.5.2 Latch Inference . . . . . . . . . . . . . . . .
1.6 VHDL Execution: Delta-Cycle Simulation . . . . .
1.6.1 Simple Simulation . . . . . . . . . . . . . .
1.6.2 Temporal Granularities of Simulation . . . .
1.6.3 Zero-Delay Simulation . . . . . . . . . . . .
1.6.4 Intuition Behind Delta-Cycle Simulation . .

Contents
1 Fundamentals of VHDL
1.1 Introduction to VHDL . . . . . . . . . . . . . . . . . . . . . . . .
1.1.1 Levels of Abstraction . . . . . . . . . . . . . . . . . . . . .
1.1.2 VHDL Origins and History . . . . . . . . . . . . . . . . . .
1.1.3 Semantics . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.4 Synthesis of a Simulation-Based Language . . . . . . . .
1.1.5 Solution to Synthesis Sanity . . . . . . . . . . . . . . . .
1.1.6 Standard Logic 1164 . . . . . . . . . . . . . . . . . . . . .
1.2 Comparison of VHDL to Other Hardware Description Languages
1.3 Overview of Syntax . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.1 Syntactic Categories . . . . . . . . . . . . . . . . . . . . .
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1.6.4.1 Introduction to Delta-Cycle Simulation . . . . . . . . .


1.6.4.2 Intuitive Rules for Delta-Cycle Simulation . . . . . . .
1.6.4.3 Example of Delta-Cycles: Back-to-Back Buffers . . .
1.6.4.4 Example of Proj Asn: Buffers . . . . . . . . . . . . . .
1.6.4.5 Example of Proj Asn: Flip-Flops . . . . . . . . . . . .
1.6.4.6 Example of Proj Asn: Comb Loop . . . . . . . . . . .
1.6.5 VHDL Delta-Cycle Simulation . . . . . . . . . . . . . . . . . . .
1.6.5.1 Informal Description of Algorithm . . . . . . . . . . . .
1.6.5.2 Example: VHDL Sim for Buffers . . . . . . . . . . . .
1.6.5.3 Definitions and Algorithm . . . . . . . . . . . . . . . .
1.6.5.4 Example: Delta-Cycle for Flip-Flops . . . . . . . . . .
1.6.5.5 Ex: VHDL Sim of Comb Loop . . . . . . . . . . . . .
1.6.5.6 Rules and Observations for Drawing Delta-Cycle Simulations . . . . . . . . . . . . . . . . . . . . . . . . .
1.6.6 External Inputs and Flip-Flops . . . . . . . . . . . . . . . . . .
1.7 Register-Transfer-Level Simulation . . . . . . . . . . . . . . . . . . . .
1.7.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7.2 Technique for Register-Transfer Level Simulation . . . . . . . .
1.7.3 Examples of RTL Simulation . . . . . . . . . . . . . . . . . . .
1.7.3.1 RTL Simulation Example 1 . . . . . . . . . . . . . . .

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1.8 Simple RTL Simulation in Software . . . . . . . . . . . . . . .


1.9 Variables in VHDL . . . . . . . . . . . . . . . . . . . . . . . .
1.10 Delta-Cycle Simulation with Delays . . . . . . . . . . . . . .
1.11 VHDL and Hardware Building Blocks . . . . . . . . . . . . .
1.11.1 Basic Building Blocks . . . . . . . . . . . . . . . . .
1.11.2 Deprecated Building Blocks for RTL . . . . . . . . .
1.11.3 Hardware and Code for Flops . . . . . . . . . . . . .
1.11.3.1 Flops with Waits and Ifs . . . . . . . . . . .
1.11.3.2 Flops with Synchronous Reset . . . . . . .
1.11.3.3 Flop with Chip-Enable and Mux on Input . .
1.11.3.4 Flops with Chip-Enable, Muxes, and Reset
1.11.4 An Example Sequential Circuit . . . . . . . . . . . .
1.12 Synthesizable vs Non-Synthesizable Code . . . . . . . . . .
1.12.1 Initial Values . . . . . . . . . . . . . . . . . . . . . .
1.12.2 Wait For . . . . . . . . . . . . . . . . . . . . . . . . .
1.12.3 Variables . . . . . . . . . . . . . . . . . . . . . . . .
1.12.4 Bits and Booleans . . . . . . . . . . . . . . . . . . .
1.12.5 Assignments before Wait Statement . . . . . . . . .
1.12.6 Different Wait Conditions . . . . . . . . . . . . . . . .
1.12.7 Multiple if rising edge in Process . . . . . . . . . .

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2 Additional Features of VHDL


2.1 Literals . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.1 Numeric Literals . . . . . . . . . . . . . . . .
2.1.2 Bit-String Literals . . . . . . . . . . . . . . . .
2.2 Arrays and Vectors . . . . . . . . . . . . . . . . . . .
2.2.1 Declarations . . . . . . . . . . . . . . . . . .
2.2.2 Indexing, Slicing, Concatenation, Aggregates
2.3 Arithmetic . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1 Arithmetic Packages . . . . . . . . . . . . . .
2.3.2 Arithmetic Types . . . . . . . . . . . . . . . .
2.3.3 Overloading of Arithmetic . . . . . . . . . . .
2.3.4 Widths for Addition and Subtraction . . . . .
2.3.5 Overloading of Comparisons . . . . . . . . .
2.3.6 Widths for Comparisons . . . . . . . . . . . .
2.3.7 Type Conversion . . . . . . . . . . . . . . . .
2.3.8 Shift and Rotate Operations . . . . . . . . . .
2.4 Types . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.1 Enumerated Types . . . . . . . . . . . . . . .
2.4.2 Defining New Array Types . . . . . . . . . . .

1.12.8 if rising edge and wait in Same Process


1.12.9 if rising edge with else Clause . . . . . .
1.12.10 Loop with Both Comb and Clocked Paths .
1.12.11 wait Inside of a for loop . . . . . . . . .
1.13 Guidelines for Desirable Hardware . . . . . . . . .
1.13.1 Know Your Hardware . . . . . . . . . . . . .
1.13.2 Latches . . . . . . . . . . . . . . . . . . . .
1.13.3 Asynchronous Reset . . . . . . . . . . . . .
1.13.4 Combinational Loops . . . . . . . . . . . . .
1.13.5 Using a Data Signal as a Clock . . . . . . .
1.13.6 Using a Clock Signal as Data . . . . . . . .
1.13.7 Tri-State Buffers and Signals . . . . . . . .
1.13.8 Multiple Drivers . . . . . . . . . . . . . . . .

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3 Overview of FPGAs
3.1 Generic FPGA Hardware . . . . . . . . . .
3.1.1 Generic FPGA Cell . . . . . . . . .
3.1.2 Lookup Table . . . . . . . . . . . . .
3.1.3 Interconnect for Generic FPGA . . .
3.1.4 Blocks of Cells for Generic FPGA .
3.1.5 Special Circuitry in FPGAs . . . . .
3.2 Area Estimation for FPGAs . . . . . . . . .
3.2.1 Area for Circuit with one Target . . .
3.2.2 Algorithm to Allocate Gates to Cells
3.2.3 Area for Arithmetic Circuits . . . . .

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CONTENTS

4 Intro to RTL Design with VHDL


4.1 Function Tables . . . . . . . . . . . . . . . . . . . .
4.1.1 Karnaugh Maps . . . . . . . . . . . . . . . .
4.1.2 Generalizations . . . . . . . . . . . . . . . .
4.1.3 Multi-Output Tables . . . . . . . . . . . . . .
4.1.4 Dont-Cares . . . . . . . . . . . . . . . . . . .
4.1.5 Dont Cares on Inputs . . . . . . . . . . . . .
4.1.6 Consistency and Unused . . . . . . . . . . .
4.2 Finite State Machines in VHDL . . . . . . . . . . . .
4.2.1 HDL Coding Styles for State Machines . . . .
4.2.2 State Encodings . . . . . . . . . . . . . . . .
4.2.3 Traditional State-Machine Notation . . . . . .
4.2.4 Our State-Machine Notation . . . . . . . . .
4.2.5 Bounce Example . . . . . . . . . . . . . . . .
4.2.6 Registered Assignments . . . . . . . . . . .
4.2.7 Summary and Analysis of Explicit vs Implicit
4.2.8 More Notation . . . . . . . . . . . . . . . . .
4.2.9 Semantic and Syntax Rules . . . . . . . . . .
4.2.10 VHDL Constructs and Patterns . . . . . . .
4.2.11 Translating VHDL to FSM . . . . . . . . . .

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4.2.12 Reset . . . . . . . . . . . . . . . . . . . . . .
4.3 Dataflow Diagrams . . . . . . . . . . . . . . . . . . . .
4.3.1 Dataflow Diagrams Overview . . . . . . . . . .
4.3.2 Dataflow Diagram Execution . . . . . . . . . .
4.3.3 Dataflow Diagrams, Hardware, and Behaviour
4.3.4 Performance Estimation . . . . . . . . . . . . .
4.3.5 Area Estimation . . . . . . . . . . . . . . . . .
4.3.6 Design Analysis . . . . . . . . . . . . . . . . .
4.3.7 Parcels . . . . . . . . . . . . . . . . . . . . . .
4.3.8 Bubbles and Throughput . . . . . . . . . . . .
4.4 Hnatyshyn with Registered Outputs . . . . . . . . . .
4.4.1 Leftovers . . . . . . . . . . . . . . . . . . . . .
4.4.2 Design Process . . . . . . . . . . . . . . . . .
4.4.3 Requirements . . . . . . . . . . . . . . . . . .
4.4.4 Data-Dependency Graph . . . . . . . . . . . .
4.4.5 Initial Dataflow Diagram . . . . . . . . . . . . .
4.4.6 Area Optimization . . . . . . . . . . . . . . . .
4.4.7 Assign Names to Registered Signals . . . . . .
4.4.8 VHDL #1: Big and Obviously Correct . . . . .
4.4.9 Allocation . . . . . . . . . . . . . . . . . . . . .

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4.4.10 VHDL #2: Post-Allocation . . . . . . . . . . . . . . . . . . .


4.4.11 Explicit State Machine . . . . . . . . . . . . . . . . . . . . .
4.4.12 VHDL Implementation #3 . . . . . . . . . . . . . . . . . . .
4.5 Design Example: Hnatyshyn with Combinational Inputs and Outputs
4.5.1 Requirements . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.2 Dataflow Diagram . . . . . . . . . . . . . . . . . . . . . . . .
4.5.3 Maximum Throughput Design . . . . . . . . . . . . . . . . . .
4.5.4 Minimum Area Design . . . . . . . . . . . . . . . . . . . . . .
4.5.5 Minimum Area Design with ASAP Parcels . . . . . . . . . . .
4.5.6 Minimum Area Design with Unpredictable Bubbles . . . . . .
4.6 Hnatyshyn with Registered Inputs and Combinational Output . . . .
4.6.1 Dataflow Diagram and Behaviour . . . . . . . . . . . . . . . .
4.7 Hnatyshyn with Registered Inputs and Outputs . . . . . . . . . . . .
4.7.1 Requirements . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.2 Data-Dependency Graph . . . . . . . . . . . . . . . . . . . .
4.7.3 Initial Dataflow Diagram . . . . . . . . . . . . . . . . . . . . .
4.7.4 Area Optimization . . . . . . . . . . . . . . . . . . . . . . . .
4.7.5 Assign Names to Registered Signals . . . . . . . . . . . . . .
4.7.6 VHDL #1: Big and Obviously Correct . . . . . . . . . . . . .
4.7.7 Tangent: Combinational Outputs . . . . . . . . . . . . . . . .

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306
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316
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325
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327
328
329
330
332
334

4.7.8 Allocation . . . . . . . . . . . . . .
4.7.9 VHDL #2: Post-Allocation . . . . .
4.7.10 Separate Datapath and Control .
4.8 Design Example: Hnatyshyn with Bubbles
4.8.1 Control Table Standard Method
4.8.2 Control Table Valid Bit Shortcut
4.9 Example: LeBlanc . . . . . . . . . . . . .
4.9.1 System Description . . . . . . . .
4.9.2 Design for ASAP Parcels . . . . .
4.9.2.1 Implicit State Machine . .
4.9.2.2 Explicit State Machine . .
4.9.2.3 Datapath Control . . . .
4.9.2.4 Final Implementation . .
4.9.2.5 Buggy Implementation .
4.9.3 Design for Unpredictable Bubbles
4.9.3.1 Implicit State Machine . .
4.9.3.2 Explicit State Machine . .
4.9.3.3 Datapath Control . . . .
4.9.3.4 Final Implementation . .
4.9.3.5 Buggy Implementation .

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335
341
343
354
360
365
371
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385
387
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389
391
393
396
401
408
409

CONTENTS

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xiii

xiv

CONTENTS

CONTENTS

5 Intermediate RTL Design


5.1 Inter-Parcel Variables: Hnatyshyn with Internal State . .
5.1.1 Requirements and Goals . . . . . . . . . . . . .
5.1.2 High-Level Model . . . . . . . . . . . . . . . . .
5.1.3 Dataflow Diagrams and Waveforms . . . . . . .
5.1.4 Implicit State Machine . . . . . . . . . . . . . . .
5.1.5 Adding Reset . . . . . . . . . . . . . . . . . . . .
5.1.6 Control Tables . . . . . . . . . . . . . . . . . . .
5.1.7 VHDL Implementation . . . . . . . . . . . . . . .
5.1.8 Summary of Bubbles and Inter-Parcel Variables
5.2 Hnatyshyn for a Finite Sequence . . . . . . . . . . . . .
5.2.1 Introduction to Hnatyshyn-Finite . . . . . . . . .
5.2.2 Requirements, Goals, and Constraints . . . . . .
5.2.3 Pseudocode . . . . . . . . . . . . . . . . . . . .
5.2.4 High-Level Model . . . . . . . . . . . . . . . . .
5.2.5 Transient-State Machine . . . . . . . . . . . . . .
5.2.6 Add Support for Bubbles . . . . . . . . . . . . .
5.2.7 Linearize Control Flow . . . . . . . . . . . . . . .
5.3 Memory Arrays and RTL Design . . . . . . . . . . . . .
5.3.1 Memory Operations . . . . . . . . . . . . . . . .
5.3.2 Memory Arrays in VHDL . . . . . . .
5.3.3 Data Dependencies . . . . . . . . .
5.4 Design Example: Massey . . . . . . . . . .
5.5 Design Example: Vanier . . . . . . . . . . .
5.5.1 Requirements . . . . . . . . . . . .
5.5.2 Algorithm . . . . . . . . . . . . . . .
5.5.3 Initial Dataflow Diagram . . . . . . .
5.5.4 Reschedule to Meet Requirements .
5.5.5 Optimization: Reduce Inputs . . . .
5.5.6 Assign Names to Registered Values
5.5.7 VHDL Implementation #1 . . . . . .
5.5.8 Tangent: Combinational Outputs . .
5.5.9 Allocation . . . . . . . . . . . . . . .
5.5.10 VHDL Implementation #2 . . . . .
5.5.11 Separate Datapath and Control . .
5.5.12 Dont-Care Instantiations . . . . .
5.5.13 VHDL Implementation #3 . . . . .
5.5.14 VHDL Implementation #4 . . . . .
5.5.15 Notes and Observations . . . . . .
xv

CONTENTS

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413
414
415
416
417
418
419
423
428
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437
440
443
446
453
453

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457
458
463
463
464
465
466
467
469
471
472
473
475
478
479
481
487
489
491

6 Advanced RTL Design: Optimization


6.1 Pipelining . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.1 Introduction to Pipelining . . . . . . . . . . . .
6.1.2 Partially Pipelined . . . . . . . . . . . . . . . .
6.1.3 Terminology . . . . . . . . . . . . . . . . . . .
6.1.4 Design Example: Pipelined Massey . . . . . .
6.1.5 Overlapping Pipeline Stages . . . . . . . . . .
6.2 Staggering . . . . . . . . . . . . . . . . . . . . . . . .
6.3 Retiming . . . . . . . . . . . . . . . . . . . . . . . . .
6.4 General Optimizations . . . . . . . . . . . . . . . . . .
6.4.1 Strength Reduction . . . . . . . . . . . . . . .
6.4.1.1 Arithmetic Strength Reduction . . . .
6.4.1.2 Boolean Strength Reduction . . . . .
6.4.2 Replication and Sharing . . . . . . . . . . . . .
6.4.2.1 Mux-Pushing . . . . . . . . . . . . . .
6.4.2.2 Common Subexpression Elimination .
6.4.2.3 Computation Replication . . . . . . .
6.4.3 Arithmetic . . . . . . . . . . . . . . . . . . . . .
6.5 Customized State Encodings . . . . . . . . . . . . . .
7 Performance Analysis
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . .
7.2 Defining Performance . . . . . . . . . . . . . . . . . .
7.3 Benchmarks . . . . . . . . . . . . . . . . . . . . . . .
7.4 Comparing Performance . . . . . . . . . . . . . . . .
7.4.1 General Equations . . . . . . . . . . . . . . . .
7.4.2 Example: Performance of Printers . . . . . . .
7.5 Clock Speed, CPI, Program Length, and Performance
7.5.1 Mathematics . . . . . . . . . . . . . . . . . . .
7.5.2 Example: CISC vs RISC and CPI . . . . . . .
7.5.3 Effect of Instruction Set on Performance . . . .
7.6 Effect of Time to Market on Relative Performance . .

CONTENTS

xvi

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493
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529
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556

xvii

xviii

CONTENTS

CONTENTS

8 Timing Analysis
8.1 Delays and Definitions . . . . . . . . . . . . . . . . . . .
8.1.1 Background Definitions . . . . . . . . . . . . . .
8.1.2 Clock-Related Timing Definitions . . . . . . . . .
8.1.2.1 Clock Latency . . . . . . . . . . . . . .
8.1.2.2 Clock Skew . . . . . . . . . . . . . . . .
8.1.2.3 Clock Jitter . . . . . . . . . . . . . . . .
8.1.3 Storage-Related Timing Definitions . . . . . . .
8.1.3.1 Flops and Latches . . . . . . . . . . . .
8.1.4 Propagation Delays . . . . . . . . . . . . . . . .
8.1.5 Timing Constraints . . . . . . . . . . . . . . . . .
8.1.6 Review: Timing Parameters . . . . . . . . . . . .
8.2 Timing Analysis of Simple Latches . . . . . . . . . . . .
8.2.1 Structure and Behaviour of Multiplexer Latch . .
8.2.2 Strategy for Timing Analysis of Storage Devices
8.2.3 Clock-to-Q Time of a Latch . . . . . . . . . . . .
8.2.4 From Load Mode to Store Mode . . . . . . . . .
8.2.5 Setup Time Analysis . . . . . . . . . . . . . . . .
8.2.6 Hold Time of a Multiplexer Latch . . . . . . . . .
8.2.7 Example of a Bad Latch . . . . . . . . . . . . . .
8.2.8 Summary . . . . . . . . . . . . . . . . . . . . .
8.3 Advanced Timing Analysis of Storage Elements . . .
8.4 Critical Path . . . . . . . . . . . . . . . . . . . . . . . .
8.4.1 Introduction to Critical and False Paths . . . .
8.4.1.1 Example of Critical Path in Full Adder
8.4.1.2 Longest Path and Critical Path . . . .
8.4.1.3 Criteria for Critical Path Algorithms . .
8.4.2 Longest Path . . . . . . . . . . . . . . . . . . .
8.4.2.1 Algorithm to Find Longest Path . . . .
8.4.2.2 Longest Path Example . . . . . . . .
8.4.3 Monotone Speedup . . . . . . . . . . . . . . .
8.5 False Paths . . . . . . . . . . . . . . . . . . . . . . . .
8.6 Analog Timing Model . . . . . . . . . . . . . . . . . .
8.6.1 Defining Delay . . . . . . . . . . . . . . . . . .
8.6.2 Modeling Circuits for Timing . . . . . . . . . . .
8.6.3 Example: Two Buffers . . . . . . . . . . . . . .
8.6.4 Ex: Two Bufs with Both Caps . . . . . . . . . .
8.7 Elmore Delay Model . . . . . . . . . . . . . . . . . . .
8.7.1 Elmore Delay as an Approximation . . . . . . .
8.7.2 A More Complicated Example . . . . . . . . .
8.8 Practical Usage of Timing Analysis . . . . . . . . . . .
xix

CONTENTS

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571
571
574
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581
582
583
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596
597
598
600
601
603
606
607
607
608
609
613
614
615
619
623
628
632
632
635
639

9 Power Analysis and Power-Aware Design


9.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . .
9.1.1 Importance of Power and Energy . . . . . . . .
9.1.2 Power vs Energy . . . . . . . . . . . . . . . . .
9.1.3 Batteries, Power and Energy . . . . . . . . . .
9.1.3.1 Do Batteries Store Energy or Power?
9.1.3.2 Battery Life and Efficiency . . . . . .
9.1.3.3 Battery Life and Power . . . . . . . .
9.2 Power Equations . . . . . . . . . . . . . . . . . . . . .
9.2.1 Switching Power . . . . . . . . . . . . . . . . .
9.2.2 Short-Circuited Power . . . . . . . . . . . . . .
9.2.3 Leakage Power . . . . . . . . . . . . . . . . . .
9.2.4 Glossary . . . . . . . . . . . . . . . . . . . . .
9.2.5 Note on Power Equations . . . . . . . . . . . .
9.3 Overview of Power Reduction Techniques . . . . . . .
9.4 Voltage Reduction for Power Reduction . . . . . . . .
9.5 Data Encoding for Power Reduction . . . . . . . . . .
9.5.1 How Data Encoding Can Reduce Power . . . .
9.5.2 Example Problem: Sixteen Pulser . . . . . . .
9.5.2.1 Problem Statement . . . . . . . . . .

xx

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641
642
642
643
644
644
645
646
649
651
653
654
655
655
655
660
666
666
670
670

9.5.2.2 Additional Information . . . . . . . . . . . .


9.5.2.3 Answer . . . . . . . . . . . . . . . . . . . .
9.6 Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . .
9.6.1 Introduction to Clock Gating . . . . . . . . . . . . . .
9.6.2 Implementing Clock Gating . . . . . . . . . . . . . .
9.6.3 Design Process . . . . . . . . . . . . . . . . . . . .
9.6.4 Effectiveness of Clock Gating . . . . . . . . . . . . .
9.6.5 Example: Reduced Activity Factor with Clock Gating
9.6.6 Calculating PctBusy . . . . . . . . . . . . . . . . . .
9.6.6.1 Valid Bits and Busy . . . . . . . . . . . . .
9.6.6.2 Calculating LenBusy . . . . . . . . . . . .
9.6.6.3 From LenBusy to PctBusy . . . . . . . . .
9.6.7 Example: Pipelined Circuit with Clock-Gating . . . .
9.6.8 Clock Gating in ASICs . . . . . . . . . . . . . . . . .
9.6.9 Alternatives to Clock Gating . . . . . . . . . . . . . .
9.6.9.1 Use Chip Enables . . . . . . . . . . . . . .
9.6.9.2 Operand Gating . . . . . . . . . . . . . . .

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671
673
680
681
682
683
684
688
690
690
692
694
696
702
703
703
704

CONTENTS

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xxi

xxii

CONTENTS

10 Review
10.1 Overview of the Term . . . . . . . . . . .
10.2 VHDL . . . . . . . . . . . . . . . . . . .
10.2.1 VHDL Topics . . . . . . . . . . .
10.2.2 VHDL Example Problems . . . .
10.3 RTL Design Techniques . . . . . . . . .
10.3.1 Design Topics . . . . . . . . . . .
10.3.2 Design Example Problems . . . .
10.4 Performance Analysis and Optimization
10.4.1 Performance Topics . . . . . . .
10.4.2 Performance Example Problems
10.5 Timing Analysis . . . . . . . . . . . . . .
10.5.1 Timing Topics . . . . . . . . . . .
10.5.2 Timing Example Problems . . . .
10.6 Power . . . . . . . . . . . . . . . . . . .
10.6.1 Power Topics . . . . . . . . . . .
10.6.2 Power Example Problems . . . .
10.7 Formulas to be Given on Final Exam . .

1.1. INTRODUCTION TO VHDL

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705
706
707
707
708
709
709
710
711
711
712
713
713
714
715
715
716
717

1.1
1.1.1

24

Introduction to VHDL
Levels of Abstraction

Transistor Signal values and time are continous (analog). Each transistor is
modeled by a resistor-capacitor network.
Switch Time is continuous, but voltage may be either continuous or discrete.
Linear equations are used.
Gate Transistors are grouped together into gates. Voltages are discrete values
such as 0 and 1.
Register transfer level Hardware is modeled as assignments to registers and
combinational signals. Basic unit of time is one clock cycle.
Transaction level A transaction is an operation such as transfering data across
a bus. Building blocks are processors, controllers, etc. VHDL, SystemC, or
SystemVerilog.
Electronic-system level Looks at an entire electronic system, with both
hardware and software.

1.1.2

VHDL Origins and History

VHDL = VHSIC Hardware Description Language


VHSIC = Very High Speed Integrated Circuit

Chapter 1
Fundamentals of VHDL

The VHSIC Hardware Description Language (VHDL) is a formal notation


intended for use in all phases of the creation of electronic systems.
Because it is both machine readable and human readable, it supports the
development, verification, synthesis and testing of hardware designs, the
communication of hardware design data, and the maintenance,
modification, and procurement of hardware.
Language Reference Manual (IEEE Design Automation Standards
Committee, 1993a)

VHDL is a lot more than synthesis of digital


hardware
23

1.1.2

VHDL Origins and History

25

26

1.1.3

CHAPTER 1. FUNDAMENTALS OF VHDL

1.1.4

Semantics

Synthesis of a Simulation-Based Language

28

1.1.4 Synthesis of a Simulation-Based


Language

The original goal of VHDL was to simulate circuits. The semantics of the language
define circuit behaviour.

This section reserved for your reading pleasure

a
c <= a AND b;

simulation

b
c

But now, VHDL is used in simulation and synthesis. Synthesis is concerned with
the structure of the circuit.
Synthesis: converts one type of description (behavioural) into another, lower level,
description (usually a netlist).
a

synthesis

c <= a AND b;

c
b

Synthesis vs Simulation

1.1.5

Solution to Synthesis Sanity

Pick a high-quality synthesis tool and study its documentation thoroughly


For synthesis, we want the code we write to define the structure of the hardware
that is generated.

Learn the idioms of the tool


Different VHDL code with same behaviour can result in very different circuits

The VHDL semantics define the behaviour of the hardware that is generated, not
the structure of the hardware.

ula

tio

sim

same
behaviour

synthesis

c
b

simulation

b
c

syn
the
sis

different
structure

Follow the coding guidelines and examples from lecture


As you write VHDL, think about the hardware you expect to get.
Note:
If you cant predict the hardware, then the hardware
probably wont be very good (small, fast, correct, etc)

a
c <= a AND b;

KISS: Keep It Simple Stupid


VHDL examples will illustrate reliable coding techniques for the synthesis
tools from Synopsys, Mentor Graphics, Altera, Xilinx, and most other
companies as well.

Be careful if you have to port VHDL code from one tool to another

same
behaviour
a

a
c
b

simulation

b
c

27

CHAPTER 1. FUNDAMENTALS OF VHDL

1.1.5

Solution to Synthesis Sanity

29

30

CHAPTER 1. FUNDAMENTALS OF VHDL

1.1.6

Standard Logic 1164

std logic 1164: IEEE standard for signal values in VHDL.


U
X
0
1
Z
W
L
H
-

uninitialized
strong unknown
strong 0
strong 1
high impedance
weak unknown
weak 0
weak 1
dont care

1.3.3

1.3.3

Entities and Architecture

32

Entities and Architecture

Each hardware module is described with an Entity/Architecture pair


entity
architecture

entity

architecture

Entity and Architecture

The most common values are: U, X, 0, 1.


If you see X in a simulation, it usually means that there is a mistake in your
code.

Entity

1.2 Comparison of VHDL to Other


Hardware Description Languages
This section reserved for your reading pleasure

1.3
1.3.1

Overview of Syntax
Syntactic Categories
This section reserved for your reading pleasure

1.3.2

library ieee;
use ieee.std_logic_1164.all;
entity and_or is
port (
a, b, c : in std_logic ;
z
: out std_logic
);
end entity;
Example of an entity

Library Units
This section reserved for your reading pleasure

31

CHAPTER 1. FUNDAMENTALS OF VHDL

1.3.3

Entities and Architecture

33

34

CHAPTER 1. FUNDAMENTALS OF VHDL

Architecture
architecture main of and_or is
signal x : std_logic;
begin
x <= a AND b;
z <= x OR (a AND c);
end architecture;
Example of architecture

1.3.4

Concurrent Statements

36

Concurrent Statements
architecture main of bowser is
begin
x1 <= a AND b;
x2 <= NOT x1;
z <= NOT x2;
end main;

architecture main of bowser is


begin
z <= NOT x2;
x2 <= NOT x1;
x1 <= a AND b;
end main;

x1

x2

The order of concurrent statements doesnt matter

1.3.4

Concurrent Statements

Types of Concurrent Statements

An architecture contains concurrent statements


Concurrent statements execute in parallel
Concurrent statements make VHDL fundamentally different from most
software languages.
Hardware (gates) naturally execute in parallel VHDL mimics the behaviour
of real hardware.
At each infinitesimally small moment of time, each gate:
1. samples its inputs
2. computes the value of its output
3. drives the output

35

CHAPTER 1. FUNDAMENTALS OF VHDL

conditional assignment similar to conventional if-then-else


c <= a+b when sel=1 else a+c when sel=0 else "0000";
selected assignment
similar to conventional case/switch
with color select d <= "00" when red , "01" when . . .;
component instantiation use a hardware module/component
add1 : adder port map( a => f, b => g, s => h, co => i);
for-generate
create multiple pieces of hardware
bgen: for i in 1 to 7 generate b(i)<=a(7-i); end generate;
if-generate
conditionally create some hardware
okgen : if optgoal /= fast then generate
result <= ((a and b) or (d and not e)) or g;
end generate;
fastgen : if optgoal = fast then generate
result <= 1;
end generate;
process
description of complex behaviour (section 1.3.6)
1.3.4

Concurrent Statements

37

38

CHAPTER 1. FUNDAMENTALS OF VHDL

1.3.5 Component Declaration and


Instantiations
This section reserved for your reading pleasure

1.3.6

Processes

Processes are used to describe complex and potentially unsynthesizable


behaviour
A process is a concurrent statement (section 1.3.4).
The body of a process contains sequential statements (section 1.3.7)
Processes are the most complex and difficult to understand part of VHDL
(sections 1.5 and 1.6)

Example Process with Sensitivity List


process (a, b, c)
begin
y <= a AND b;
if (a = 1) then
z1 <= b AND c;
z2 <= NOT c;
else
z1 <= b OR c;
z2 <= c;
end if;
end process;

39

1.3.6

Processes

40

Example Process with Wait Statements


process
begin
y <= a AND b;
z <= 0;
wait until rising_edge(clk);
if (a = 1) then
z <= 1;
y <= 0;
wait until rising_edge(clk);
else
y <= a OR b;
end if;
end process;

Sensitivity Lists and Wait Statements


Processes must have either a sensitivity list or at least one wait statement on
each execution path through the process.
Processes cannot have both a sensitivity list and a wait statement.

CHAPTER 1. FUNDAMENTALS OF VHDL

1.3.6

Processes

41

42

CHAPTER 1. FUNDAMENTALS OF VHDL

Sensitivity List

1.3.8

A Few More Miscellaneous VHDL Features

44

1.3.8 A Few More Miscellaneous VHDL


Features

The sensitivity list contains the signals that are read in the process.

This section reserved for your reading pleasure

A process is executed when a signal in its sensitivity list changes value.


An important coding guideline to ensure consistent synthesis and simulation
results is to include all signals that are read in the sensitivity list.
There is one exception to this rule: for a process that implements a flip-flop with
an if rising edge statement, it is acceptable to include only the clock signal in
the sensitivity list other signals may be included, but are not needed.

1.3.7

Sequential Statements

Used inside processes and functions.


wait
signal assignment
if-then-else
case

loop
while loop
for loop
next

wait until . . . ;
. . . <= . . . ;
if . . . then . . . elsif . . . end if;
case . . . is
when . . . | . . . => . . . ;
when . . . => . . . ;
end case;
loop . . . end loop;
while . . . loop . . . end loop;
for . . . in . . . loop . . . end loop;
next . . . ;

1.4

Concurrent vs Sequential Statements

All concurrent assignments can be translated into sequential statements. But, not
all sequential statements can be translated into concurrent statements.

1.4.1

Concurrent Assignment vs Process

The two code fragments below have identical behaviour:


architecture main of tiny is
begin
b <= a;
end main;

architecture main of tiny is


begin
process (a) begin
b <= a;
end process;
end main;

The most commonly used sequential statements

43

CHAPTER 1. FUNDAMENTALS OF VHDL

1.4.1

Concurrent Assignment vs Process

45

46

CHAPTER 1. FUNDAMENTALS OF VHDL

1.4.2 Conditional Assignment vs If


Statements

1.4.4

1.4.4

Coding Style

48

Coding Style

Code thats easy to write with sequential statements, but difficult with concurrent:
The two code fragments below have identical behaviour:
Concurrent Statements
t <=
<val1> when <cond>
else <val2>;

Sequential Statements
if <cond> then
t <= <val1>;
else
t <= <val2>;
end if

1.4.3 Selected Assignment vs Case


Statement
The two code fragments below have identical behaviour
Concurrent Statements
with <expr> select
t <= <val1> when <choices1>,
<val2> when <choices2>,
<val3> when <choices3>;

47

Sequential Statements
case <expr> is
when <choices1> =>
t <= <val1>;
when <choices2> =>
t <= <val2>;
when <choices3> =>
t <= <val3>;
end case;

CHAPTER 1. FUNDAMENTALS OF VHDL

case <expr> is
when <choice1> =>
if <cond> then
o <= <expr1>;
else
o <= <expr2>;
end if;
when <choice2> =>
...
end case;

1.5

Overview of Processes

Processes are the most difficult VHDL construct to understand. This section gives
an overview of processes. section 1.6 gives the details of the semantics of
processes.

Within a process, statements are executed almost sequentially


Among processes, execution is done in parallel
Remember: a process is a concurrent statement!

1.5. OVERVIEW OF PROCESSES

49

50

CHAPTER 1. FUNDAMENTALS OF VHDL

1.5. OVERVIEW OF PROCESSES

Process Semantics

Process Semantics

52

VHDL mimics hardware


Hardware (gates) execute in parallel
Processes execute in parallel with each other
All possible orders of executing processes must produce the same simulation
results (waveforms)
If a signal is not assigned a value, then it holds its previous value

All orders of executing concurrent


statements must produce the same
waveforms

Process Semantics
execution sequence

execution sequence

All execution orders must have same behaviour

1.5.1 Combinational Process vs Clocked


Process
execution sequence

Each well-written synthesizable process is either combinational or clocked.

architecture
procA: process
stmtA1;
stmtA2;
stmtA3;

A1

A1
A2
A3

Combinational process:

A1
A2

A2
A3

A3

Executing the process takes part of one clock cycle


Target signals are outputs of combinational circuitry

end process;
procB: process

A combinational processes must have a sensitivity list

stmtB1;
stmtB2;
end process;

B1

B1
B2

single threaded:
procA before
procB

51

B1
B2

single threaded:
procB before
procA

CHAPTER 1. FUNDAMENTALS OF VHDL

A combinational process must not have any wait statements


B2

multithreaded:
procA and procB
in parallel

A combinational process must not have any rising_edges, or


falling_edges
The hardware for a combinational process is just combinational circuitry

1.5.1

Combinational Process vs Clocked Process

53

54

CHAPTER 1. FUNDAMENTALS OF VHDL

Clocked process:

1.5.1

Combinational Process vs Clocked Process

56

Combinational or Clocked Process? (2)

Executing the process takes one (or more) clock cycles


Target signals are outputs of flops
Process contains one or more wait or if rising edge statements
Hardware contains combinational circuitry and flip flops

process
begin
wait until rising_edge(clk);
b <= a;
end process;

Note:
Clocked processes are sometimes called sequential
processes, but this can be easily confused with sequential
statements, so in E&CE 327 well refer to synthesizable
processes as either combinational or clocked.

Combinational or Clocked Process? (1)


process (a,b,c)
p1 <= a;
if (b = c) then
p2 <= b;
else
p2 <= a;
end if;
end process;

55

Combinational or Clocked Process? (3)


process (clk)
begin
if rising_edge(clk) then
b <= a;
end if;
end process;

CHAPTER 1. FUNDAMENTALS OF VHDL

1.5.1

Combinational Process vs Clocked Process

57

58

CHAPTER 1. FUNDAMENTALS OF VHDL

Combinational or Clocked Process? (4)

1.5.2

1.5.2

Latch Inference

60

Latch Inference

The semantics of VHDL require that if a signal is assigned a value on some


passes through a process and not on other passes, then on a pass through the
process when the signal is not assigned a value, it must maintain its value from
the previous pass.

process (clk)
begin
a <= clk;
end process;

process (a, b, c)
begin
if (a = 1) then
z1 <= b;
z2 <= b;
else
z1 <= c;
end if;
end process;

a
b
c
z1
z2

Example of latch inference

Combinational or Clocked Process? (5)


process
begin
wait until rising_edge(a);
c <= b;
end process;

Latch Inference
When a signals value must be stored, VHDL infers a latch or a flip-flop in the
hardware to store the value.
If you want a latch or a flip-flop for the signal, then latch inference is good.
If you want combinational circuitry, then latch inference is bad.

59

CHAPTER 1. FUNDAMENTALS OF VHDL

1.5.2

Latch Inference

61

62

CHAPTER 1. FUNDAMENTALS OF VHDL

Loop, Latch, Flop


a
b

z
a

Combinational loop

Question:

EN

Latch

Write VHDL code for each of the above circuits

Flip-flop

1.6 VHDL Execution: Delta-Cycle


Simulation
1.6.1

Simple Simulation

Hardware runs in parallel: At each infinitesimally small moment of time, each


gate:
1. samples its inputs
2. computes the value of its output
3. drives the output
0ns
a
a

d
e

c
d
e

10ns 12ns

15ns

64

CHAPTER 1. FUNDAMENTALS OF VHDL

Different Programs, Same Behaviour


All three programs below synthesize to the circuit on the previous slide.
The goal of VHDL semantics is that all three programs have the same behaviour.
process (a,b)
begin
c <= a and b;
end process;
process (b,c,d)
begin
d <= not c;
e <= b and d;
end process;

1.6.2

process (a,b,c,d)
begin
c <= a and b;
d <= not c;
e <= b and d;
end process;

process (a,b)
begin
c <= a and b;
end process;
process (c)
begin
d <= not c;
end process;
process (b,d)
begin
e <= b and d;
end process;

Temporal Granularities of Simulation

1.6.3

1.6.3

Zero-Delay Simulation

66

Zero-Delay Simulation

Register-transfer-level and delta-cycle simulation are both examples of zero-delay


simulation.
There are two fundamental rules for zero-delay simulation:
1. Events appear to propagate through combinational circuitry instantaneously.
2. All of the gates appear to operate in parallel

1.6.4 Intuition Behind Delta-Cycle


Simulation

register-transfer-level

smallest unit of time is a clock cycle


combinational logic has zero delay
flip-flops have a delay of one clock cycle
timing simulation

smallest unit of time is a nano, pico, or fempto second


combinational logic and wires have delay as computed by timing analysis
tools
flip-flops have setup, hold, and clock-to-Q timing parameters
delta cycles

units of time are artifacts of VHDL semantics and simulation software


simulation cycles, delta cycles, and simulation steps are infinitesimally small
amounts of time
VHDL semantics are defined in terms of these concepts
65

CHAPTER 1. FUNDAMENTALS OF VHDL

1.6.4.1 Introduction to Delta-Cycle


Simulation
To make it appear that events propagate instantaneously through
combinational circuitry: VHDL introduces the delta cycle
Infinitesimally small artificial unit of time
In each delta cycle, every gate in the circuit
1. samples its input signals
2. computes its result value
3. drives the result value on its output signal
To make it appear that gates operate in parallel: VHDL introduces the
projected assignment
the effect of simulating a gate remains invisible until the beginning of the next
delta cycle
1.6.4

Intuition Behind Delta-Cycle Simulation

67

68

CHAPTER 1. FUNDAMENTALS OF VHDL

1.6.4

1.6.4.4

1.6.4.2 Intuitive Rules for Delta-Cycle


Simulation

Intuition Behind Delta-Cycle Simulation

70

Example of Proj Asn: Buffers

1ns

1. Simulate a gate if any of its inputs changed. (If no input changed, then the
current value of the output is correct and the output can stay at the same value.)
3. When a gate is executed, the projected (i.e., new) value of the output remains
invisible until the beginning of the next delta cycle.
4. Increment time when there is no need for another delta cycle (no gate had an
input change value in the current delta cycle).

Delta-cycle simulation
with projected values

2. Each gate is simulated at most once per delta cycle.

Simple
simulation

1ns

Delta-cycle simulation
1ns

process (a) begin


b <= a;
end process;

2ns

-cycle

a
b
c

1.6.4.5

1.6.4.3 Example of Delta-Cycles:


Back-to-Back Buffers

2ns

Example of Proj Asn: Flip-Flops

p_b: process (clk) begin


if rising_edge(clk) then
b <= a;
end if;
end process;

10ns

11ns

p_c: process (clk) begin


if rising_edge(clk) then
c <= b;
end if;
end process;

b
c

process (b) begin


c <= b;
end process;

9ns

clk

Simple simulation
1ns

b
a

a
c

clk

69

CHAPTER 1. FUNDAMENTALS OF VHDL

1.6.4

Intuition Behind Delta-Cycle Simulation

71

1.6.4.6

Example of Proj Asn: Comb Loop

1ns

-cycle

-cycle

Final value

We begin with a truly parallel simulation of the circuit.

a
b

simulation of gates b,c, and d


done truly in parallel, therefore
no need for projected assignment

73

CHAPTER 1. FUNDAMENTALS OF VHDL

1.6.4

Hardware Runs in Parallel

Intuition Behind Delta-Cycle Simulation

75

Combinational Loop: Incorrect Simulation

Recall the following about the simulation done in a delta cycle:

a
b

1ns

-cycle

-cycle

The choice of in which order to simulate the gates must not affect the result.
a

1ns

-cycle

-cycle

a
1

b
0

c
0

d
0

Execution order: b, c, d

Combinational Loop: Correct Simulation

1.6.5

Execution order: b, d, c

VHDL Delta-Cycle Simulation

The algorithm presented here is a simplification of the actual algorithm in the


VHDL Standard.

a
b

Final value

The execution of each gate must be independent of the other gates.

Final value

The simulation of the gates must be done in parallel.

-cycle

-cycle

1ns

-cycle

-cycle

a
1

delayed assignments; for example: a <= b after 2 ns;


resolution, which is where multiple processes write to the same signal (usually a
mistake, but useful for tri-state busses)

b
0

c
1

d
1

Execution order: b, c, d

74

Final value

1ns

Final value

This algorithm does not support:

Execution order: b, d, c

CHAPTER 1. FUNDAMENTALS OF VHDL

1.6.5

VHDL Delta-Cycle Simulation

76

77

CHAPTER 1. FUNDAMENTALS OF VHDL

1.6.5.1 Informal Description of Algorithm


Processes have three modes:
Resumed : The process has work to do and is waiting its turn to execute.
Executing : The process is running.
Suspended : The process is idle and has no work to do.
A simulation run is initialization followed by a sequence of simulation rounds
Initialization:
Each process starts off resumed.
Each signal starts off with its default value. (U for std logic)
In each simulation round:
Increment time
Resume all processes that are waiting for the current time
A simulation round is a sequence of simulation cycles.
In each simulation cycle:
Copy projected value of signals to current value.
Resume processes based on sensitivity lists and wait conditions.
Execute each resumed process.
If no projected assignment changed the value of a signal, then increment time
and start next simulation round.

1.6.5.2

Example: VHDL Sim for Buffers

proc_a : process begin


a <= 0;
wait for 1 ns;
a <= 1;
wait;
end process;

Time
Sim rounds
Sim cycles
proc_a
proc_b
proc_c
a

0ns

proc_b : process (a)


begin
b <= a;
end process;
proc_c : process (b)
begin
c <= b;
end process;

a
values
old new

graphical
symbol

text

U 0

U U

0 1

79

CHAPTER 1. FUNDAMENTALS OF VHDL

1.6.5.3 Definitions and Algorithm


Notes on Simulation Algorithm
At a wait statement, the process will suspend even if the condition is true in the
current simulation cycle. The process will resume the next time that a signal in
the condition changes and the condition is true.

1.6.5

More Formal Description of Algorithm

( initialization )
set all signals to default value;
add to resume set all processes;
set time to 0 ns;
( simulation loop )
while time <
{

( begin simulation round )


add to resume set all processes that are waiting for current time;

If we execute multiple assignments to the same signal in the same process in


the same simulation cycle, only the last assignment actually takes effect all
but the last assignment are ignored.

while time does not change {


( begin simulation cycle )
copy projected values of signals to current values;
add to resume set any process that:
is sensitive to a signal that changed value
or whose wait-condition became true;
execute all processes in resume set;
( assign to projected values of signals )
( execute until suspend on a wait statement or sensitivity list )
clear resume set; ( resume set =
6 )
if none of the executing processes performed a signal assignment then {
increment time to the minimum of the wait times for processes;
}
}

In a simulation round, the first simulation cycle is not a delta cycle.


The mode of a process is determined implicitly by keeping track of the set of
processes that are resumed (the resume set) and the process(es) that is(are)
executing. All other processes are suspended.

VHDL Simulation Definitions


Definition simulation step: Executing one sequential assignment or process
mode change.

Definition simulation cycle: The operations that occur in one iteration of the
simulation algorithm.

Definition delta cycle: A simulation cycle that does not advance simulation
time.

Definition simulation round: A sequence of simulation cycles that all have the
same simulation time.

80

CHAPTER 1. FUNDAMENTALS OF VHDL

VHDL Delta-Cycle Simulation

81

1.6.5.4

Example: Delta-Cycle for Flip-Flops

proc_a : process
begin
a <= 0;
wait for 9 ns;
a <= 1;
wait;
end process;
Time
Sim rounds
Sim cycles
proc_a
proc_clk
proc_flops
a

clk

0ns

proc_clk : process
begin
clk <= 0;
wait for 10 ns;
clk <= 1;
wait for 10 ns;
end process;

proc_flops : process
begin
wait until re(clk);
b <= a;
c <= b;
end process;
re=rising edge

Back-to-Back Flip-Flops with If-Rising Edge


proc_flops1 :
process
begin
wait until re(clk);
b1 <= a;
c1 <= b1;
end process;
proc_flops2 :
process (clk)
begin
if re(clk) then
b2 <= a;
c2 <= b2;
end if;
end process;

Time
Sim rounds
Sim cycles
proc_a
proc_clk
proc_flops1
proc_flops2

10ns

R E

S
R E

clk

b1
U
U
c1
U
U
b2
U
U
c2
U

84

CHAPTER 1. FUNDAMENTALS OF VHDL

1.6.5.5 Ex: VHDL Sim of Comb Loop


proc_a : process begin
a <= 0;
wait for 1 ns;
a <= 1;
wait;
end process;

a
b

proc_b : process (a)


begin
b <= not( a );
end process;
proc_c : process (a,b,d)
begin
c <= not( a ) or b or d;
end process;
proc_d : process (a,c)
begin
d <= a and c;
end process;

a
b

Time
Sim rounds
Sim cycles
proc_a
proc_b
proc_c
proc_d
a

0ns

86

CHAPTER 1. FUNDAMENTALS OF VHDL

1.6.6

External Inputs and Flip-Flops

1.6.5.6 Rules and Observations for


Drawing Delta-Cycle Simulations

1.6.6

The VHDL Language Reference Manual gives only a textual description of the
VHDL semantics. The conventions for drawing the waveforms are just our own.

architecture mathilde of sauv


e is
signal clk, a, b : std_logic;
begin
process begin
clk <= 0;
wait for 10 ns;
clk <= 1;
wait for 10 ns;
end process;
process begin
wait for 10 ns;
a1 <= 1;
end process;
process begin
wait until rising_edge(clk);
a2 <= 1;
end process;
process begin
wait until rising_edge( clk );
b1 <= a1;
b2 <= a2;
end process;
end architecture;

Each column is a simulation step.


In a simulation step, either exactly one process changes mode or exactly one
signal changes value, except in the first two simulation steps of each simulation
cycle, when multiple current values may be updated and multiple processes
may resume.
If a projected assignment assigns the same value as the signals current
projected value, the assignment must still be shown, because this assignment
will force another simulation cycle in the current simulation round.
If a signals current value is updated with the same value as it currently has, this
assignment is not shown, because it will not trigger any sensitivity lists.
Assignments to signals may be denoted by either the number/letter of the new
value or one of the edge symbols:

old value

new value
U 0 1

88

External Inputs and Flip-Flops

Question: Do the signals b1 and b2 have the same behaviour from


1020 ns?

1.7

Register-Transfer-Level Simulation

U
0
1

1.7.1

Overview

Much simpler than delta cycle


Some observations about delta-cycle simulation waveforms that can be helpful in
checking that a simulation is correct:

In the first simulation step of the first simulation cycle of a simulation round (i.e.,
the first simulation step of a simulation round), at least one process will resume.
This is contrast to the first simulation step of all other simulation cycle, where
current values of signals are updated with projected values.

Columns are real time: clock cycles, nanoseconds, etc.


Can simulate both synthesizable and unsynthesizable code
Cannot simulate combinational loops
Same values as delta-cycle at end of simulation round

At the end of a simulation cycle all processes are suspended.


In the last simulation cycle of a simulation round either no signals change value,
or any signal that changes value is not in the sensitivity list of any process.

87

CHAPTER 1. FUNDAMENTALS OF VHDL

1.7. REGISTER-TRANSFER-LEVEL SIMULATION

89

90

CHAPTER 1. FUNDAMENTALS OF VHDL

Question: In this code, what


value should b have at 10 ns
does it read the new value of a or
the old value?

process begin
a <= 0;
wait for 10 ns;
a <= 1;
...
end process;

1.7.3

1.7.3

Examples of RTL Simulation

92

Examples of RTL Simulation

1.7.3.1

RTL Simulation Example 1

We revisit an earlier example from delta-cycle simulation, but change the code
slightly and do register-transfer-level simulation.

process begin
b <= 0;
wait for 10 ns;
b <= a;
...
end process;

proc1: process (a, b, c) begin


d <= NOT c;
c <= a AND b;
end process;
proc2: process (b, d) begin
e <= b AND d;
end process;

1.7.2 Technique for Register-Transfer


Level Simulation
1. Pre-processing
(a) Separate processes into timed, clocked, and combinational
(b) Decompose each combinational process into separate processes with one
target signal per process
(c) Sort combinational processes into topological order based on dependencies

proc3: process begin


a <= 1;
b <= 0;
wait for 3 ns;
b <= 1;
wait for 99 ns;
end process;

Decompose and sort comb procs


proc1d: process (c) begin
d <= NOT c;
end process;

proc1c: process (a, b) begin


c <= a AND b;
end process;

proc1c: process (a, b) begin


c <= a AND b;
end process;

proc1d: process (c) begin


d <= NOT c;
end process;

proc2: process (b, d) begin


e <= b AND d;
end process;

proc2: process (b, d) begin


e <= b AND d;
end process;

2. For each moment of real time:


(a) Run timed processes in any order, reading old values of signals.

Decomposed

Sorted

(b) Run clocked processes in any order, reading new values of timed signals
and old values of registered signals.
(c) Run combinational processes in topological order, reading new values of
signals.

91

CHAPTER 1. FUNDAMENTALS OF VHDL

1.7.3

Examples of RTL Simulation

93

94

CHAPTER 1. FUNDAMENTALS OF VHDL

Waveforms
0ns
a

1ns

2ns

3ns

102ns

Example: Procs with Multiple Waits

huey: process
begin
clk <= 0;
wait for 10 ns;
clk <= 1;
wait for 10 ns;
end process;
dewey: process
begin
a <= to_unsigned(0,4);
wait until re(clk);
while (a < 4) loop
a <= a + 1;
wait until re(clk);
end loop;
end process;

clk
a
d

louie: process
begin
d <= 1;
wait until re(clk);
if (a >= 2) then
d <= 0;
wait until re(clk);
end if;
end process;

96

1.8

CHAPTER 1. FUNDAMENTALS OF VHDL

Simple RTL Simulation in Software

1.10. DELTA-CYCLE SIMULATION WITH DELAYS

1.10

Delta-Cycle Simulation with Delays

This is an advanced section.


It is not covered in the course
and will not be tested.

1.9

Variables in VHDL
This is an advanced section.
It is not covered in the course
and will not be tested.

98

This is an advanced section.


It is not covered in the course
and will not be tested.

1.11

VHDL and Hardware Building Blocks

1.11.1

Basic Building Blocks

Different classes of building blocks:

Conditional
Arithmetic
Storage

97

CHAPTER 1. FUNDAMENTALS OF VHDL

1.11. VHDL AND HARDWARE BUILDING BLOCKS

99

100

CHAPTER 1. FUNDAMENTALS OF VHDL

Basic Building Blocks: Boolean

1.11.1

OR

gate

and gate

xor

exclusive-or gate

Basic Building Blocks: Conditional


if-then-else,
when-else,
Multiplexer
with-select,
case

adder

subtracter

asl, lsl left shifter

not inverter
nand NAND gate
nor

102

Basic Building Blocks: Arithmetic

Schematic VHDL Description


and AND gate
or

Basic Building Blocks

asr, lsr right shifter

Basic Building Blocks: Storage


D

clocked process

CE

flip flop

S
WE
A

DO

memory component single-port memory

DI

WE
A0

DO0

memory component dual-port memory

DI0
A1

101

CHAPTER 1. FUNDAMENTALS OF VHDL

DO1

1.11.1

Basic Building Blocks

103

104

CHAPTER 1. FUNDAMENTALS OF VHDL

1.11.2

Deprecated Building Blocks for RTL

Some of the common gates you have encountered in previous courses should be
avoided when synthesizing register-transfer-level hardware, particularly if FPGAs
are the implementation technology.
Latches : Use flops, not latches
T, JK, SR, etc flip-flops : Limit yourself to D-type flip-flops
Tri-State Buffers : Use multiplexers, not tri-state buffers
Note:
Unfortunately and surprisingly, PalmChip has been
awarded a US patent for using uni-directional busses (i.e.
multiplexers) for system-on-chip designs. The patent was filed in
2000, so all fourth-year design projects completed after that date
will need to pay royalties to PalmChip

What is This?
process (a)
begin
if rising_edge(a) then
c <= b;
end if;
end process;

105

CHAPTER 1. FUNDAMENTALS OF VHDL

1.11.3

1.11.3
1.11.3.1

Hardware and Code for Flops

106

Hardware and Code for Flops


Flops with Waits and Ifs

process (clk)
begin
if rising_edge(clk) then
q <= d;
end if;
end process;

VHDL Code for Flip-Flop: Wait-Style


process
begin
wait until rising_edge(clk);
q <= d;
end process;

1.11.3

Hardware and Code for Flops

107

108

CHAPTER 1. FUNDAMENTALS OF VHDL

1.11.3.2

1.11.3

Flop with Synchronous Reset: Wait-Style


process
begin
wait until rising_edge(clk);
if reset = 1 then
q <= 0;
else
q <= d;
end if;
end process;

110

Variation on a Floppy Theme

Flops with Synchronous Reset

process (clk)
begin
if rising_edge(clk) then
if (reset = 1) then
q <= 0;
else
q <= d;
end if;
end if;
end process;

Hardware and Code for Flops

Question:

What is this?

process (clk, reset)


begin
if reset = 1 then
q <= 0;
else
if rising_edge(clk) then
q <= d;
end if;
end if;
end process;

Flop with Chip-Enable


process (clk)
begin
if rising_edge(clk) then
if ce = 1 then
q <= d;
end if;
end if;
end process;
Wait-style flop with chip-enable included in course notes

109

CHAPTER 1. FUNDAMENTALS OF VHDL

1.11.3

Hardware and Code for Flops

111

112

CHAPTER 1. FUNDAMENTALS OF VHDL

1.11.3

Q: Flop with a Mux on the Input?

Hardware and Code for Flops

Behavioural Comparison

sel

d0

d0
D

114

q0
sel

sel

d0

d1

clk

d1

d1

clk

q1

clk

Question: For the two circuits above, does q have the same behaviour in
both circuits?
Mux on output

Mux on input

Q: Flops with a Mux on the Output?


d0

q0

clk
d1

sel

d0

d0

d1

d1

1.11.3.3 Flop with Chip-Enable and Mux on


Input
Hint: Chip Enable
process (clk)
begin
if rising_edge(clk) then
if ce = 1 then
q <= d;
end if;
end if;
end process;

q1

clk

113

clk

sel

sel

q
D

clk

CHAPTER 1. FUNDAMENTALS OF VHDL

1.11.3

Hardware and Code for Flops

115

116

CHAPTER 1. FUNDAMENTALS OF VHDL

1.11.3.4 Flops with Chip-Enable, Muxes,


and Reset

1.12.1

1.12.1

Initial Values

118

Initial Values

Initial values on signals (UNSYNTHESIZABLE)


This section reserved for your reading pleasure
signal bad_signal : std_logic := 0;

1.11.4

An Example Sequential Circuit

Reason: At powerup, the values on signals are random (except for some FPGAs).

This section reserved for your reading pleasure

1.12 Synthesizable vs Non-Synthesizable


Code

1.12.2

Wait For

Wait for length of time (UNSYNTHESIZABLE)


For us to consider a VHDL progam synthesizable, all of the conditions below must
be satisfied:

wait for 10 ns;

the program must be theoretically implementable in hardware


the hardware that is produced must be consistent with the structure of the
source code
the source code must be portable across a wide range of synthesis tools, in that
the synthesis tools all produce correct hardware

Reason: Delays through circuits are dependent upon both the circuit and its
operating environment, particularly supply voltage and temperature. For example,
imagine trying to build an AND gate that will have exactly a 2ns delay in all
environments.

Synthesis is done by matching VHDL code against templates or patterns.


Its important to use idioms that your synthesis tools recognize.
Think like hardware: when you write VHDL, you should know what hardware you
expect to be produced by the synthesizer.
117

CHAPTER 1. FUNDAMENTALS OF VHDL

1.12.2

Wait For

119

120

CHAPTER 1. FUNDAMENTALS OF VHDL

1.12.3

Variables

process
variable bad : std_logic;
begin
wait until rising_edge(clk);
bad := not a;
d <= bad and b;
e <= bad or c;
end process;
Use signals, do not use variables
reason The intention of the creators of VHDL was for signals to be wires and
variables to be just for simulation. Some synthesis tools allow some uses of
variables, but when using variables, it is easy to create a design that works in
simulation but not in real hardware.

1.12.4

Bits and Booleans

signal bad1 : bit;


signal bad2 : boolean;
Use std_logic signals, do not use bit or Boolean signals.
reason std_logic is the most commonly used signal type across synthesis
tools and simulation tools.

1.12.5

1.12.5

Assignments before Wait Statement

122

Assignments before Wait Statement

If a synthesizable clocked process has a wait statement, then the process must
begin with a wait statement.
process
process
c <= a;
wait until rising edge(clk);
wait until rising edge(clk);
d <= b;
wait until rising edge(clk);
d <= b;
c <= a;
wait until rising edge(clk);
end process;
end process;
Unsynthesizable
Synthesizable
Reason: In simulation, any assignments before the first wait statement will be
executed in the first delta-cycle. In the synthesized circuit, the signals will be
outputs of flip-flops and will first be assigned values after the first rising-edge.

1.12.6

Different Wait Conditions

wait statements with different conditions in a process (UNSYNTHESIZABLE)


-- different clock signals
process
begin
wait until rising_edge(clk1);
x <= a;
wait until rising_edge(clk2);
x <= a;
end process;
Reason: Would require the flip flops to use different clock signals at different
times.

121

CHAPTER 1. FUNDAMENTALS OF VHDL

1.12.6

Different Wait Conditions

123

124

CHAPTER 1. FUNDAMENTALS OF VHDL

Different Wait Conditions


-- different clock edges
process
begin
wait until rising_edge(clk);
x <= a;
wait until falling_edge(clk);
x <= a;
end process;
Reason: Would require flip-flop to be sensitive to different clock edges at different
times.

1.12.8

if rising edge and wait in Same Process

126

1.12.8 if rising edge and wait in Same


Process
An if rising edge statement and a wait statement in the same process
(UNSYNTHESIZABLE)
process
begin
if rising_edge(clk) then
q0 <= d0;
end if;
wait until rising_edge(clk);
q0 <= d1;
end process;
Reason: The idioms for synthesis tools generally expect just a single type of
flop-generating statement in each process.

1.12.7

Multiple if rising edge in Process

1.12.9

if rising edge with else Clause

Multiple if rising edge statements in a process (UNSYNTHESIZABLE)

The if statement has a rising edge condition and an else clause


(UNSYNTHESIZABLE).

process (clk)
begin
if rising_edge(clk) then
q0 <= d0;
end if;
if rising_edge(clk) then
q1 <= d1;
end if;
end process;

process (clk)
begin
if rising_edge(clk) then
q0 <= d0;
else
q0 <= d1;
end if;
end process;

Reason: The idioms for synthesis tools generally expect just a single if
rising edge statement in each process.

Reason: The idioms for the synthesis tools expect a signal to be either registered
or combinational, not both.

The simpler the VHDL code is, the easier it is to synthesize hardware.
Programmers of synthesis tools make idiomatic (idiotic?) restrictions to make their
jobs simpler.
125

CHAPTER 1. FUNDAMENTALS OF VHDL

1.12.9

if rising edge with else Clause

127

128

CHAPTER 1. FUNDAMENTALS OF VHDL

1.12.10
Paths

Loop with Both Comb and Clocked

loops where some paths are clocked and some are not (UNSYNTHESIZABLE)
process begin
while c /= 1 loop
if b = 1 then
wait until rising_edge(clk);
e <= d;
else
e <= not d;
end if;
end loop;
e <= b;
end process;
Reason: if the loop condition is true and the if-then-else condition is false, then
the combinational path is taken and the process will get stuck in an infinite loop
going through the combinational path.

1.12.11

wait Inside of a for loop

wait statements in a for loop (UNSYNTHESIZABLE)

1.12.11

wait Inside of a for loop

130

Synthesizable Alternative to Wait-Inside-For


while loop (synthesizable)
This is the synthesizable alternative to the the wait statement in a for loop above.
process
begin
-- output values from 0 to 4 on i
-- sending one value out each clock cycle
i <= to_unsigned(0,4);
wait until rising_edge(clk);
while (4 > i) loop
i <= i + 1;
wait until rising_edge(clk);
end loop;
end process;

1.13

Guidelines for Desirable Hardware

Code that is synthesizable, but undesirable (i.e., bad coding practices):

latches
process
begin
for i in 0 to 7 loop
wait until rising_edge(clk);
x <= to_unsigned(i,4);
end loop;
end process;

asynchronous resets
combinational loops
using a data signal as a clock
using a clock signal as data
tri-state buffers and signals
multiple drivers for a signal

Reason: Idiom of synthesis tools; while-loops with the same behaviour are
synthesizable.

129

CHAPTER 1. FUNDAMENTALS OF VHDL

1.13. GUIDELINES FOR DESIRABLE HARDWARE

131

132

CHAPTER 1. FUNDAMENTALS OF VHDL

1.13.1

Know Your Hardware

The most important guideline is: know what you want the synthesis tool to build for
you.

For every signal in your design, know whether it should be a flip-flop or


combinational. Check the output of the synthesis tool see if the flip flops in your
circuit match your expectations, and to check that you do not have any latches
in your design.
If you cannot predict what hardware the synthesis tool will generate, then you
probably will be unhappy with the result of synthesis.

1.13.2

Latches

134

Signals Missing from Sensitivity List


process (a)
begin
c <= a and b;
end process;
For a combinational process, the sensitivity list should contain all of the signals
that are read in the process.
reason Gives consistent results across different tools. Many synthesis tools
will implicitly include all signals that a process reads in its sensitivity list. This
differs from the VHDL Standard. A synthesis tool that adheres to the
standard will either generate an error or will create hardware with latches or
flops clocked by data sigansl if not all signals that are read from are included
in the sensitivity list.
exception In a clocked process using an if rising edge, it is acceptable to
have only the clock in the sensitivity list

1.13.2

Latches

Combinational if-then without else


process (a, b)
begin
if (a = 1) then
c <= b;
end if;
end process;
For a combinational process, every signal that is assigned to, must be assigned
to in every branch of if-then and case statements.
reason If a signal is not assigned a value in a path through a combinational
process, then that signal will be a latch.
note For a clocked process, if a signal is not assigned a value in a clock cycle,
then the flip-flop for that signal will have a chip-enable pin. Chip-enable pins
are fine; they are available on flip-flops in essentially every cell library.

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1.13.3

Asynchronous Reset

In an asynchronous reset, the test for reset occurs outside of the test for the clock
edge.
process (reset, clk)
begin
if (reset = 1) then
q <= 0;
elsif rising_edge(clk) then
q <= d;
end if;
end process;
All reset signals should be synchronous.
reason If a reset occurs very close to a clock edge, some parts of the circuit
might be reset in one clock cycle and some in the subsequent clock cycle.
This can lead the circuit to be out of sync as it goes through the reset
sequence, potentially causing erroneous internal state and output values.
1.13.3

Asynchronous Reset

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1.13.4

Combinational Loops

A combinational loop is a cyclic path of dependencies through one or more


combinational processes.
process (a, b, c) begin
if a = 0 then
d <= b;
else
d <= c;
end if;
end process;

1.13.6

1.13.6

Using a Clock Signal as Data

138

Using a Clock Signal as Data

process begin
wait until rising_edge(clk);
count <= count + 1;
end process;
b <= a and clk;
Clock signals should be used only as clocks.
reason Clock signals have two defined values in a clock cycle and transition in
the middle of the clock cycle. At the register-transfer level, each signal has
exactly one value in a clock cycle and signals transition between values only
at the boundary between clock cycles.

process (d, e) begin


b <= d and e;
end process;
If you need a signal to be dependent on itself, you must include a register
somewhere in the cyclic path.

1.13.5

Using a Data Signal as a Clock

process begin
wait until rising_edge(clk);
count <= count + 1;
end process;
process begin
waiting until rising_edge( count(5) );
b <= a;
end process;
Data signals should be used only as data.
reason All data assignments should be synchronized to a clock. This ensures
that the timing analysis tool can determine the maximum clock speed
accurately. Using a data signal as a clock clock signals can lead to
unpredictable delays between different assignments, which makes it
infeasible to do an accurate timing analysis.

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1.13.7

Tri-State Buffers and Signals


Z as a Signal Value

process (sel, a0)


b <= a0 when sel = 0
else Z;
end process;
process (sel, a1)
b <= a1 when sel = 1
else Z;
end process;
Use multiplexers, not tri-state buffers.
reason Multiplexers are more robust than tri-state buffers, because tri-state
buffers rely on analog effects such as drive-strength and voltages that are
between 0 and 1. Multiplexers require more area than tri-state buffers,
but for the size of most busses, the advantage in a more robust design is
worth the cost in extra area.
1.13.7

Tri-State Buffers and Signals

139

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Inout and Buffer Port Modes


entity bad is
port (
io_bad : inout std_logic;
buf_bad : buffer std_logic
);
end entity;
Use in or out, do not use inout or buffer
reason inout and buffer signals are tri-state.
note If you have an output signal that you also want to read from, you might be
tempted to declare the mode of the signal to be inout. A better solution is to
create a new, internal, signal that you both read from and write to. Then, your
output signal can just read from the internal signal.

1.13.8

Multiple Drivers

process begin
wait until rising edge(clk);
if reset = 1 then
y <= 0;
z <= 0;
end if;
end process;
process begin
wait until rising edge(clk);
if reset = 0 then
if a = 1 then
z <= b and c;
else
z <= d;
end if;
end if;
end process;

process begin
wait until rising edge(clk);
if reset = 0 then
if b = 1 then
y <= c;
end if;
end if;
end process;

Each signal should be assigned to in only one process. This is often called the
single assignment rule.
reason Multiple processes driving the same signal is the same as having
multiple gates driving the same wire. This can cause contention, tri-state
values, and other bad things.
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