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Jul 01, 2015

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Noise in circuits

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Noise in circuits

© All Rights Reserved

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Lecture 10

NOISE IN SC CIRCUITS

Richard Schreier

richard.schreier@analog.com

Trevor Caldwell

trevor.caldwell@utoronto.ca

Course Goals

Deepen Understanding of CMOS analog circuit

design through a top-down study of a modern

analog system

The lectures will focus on Delta-Sigma ADCs, but you

may do your project on another analog system.

some nifty little circuits

The circuit world is filled with many little gems that

every competent designer ought to recognize.

ECE1371

10-2

Date

Lecture

Ref

Homework

S&T 2-3, A

Matlab MOD2

2008-01-14 RS 2

2008-01-21 RS 3

Q-level sim

2008-01-28 TC 4

J&M 11,13

Pipeline DNL

2008-02-04

ISSCC No Lecture

Advanced '6

2008-02-11 RS 5

2008-02-18

2008-02-25 RS 6

J&M 7

2008-03-03 TC 7

SC Circuits

2008-03-10 TC 8

Amplifier Design

2008-03-17 TC 9

Amplifier Design

2008-03-24 TC 10

Noise in SC Circuits

2008-03-31 RS 11

Switching Regulator

2008-04-07

S&T C

Project Presentations

2008-04-14 TC 12

Project Report

ECE1371

10-3

Need CMFB for Gain Booster

One option is to use standard CT CMFB (Lecture 9)

Is there an easier way with less circuitry?

VB4

M11

VB3

M12

M9

M7

OUT

EFF

IN

M1

M3

ECE1371

M2

VB1

M4

IN

M5

VB4

VB3

VB2

M10

M8

OUT

M6

B2

M3

VB1

M4

10-4

Highlights

(i.e. What you will learn today)

1. How to analyze noise in switched-capacitor

circuits

2. Significance of switch noise vs. OTA noise

Power efficient solution

Impact of OTA architecture

ECE1371

10-5

Review

Previous analysis of kT/C noise

(ignoring OTA/opamp noise)

Phase 1: kT/C1 noise (on each side)

Phase 2: kT/C1 added to previous noise (on each side)

Total Noise (input referred): 2kT/C1

Differentially: 4kT/C1

ECE1371

10-6

Review

SNR

Total noise power: 4kT/C1

Signal power: V2/2

SNR: V2C1/8kT

SNR (single-ended)

Total noise power: 2kT/C1 (sampling capacitor C1)

Signal power: V2/2 (signal from -V to V)

SNR: V2C1/4kT

ECE1371

10-7

Single-Ended Example

Noise current from each transistor is I n2

Assume J 2 / 3

ECE1371

4 kTJ gm

10-8

Single-Ended Example

Thermal noise in single-ended OTA

Assuming paths match, tail current source M5 does

not contribute noise to output

8kT

PSD of noise voltage in M1 (and M2):

3 gm1

8kTgm 3

PSD of noise voltage in M3 (and M4):

3 gm2 1

Total input referred noise from M1 - M4

gm 3 16kT

16kT

Sn,eq

nf

1

gm1 3 gm1

3 gm1

Noise factor nf depends on architecture

ECE1371

10-9

Analyze output noise in single-stage OTA

Use capacitive feedback in the amplification /

integration phase of a switched-capacitor circuit

n,eq

ECE1371

10-10

Transfer function of closed loop OTA

VOUT

Vn,eq

H ( s)

G

1 s / Zo

1

G|

1 C1 / C2

Zo

E gm1

CO

for a single-stage, it is CL+C1C2/(C1+C2), while for a

two-stage, it is the compensation capacitor CC

ECE1371

10-11

Integrate total noise at output

f

2

OUT

Sn,eq (f ) H ( j 2S f ) df

0

16kT Z o 2

nf

G

3 gm1

4

4 kT

nf

3 E CO

Minimum output noise for E=1 is

4 kT

nf

3CO

to gm1 while PSD is inversely proportional to gm1

ECE1371

10-12

Graphically

wall response with a cut-off frequency of Sfo/2

Total noise at VOUT is the integral of the noise within

the brick wall filter (area is simply Sfo/2 x 1/E2)

ECE1371

10-13

What happens to noise once it gets sampled?

Total noise power is the same

Noise is aliased folded back from higher

frequencies to lower frequencies

PSD of the noise increases significantly

2

1

OUT

n,eq

ECE1371

IN

S

O,S

10-14

Vo,s

Aliased

Noise

Vout

s

G2 Sn,eq

SVout (f )

4W fS / 2

2

VOUT

fS / 2

4 kT

1

nf

3 E CO fS / 2

1

2W fS

S f3 dB

ECE1371

fS

10-15

1/f3dB is the settling time of the system, while

1/2fS is the settling period for a two-phase clock

e

1/ 2 fS

2 ( N 1)

S f3 dB

! ( N 1)ln2

fS

PSD is increased by at least ( N 1)ln2

If N = 10 bits, PSD is increased by 7.6, or 8.8dB

But noise is reduced by oversampling ratio after

digital filtering

ECE1371

10-16

Noise in a SC Integrator

Using the parasitic-insensitive SC integrator

1) Sampling Phase

Includes noise from both I1 switches

2) Integrating Phase

Includes noise from both I2 switches and OTA

ECE1371

10-17

Noise in a SC Integrator

Phase 1: Sampling

Ron1

ON

ON

Ron2

Ron

ON

C1

Time constant of R-C filter: W 2RON C1

PSD of noise voltage across C1

8kTRON

SC 1 (f )

1 (2S fW )2

ECE1371

10-18

Noise in a SC Integrator

Phase 1: Sampling

Integrated across entire spectrum, total noise power

in C1 is

8kTRON kT

VC21,sw 1

4W

C1

Independent of RON (PSD is proportional to RON,

bandwidth is inversely proportional to RON)

After sampling, charge is trapped in C1

ECE1371

10-19

Noise in a SC Integrator

Phase 2: Integrating

Noise PSD from two switches: SRon (f )

ECE1371

8kTRON

16kT

Svn,eq (f )

nf

Noise PSD from OTA:

3 gm1

Noise voltage across C1 charges to 2VRon Vn,eq

10-20

Noise in a SC Integrator

What is the time-constant?

IN

Ron

ON

1

OUT

C1

m1

1/ sC2 RL

1 gm1RL

Resulting time constant W

1

gm1

ECE1371

10-21

Noise in a SC Integrator

Total noise power with both switches and OTA

on integrating phase

VC21,op

Svn,eq (f )

4W

nf

16kT

3 gm1 4(2RON 1/ gm1 )C1

VC21,sw 2

4 kT nf

3C1 (1 x)

Introduced extra parameter x

ECE1371

SRon (f )

4W

8kTRON

4(2RON 1/ gm1 )C1

kT x

C1 (1 x)

2RON gm1

10-22

Noise in a SC Integrator

Total noise power on C1 from both phases

VC21

4 kT nf

kT x

kT

3C1 (1 x) C1 (1 x) C1

kT 4 nf / 3 1 2 x

1 x

C1

2kT

2

In this case, VC 1

C1

What was assumed to be the total noise was actually

the least possible noise!

ECE1371

10-23

Noise Contributions

Percentage noise contribution from switches

and OTA (assume nf=1.5)

100

Switch

OTA

80

60

40

20

0

0

10

x=2RONgm1

ECE1371

10-24

Noise Contributions

When gm1 >> 1/RON (x >> 1)

Switch dominates both bandwidth and noise

Total noise power is minimized

OTA dominates both bandwidth and noise

Power-efficient solution

Minimize gm1 (and power) for a given settling

time and noise

kT 4

gm1

n

1

2

x

W VC21 3

Minimized for x=0

ECE1371

10-25

Maximum Noise

How much larger can the noise get?

Depends on nf (table excludes cascode noise)

Architecture Relative VEFFs

nf

Maximum

Noise (x=0)

+dB

Telescopic/

Diff.Pair

VEFF,1=VEFF,n/2

1.5

3.kT/C1

1.76

Telescopic/

Diff.Pair

VEFF,1=VEFF,n

3.67.kT/C1

2.63

Folded

Cascode

VEFF,1=VEFF,n/2

2.5

4.33.kT/C1

3.36

Folded

Cascode

VEFF,1=VEFF,n

6.33.kT/C1

5.01

ECE1371

10-26

Using separate input caps increases noise

Each additional input capacitor adds to the total noise

Separate caps help reduce signal dependent

disturbances in the DAC reference voltages

2

1

1

I

2

1a

DAC

1

VC21

C1a

kT 4 nf / 3 1 2 x

1

...

1 x

C1

C1

ECE1371

10-27

All previous calculations assumed single-ended

operation

For same settling time, gm1,2 is the same, resulting in

the same total power [0dB]

Differential input signal is twice as large [gain 6dB]

Differential operation has twice as many caps and

therefore twice as much capacitor noise (assume

same size per side C1 and C2) [lose ~1.2dB for

nf=1.5, x=0 less for larger nf]

ECE1371

10-28

Single-Ended Noise

VC21,se

kT 4 nf / 3 1 2 x

C1

1 x

Differential Noise

VC21,diff

4 kT nf

2kT x

2kT

3C1 (1 x)

C1 (1 x)

C1

kT 4 nf / 3 2 4 x

1 x

C1

VC21,diff 4 nf / 3 2 4 x 4

4 nf / 3 1 2 x

VC21,se

ECE1371

10-29

Noise in an Integrator

What is the total output-referred noise in an

integrator?

Assume an integrator transfer function

kz 1

H ( z)

1 P (1 k ) (1 P ) z 1

1

C1

where k

and P

A

C2

2

1

1

I

C1

1

OUT

ECE1371

10-30

Noise in an Integrator

Total output-referred noise PSD

2

SC1(f ) H ( z ) SOUT (f )

SINT (f )

2

where VOUT

2

and VC 1

4 kT

nf

3 E CO

kT 4 nf / 3 1 2 x

1 x

C1

Vx2

Sx

fS / 2

To find output-referred noise for a given OSR

fS /(2OSR )

ECE1371

2

INT

SINT (f )df

10-31

a '6 modulator?

1) Find all thermal noise sources

2) Find PSDs of the thermal noise sources

3) Find transfer functions from each noise source to

the output

4) Using the transfer functions, integrate all PSDs

from DC to the signal band edge fS/2.OSR

5) Sum the noise powers to determine the total

output thermal noise

6) Input noise = output noise (assuming STF is ~1 in

the signal band)

ECE1371

10-32

Example:

fS = 100MHz, T = 10ns, OSR = 32

SNR = 80dB (13-bit resolution)

Input Signal Power = 0.25V2 (-6dB from 1V2)

Noise Budget: 75% thermal noise

Total input referred thermal noise:

2

VTH

(43.4 PV )2

IN

OUT

ECE1371

10-33

1) Find all thermal noise sources

Vni2 1

kT 4 nfA / 3 1 2 xA

C1A

1 xA

Vni2 2

kT 4 nfB / 3 1 2 xB

C1B

1 xB

2

Vno

1

4 kT

nfA

3 E ACOA

2

Vno

2

4 kT

nfB

3 E BCOB

Vn23

ECE1371

Cf 2 Cf 3

2kT

1

Cf 1

Cf 1 Cf 1

2kT

(1 2 1)

Cf 1

10-34

2) Find PSDs of the thermal noise sources

For each of the mean square voltage sources,

Sx

Vx2

fS / 2

to the output

Assume ideal integrators

z 1

H A ( z ) HB ( z )

1 z 1

STF( z ) 1

NTF( z )

(1 z 1 )2

ECE1371

1

1 2H ( z) H ( z )2

10-35

3) Find transfer functions from each noise source

to the output

From input of HA(z) to output

NTFi 1 ( z )

2H ( z) H ( z) NTF( z)

2

2H ( z ) H ( z )2

1 2H ( z) H ( z )2

2 z 1 z 2

NTFo1 ( z )

2 H ( z) NTF( z)

2 H ( z)

1 2H ( z) H ( z )2

ECE1371

(1 z 1 )(2 z 1 )

10-36

3) Find transfer functions from each noise source

to the output

From input of HB(z) to output

NTFi 2 ( z )

H ( z ) NTF( z )

H ( z)

1 2H ( z ) H ( z )2

z 1 (1 z 1 )

function at input of summer to output)

NTFo 2 ( z )

(1 z 1 )2

NTF( z )

ECE1371

10-37

3) Find transfer functions from each noise source

to the output

Most significant is NTFi1

20

Magnitude (dB)

Signal Band

0

-20

|NTFi1|

|NTFo1|

-40

|NTFi2|

|NTFo2|

-60 -3

10

ECE1371

10

-2

10

Normalized Frequency

-1

10-38

4) Using the transfer functions, integrate all PSDs

from DC to the signal band edge fS/2.OSR

Use MATLAB/Maple to solve the integrals

N

Vni2 1

fS / 2

2

i1

fS /(2OSR )

NTFi 1 (f ) df

2fS

Vni2 1 5fS

S

sin

fS / 2 2 OSR S

OSR

N

2

Vno

1

fS / 2

2

o1

fS /(2OSR )

NTFo1 (f ) df

2

2fS

Vno

S

S 9fS

S

1 7 fS

sin

cos

sin

fS / 2 OSR S

OSR

OSR S

OSR

ECE1371

10-39

4) Using the transfer functions, integrate all PSDs

from DC to the signal band edge fS/2.OSR

N

2

i2

fS

Vni2 2 fS

S

sin

fS / 2 OSR S

OSR

2

o2

2

2

Vno

2 Vn 3

fS / 2

fS

3fS

S

S

OSR S sin OSR cos OSR

S

sin

S

OSR

4fS

ECE1371

10-40

5) Sum the noise powers to determine the total

output thermal noise

Assume xA = xB = 0.1 and nfA = nfB = 1.5

2.9kT 1

2kT

S2

2.9kT S 2

V |

C1A OSR E ACOA 3OSR 3

C1B 3OSR3

2

TH

2kT

S4

8kT S 4

E BCOB 5OSR5 Cf 1 5OSR5

(assume EA = EB = 1/3)

2

VTH

| 9.1u 10 2

kT

kT

kT

6.0 u 10 4

2.9 u 10 4

C1A

COA

C1B

ECE1371

10-41

6) Input noise = output noise (assuming STF is ~1

in the signal band)

2

VTH

| 9.1u 10 2

kT

C1A

(43.4 PV )2

Assuming other capacitors are smaller than C1A,

then subsequent terms are insignificant and the

approximation is valid

If lower oversampling ratios are used, other terms

may become more significant in the calculation

ECE1371

10-42

Similar procedure to '6 modulator, except

transfer functions are much easier to compute

Differences

Input refer all noise sources

Gain from each stage to the input is a scalar

Noise from later stages will be more significant since

typical stage gains are as low as 2

Sample-and-Hold adds extra noise which is input

referred with a gain of 1

Entire noise power is added since the signal band is

from 0 to fS/2 (OSR=1)

ECE1371

10-43

Example

If each stage has a gain G1, G2, GN

N

2

i

2

2

2

2

2

Vno

Vno

VnoN

1 Vni 2

2 Vni 3

V

2 2

G12

G12G22

G1 G2 GN2

2

ni 1

ECE1371

10-44

ECE1371

10-45

1. Noise analysis for switched-capacitor circuits

2. Contributions of both switch noise and OTA

noise

Finding a power efficient solution

Significance of OTA architecture

ECE1371

10-46

General:

1) Corners: Do not need to simulate

2) Noise analysis: use calculations to size the

capacitors, but use Cadence to find OTA noise

3) Clock Generator: dont need to design nonoverlapping clock generator, but buffer the ideal

clocks and take into account the buffer size for

power calculations (if you have other clock phases

not just I1 and I2 you should indicate how you

would generate these)

4) Biasing: Ideal voltage source for VDD/VSS and

reference ladder edges; Ideally one current source

from which all currents are derived (at least use

only one current source per circuit block)

ECE1371

10-47

Presentation: 15-20 minutes

12 Slides (1 title, 11 content)

Focus on major design issues and circuit blocks

(what you consider the most important design

decisions)

Report

We should be able to replicate your circuit with the

information provided in the report

Give transistor sizes, preferably annotated on figures

Try to avoid Cadence schematics (if you use them,

make them more readable without all the unnecessary

annotations)

ECE1371

10-48

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