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1 DSP Applications
INTRODUCTION TO DSP
PROCESSORS
Voice mail
Digital cameras
Navigation equipment
Modems
Audio production
Noise cancellation
Videoconferencing
Medical ultrasound
Pagers
Patient monitoring
Music synthesis, effects
Radar
INTRODUCTION TO DSP
PROCESSORS
16.1 DSP Applications
16.2 The Evolution of DSP Processors
16.3 The TMS320C6xxx Core CPU
Architecture
16.4 The TMS320C6xxx Memory Architecture
16.5 The TMS320C6xxx Peripherals
16.6 The TMS320C6xxx Software
Development
611 37100 Lecture 16-2
Disadvantages
Speed and cost
Longer hardware and software design time
Problem of Finite word length error
611 37100 Lecture 16-7
Data path
DSP Processors
General-Purpose Processor
Specialized hardware
performs all key arithmetic
operations in 1 cycle.
Shifters
Guard bits
Saturation
Instruction set
DSP Processors
General-Purpose Processor
Specialized, complex
instructions
General-purpose instructions
Memory architecture
DSP Processors
General-Purpose Processor
Harvard architecture
Typically 1 access/cycle
No cacheson-chip SRAM
Addressing
DSP Processors
General-Purpose Processor
Dedicated address
generation units
Specialized addressing
modes; e.g.:
General-purpose addressing
modes
Modulo (circular)
Clock rates
Numeric representations
Autoincrement
Sampling rates
Fixed-point numeric
Float-point numeric
TMS32010)
Introduced in 1982
16-bit fixed-point
Harvard architecture
Accumulator
Specialized instruction set
390 ns MAC time
(228 ns today)
INTERNAL BUS
DATA
CPU
PERIPHERALS
MEMORY
ADDRESS
EMIF
DP
(1 cycle)
On chip memory
Data RAM
Program RAM
DC
(1 cycle)
[8 units]
On chip peripherals
Internal buses
EMIF (External Memory Interface)
PG
PR*
Memory
PS
PW
Data Path 2
Control Registers
Test, Emulation, Control
And Interrupt Logics
Data Path 2
Register File A
Register File B
Control Registers
Test, Emulation, Control
And Interrupt Logics
.D1
*A0
Register
File A
Data path 1
Data path 2
.D2
DA2
B1
*B0
Register
File B
Cross paths
Cross paths enable linking of one side of the
CPU to the other.
Type of operand cross paths:
Data cross path
Address cross path
Functional units
There are four functional units for each data path.
. L units
.M units
.S units
.D units
Register a
a
MPY
a,b,c
MPYH
a,b,c
MPYHL
a,b,c
MPYLH
a,b,c
Register b
X
Register c
=
axb
AxB
Axb
axB
Functional units
Control registers
The C62xx devices have 10 registers for control
purposes, while the C67xx have 13 control
registers.
Reading and writing to the control registers can
only be performed via the .S2 unit.
All the control registers can only be accessed by
the MVC (move constant) instruction.
Register files
Each data path contains a register file composed
of 16 32-bit general purpose registers (A0-A15
for data path 1 and B0-B15 for data path 2).
These registers can support 32- and 40-bit fixed
point data or 64-bit double-precision floating point
data for the case of the C67xx.
The general-purpose register can be used for:
Data
Data address pointer
Conditional registers
Control registers
Memory map
Memory map 0 (direct execution)
Memory map
point operations
Cache architecture
Internal memory
TMS320C6000 Peripherals
10
Internal timers
Full-duplex communication
Double-buffered data registers, which allow a continuous
data stream
Independent framing and clocking for reception and
transmission
Direct interface to industry-standard codecs, analog
interface chips (AICs), and other serially connected A/D
and D/A devices
External shift clock generation or an internal programmable
frequency shift clock
Internal timers
The timer has two signaling modes and can be
clocked by an internal or an external source.
The timer has an input pin (TINP) and an output
pin (TOUT). The TINP pin can be used as a
general-purpose input, and the TOUT pin can be
used as a general-purpose output.
With an internal clock, the timer can signal an
external A/D converter to start a conversion, or it
can trigger the DMA controller to begin a data
transfer.
With an external clock, the timer can count
external events and interrupt the CPU after a
specified number of events.
Interrupts
The C62x/C67x CPU has 14 interrupts. These
are reset, the nonmaskable interrupt (NMI), and
interrupts 415. These interrupts correspond to
the RESET, NMI, and INT4INT15 signals on the
CPU boundary.
In some C62x/C67x devices, these signals may
be tied directly to pins on the device, connected
to on-chip peripherals, or may be disabled
permanently by being tied inactive on chip.
Generally, RESET and NMI are connected
directly to pins on the device.
11
Interrupts
Interrupts
Interrupts
Instruction set
Interrupt source
ISFP address
Reset
0x0000
NMI
0x0020
Reserved
0x0040
Reserved
0x0060
INT4
0x0080
INT5
0x00A0
INT6
0x00C0
INT7
0x00E0
INT8
0x0100
INT9
0x0120
INT10
0x0140
INT11
0x0160
INT12
0x0180
INT13
0x01A0
INT14
0x01C0
INT15
0x01E0
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Instruction syntax
Label
Mnemonic
Instruction
Directive
Unit specifier
Operand field
A register (e.g. A1) or a register pointer (e.g. *A1)
A symbol (e.g. loop) or constant (e.g. 390)
An expression (e.g. if label >= 100)
Comment field
Pipeline operation
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Pipeline operation:
One execute packet per fetch packet
C compiler
Assembly optimizer
Assembler
Linker
Evaluation tools
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