http://www.rficdesign.

com/vlsi-interview-question
1. Go through VLSI book from beginning to the end
2. If possible solve all the problems at the end of the chapter
3. Most basic question is draw digital gates using transistors, difference between bipolar and
cmos , analog and digital
4. Go through the details on your project
5. Refresh your circuit theory, basic LCR circuit , transfer function , ..

Additional questions can be reffered as

• vlsi interview 6
• Verilog interview Question
• analog IC interview
• asic interview 4
• asic interview 3
• asic interview 2
• vlsi interview 3
• vlsi interview 4
• vlsi interview 7
• vlsi interview 5
• electronics interview
• vlsi interview question 2
• asic interview 1
• vlsi interview question 1
• analog IC Interview 2
• VLSI Interview 2
• VLSI Interview 3
• VLSI Interview 4
• VLSI Interview 5
• ASIC Interview
• VLSI Interview 6
• VLSI Interview 7

1. before going for these types of interview questions , study any good vlsi book
2. measure your capability by your shelf, you can go to any chapter end questions and see
how many questions you can solve
3. for experienced professionals prepare one of your projects thoroughly, most common
question for vlsi experienced professionals is explain one of the projects , remember you have
to explain relevant experience which are suitable for the job requirement
4. for fundamentals you may be asked on deep sub micron technology , channel length
modulation, mos characteristics, noise , ..

vlsi interview questions and answers

1) Give two ways of converting a two input NAND gate to an inverter
2) Given a circuit, draw its exact timing response. (I was given a Pseudo Random Signal
Generator; you can expect any sequential ckt)
3) What are set up time & hold time constraints? What do they signify? Which one is critical
for estimating maximum clock frequency of a circuit?
4) Give a circuit to divide frequency of clock cycle by two
5) Design a divide-by-3 sequential circuit with 50% duty circle. (Hint: Double the Clock)
6) Suppose you have a combinational circuit between two registers driven by a clock. What
will you do if the delay of the combinational circuit is greater than your clock signal? (You can’t
resize the combinational circuit transistors)
7) The answer to the above question is breaking the combinational circuit and pipelining it.
What will be affected if you do this? What are the different Adder circuits you studied?
9) Give the truth table for a Half Adder. Give a gate level implementation of the same.
10) Draw a Transmission Gate-based D-Latch.
11) Design a Transmission Gate based XOR. Now, how do you convert it to XNOR? (Without
inverting the output)
12) How do you detect if two 8-bit signals are same?
13) How do you detect a sequence of “1101? arriving serially from a signal line?
14) Design any FSM in VHDL or Verilog

additional questions

what is your roles and responsibilities in that project

what all cores where present in that chip
what is the technology like 130,90,65,45nm
what is the clock-frequency
how many clock-domains
what is the voltage value
what is the macro-count
what is the flip-flop count
what are the various analog macros
how many pads were there
what is your skew you had achieved
what is your insertion delays
what is your pll jitter
how did you model your uncertainities or variations
how many power-domains were there
did you have multi-VDD
if you had multi-VDD how did you handle insertion of level-shifters
what is the SSN(simultaneous switching noise) pad ratios used in your design.
how did you prevented noise in your chip
how many placeable instances
what is the cell-row utilization
is your design pad-limited or core-limited
did you multiplexed your pads
what type of package wafer bond or flip-chip
if flip-chip how did you distributed power bumps any special strategy
how many metal layers in your technology
did you used in house library or from any vendor
what is the die-area of your chip