A

New Single Phase AC to DC Harmonic Reduction Converter Based on the Voltage-Doubler Circuit
H.O. Aintablian, H.W. Hill Department of Electrical and Computer Engineering Ohio University Athens, OH 45701

Abrtrrct-Nodom power oloctronic e i p a t that U80 .witch-modo tocbnology aro major 80urcoa of harmonic currontm. Sovoralmethod8 of pawor factor hprovomont through h a d c elimination havo boon dovolopod that u80 high froquoncy -itch08 to activoly 8hapo tho input curront. In +hi8 papor, a minglophaso harmonic roduction aircuit ba8od on tho voltago-doublor circuit 18 pr08mt.d that U808 a witch opratod on lino-froquoncy. Significant roduction of tho l'HD of tho mapply curront i 8 achiovod with tho p o o . rp8d mothod. Thoorotical, mimulation and laboratory wavoform8 of tho input curront and it# harmonic cosagononto aro promontod. Tho advantage8 and di88dVatag08 Of tho p o o . rp8d circuit aro atlinod.

due to their high costs and low reliabilities [ 2 1 . This paper describes a singlephase harmonic reduction circuit based on line-frequency operation using the voltage-doubler circuit with an additional switch. Theoretical and simulation results depicting the input current waveform of the new circuit and its harmonic currents are presented. Finally, the proposed circuit is tested in a laboratory setting and experimental results are discussed.

11. DESCRIPTION AND ANALYSIS

OF THE PROPOSED CIRCUIT
The proposed harmonic reduction circuit that is based on the voltagedoubler circuit is shown in figure 1. The new circuit has an additional switch that is operated on line frequency (60 Hz). When the switch is open the circuit acts as a full-wave bridge rectifier. During each halfcycle a pair of diodes conduct until the dc output voltage rises above the supply voltage. When the switch is closed the circuit acts as a voltagedoubler rectifier each capacitor getting charged to approximately the peak of the ac voltage. To better understand the operation of the new circuit, the circuit of the uncompensated bridge rectifier is considered first as shown in figure 2.

I. INTRODUCTION
The Switch-mode power supplies employed in personal computers and other non-linear loads generate high levels of harmonic currentsIl1. The triplen harmonic components of the input current are a major concern to the power engineer since these components add in phase in the neutral conductor of an existing power system[ll. It is in the interest of the computer industry to build harmonic-free power supplies in order to extract more power from a wall outlet. The excessive harmonic currents due to the increase in the usage of switch-mode technology have led to legislation of new standards to limit harmonics; among them are the IEEE-519 and the IEC-555 121. In the past 10 years an ample amount of literature has been published dealing with methods of power factor improvement of single-phase ac-to-dc converters through harmonic elimination. Among the different harmonic elimination circuits, the boost converter is the most popular and has a high performanceI21. However, active methods of power factor correction such as the boost methods have not gained marketability

Figure 1: Schematic of the proposed harmonic reduction circuit

0-7803-1328-3/94$03.0001994 IEEE

452

PSpice analysis of the circuit of Figure 3 figure 2 was performed. shows the PSpice results of the input current waveform of the bridge rectifier circuit. The current can be pulsewidth of figure 3 increased by stepping up the supply voltage before the current starts to flow and after the current becomes zero. This is achieved by operating the circuit of figure 1 as a voltagedoubler (switch is closed) outside the normal current conduction times. The switch is opened during the normal current conduction time and the circuit operates as an ordinary bridge rectifier. Figures 4 shows the simulated input current waveform when the new scheme is used. The durations of the conduction periods (t,and t, in figure 4) of the switch can be determined either by performing a PSpice simulation or a theoretical analysis of the bridge rectifier circuit and reading the zero crossings of the input current. Figures 5 and 6 show the input current magnitude spectra of the bridge rectifier circuit and the new harmonic reduction circuit obtained by Pspice. It is obvious from these
A

4 Mt a

WllshoOen

.I . .

Figure 4: Input current waveform of the proposed circuit obtained by Pspice

Figure 5: Magnitude spectrum of input current of bridge rectifier obtained from PSpice Figure 2 : Schematic of uncompensated bridge rectifier circuit

4 t

I

I

t
I

i

4
I
U ' .
Y

i i 1

i
I

Figure 3 : Input current waveform of uncompensated bridge-rectifier circuit simulated by PSpice

453

figures that the harmonic content of the input current decreases significantly with the new circuit. The total harmonic distortion (THD) can be calculated from equation 1 [ 3 1 .

m - 1 0 0

@
I 1

(1)

The current shown in fiaure 5 has a THD of 69.5% while the current of figure 6 has a THD of 39.4%. Moreover, the third harmonic component of the current is reduced from .615 A to .21 A , a reduction of 65.8%.

111. THEORETICAL ANALYSIS
The analysis of the voltage-doubler circuit is very similar to the analysis of the bridge rectifier circuit. The equivalent circuit of a bridge rectifier which represents the input section of a typical power supply is shown in figure 7.

Figure 8: Theoretical voltage and current waveforms for C=O.5 mF, L=l mH and R = 1 0 0 f2

1

D

m d

Figure 7: Equivalent Circuit of bridge rectifier Figure 9 : Theoretical current waveform of the proposed harmonic reduction circuit The equivalent circuit is analyzed under both transient and steady-state conditions. The appendix outlines the details of the analysis and the formulas that are generated. Figure 8 shows waveforms of the input current and the output voltage over the positive half-cycle for C=0.5 mF, L=l mH and R=100 ohms. This analysis can be extended to the voltage-doubler circuit by choosing the appropriate capacitance and initial conditions. First, the circuit is analyzed as a voltagedoubler with C=0.5 mF. Near the end of the first conduction period the

analysis is switched to the bridge rectifier by dividing the capacitance by two (two capacitors in series) and using double the output voltage as an initial condition. When the current reaches zero the analysis is switched back to the voltage-doubler circuit. The input current waveform of the new harmonic reduction circuit is shown in figure 9 . It resembles the simulation results of figure 4 closely.

454

IV. LABORATORY VERIFICATION
prototype circuit as shown in figure 1 0 was developed to verify the operation of the proposed circuit.
A

Vln

-.

-

-

+

-

coEmyxcRcurr

Figure 11: Control circuit voltages

L U -

n

PoWERcIm
Figure 1 0 : Laboratory circuit

The control circuit uses a window comparator that gives an output high when the input voltage falls between , preset lower and upper limits V and V, ,. The signals of Vi*, V , V and V , , , are shown in figure 11. The npn transistor 42 in the power circuit is used as a switch during the positive , half-cycle and is controlled by V. A pnp transistor (not shown in figure 1 ) is connected back-to-back to Q2 1 and performs the switching function during the negative half-cycle. In the power circuit the ac supply voltage was set at 3 0 V instead of 1 2 0 V in order not to exceed the ratings of the components that were available.

The shape of the input current should not be affected by this because the magnitudes of the harmonics would be off by a constant factor. In addition, to keep the control circuit , had simple the control voltage v half-wave symmetry i.e. the conduction periods of the switch were chosen to be equal. The harmonic components of the input current would be lower in magnitude if this simplification was not made. Time waveforms were measured in the laboratory using an HP Signal Analyzer (HP 3 5 6 1 A ) . Figure 1 2 shows the time waveform of the input current for the bridge rectifier circuit and figure 1 3 shows its magnitude spectrum. As can be seen in figure 1 3 the harmonic content of the input current is quite high. Figures 14 and 1 5 show the corresponding waveforms of the proposed harmonic reduction circuit. In figure 15, there is a significant reduction in the harmonic components of the input current in particular the third harmonic current. The THDs of figures 1 3 and 15 are 7 0 . 1 % and 3 0 . 7 % respectively.

V. CONCLUSIONS
This paper describes a harmonic reduction ac-to-dc converter based on a line-frequency voltage-doubler circuit with a switch. Simulation and experimental waveforms of the supply current are presented. The current

455

0

I

4

@

a
-W

1
lb
11

14

l@

o

I

4

6

a
*on*)

io

iz

1
14
1 1

Figure 12: Laboratory waveform of input current without harmonic reduction

Figure 14: Laboratory waveform of input current with harmonic reduction

J
l t

3 =-

I :::
A

-0rg

Figure 13: Measured magnitude spectrum of input current waveform without harmonic reduction

harmonics are reduced substantially by carefully closing and opening a switch during half a cycle, thus increasing the pulsewidth of the current. The THD of the input current is reduced considerably and so is the magnitude of the third harmonic. The advantages of this ac-to-dc harmonic reduction converter over the high-frequency boost converter are its low cost, high reliability and simplicity of control. The disadvantage is its inability to eliminate the harmonic currents completely. The proposed method of harmonic reduction can be applied to loads of a wide power range. In situations where the load is highly variable a controller can be added that detects the zero crossings of the current and can set the firing angles

of the switch for maximum harmonic reduction. VI. APPENDIX Two modes of operation exist for the circuit of figure 7. During mode #1, the diode is forward biased and the capacitor charges through the supply. During mode # 2 , the diode is reverse biased and the capacitor discharges through the load. The current and voltage waveforms are illustrated in figure 8. To find the supply current i(t) and the output voltage v,(t), the circuit of figure 7 is examined under both transient and steady state conditions. During mode #1, using Kirchhoff's laws yields,

456

During mode #2, the capacitor discharges with a time constant R x C and

(3)
In ( 3 ) the second-order differential equation is solved for v,(t) and from ( 2 ) the response i(t) is obtained. The complete response is the sum of the natural response and the forced response.

The following initial conditions are applied in order to find the constants K,, K and K : , , During mode #1, vc(0) = v at end of mode # 2 , i(0) = 0 During mode #2,

Where,

v,(O) = v, at end of mode #1
VII. REFERENCES [ l l H.O.Aintablian, H.W.Hil1, Jr., 'Harmonic Currents of Personal Computers and their Effects on the Distribution System Neutral Current,' Proceedings of the IAS Annual Meeting, Oct. 93, Toronto, Ontario. [21 T.S. Key, Jih-Sheng Lai, "Comparison of Standards and Power supply Design Options for Limiting Harmonic Distortion in Power Systems," IEEE Trans. on Ind. Appl., VOL. 29, NO. 4 , PP. 688-695, July/Aug. 93.
[ 3 ] N. Mohan, T.M. Undeland, W.P. Robbins, 'Power Electronics: Converters, Applications and Design,' PP. 26-33, J. Wiley & Sons, NY, 1 9 8 9 .
[ 4 1 M.A.Geisler, "Predicting Power Factor and Other Input Parameters for Switching Power Supplies,' Proceedings of APEC , March 90, Dallas, Texas.

a=-- 1 RC

The constants K1 and K , are determined by applying initial conditions to the complete response. The forced response of vc(t) is given by :

where,

[51 P.N. Enjeti, R. Martinez, " A High Performance Single Phase AC to DC Rectifier with Input Power Factor Correction,' Proceedings of APEC, March 93, San Diego, California.

457