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TPD4E6B06
SLVSCK3 MAY 2014

TPD4E6B06 4-CH Bidirectional Low Capacitance ESD Protection Device With 15 kV


Contact and Ultra Low Clamping Voltage
1 Features

3 Description

The TPD4E6B06 is a four channel Electrostatic


Discharge (ESD) Protection device in an ultra small
DPW package. It is the industrys smallest 4-CH
Transient Voltage Suppressor (TVS) diode with a
0.48-mm pitch. This larger pitch helps save on printed
circuit board (PCB) manufacturing costs. The device
provides IEC61000-4-2 compliance up to 15kV
contact discharge. It has an ESD clamp circuit with
back-to-back diodes for bipolar/bidirectional signal
support. The 4.8-pF (Typ) line capacitance is suitable
for a wide range of applications supporting data rates
up to 700 MHz.

IEC 61000-4-2 Level 4


15 kV (Contact Discharge)
15 kV (Air Gap Discharge)
IEC 61000-4-5 (Surge): 3 A (8/20 s)
IO Capacitance: 4.8 pF (Typ)
RDYN: 0.75 (Typ)
DC Breakdown Voltage: 6 V (Min)
Ultra Low Leakage Current: 100 nA (Max)
Clamping Voltage: 10 V (Max at IPP = 1 A)
Industrial Temperature Range: 40C to 125C
Space Saving DPW Package (0.8 mm x 0.8 mm)

Device Information(1)
PART NUMBER

PACKAGE

BODY SIZE (NOM)

2 Applications

TPD4E6B06

(1) For all available packages, see the orderable addendum at


the end of the datasheet.

Audio Lines
Microphone
Earphone
Speakerphone
SD Interface
SIM Interface
Mobile Keyboard or Other Buttons
Cell Phones
eBook
Portable Media Players
Digital Camera
Tablet PC
Wearables

X2SON (4)

0.80 mm 0.80 mm

4 Simplified Schematic

2
GND

System

Connector

1
1

GND

0.8 mm x 0.8mm X2SON Package


(Bottom View)

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPD4E6B06
SLVSCK3 MAY 2014

www.ti.com

Table of Contents
1
2
3
4
5
6
7

Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................

1
1
1
1
2
3
3

7.1
7.2
7.3
7.4
7.5
7.6

3
3
4
4
4
5

Absolute Maximum Ratings ......................................


Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................

8.2 Functional Block Diagram ......................................... 7


8.3 Feature Description................................................... 7
8.4 Device Functional Modes.......................................... 8

Application and Implementation .......................... 8


9.1 Application Information.............................................. 8
9.2 Typical Application ................................................... 8

10 Layout................................................................... 10
10.1 Layout Guidelines ................................................. 10
10.2 Layout Examples................................................... 10

11 Device and Documentation Support ................. 11


11.1 Trademarks ........................................................... 11
11.2 Electrostatic Discharge Caution ............................ 11
11.3 Glossary ................................................................ 11

12 Mechanical, Packaging, and Orderable


Information ........................................................... 11

Detailed Description .............................................. 7


8.1 Overview ................................................................... 7

5 Revision History

DATE

REVISION

NOTES

May 2014

Initial release.

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6 Pin Configuration and Functions


5 Terminal X2SON (DPW) Package
0.8 mm 0.8 mm
(Bottom View)

IO1

IO2

2
GND

IO3

IO4

Pin Functions
PIN

TYPE

DESCRIPTION

NAME

NO

IO1

IO

ESD protected line

IO2

IO

ESD protected line

IO3

IO

ESD protected line

IO4

IO

ESD protected line

GND

Ground

7 Specifications
7.1 Absolute Maximum Ratings (1) (2)
over operating free-air temperature range (unless otherwise noted)
Operating Temperature
IEC 61000-4-5 Current (tp 8/20 s)

Peak Pulse
(1)
(2)
(3)

MIN

MAX

UNIT

-40

125

(3)

IEC 61000-4-5 Power (tp 8/20 s) (3)

40

Absolute maximum ratings apply over recommended junction temperature range.


Voltages are with respect to GND unless otherwise noted.
Measured at 25C

7.2 Handling Ratings


Tstg

Storage temperature range

V(ESD)

(1)
(2)

Electrostatic discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all


pins (1)
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)

MIN

MAX

UNIT

65

155

kV

500

500

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as 2 kV
may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 500 V
may actually have higher performance.

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SLVSCK3 MAY 2014

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7.3 Recommended Operating Conditions


over operating free-air temperature range (unless otherwise noted)
MIN

MAX

UNIT

VIO

Input pin voltage

5.5

5.5

TA

Operating free-air temperature

40

125

7.4 Thermal Information


TPD4E6B06
THERMAL METRIC (1)

DPW

UNIT

5 PINS
RJA

Junction-to-ambient thermal resistance

291.8

RJC(top)

Junction-to-case (top) thermal resistance

224.2

RJB

Junction-to-board thermal resistance

245.8

JT

Junction-to-top characterization parameter

31.4

JB

Junction-to-board characterization parameter

245.6

RJC(bot)

Junction-to-case (bottom) thermal resistance

195.4

(1)

C/W

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics


TA = 40C to 125C (unless otherwise specified)
PARAMETER

TEST CONDITION

MIN

VRWM

Reverse stand-off voltage

IIO = 10 A

VBRF

Break-down voltage

IIO to GND = 1 mA

VBRR

Break-down voltage

IGND to IO = 1 mA

ILEAK

Leakage current

VIO = 5 V

VCLAMP

Clamp voltage with ESD strike

RDYN

Dynamic resistance

CL

IO Capacitance

(1)
(2)

TYP

5.5

MAX
5.5

UNIT
V
V
V

100

nA

I = 1 A, IO to GND, 8/20 s (1)

10

(1)

I = 5 A, IO to GND, 8/20 s

13

I = 1 A, IO to GND, 8/20 ss (1)

I = 5 A, IO to GND, 8/20 s (1)

13

(2)

0.75

GND to any IO Pin (2)

0.65

Any IO to GND Pin


VIO = 2.5 V

4.8

pF

Non-repetitive current pulse 8/20 us exponentially decaying waveform according to IEC61000-4-5


Extraction of RDYN using least squares fit of TLP characteristics between I = 10 A and I =20 A

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60

10

50

40

10

Amplitude (dB)

30
20

20
30

10

40

50

10
15

15

30

45

60 75 90
Time (ns)

60
15

105 120 135 150

Figure 1. IEC 61000-4-2 Clamping Voltage, +8kV Contact


10

10

8
Current (A)

Current (A)

45

60 75 90
Time (ns)

105 120 135 150


G002

6
5
4

6
5
4

1
0

12
15
18
Voltage (V)

21

24

27

30

G003

Figure 3. TLP, tPW = 100nS, tRISE = 10nS, IO to GND

12
15
18
Voltage (V)

21

24

27

30
G004

Figure 4. TLP, tPW = 100nS, tRISE = 10nS, GND to IO


50

0.0010

4.0

0.0008

3.6

0.0006

3.2

40

0.0004

2.8

35

2.4

30

2.0

25

1.6

20

0.0004

1.2

15

0.0006

0.8

10

0.4

Current (A)

Current (A)

30

RDYN = 0.42
tPW = 100 ns*
tRISE = 10 ns*

15

Figure 2. IEC 61000-4-2 Clamping Voltage, -8kV Contact

RDYN = 0.45
tPW = 100 ns*
tRISE = 10 ns*

G001

0.0002
0.0000
0.0002

0.0008
0.0010
10 8

0.0

0
2
4
Voltage (V)

10

12

Current
Power

10

15

20
25
30
Time (s)

35

40

45

50

45

Power (W)

Voltage (V)

7.6 Typical Characteristics

0
G006

G005

Figure 6. Surge Curves, IO to GND

Figure 5. IV Curve

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Typical Characteristics (continued)


6.0

45

5.8

3.2

40

5.6

2.8

35

5.4

2.4

30

2.0

25

1.6

20

1.2

15

0.8

10

0.4

Current (A)

0.0

10

15

20
25
30
Time (s)

35

40

45

50

Power (W)

Current
Power

3.6

Capacitance (pF)

50

4.0

5.2
5.0
4.8
4.6
4.4
4.2

4.0

0.5

Figure 7. Surge Curves, GND to IO

Loss (dB)

1.5

G007

2
2.5
3
Bias Voltage (V)

3.5

4.5

5
G008

Figure 8. Capacitance

3
0
3
6
9
12
15
18
21
24
27
30
33
100k

1M

10M
100M
Frequency (Hz)

1G

3G
G009

Figure 9. Insertion Loss

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8 Detailed Description
8.1 Overview
The TPD4E6B06 is a four channel ESD Protection device in an ultra small DPW package. It is the industrys
smallest 4-CH ESD protection device with 0.48-mm pitch. This larger pitch helps save on PCB manufacturing
costs. The device provides IEC61000-4-2 compliance up to 15-kV contact discharge. It has an ESD clamp circuit
with back-to-back diodes for bipolar/bidirectional signal support. The 4.8-pF (Typ) line capacitance is suitable for
a wide range of applications supporting frequencies up to 700 MHz.

8.2 Functional Block Diagram

IO1

IO2

IO3

IO4

GND

8.3 Feature Description


8.3.1 IEC 61000-4-2 Level 2 ESD Protection
The IO pins can withstand ESD events up to 15 kV contact and 15 kV air. An ESD/surge clamp diverts the
current to ground.
8.3.2 IEC 61000-4-5 Surge Protection
The IO pins can withstand surge events up to 3 A and 40 W (8/20 s waveform). An ESD/surge clamp diverts
this current to ground.
8.3.3 IO Capacitance
The capacitance between any IO pin to ground is 4.8 pF (Typ). This capacitance supports frequencies up to 700
MHz.
8.3.4 RDYN
The low RDYN of 0.75 (Typ) allows for lower clamping voltages.
8.3.5 DC Breakdown Voltage
The DC breakdown voltage of any IO pin is a minimum of 6 V. This ensures that sensitive equipment is
protected from surges above the reverse standoff voltage of 5.5 V (Min).
8.3.6 Ultra Low Leakage Current
The IO pins feature an ultra-low leakage current of 100 nA (Max) with a bias of 2.5 V.

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Feature Description (continued)


8.3.7 Clamping Voltage
The IO pins feature an ESD clamp capable of clamping the voltage to 10 V (IO to GND) or 9 V (GND to IO) of
IEC61000-4-5 surge when IPP = 1 A.
8.3.8 Industrial Temperature Range
This device features an industrial operating range of 40 C to 125 C.
8.3.9 Space Saving DPW Package
The small 0.8 mm x 0.8 mm package size saves board space and makes it easy to add ESD protection.

8.4 Device Functional Modes


TPD4E6B06 is a passive integrated circuit that triggers when voltages are above VBRF or VBRR. During ESD
events, voltages as high as 15 kV (air) can be directed to ground via the internal diode network. Once the
voltages on the protected line fall below the trigger levels of TPD4E6B06 (usually within 10s of nano-seconds)
the device reverts to passive.

9 Application and Implementation


9.1 Application Information
TPD4E6B06 is a diode array type TVS. These low capacitance types of TVSs are typically used to provide a
path to ground for dissipating ESD events on hi speed signal lines between a human interface connector and a
system. During high voltage ESD strikes, the device clamps to a safe voltage level to protect the system.
The typical application of the TPD4E6B06 is to be placed in between the connector and the system. The low
capacitance of the TPD4E6B06 gives flexibility in the end application, as it can be used on many different high
speed interfaces.

System

Connector

9.2 Typical Application

GND

Figure 10. Protecting Data Lines


9.2.1 Design Requirements
Table 1. Design Parameters
DESIGN PARAMETER

EXAMPLE VALUE

Signal range on Data Lines

5.5 V to 5.5 V

Operating Frequency

Up to 700 MHz

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9.2.2 Detailed Design Procedure


The designer needs to know the following:
Signal range on all the protected lines
Operating frequency
9.2.2.1 Signal Range
TPD4E6B06 has 4 protection channels for signal lines. Any I/O will support a signal range of 5.5 V to 5.5 V.
9.2.2.2 Operating Frequency
The TPD4E6B06 has 4.8 pF of capacitance (Typ), supporting up to 700 MHz frequencies.

Loss (dB)

9.2.3 Application Curves


3
0
3
6
9
12
15
18
21
24
27
30
33
100k

1M

10M
100M
Frequency (Hz)

1G

3G
G009

Figure 11. Insertion Loss (Any IO to GND)

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10 Layout
10.1 Layout Guidelines

Place the device as close to the connector as possible.


EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
The PCB designer should minimize the possibility of EMI coupling by keeping any unprotected traces
away from the protected traces which are between the TVS and the connector.
Route the protected traces as straight as possible.
Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
Electric fields tend to build up on corners, increasing EMI coupling.

10.2 Layout Examples

= VIA to GND Plane

Figure 12. Single Layer Routing

= VIA

GND

Figure 13. Double Layer Routing

10

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11 Device and Documentation Support


11.1 Trademarks
All trademarks are the property of their respective owners.

11.2 Electrostatic Discharge Caution


These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.3 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms and definitions.

12 Mechanical, Packaging, and Orderable Information


The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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11

PACKAGE OPTION ADDENDUM

www.ti.com

21-Apr-2015

PACKAGING INFORMATION
Orderable Device

Status
(1)

TPD4E6B06DPWR

ACTIVE

Package Type Package Pins Package


Drawing
Qty
X2SON

DPW

3000

Eco Plan

Lead/Ball Finish

MSL Peak Temp

(2)

(6)

(3)

Green (RoHS
& no Sb/Br)

CU NIPDAU | Call TI

Level-1-260C-UNLIM

Op Temp (C)

Device Marking
(4/5)

-40 to 125

B1

(1)

The marketing status values are defined as follows:


ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

Samples

PACKAGE OPTION ADDENDUM

www.ti.com

21-Apr-2015

Addendum-Page 2

PACKAGE MATERIALS INFORMATION


www.ti.com

18-Sep-2014

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

TPD4E6B06DPWR

Package Package Pins


Type Drawing
X2SON

DPW

SPQ

Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)

3000

180.0

9.5

Pack Materials-Page 1

0.94

B0
(mm)

K0
(mm)

P1
(mm)

0.94

0.5

2.0

W
Pin1
(mm) Quadrant
8.0

Q1

PACKAGE MATERIALS INFORMATION


www.ti.com

18-Sep-2014

*All dimensions are nominal

Device

Package Type

Package Drawing

Pins

SPQ

Length (mm)

Width (mm)

Height (mm)

TPD4E6B06DPWR

X2SON

DPW

3000

184.0

184.0

19.0

Pack Materials-Page 2

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