Object Oriented Interaction

by UML in Distributed Environment

Thesis submitted in partial fulfillment of the requirements for the degree

of

Master of Technology
in
Computer Science and Engineering
by

Neeru Goswami
(Roll No.- 1320310007)
under the supervision of

Prof. Anil Pandey

Department of Computer Science and Engineering

Invertis University Bareilly

ABSTRACT
This paper presents the concepts of distributed systems as well as the overview of the
use of Unified Modeling Language (UML) as a standard notation in developing object
oriented design methodology for computer applications.
In this, a detailed study of dynamic interconnection networks has done for the
Distributed Computer Systems. A comparative study is done for Bus, Cross-bar and
Multistage network topologies and their performance is also evaluated after designing
Object, Interaction and Use-case diagrams for the same.
Keywords : Network Topology, Object Diagram, Interaction Diagram and Use-case Diagram

ACKNOWLEDGEMENT
Many people have helped me in the course of this project. It is a pleasure to acknowledge them.
I would like to express our gratitude to Dr. R.M Shukla, dean academics and Mr R.K . Shukla,
H.O.D of Computer Science Department for providing me an opportunity to do my research
work on Object Oriented Interaction by UML in Distributed Environment.
For several fruitful discussions, doubt clearing sessions and lectures, I thank Mr. Anil Pandey of
CS department who is our project guide.
I thank all staff members of the Computer Science Engineering department, for all their support
and cooperation,
I thank all my friends, for their support and cooperation.

CONTENTS
1.

Introduction

1
1.1 Overview of UML
1
1.2 Overview of Network Topologies

2. Literature Study

2
2.1 Interconnection Netwoks
2.2 Network Topologies 4

3. Multistage Interconnection Network

9
3.1 Parallel Architecture & Memory Organization
9
3.2 Conflicts in Parallel Architecture
12
3.3 SMP....................................................................................................................................

4. Interconnection Network 15
4.1 Characteristics of Interconnection Network 15
4.2 Related Definition
15
4.3 Classification of Interconnection Network.......................................................................17

5. Distributed System Configuration Framework

6. Distributed System Modeling using UML

.21

21

37

7. Process 38
7.1. Process
Topologies...........................................................................................................39

8. UML Diagrams

40

5.1.3 Interaction Diagram2

5.1.4 Use Case Diagram......................................................................................2
5.3.1 Class Description 26
5.3.2 Sequence Diagram 35

9. Comparison of Cost Performance

42

9.1 Bus Network 2

9.2 Crossbar Network...........................................................................................2
9.2 Multistage Network.......................................................................................

10.Conclusion
References 48

47

LIST OF FIGURES
LIST
Figure 5.1
Figure 6.1
Figure 6.2
Figure 6.3
Figure 6.4

FIGURE
Distributed System Representation Framework
Distributed Computer System
Distributed Representation model
Process Component Representation
Process Topology

Page No
28
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37

1. INTRODUCTION
1.1 OVERVIEW OF UML
High Performance computation is required for many engineering problems. A popular
approach for computing in nowadays is distributed computer system as it delivers high
end performance. A lot of work on UML modeling have been done by various
researchers, but limited research papers are available for distributed computer systems
related to the UML modeling. UML is used as a standard notation for modeling the
different real-world objects. It is used as an standard modeling language with a graphical
notation, and set of diagrams and elements.
UML is the most visual presentation platform for modeling the real-world problems and
is developed by Booch et al. [1]. The extensions in UML for modeling the design issues
related to any web application architecture are defined by Conallen [2]. The UML is a
very expressive language, addressing all the views needed to develop and then deploy
such systems. It is easy to understand. The major challenges regarding the distributed
system through architecture is explored by Coulouris, G. et al. [3], where various
technologies and case studies on Ethernet and ATM are also discussed. The performance
of ring and tree based topologies for the distributed systems is compared by Huang and
Bode [4]. The way by which one can do the UML modeling for high performance
applications, is suggested by Pllana and Fahringer [8].

What is UML?
Unified Modeling Language or UML is defined as a standardized general-purpose modeling
language in the field of object-oriented software engineering. The standard is managed, and was
created, by the Object Management Group (OMG). It was first added to the list of OMG adopted
technologies in 1997, and has since become the industry standard for modeling softwareintensive systems [2]. It includes a set of graphic notation techniques to create visual models of
object-oriented software-intensive systems.
The UML is a tool for specifying and visualizing software systems. It includes standardized
diagram types that describe and visually map a computer application or a database systems
design and structure. The use of UML as a tool for defining the structure of a system is a very
useful way to manage large, complex systems. Having a clearly visible structure makes it easy to
introduce new people to an existing project [4].
The UML is used to specify, visualize, modify, construct and document the artifacts of an objectoriented software-intensive system under development. It offers a standard way to visualize a
system's architectural blueprints, including elements such as [2]:

 activities
actors
business processes
database schemas
(logical) components
programming language statements
reusable software components.
The UML combines techniques and processes from the data modeling (entity relationship
diagrams), business modeling (work flows), object modeling, and component modeling. It can be
used with all processes, throughout the software development life cycle, and across different
implementation technologies [2].

1.2 OVERVIEW OF NETWORK TOPOLOGIES

2D Mesh , Torus and Hypercube are the three network topologies, which are
this; they are commonly used for executing the concurrent processes in
environment. The UML modeling for these three network topologies is also
and the process execution under distributed environment is also represented
sequence diagram.

compared in
a distributed
done in this,
by using the

The interconnection network is responsible for fast and reliable communication among
processing nodes in any parallel computer. The demands on the network depend on the parallel
computer architecture in which the network is used. Two main parallel computer architectures
exist (1).
In the physically shared-memory parallel computer, N processors access M memory modules
over an interconnection network. In the physically distributed-memory parallel computer, a
processor and a memory module form a processormemory pair that is called processing element
(PE). All N PEs are interconnected via an interconnection network as depicted in Fig. 1(b). In a
message-passing system, PEs communicate by sending and receiving single messages (2), while
in a distributed-shared-memory system, the distributed PE memory modules act as a single
shared address space in which a processor can access any memory cell (3). This cell will either
be in the memory module local to the processor, or be in a different PE that has to be accessed
over the interconnection network.

2. LITERATURE STUDY
The UML defines nine diagram types, which allow different aspects of a system to be expressed.
Each diagram type describes a system or parts of it from a certain point of view. For the purpose
of modeling performance-oriented distributed and parallel applications we concentrate on a
subset of the UML that consists of class, activity and collaboration diagrams. In this section we
present some background information that will be helpful to understand the remainder of this
paper.
A comprehensive discussion on UML can be found in Rumbaugh et al. (1999). Our approach
relies on the UML extension mechanisms to customize UML for the domain of performance
oriented parallel and distributed computing. The UML extension mechanisms(OMG2001)
describe how to customize specific UML model elements and how to extend them with new
semantics by using stereotypes, constraints, tag definitions, and tagged values.
Stereotypes are used to define specialized model elements based on a core UML model element.
A stereotype refers to a base class in the UML metamodel (see Figure 2.a), which indicates the
element to be stereotyped. stereotype may introduce additional values, additional constraints,
and a new graphical representation. Stereotypes are notated by the stereotype name enclosed in
guillemets << >> or by a graphic icon. We are employing stereotypes to define modeling
elements for constructs such as SEND, RECEIVE, PARALLEL, CRITICAL, etc. UML
properties in form of a list of tag-value pairs are introduced to attach additional information
to modeling elements.
A tag represents the name of an arbitrary property with a given value and may appear at most
once in a property list of any modeling element. It is recommended to define tags within the
context of a stereotype. The notation of tags follows a specific syntax: {tag = value}, for
instance, {time=10}. A constraint allows to linguistically specify new semantics for
a model element by using expressions in a designated constraint language.
The usage of UML extension mechanisms is illustrated in Figure 2. Figure 2.a depicts the
definition of the modeling element action+ by stereotyping the base class ActionState. An
ActionState is used to model a step in the execution of an algorithm.
The compartment of the stereotype action+ named Tags specifies a list of tag definitions which
includes id, type, and time. Tag id can be used to uniquely identify the modeling element
action+; tag type specifies the type of action+, and tag time the time spent to complete action+.
We are using action+ (see example in Figure 2.b) to model various types of single-entry singleexit code regions, whereas tags are employed to describe performance relevant information,
such as estimated or measured execution times.

The set of the tag definitions is not limited to those shown in Figure 2.a but can be arbitrarily
extended to suffice a modeling objective. In the remainder of this paper, programming language
constructs will be denoted with capital letters, for instance non-blocking SEND, and UML
modeling elements with small letters, for instance nbsend. For the sake of simplicity, in some
examples the properties of a modeling element are suppressed.

2.1 Interconnection Networks

The interconnection network is responsible for fast and reliable communication among the
processing nodes in any parallel computer. The demands on the network depend on
the parallel computer architecture in which the network is used. Two main parallel computer
architectures exist (1).
In the physically shared-memory parallel computer, N processors accessMmemory modules over
an interconnection network as depicted in Fig. 1(a). In the physically distributed-memory parallel
computer, a processor and a memory module form a processormemory pair that is called
processing element (PE). All N PEs are interconnected via an interconnection network as
depicted in Fig. 1(b).
In a message-passing system, PEs communicate by sending and receiving single messages (2),
while in a distributed-shared-memory system, the distributed PE memory modules act as a single
shared address space in which a processor can access any memory cell (3). This cell will either
be in the memory module local to the processor, or be in a different PE that has to be accessed
over the interconnection network.
Parallel computers can be further divided into SIMD and MIMD machines. In single-instructionstream multiple- data-stream (SIMD) parallel computers (4), each processor
executes the same instruction stream, which is distributed to all processors from a single control
unit.
All processors operate synchronously and will also generate messages to be transferred over the
network synchronously. Thus, the network in SIMD machines has to support
synchronous data transfers. In a multiple-instructionstream multiple-data-stream (MIMD)
parallel computer (5), all processors operate asynchronously on their own
instruction streams.
The network in MIMD machines therefore has to support asynchronous data transfers.
The interconnection network is an essential part of any parallel computer. Only if fast and
reliable communication over the network is guaranteed will the parallel system exhibit high
performance.
Many different interconnection networks for parallel computers have been proposed (6).
One characteristic of a network is its topology. In this article we consider only point-to-point
(non-bus-based) networks in which each network link is connected to only two devices.

These networks can be divided into two classes: direct and indirect networks. In direct networks,
each switch has a direct link to a processing node or is simply incorporated directly into the
processing node. In indirect networks, this one-to-one correspondence between switches and
nodes need not exist, and many switches in the network may be attached only to other switches.
Direct and indirect network topologies are discussed in the following section.
The mechanism to transfer a message through a network is called switching. A section below is
devoted to switching techniques. Switching does not take into consideration the actual route that
a message will take through a network. This mechanism is termed routing, and will be discussed
in turn. In indirect networks, active switch boxes are used to transfer messages. Switch box
architectures are discussed in a final section.

NETWORK TOPOLOGIES
Direct Networks
Direct networks consist of physical interconnection links that connect the nodes (typically PEs)
in a parallel computer. Each node is connected to one or more of those interconnection links.
Because the network consists of links only, routing decisions have to be made in the nodes.
In many systems, dedicated router (switch) hardware is used in each node to select one of the
interconnection links to send a message to its destination. Because a node is normally not
directly connected to all other nodes in the parallel computer, a message transfer from a source to
a destination node may require several steps through intermediate nodes to reach its destination
node. These steps are called hops.
Two topology parameters that characterize direct networksare the degree and the network
diameter. The degreeG of a node is defined as the number of interconnection linksto which a
node is connected. Herein, we generally assume that direct network links are bidirectional,
although this need not always be the case. Networks in which all nodes
have the same degree n are called n-regular networks.
The network diameter F is the maximum distance between two nodes in a network. This is equal
to the maximum number of hops that a message needs to be transferred from any source to any
destination node. The degree relates the network topology to its hardware requirements (number
of links per node), while the diameter is related to the transfer delay of a message (number of
hops through the network). The two parameters depend on each other. In most direct network, a
higher degree implies a smaller diameter because with increasing degree, a node is connected
to more other nodes, so that the maximum distance between two nodes will decrease.
Many different direct network topologies have been proposed. In the following, only the basic
topologies are studied. Further discussion of other topologies can be found in Refs. 79. In a ring
network connecting N nodes, each node is connected to only two neighbors (G 2), with PE i
connected to PEs i _ 1 mod N and i 1 mod N. However, the network has a large diameter of F
bN/2c (assuming bidirectional links). Thus, global communication performance

in a ring network will decrease with increasing number of nodes.

Indirect Networks
In indirect networks, each processing node is connected to a network of switches over one or
more (often bidirectional) links. Typically, this network consists of one or more stages of switch
boxes; a network stage is connected to its successor and predecessor stage via a set of
interconnection links.
Depending on the number of stages, the number of switch boxes per stage, and the interstage
interconnection topology, indirect networks provide exactly one path (single path networks) or
multiple paths (multipath networks) from each source to each destination.
Many different indirect network topologies have been proposed. This section is a brief
introduction to multistage cube and fat-tree networks. Further discussion of these and
other topologies can be found in Refs. 1417.
One important indirect single-path network topology is the generalized-cube network topology
(10), based on the cube interconnection function. A generalized-cube network that connects N
2n sources with N destinations consists of s logB N stages of B _ B switch boxes. The stages
are numbered from s _ 1 (stage next to the sources) to 0 (stage next to the destination).
Each stage consists of N/B switch boxes; two consecutive stages are connected via N
interconnection links. In Fig. 4(a), an 8 _ 8 generalized-cube network comprising 2 _ 2 switch
boxes is shown, while Fig. 4(b) depicts a 16 _ 16 generalized-cube network with 4 _ 4 switches.
Consider the link labeling depicted in Fig. 4(a). The labels at the input (and output) side of each
switch box differ in exactly one bit, which is bit k in stage k. Thus, if a message is routed straight
through a switch box, its link Figure 3.

3. Multistage Interconnection Networks

As the complexity of software increases along with its scale and solution quality, demand for
faster
high processors have also increased. Specially in the areas of aerospace, defense, automotive
applications and science, grand challenge problems are present which require tremendous
amount of computational power ranging from Gigaflops (109 floating point instructions per
second) to Teraflops (1012 floating point instructions per second). This is where parallel
computers with multiple processors come into play.
Parallel computing, or parallelism, can be defined as the usage of more than one processing unit
in order to solve one particular problem. A parallel architecture can be defined as an explicit,
high-level framework for the development of parallel programming solutions by providing
multiple processors, whether simpler or complex, which cooperate to solve problems through
concurrent execution.

Communication subsystems play a very significant role in the todays parallel computers. These
subsystems are used to interconnect the various processors, memories, disks and other
peripherals. The specific requirements of these communications subsystems depend on the
architecture of the parallel computer.
Multistage Interconnection Networks (MINs) are widely used in parallel multiprocessors systems
to connect processors to processors and/or to memory modules. Their popularity is due to the
high switching cost of crossbar networks. Various topologies of MINs have been proposed ad
studied in the last few decades. Most of these topologies are derived from the well know
undirected graph topologies including mesh, star, shuffle exchange, tree networks and cubeconnected networks, among various others.

3.1 Parallel Architecture and Memory Organization

In a multiprocessor system, also called shared memory, all processors share the same memory
space. In order to permit parallel access to this shared memory, it is divided into several memory
modules. The granularity of the memory system is defined by the size of the memory modules.
Granularity is an essential aspect in the design of a parallel architecture.
There must also be a medium present which allows the processors to share memory and also
should be capable of transferring data among all processors and memory modules. Shared
memory parallel computers are distinguished by their programming facility. Every PE
(Processing Element) in a distributed memory system, also called multi-computer, has its own
memory; and data access to another memory node is achieved by communicating with the
processors connected to it.
Figures.1 and .2 shows the difference between the two systems. Note that in modern shared
memory systems, each processor has a small cache memory which is not accessible directly by
other processors.
In both architectures, a communication medium (interconnection network) is used to connect
different nodes of the system. In the distributed memory system, it links the different processors
using a message passing network, and for the shared memory architecture, it connects processors
to processors and/or to memory modules.
When more than one PE needs to access a memory module for a read or write operation,
conflicts might arise. In a parallel system, conflicts can also occur in the communications
systems. The following is a brief discussion of conflicts in parallel computers.

3.2 Conflicts in Parallel Architectures

In a parallel computer communication system, a conflict occurs when more than one message
tries to utilize the same communication medium. We call a communication resource a link or a
Switching Element (SE) output; and in a buffered communication system, an input buffer. When
a conflict occurs in a buffered system, one message passes to its destination and others are
queued in order to be routed in the subsequent cycles.

In an unbuffered system, or in case of full buffer, conflicts cause only one message to pass and
other messages are rejected and can be retransmitted later. Three types of conflicts can occur in
parallel computers [22] : Network conflicts, bank busy conflicts, and simultaneous bank
conflicts. The last two can be grouped as to form memory conflicts.
The memory conflicts can be removed by a technique called data skewing [7] which causes data
arrangement in memory. When a memory conflict is unavoidable, consistency rules are used.
One rule is the EREW(Exclusive Read, Exclusive Write) where only one processor can execute
an R/W operation on the same memory bank at the same time. On the other hand, CRCW
(Concurrent Read, Concurrent Write) enables more than one processor to read/write data from/to
the same memory module at the same time. Conflicts on write requests can be solved by special
algorithms. A practical solution is the usage of CREW (Concurrent Read Exclusive Write)
mechanism.
Practical parallel systems use different techniques in order to avoid or resolve conflict issues.
Some practical examples are given below to give an idea about the differences present between
machines belonging to same family or having same architecture model. We focus on two
architecture families: SMP Machines and MPSoCs.

3.3 SMP
SMP (Symmetric Multiprocessors or Shared Memory processors according to some references)
architectures as well as their NUMA extensions are used to build nearly all parallel servers. They
have advantages of symmetry, unique address space and low communication latency.
SMP also do not suffer from the problems of Asymmetrical parallel systems where the
unavailability of the master processor may lead to a degradation of system performance or even
total system blockage. Communications in SMP are simple load/store operations.
Cache coherence is controlled, generally, by the hardware. For multicomputer systems,
communication tasks may be more difficult, as they have to take place between different
processors. A detailed example of an SMP architecture performance evaluation study can be
found in [26].
There are also cases of SMP machines, where the communication system is a simple or improved
bus. An example is of the Intel Standard High-Volume (SHV) Server. Figure.3 shows only the
communication system to connect the processors to the memory modules. The system supports
cache coherence.
It was the result of collaboration between Microsoft and Intel which led the latter to built
Windows NT SHV systems with more than 4 processors [27] . However due to scalability
problems with NT, Windows 2000 was selected as it had better processor and memory managing
capabilities. Yet due to traffic bottle neck on the bus, most of the systems supporting this
technology are limited to 4 or 8 processors.

In order to avoid the bottleneck caused by the use of bus, IBM proposed an architecture with
a bus for the snoopy and a switch (crossbar) used for the interconnections among the processors

as well as their communications with the memory [16]. This was a Crossbar-Bus Hybrid
structure. The switch allows multiple parallel communications which are faster than those that
can be routed on a bus. The use of a crossbar allows increasing of the memory bandwidth by
providing multiple buses.

3.4 Multiprocessor System-on-Chip (MPSoC)

A System-on-Chip (SoC) is defined as an integration of a complete system on only one silicon
chip. No exterior software or hardware components are expected to interfere in the task
execution of a SoC. SoCs are a novel possibility for the construction of computing systems as
they solve a key problem of memory latency, from which the traditional systems suffer greatly.
Using multiple processors is an attractive solution because of its price-performance ratio, locality
constrains (data processing must take place close to sensors or actuators), reliability (replicating
of computing resources provides fault-tolerance), high throughput (parallel task execution) and
high schedulability (many scheduling possibilities). Even if the memory access time of a SoC is
still much higher than a processor timing cycle, it is still remarkably less compared to that of a
traditional computer.
Also, with evolving technology, it is possible to increase the performance of the processors
and/or multiprocessing. The study of the communication system of a MPSoC is a recent research
branch dealing with what is called Network on Chip (NoC) [21]. The on-chip communication
backbone connects a large number of heterogeneous or homogeneous processing clusters and
memory modules. NoCs can be seen as a layered approach of communication similar to that
defined by the communications networks community to address the problem of connecting a
large number of computers on
wide-area, and is used for on-chip communication design. An advantage of the NoC based
designs
is that they do not need to be synchronized with other subsystem cores like in bus based MPSoC
designs. An other advantage of NoC is that it provides better power aware optimizations.
While bus structures in SoC such as [2], [11] and [20] are attractive because of their simplicity
and crossbars because of their performance, neither are totally practical solutions for large scale
computer systems. An intermediate solution is the interconnection networks. They are presented
in the next subsection.

3.5 Interconnection Networks

As described earlier, communication between the different PEs themselves and/or
communication with the memory system must be carried out by means of a medium. In fact,
interconnecting processors and linking them effectively to the memory modules in a parallel
computer is of paramount importance.

However, this task is a complicated one, due to the complexity/performance tradeoff that must be
made. Use of bus architectures is not a practical solution, because bus is only a good choice
when the number of connected components is small. However, as the number of components in
SoC is increasing with time, it seems that a simple bus is no longer a preferable solution for SoC
interconnection requirements.
They are not scalable, testable and have lack of modularity, resulting in poor fault tolerance
performance of buses. On the other hand, a crossbar as shown in figure.4, which provides full
interconnection between all the nodes of a system is deemed very complex, expensive to design,
and hard to control. For this reason, Interconnection Networks (INs) [31] are considered a good
communication medium for parallel systems. They limit the paths between different
communicating nodes in order to minimize the switch complexity, while giving a certain level of
parallelism which is superior to that of a bus.
Functionally, the role of an IN in a parallel system is to transfer information between the source
nodes to the destination nodes. The following section lists the most important characteristics of
an IN from a high level architecture point of view. An architectural classification of INs is
proposed and then it is surveyed. After that, some networks of special interest for the
dissertation, are presented in detail.

3.5.1 Characteristics of INs

In general, an Interconnection network is characterized by its topology, communication
(switching) strategy, synchronization philosophy [3], control strategy, and routing mechanism
[13]. Some informal definitions of the properties of Interconnection networks are given ahead.

Topology
The physical structure of an Interconnection network is defined by its topology. The topology of
an Interconnection network is defined mathematically by a graph G = (V,E), where V is a set of
nodes (processors, memory modules, computers and/or intermediate SEs) and E is a set of links.
It is evident that the routing algorithm, which defines the path of a message to be routed between
a source and a destination, depends largely on the network topology.

Switching Strategy
Basically, two switching strategies are used, circuit switching and packet switching. In the
former, the whole path between the source and the destination of a message has to be reserved
before the communication takes place and this reservation has to be valid until the message
reaches its destination.
In the latter, a message is divided into a number of information sequences, of the same or
different sizes called packets. These packets are routed individually to their destinations. The

transmission is established by steps. Only the path between intermediate nodes must be reserved
at each step of a communication.
While modern telephone switching systems use packet switching, circuit switching was largely
used for INs. Today, modern optical parallel and communication systems use circuit switching
because of technical difficulties imposed by packet switching in optical systems. Improved
communication strategies based on these basic strategies can be found in literature.

Synchronization
In a synchronized interconnection network, a central clock controls the operation of SEs and I/O
nodes. Handshaking strategies are needed in asynchronous systems.

Control Strategy
The control of a network can be centralized or distributed. In a centralized control strategy, a
central controller must have at each moment, all the information concerning the global state of
the system. It will generate and send control signals to different nodes of the network according
to its collected information. Obviously, the complexity of such a system increases rapidly with
the increase in the number of nodes and its breakdown causes the whole system to stop. In
contrast, routed messageson non centralized networks (also called self routing) contain necessary
routing information. This information is added to the message and will be read and used by the
SEs [35].

Routing Algorithm
The routing algorithm defines, depending on the source and destination of the message, the
interconnection links to be used while traversing through the network. Routing can be adaptive
or deterministic. Paths with deterministic routing mechanisms can not be changed according to
the existent traffic in the network.
Before describing the architecture of Interconnection networks, some classical definitions must
be mentioned. They are presented in the following section.

3.5.2 Related Definitions

In order to consider the functionality of an IN, some classifications and definitions should be
recalled as first defined in [1].
An Alignment IN is a network capable of providing access to a certain number of data structures
with maximum performance.
A permutation IN is a network in which all N! permutations can be realized where N is the

number of inputs and outputs of the network. An IN is characterized by its size and degree. By
size, we mean the number of inputs and outputs of an IN where as the degree of a IN is defined
as the size of SEs used to build it.

3.5.3 Classification of Interconnection Networks

Interconnection networks can be either static, dynamic or hybrid in nature. Hybrid networks are
those INs which have complicated structures such as hierarchical or hyper graph topologies. In
the following sections we will present the two network families of static and dynamic networks.
Since we are only concerned with Dynamic INs in the report, the section related to static
networks is not exhaustive and only Dynamic Interconnection networks are explored in detail.

3.5.4 Static Interconnection Networks (Direct Networks)

In a Static Interconnection network, links among diferent nodes of the system are
considered passive and only graph theoretical adjacent processors can communicate in a
given step [5]. Thus each node is directly connected to a small subset of nodes by
interconnecting links. Each node performs both routing and computing. Important topology
properties of the network include :

Node Degree: (the number of links connected to the node linking the node to its neighbors);
Diameter: (the maximum distance between two nodes in the network);
Regularity: (a network is regular when all its nodes have the same degree);
Symmetry: (a network is symmetric when it looks the same from each nodes perspective) and
Orthogonal property: (a network is orthogonal if its nodes and interconnecting links can be
arranged in n dimensions such that the link is placed in exactly one dimension). In a weakly
orthogonal topology, some nodes may not have any link in some dimensions.
In static networks, the paths for message transmission are selected by routing algorithms. The
switching mechanisms determine how inputs are connected to outputs in a node. All the
switching techniques can be used in direct networks.
The simplest static network is the bus. As described earlier, the use of a simple bus is not a
practical choice for parallel computers as only one message can be transferred at a time and
improved bus architectures such as hierarchical buses, cannot afford acceptable level of
parallelism.
Other static INs such as shown in fig.6 can contain among others, linear arrays, rings, meshes,
hypercube, trees, etc. In a linear array, each processor is connected to its two neighbors.

3.6 Dynamic (Indirect Networks) and Multistage Interconnection Networks

As compared to static networks, in which the interconnection links between the nodes are
passive, the linking configuration in a Dynamic IN is a function of the SEs states. In layman
terms, the paths between the graph nodes of a Dynamic IN change as the SEs states change. As
Dynamic networks are built using crossbars (especially of size 2 2); fig.7 illustrates the
different states of crossbars of size 2 2.

3.6.1 Single Stage INs

Dynamic INs can be built as a single stage or Multistage INs (MINs). A single stage IN is a
dynamic network composed of one linking stage and two end SE stages. It should be noted that
in some references, a single stage IN is composed of only one switching stage and one linking
stage.
Figure.8 shows a general schematic of a single stage IN. Crossbars, which provide a full
connection between all nodes of the system, are considered as non blocking single stage
intercommunication networks for parallel computers.
The linking stage in the figure is a permutation function connecting the outputs of the SE to
the stage furthest to the left to the inputs of the others SE stage. It should be noted that more than
one path through the network may be required for effective communication between a source and
a destination. Also, not all permutation configurations can lead to a connected network, i.e.
capable to connecting any source to any destination. A study of such single stage INs can be
found in [8].

3.6.2 Multistage Interconnection Networks

A MIN can be defined as a network used to interconnect a group of N inputs to a group of M
outputs through a number of intermediate stages of small size SEs followed (or leaded) by
interconnection linking stages.
More formally, a MIN is a succession of stages of SEs and interconnection links. SEs in their
most general architecture are themselves small size interconnection networks. The most used SEs
are hyperbars and more specifically crossbars.
Linking stages are interconnection functions [32], each function is a bijection of the group of the
previous stage switches addresses which connect all SEs outputs from a given stage to the inputs
of the next stage.
In a multiprocessor environment, the first stage of links is connected to the sources (usually
processors) and the last stage is connected to the destinations (memory modules). The minimum
numbers of stages of a MIN must provide a full connection of input nodes to output nodes.

3.6.3 Classification of MINs

We propose a classification of MIN and restate some definitions necessary for the proposed
classification. The topological classification of MINs based on the following definitions is given
in figure.10.
A uniform MIN is one, in which all the switching elements of a stage are of the same degree.
A rectangular network is one that has the same number of inputs and outputs. A Square MIN is
one, in which a MIN of degree r is built from SEs of size r. MINs have been classified into three
classes depending on the availability of paths to establish new connections. They are:

1. Blocking: A connection between free input/output pair is not always possible because of
conflicts with existing connections. Typically, there is a unique path between every input/output
pair, thus minimizing the number of switches and stages. A uni-path network is also called a
Banyan Network.
A Banyan network is defined as a class of multistage interconnection networks in which there
is one and only one path from any input node to any output node.
One of the most critical issues concerning an IN topology is the existence or absence of multiple
paths. By providing multiple paths in Blocking networks, conflicts can be reduced and fault
tolerance can be increased. These Blocking networks are also known as multipath networks.

2. Non Blocking: Any input can be connected to any free output port without affecting the
existing connections. They require extra stages and have multiple paths between every input and
output. A popular example of Non-blocking networks is a Clos network [9].

3. Rearrangable : Any input port can be connected to any free output. However the existing
connections may require rearrangement of paths. These networks also require multiple paths
between every input and output, but the number of paths and the cost is smaller than in the
case of Non blocking networks.
Depending on the kind of channels and switches, MINs can be either:
1. Unidirectional MINs. Channels and switches are unidirectional.
2. Bidirectional MINs. Channels and switches are bidirectional. This implies that information
can be transmitted simultaneously in opposite directions between neighboring switches.
Additionally, each channel can be either multiplexed or be replaced by two or more channels.
The latter case is referred to as a dilated MIN. Since we are concerned only with unidirectional
Delta Square Uniform Banyan networks which are a subset of Banyan networks, we only specify
the characteristics of unidirectional MINs now.

3.6.4 Delta Networks

In the formal definition given by Patel [28, 29], Delta networks are built using an bn (where n
is the number of stages) digit controlled crossbars of which no input and output can be left
unconnected.
The total number of crossbars required to construct a Delta MIN is:
It should be noted that a N-node Delta Network (N = kn) contains n stages where each stage
contains N k switches. The delta or self routing property of Delta MINs allows automatic self
routing of messages from a source to a destination.
The self routing property of Delta networks as shown in figure.13 allows the routing decision to
be determined by the destination address, regardless of the source address. Self-routing is
performed by using routing tags. For a k k switch, there are k output ports. If the value of the
corresponding routing tag is i where 0 i k 1, the corresponding packet will be forwarded via
port i. For an n-stage MIN, the routing tag is T = tn1 . . . t1 t0, where ti controls the switch at
stage Ci. A mathematical generalization of Delta property is given in [1].
There may exist, large numbers of link patterns available for an bn delta network. It should be
noted that the probability of acceptance or blocking of messages is identical in all delta networks.
That means one type of Delta network can be replaced by another one.
As a result, each different setting of a b switch generates (b!)nbn1 distinct permutations. This
is a small fraction of possible permutations. For example, the probability that a random
permutation of 32 inputs can be generated by a 25 25 delta network is 4.6 1012 [28].
In order to simplify the construction of a Delta MIN as well as the design of a routing algorithm,
Patel proposed a regular link pattern which can be used between all stages and thus avoid the
difficult construction procedure for every different delta network.
Patel termed the regular link pattern : the q-shuffle. The q-shuffle of a group of qr elements is a
permutation of these elements defined by:
S qr(i) = (qi +
i
r
) mod qr; 0 i qr 1 (5)
Alternatively, the same function can be expressed as:
S qr(i) = qi mod (qr 1); 0 i < qr 1 (6)
= i i = qr 1 (7)
A q-shuffle of qr playing cards can be viewed as follows. Divide the deck of qr cards into q piles
of r cards each; top r cards in the first pile, next r cards in the second pile and so on. Now pick
the cards, one at a time, from the top of each file; the first card from the top of pile one, second
pile from the top of pile two, and so on in a circular fashion until all the cards are picked up. This
new order of cards represent a S qr permutation of the previous order. For determining the
values of q and r for an Delta MIN of size N M, we use the formula S abn1 , and a and b

corresponding to the inputs and outputs of the crossbar, and n corresponding to the number
of stages. The final values in place of a and bn1 are taken as values of q and r for the qshufe formula. Consider, a Delta MIN of size
16 9 as shown in the fig.14, i.e. a 42 32.

Putting the values in the formula, we obtain the values of 4 and 3 for q and r respectively. Thus
we obtain a S 43 function, figure.15 shows an example of 4-Shuffle of 12 indices, which
corresponds to the S 43 function. As it can be observed, the link pattern is the same in both
figure.14 and figure.15.
Furthermore, applying the q-shuffle function on a number represented in base q corresponds to
the application of a cyclic shift on said numbers. This leads to a construction of a class of MINs
called shuffle-exchange MINs [28], [37]. Omega networks [24] which were first defined by
Laurie, and one of the most popular types of Delta networks are usually described as shuffle
exchange MINs.
In fact all delta networks are shuffle-exchange MINS. An exchange function is defined by
changing the least significant digit of the output address [19].

3.7 Types of Delta networks

There exists various popular MINs which we have grouped to be considered as different types of
Delta networks. The difference between each of these networks is the topology of
interconnection links between the crossbar stages. A study of equivalence of various types of
Delta MINs has been studied in [10]. All delta networks are considered to be topologically
equivalent as well as functionally equivalent [42]. We thus classify the following popular types
of Delta MINs.
-:- Omega networks
-:- Butterfly networks
-:- Baseline networks
-:- (Generalized) Cube networks
and their reverse networks
-:- Flip networks
-:- Reverse Butterfly networks
-:- Reverse Baseline networks
-:- Indirect Binary n-cube networks
In current literature, usually the first four network types are discussed. This is due to the reason

because the last four types are mirror images of the first four types respectively, (i.e. Flip
network is a reverse image of Omega network and so on). In the report, we also explain the last
four types in the respective sections of the first four types.
We assume that these networks are built using k k switches, and that there are N = kn inputs
and outputs, however some of the permutations for the interconnection links are only defined for
the case where N is a power of 2. With N = kn ports,
Let X = xn1 xn2 . . . x0 be an arbitrary port number, 0 X N 1 where 0 xi k 1 and
0 i n 1.

3.7.1 Omega Network

Omega networks are considered to be the most popular of Delta networks. They use the perfect
shuffle which is a special case of a q-shuffle. A more intelligent way to describe the perfect kshuffle permutation _k defined as:
_k(xn1 xn2 . . . x1 x0) = xn2 . . . x1 x0 xn1 (8)
The perfect k-shuffle permutation performs a cyclic shifting of the digits in x to the left for one
position. For k = 2, a perfect shuffling of a deck of N cards take place. The perfect shuffle cuts
the deck into two halves from the center and intermixes them evenly. Figure.16 and figure.17
show schematics of Omega (16,4) and Omega (16,2) respectively. (Here the first parameter
refers to the RR n values of q and r as defined in k-shuffle formula are respectively S 44 and S
22 for these Omega networks.
Normally an Omega network has the same interconnection links between the crossbar stages
as seen in the mentioned figures. However, as described by Laurie [24], an Omega network can
be constructed with different interconnection links between the switching stages as shown in the
figure.18.
In an Omega network, connection pattern Ci is described by the perfect k-shuffle permutation _k
for 0 i n1. Connection pattern Cn is selected to be _k 0. Thus, all the connection patterns but
the last one are identical. The last connection pattern which is _k 0 does not produce any
permutations.
Therefore the patterns can be summed up as
Ci(0 i n 1),_k;Cn, _k
0 (9)
A Flip network [3] is considered to be a mirror image of the Omega network. It uses the inverse
perfect shuffle permutation _k1 which is defined by
_k1 (xn1 xn2 . . . x1 x0) = x0 xn1 . . . x2 x1 (10)
The connection patterns of Flip network are

C0, _k
0;Ci(1 i n),_k1 (11)
Fig.19 shows a Flip (8,2) network.

3.7.2 Butterfly Network

A Butterfly network is basically an unfolded hypercube. The dimensions of the hypercube
correspond to the number of interconnection links between the crossbar stages of the Butterfly
networks.
The ith kary butterfly permutation _k
i , for 0 i n 1, is defined by
_k
i (xn1 xn2 . . . xi+1 xi xi1 . . . x1 x0) = xn1 xn2 . . . xi+1 x0 xi1 . . . x1 xi (12)
C0, _k
0;Ci(1 i n 1), _k
ni;Cn, _k
0 (13)
The ith butterfly permutation interchanges the zeroth and ith digits of the index. It should be
observed that _k 0 defines a straight one-to-one permutation and is also called identity
permutation. In a Butterfly MIN, connection pattern Ci is described by the ith butterfly
permutation _k
i for 0 i n 1. Connection pattern Cn is selected to be _k 0. Thus the patterns can be summed
up as.
A Butterfly (16,2) network is shown in the fig.20. It should be observed that in some references,
this schematic is represented as a Reverse butterfly network.
An important point to be considered is that except Omega and its reverse network, all other Delta
Networks are built using recursive composition as illustrated in Figure.21. For a Delta network
of size N N, the first stage consists of N k crossbars and 2 smaller Delta networks of size N2 .
That is the inverse case for reverse networks. figure.22 shows the recursive nature of a Butterfly
(8,2) network. Butterfly (8,2) means a Butterfly network of size 8 and degree 2. Here, the first
stage of a Butterfly (8,2) network contains N2 = 4 switching elements followed by two smaller
Butterfly networks of size 4 4.
A Reverse Butterfly (16,2) network is shown in the fig.23. It uses the same permutations as the
Butterfly network, however in a reverse order such that the connection patterns can be described
as:
C0, _k
0;Ci(1 i n 1), _k
i ;Cn, _k
0

3.7.3 Baseline Network

In a Baseline network [42], the ith kary baseline permutation _ i , for 0 i n1, is defined by
_k i (xn1 xn2 . . . xi+1 xi xi1 . . . x1 x0) = xn1 xn2 . . . xi+1 x0 xi xi1 . . . x1 (15)
The ith baseline permutation performs a cyclic shifting of the i+1 least significant digits in the
index to the right for one position. It should be observed that _k 0 also defines the identity
permutation I. The patterns for the baseline network can be summed up as
C0,_k;Ci(1 i n), _k ni

(16)

Thus the initial pattern from the sources to the first switching stage is an omega
permutation and
the rest are according to the baseline permutation. A Baseline network is also composed
recursively
like a butterfly network. Fig.24 shows a Baseline (8,2) network.

For a Reverse Baseline network, the reverse baseline permutation for 0 i n 1, is defined by
_k1 i (xn1 xn2.... xi+1 xi xi1.... x1 x0) = xn1 xn2.... xi+1 xi1.... x1 x0 xi
(17)
Thus the patterns for the reverse baseline network can be summed up as
Ci(0 i n 1), _k1
i ;Cn,_k1

(18)

Thus the final pattern from the last switching stage to the destinations is a flip permutation. The
Figure of a Reverse Baseline (8,2) network is shown in the fig.25.

3.7.4 (Generalized) Cube Network

In a Generalized Cube Network [34], [33], the ith cube permutation Ei , for 0 i n1; is
defined
only for k = 2 by

Ei(xn1 xn2 . . . xi+1 xi xi1 . . . x1 x0) = xn1 xn2 . . . xi+1 xi xi1 . . . x1 x0

(19)

The ith cube permutation complements the ith bit of the index. The permutation E0 is also called
exchange permutation.
For a cube MIN (or Multistage cube network [33]), connection pattern Ci is described by the n ith butterfly permutation _k ni for 1 i n . Connection pattern C0 is selected to be _k.
Therefore
the connection patterns can be summed up as
C0,_k;Ci(1in),_kni

3.8 Equivalence of Delta Networks

(20)

The topological equivalence of these MINs can be viewed as follows: consider that each input
link to the first stage is numbered using a string on n digits sn1 sn2 . . . s1 s0, where 1 si k
1, for 0 i n 1. The least significant digit s0 gives the address of the input port at the
corresponding switch, and the address of the switch is given by sn1 sn2 . . . s1.
At each stage, a given switch is able to connect any input port with any output port. This can be
viewed as changing the value of the least significant digit of the address. For the connection to
work, it should be possible to change the values of all the digits. As each switch only changes the
value of the least significant digit of the address, connection patterns between stages are
specified so that the position of digits is permuted; and after n stages, all the digits have occupied
the least significant position.
Thus the difference of the above mention types of delta networks is the order in which the
digits occupy the least significant position.

3.9 Multilayer and Replicated MINs

In literature, there exist also Multilayer MINs and Replicated MINs. Replicated MINs enlarge
MINs by replicating them L times. Multilayer MINs can be considered an enhanced extension
where the number of layers can be increased in each stage. A review of Multilayer MINs and
Replicated MINs can be found in [40].

4 Overview Of UML Diagrams

Unified Modeling Language (UML) is defined as a graphical idiom for envisioning, identifying,
creating and documenting the artifacts of a software system. UML is a blueprint of the actual
system and helps in documentation of the system [3].
It makes any complex system easily understandable by the disparate developers who are working
on different platforms. Another benefit is that UML model is not a system or platform specific.
Modeling is an indispensable part of the huge software project, which as well facilitates in the
improvement of Medium and small projects.
The UML 2.0 has fourteen diagrams, to model diferent software artifacts. The increase in its
popularity encourages us to use these models as an important source for test case generation.
There are three important types of uml diagrams.
1. Structure diagram: Structure diagrams highlight the things that must be available in the
system being modelled. Structure modeling captures static features of a system. Some of

structural diagrams are Object Diagram, Component Diagram, Class Diagram, Package Diagram,
Composite Structure Diagram, and Deployment Diagram etc.
2. Behavioral diagram: behavioral diagrams describe the interaction in the system. It represents
the interaction among the structural diagram. Behavioral diagram shows the dynamic nature of
the system. Some of behavioral diagrams are Activity Diagram, Use Case Diagram, and State
Machine Diagram etc.
3. Interaction diagrams : It highlights the of data and control among the things present in the
system being modeled. Some of interaction diagrams are Interaction Overview Diagram,
Sequence Diagram, Communication Diagram, Timing Diagram and etc.

5. DISTRIBUTED SYSTEM CONFIGURATION FRAMEWORK

Distributed systems are composed of distributed applications and the underlying network.
Distributed applications are currently built based on client-server models and consist of multiple
tiers [19]. The underlying network consists of heterogeneous Intranets and Internet connections
usually integrated through TCP/IP protocol stack. Users have their own workstation (diskless or
not), while server processes are executed on dedicated server nodes.
The proposed distributed system configuration stages and their interaction are analytically
described in [12, 14]. Functional configuration (stage 1) corresponds to the description of system
specifications. Logical and physical configuration (stages 2 and 3) deal with application
configuration (process/data allocation and replication policies) and network design respectively.
As resource allocation and network configuration problems cannot be independently solved,
stages (2) and (3) are repeatedly invoked until an acceptable solution is reached. System
configuration phase must facilitate the performance evaluation (stage 4) of the proposed solution
prior to implementation.
If system requirements are not satisfied, logical and physical configuration are re-initiated.
Stages 2 and 3 are usually automated by software tools as those described in [11, 5, 18, 3]. Stage
4 is usually performed using discrete event simulation [13, 7].
We decided to adpt UML to represent distributed systems, since a) it is a widely accepted
standard and most system designers are familiar with it, b) it allows the graphical representation
of specifications and c) it facilitates the automated implementation of model extensions. Three
alternative views are utilized emphasizing specific requirements of each configuration stage.
Application view is used to describe functional specifications (e.g. application logic and user
behavior). Site view facilitates the definition of system access points and the resource allocation

and replication. Resources (e.g. processes and data) and the way they interact are already
described through application view.
Physical view provides for network infrastructure modeling. The site and physical view
correspond to application and network architecture respectively, thus they are interrelated. This
interrelation must be reflected to the corresponding UML diagram entities to ensure distributed
system performance. Both site and physical views are decomposed into hierarchical levels of
detail. At the lower level, network nodes are related to process/data replicas.
A UML profile is introduced to implement the distributed system model. This profile, called
Distributed System Modeling, is imported within Rational Rose platform ([17]), which acts as
the user interface for the system designer (figure 1). In order to model all aspects of distributed
system configuration process, different UML diagrams are integrated and properly extended.

Figure 1: Distributed System Representation Framework

Additional functionality needed to manipulate the model was embedded within Rose platforms
(as addins). Functional configuration is strongly related to model definition. Thus, it is performed
within Rose environment. Application, Site and Physical views are created within Rose by the
designer as extended UML diagrams.
Additional functionality is embedded within Rose, as custom scripts, to facilitate the description
of specific distributed system characteristics. Logical and physicalconfiguration stages are semiautomated using heuristics by appropriate decision-support software, for example IDIS [11].
They aim at filling specific properties of site and physical view respectively.
To evaluate distributed system performance, the discrete event simulation tool described in [13]
can be used. The simulator uses as input the overall distributed system model, after the
construction of application, site and physical view. Thus, there is a need for data exchange
between Rose and the tools used to automate these stages. XML was adopted for this purpose.
The model created by the designer through Rose is exported in XML in order to be used by the
proper configuration tool and imported again in order for the designer to view corresponding
results. Additional functionality is embedded within Rose to enable view management and
invocation of external software tools.In the following, we focus on UML extensions needed to
efficiently model distributed system architectures.

6. DISTRIBUTED SYSTEM MODEL USING UML

6.1. Distributed Computer System

A distributed computer system consists of autonomous computers,
connected via network. The computers involved in the distributed system
can share both the localized as well as remote
resources.
However, it is quite expensive to access any remote resources in terms of
CPU overhead and communication cost. Nowadays, a trend to develop
distributed system is increasingly moving ahead due to its features like high
performance computing, scalability.
Nowadays computation labs are adopting the concept of distributed
computer systems, which

is shown below in Figure 1. This figure shows the connection of N

autonomous clients to diferent servers connected through a communication
network.

Figure 2: Distributed Computer System

This network can be based upon any kind of network topology as required,
in terms of complexity, reliability and security
In the following, we discuss alternative model views and corresponding modeling issues. UML
diagrams are used to represent different aspects of the distributed system model suitable for each
view. Distributed system entities are depicted as UML model elements included in the
corresponding diagram, properly extended to include additional properties and support additional
constraints.

The stereotype mechanism was efficient to create the distributed system meta-model. Physical
view refers to the aggregate network. Network is a composite entity, which is repeatedly refined
to represent network topology. Network nodes are either workstations allocated to users or
server stations, running server processes. Specifically, nodes consist of one processing, one
storage and one communication element. UML deployment diagrams are commonly used to
represent network architectures [6]. In the proposed model, physical view is represented as a
deployment diagram.
No additional stereotypes are needed to represent network architecture, thus physical view is not
further discussed. Instead, we focus on application architecture and functionality representation.
The corresponding model supported during configuration stages is presented in figure 2, as a
UML class diagram.

All classes of the model are related to stereotypes defined within different system UML views.
Stereotypes are illustrated by shaded boxes. The model classes retrieve data from the stereotypes,
excluding though the representation information. Based on this class diagram, distributed system
models, generated using Rational Rose, are exported and imported in XML format.
6.2. Application View
Application view comprises all the applications supported by the distributed system, as well as
the interactions among them. Applications are conceived as sets of interacting processes and data
repositories (i.e. files) accessed by them. A process, which can be either server or client, consists
of components, each representing the specific set of tasks (or operations) executed when the
process is activated in a certain way (based on its input parameters).
Thus, components stand for all alternative activation ways. Component implementation consists
of simple tasks occurring upon process activation, called operations. These are selected from a
predefined operation set, that is, the operation dictionary.
User behavior is also described in the application view, through user profiles activating clients.
Each profile includes user requests, which invoke specific components of client processes
operating on the users workstation.
6.3 Representation Model

An example of application view is presented in figure 3. In this example, a user (a student)

initiates a simple search in a library OPAC, thus performs a database search through the
appropriate CGI in the web server. UML use case diagram was extended for application view
representation.

Client and server processes are modeled as package stereotypes, depicted by rounded rectangles
respectively labeled. Process components are illustrated using a double-lined use case icon.
Arrows between use cases, denote the interaction among components and hence among
processes.
User profiles are illustrated using UML actor icon. Each use case conceals the internal actions
occurring when the process is activated through the respective component interface

Internal actions are illustrated by a UML activity diagram which appears, as shown in figure 3,
when selecting the corresponding name from a menu that opens up when right clicking on a
component use case.

Process Component Representation

Actions included in this activity diagram are selected from the operation dictionary through a
submenu (figure 4). Depending on the operation selected, a form appears containing the
parameters of the specific operation. Through this form, the system designer may specify a value
for every parameter.
In figure 4, the UML activity diagram for the Simple Search component of Web Client process is
depicted. The form_access (form_name, no_fields, avg_fsize, processing) operation concerns
accessing, activating and processing of a web form. For the operations that invoke other
components, the target process component is specified through the same form.

This information enables the automatic generation of arrows among components in the external
part of the application view when the activity diagram window is closed. Arrows are labeled
using the name and the id of the operation initiating process activation.

6.4. UML Extensions

Figures 5 and 6 represent UML 2.0 extensions (additional stereotypes are depicted in a shaded
manner) defined for the external and internal representation of processes in the Application View.
Packages in UML constitute a general grouping mechanism. Therefore, server and client
processes are conceived as packages, as they both group components. They are defined as
stereotypes of Package by the name ProcessPackage. As shown in the figure 3, the
corresponding view elements are rounded rectangles with the corresponding label. Components
are conceptually related to use cases, as a use case in UML is a kind of classifier, representing a
coherent unit of functionality provided by a system. Thus, the stereotype ComponentUseCase is
defined as a specialization of UseCase.

The stereotype Invokes concerns the relationship among components. If, for example, component
Simple Search invokes component Get Page (figure 3), it is entailed that Simple Search requires
Get Page in order to be accomplished. This implies a dependency relationship among operations,
as opposed to use cases in UML use case diagrams which may be connected to each other only
by Extend, Include and Generalization relationships.

Thus, we have defined Invokes relationship as a stereotype of UML Dependency and more
specifically of Usage. Usage is a kind of dependency in which one element requires another for
its full implementation. This is exactly the case with the relationship between components.

The stereotype Invokes includes two additional attributes, namely the operationId and the
operationName, i.e. the id and name of the internal action that initiates the invocation.

The stereotype UserProfileActor is a specialization of the Actor classifier of the UML metamodel with additional properties, as activationProbabilities. ApplicationView, formed of
ProcessPackages, UserProfileActors, ComponentUseCases and Invokes relationships among
them, constitutes a stereotype of Model.
Component implementation is represented through an activity graph, hence the relation between
ActivityNode and ComponentUseCase in figure 5.
Each component implementation maps to a UML activity with the differentiation that it is not
composed of activities in general, but specifically of operations that have been defined in the
Operation Dictionary (figure 6). ComponentImplementation is formed of OperationActivities.
The stereotype OperationActivity extends the semantics of ActivityNode with the additional
properties valueList and targetProcessComponent. These properties have been described in the
previous section (see 3.1.1).

3.5 Site View

Defining the access points of the system is supported through the site concept. The term site is
used to characterize any location (i.e. a building, an office, etc.). As such, a site is a composite
entity which can be further analyzed into subsites, forming thus a hierarchical structure.
User profiles and processes are associated with atomic sites, i.e. sites which cannot be further
decomposed, constituting therefore the lowest level of the hierarchy.
In essence, the hierarchy indicates where (in which location) each process instance runs and
each user profile is placed. The site view is represented using UML component diagrams.
Introducing progressive site refinement and linking site range to network range, enables the
identification of dependencies between application configuration and network topology.
Thus, component diagrams representing site view and deployment diagrams representing
physical view are interrelated. This is facilitated by the relationship between node and
component model entities already supported in core UML meta-model.

6.5.1 Representation Model

As indicated in figure 7, sites are modeled using UML packages. At the lowest level, server and
client processes are illustrated as UML components, the shaded ones standing for client
processes, while UML actor icon is used to represent user profiles.

6.5.2 UML Extensions

The hierarchical site structure indicates a grouping of sites when moving from lower levels
to the root of the hierarchy. As such, we have defined site as a stereotype of Package, named
SitePackage (figure 8). SitePackages relate to each other through an Abstraction relationship, a
dependency which relates two elements or sets of elements representing the same concept at
different levels of abstraction. Sites constitute a more detailed view of their parent site, while
root site is the most abstract one.
Processes are modeled as UML components, since they are essentially pieces of software. Hence,
ServerComponent and ClientComponent are defined as stereotypes of UML Component.
ServerComponents and ClientComponents are connected through Dependency relationships, like
components in the respective UML diagrams.

These stereotypes extend the semantics of Component by including the additional attribute
numberOfInstances. User profile has been defined as a stereotype of Actor, named
UserProfileActor, including the same attribute.

7. PROCESS
The concept of a process originates from the field of operating systems where it is
generally defined as a program in execution, that is, a program that is currently being
executed on one of the operating system's virtual processors. A process is the basic entity
of execution in any distributed computing environment.
It is a macro, subprogram, subroutine or block of code, consists of an identification
number called a process_id.Specialized model elements which are based on a core UML
model element are defined by stereotypes. A stereotype is a base class is the UML meta
model, as shown in Figure, which indicates the element to be stereotyped.
Additional values, additional constraints and a new graphical representation may also
introduced by stereotypes. They are notated by the stereotype name enclosed in guillemets
<<....>> or by a graphic ion.Figure 2.a defines the modeling element action+ by
stereotyping the base class ActionState, a class ActionState is used to model a step in
the execution of an algorithm. A stereotype parallel region UML class diagram is made
and associated activities representation is also given. For defining specialized model
elements based on a core UML model element, we are using stereotypes.

7.1 PROCESS TOPOLOGIES

The multiple threads are handling the processes which are going to be executed, in a
concurrent manner by using the parallel region. A network topology is arranged for the
communication and execution purposes of these processes.

p1

p4

p2

p5

p3

p6

Figure : Class Diagram for Bus Topology

M1

M2

P1

P2

P3

Figure : Class Diagram for Cross-bar Topology

M3

In this, different types of topologies are used for setting the labs for distributed
computations. A process execution time can be saved by using these topologies since they
are executed in concurrent fashion
The topological arrangement of a network may be physical or logical. In physical
topology, various components of a network are placed, it also includes device location
and cable installation, while logical topology explain the flow of data in a network,
regardless of its physical design.
A process topology is a
group of processes that have a predefined regular
interconnection topology such as a farm, ring, 2D mesh or tree. The process topology is
machine-independent and depends on the application. The process can access the code
region as per the availability of the resources, for faster execution by using the topology.

Bus-based networks are one of the simplest and efficient solution when the cost and a
moderate number of processors is involved.
Crossbar networks are those in which all the processors have dedicated buses directly
connected to all memory blocks. They are non-blocking network , as a connection of a
processor to a memory does not block the connection of any other processor to any
other memory block.
Multi-stage Interconnection Network connects a number of processors to a number of
memory banks by using a number of switches organized in layer.

P000
S2

S1

S0

P001

M000
M001

P010

M010
S2

S1

S0
M110

P011

P100
P101

M100
S2

S1

S0

M101

M110
P110

S2

S1

S0
M111

P111

Figure: Class Diagram for Multistage Network

3. OBJECT DIAGRAM FOR DISTRIBUTED SYSTEM

The object diagrams are generally used for modeling the instances of things contained in
the class diagrams. They shows a set of objects and their relationships at a point in time.
An object diagram contains a set of instances of the things found in a class diagram.

I_Cache

D_Cache
PROCESS

Process_Execution_Contr
oller

Processor

COMMUNICATIONLINE

Memory
SIGNAL

NETWORK TOPOLOGY

Bus

CrossBar

MultiStage

Therefore, an object diagram, expresses the static part of an interaction, consisting of the
objects that collaborate but without any of the messages passed among them. Graphically,
an object diagram is a collection of vertices and arcs. It is a special kind of diagram
and shares the same common properties like a name and graphical contents that are a
projection into a model. The messages in the distributed computing environment, get
communicated to and from the nodes in the form of signals for the process
synchronization.

In the above figure, one can see that the object Process_Execution_Controller (PEC) is
directly linked with the object Process, Communication_Line, Processor, Memory and
D_Cache (Data Cache) , I_Cache (Instruction_Cache). Here, object I_Cache is responsible
for caching the instructions whereas D_Cache is responsible for caching the data.
Here, PEC is responsible for any process like storing and searching the needed
instruction or data during the process execution with the help of Processor and Memory.
The object Communication_Lines is directly linked with the object Network_Topology
because for sending a message for communicating with the other object in the distributed
environment, it needs a topology. So, adopting the network topology for the
communication is one of a key point for measuring the performance of any distributed
computer system.
Here in the figure, one can also see that the object Process is directly communicating or
linked with the object Communication_Line for sending and receiving messages to or
from other processes running concurrently in the distributed environment. Also the object
Communication_Line is directly linked with the object Signal and Network_Topology, for
getting the signal and topological specification of communication network.
The object Processor is directly linked with the object Memory, through which it can
take space whenever needed for executing the instructions, which is further linked with
the object Processor_Execution_Controller

4 . INTERACTION DIAGRAM FOR DISTRIBUTED SYSTEM

The interaction diagrams are used to describe some type of interactions among the
different elements in the model. So, this interaction is a part of dynamic behavior of the
system. Their purpose is to visualize the interactive behavior of the system. They are
basically used for capturing the dynamic behavior of a system, for describing the
message flow in the system, for describing the structural organization of the objects and
for describing the interaction among the objects.
As this is already discussed that the purpose of interaction diagram is to capture the
dynamic aspect of a system. So, for capturing the dynamics aspects, we need to
understand what a dynamic aspect is and how it is visualized. The dynamic aspect can
be defined as the snapshot of the running system at particular moment.
The following things are to be identified clearly before drawing the interaction diagram:

Objects taking part in the interaction.

Message flow among the objects.
The sequence in which the messages are flowing.

Communication_Line

I_Cache

get message

send message
1.3: loading instructions

loading complete

1.6: get instructions

send instructions

1.1 : send process stream

Process

process retrieval

1.2: load data

Process_Exec
1.5 : get data
ution_Controll
er
D_Cache

loading complete
send data
1.4: start decoding of instructions

Load Operands and instructions

Processor

Figure : Interaction Diagram For Process Execution under distributed computer environment

The interaction diagrams are used for modeling the flow of control by time sequence,
for modeling the flow of control by structural organization and for forward and reverse
engineering.
The messages are carrying through the communication channels in the form of signals
among the processes in order to execute concurrently in the distributed computing
environment. In Figure, it is shown how the messages are passing among various classes

like Process, Process_Execution_Controller, Communication_Lines, D_Cache, I_Cache and

Processor, involved in process execution under distributed computer environment.
In the figure, first of all the class Process receives a message form a class
Communication_Line,
then
it
sends
a
process
stream
to
a
class
Process_Execution_Controller for execution. After receiving complete process stream, PEC
starts caching the needed data and instructions separately into D_Cache and I_Cache
respectively. Now PEC starts sending the message the processor to start decoding now
after decoding the processor load Operands and instructions to the class PEC.

5. USE-CASE DIAGRAM FOR DISTRIBUTED COMPUTER SYSTEM

For modeling a system the most important aspect is to capture the dynamic behavior.
Dynamic behavior means the behavior of a system when it is running. Use Case diagrams
are used for modeling the functionality of a system by using actors and use cases. Use
cases are services or functions which are provided by the system to its users. Use-case
diagrams consists of actors, use cases and their relationships. They are generally used to
model the system of an application. A single use-case diagram captures a particular
functionality of a system.
Their purpose is to capture the dynamic aspects of a system. They are used to gather the
requirements of a system including internal and external influences. Their requirements are
mostly design requirements. So, whenever a system is analyzed to gather its
functionalities, use cases are prepared and actors are identified.
In brief, the purpose of use case diagrams can be as follows

Used to gather requirements of a system.

Used to get an outside view of a system,
Identify external and internal factors influencing the system.

Use-case diagrams are considered for high level requirement analysis of a system. So, we
can say that the use cases are the system functionalities written in an organized manner.
Now, the other thing which is relevant to the use cases is the actor. Actors can be
defined as something that interacts with the system. The actors can be human user, some
internal or external applications.
Use-case diagrams specifies the events of a system and their flows. They never describes
hoe they are implemented. It can be imagined as a black box where only the input,
output and the function of the black box is known.

6. COMPARISON OF COST PERFORMANCE AMONG TOPOLOGIES

TOPOLOGY

WIRE COST

SWITCH COST

BUS

CROSSBAR

N^2

MULTISTAGE

N Log N

N Log N

Table 1. Cost performance for Bus , Crossbar , Multistage Topologies

The communication on the basis of which the comparison is done for Bus , Crossbar and
Multistage networks is considered as wire cost and switch cost. The above table gives the
measurements of cost performance, which will show the comparison as the number of
nodes in the network system is increasing under the distributed environment. On the
basis of the above table, three more tables can also be designed, which are used for
showing the comparison of space complexities.

COST PERFORMANCE FOR BUS TOPOLOGY

M*N

No. Of Nodes

Wire Cost

Switch Cost

2*2

2*3

2*4

2*5

10

2*6

12

2*7

14

2*8

16

Figure : Table 2 for Bus Topology

COST PERFORMANCE FOR CROSS-BAR TOPOLOGY

M*N

No. Of Nodes

Wire Cost

Switch Cost

2*2

2*3

2*4

16

2*5

10

25

2*6

12

36

2*7

14

49

2*8

16

64

Figure : Table 3 for Cross-bar Topology

COST PERFORMANCE FOR MULTISTAGE TOPOLOGY

M*N

No.
Nodes

Of

Wire Cost

Switch Cost

2*2

2*3

2*4

2*5

10

2*6

12

2*7

14

2*8

16

Figure : Table 4 for Multistage Topology

On the basis of Table 1, Table 2, 3 and 4 are designed, which shows the comparison of
cost performance as the number of nodes in the network system under distributed
environment is increasing. As nodes are increasing, the performance of Bus topology
comes best over the Cross-bar and Multistage since the cost is low in case of Bus
topology for wires as well as for switches.
In case of wire cost , the behavior of Cross-bar is better than that of Multistage network
topologies whereas, in case of Switch cost Multistage topologies perform well than those
of Cross-bar network topologies.

10. Conclusion
From the above work, it is concluded that UML is one of the important modeling languages
used for the visual representation of research problem/software design. In this paper,
performance of three kinds of topologies i.e. Bus, Crossbar, Multistage is considered under
the distributed environment and it is concluded that the Bus topology is the best kind
of arrangement of computer system under distributed environment since the space complexity is
less as the nodes are increasing in comparison with other topologies. Since the present work
is only confined to the dynamic interconnection of the network topologies, this research work
can also be extended further, by considering the Combination of both static and dynamic of
interconnection of computer network.

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