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Xilinx Tools Tutorial -1

Using ISE for FPGA Implementation

Design of half adder using dataflow modeling.

Syntax Check
Create test fixture using tools wizard
Simulation of half adder
Design of full adder using gate level modeling (instantiation of half adders).

ISE v- 12.1

FPGA Kit- Digilent Nexys2 (Spartan 3E ) board

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1. Run ISE, the Integrated Simulation Environment:

Double click the icon

Or Start Menu  All Programs  Xilinx ISE Design Suite 12.1  ISE Design Tools  Project Navigator.

Take your time and make yourself familiar with the interface.

Before starting to code for Synthesis the designer must know the concept of RTL and should
have gone through the Synthesis tools reference manual.
Though while doing beginner exercises for practice you might not have read the Synthesis and
that is OK (you may skip & it may be acceptable while doing simulations) but later as you will
go forward to code for synthesis or working on a real project you MUST know the concept of
Synthesis and must have gone through the Synthesis Manual.

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2. Make New Project:

Click New project. A new project is made once for a new design (the design may have many leaf cells in the
hierarchy these cells are created within the existing project). To open and work with existing design, use open
project. Though, mostly, ISE Project navigator keeps last active project on startup.

The project is named adder_sample. It is located in the directory E:\xilinx_proj.

It is suggested that the designer always organize the directory structure and must know where
the design project has been created.

It is important how the project is organized. It is strongly recommended that the naming is done
sensibly. As a convention, name the Verilog file same as the module name and the variations of
similar module be name with a variation. For instance, if I am to design a 4 bit ripple carry
adder, I may name the adder as adder_4bit_ripl.v, its module name as adder_4bit_ripl.

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Typically, a mixed approach is used in designing. In the first step the top design is broken down
to the leaf cells, this is called top down approach. Now the design is built/coded from the very
leaf/child cell (lowest level). Once all the lowest level leaf/child cells are created the upper level
cells are created using these lowest level leaf/child cells. In this way the top level design is

It is just like building a house. First an architecture is drafted on a paper. Then basic building
blocks like concrete and bricks etc are used to create rooms and bit by bit a house(top level) is

Choose the Kits FPGA available:

After filling the FPGA device form  Next.

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See the project summary, if everything looks OK,  Finish. Otherwise go back to select correct options and
finally chose Finish.

Tool Control:
Figure below shows two important aspects of the tool.

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3. Adding Files:
Now new files can be created or existing files can be added to the project.
In the Xilinx Tool Bar select Project  New Source

In New Source Wizard  Verilog Module (in the list on the LHS)  Give appropriate name for the verilog
module ` half_adder_dfl (half adder using dataflow modeling)  Next :

Insert the port names:

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Check that the Summary details are correct. Go back to change until sure that everything is OK.

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Once a Verilog module is created using a wizard, the Project Navigator will look like as shown below:

An outline of module with input output ports just specified is created. Now, body part can be coded. Also,
Notice (in figure above) that the design is added as a top module under the FPGA device chip in the Design
section. And since the design is top module and is selected, processes section will show all the available
options for the module.

Remember, only Top Module can be implemented on the FPGA.

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Half adders body has been coded by using datflow level modeling as shown below:

4. Check Syntax:
The code should be checked for any syntax errors.

Check the Console to see if succeeded:

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There is an error, compiler cannot find inb, it should be in_b instead.

Make changes and Check syntax again:

Code is OK Syntactically!

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5. Run the Simulation:
Create New Source for the project but this time the new source will be Verilog Test Fixture and click Next:

Associate the source with the appropriate module and click Next:

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See the project summary, if everything looks OK,  Finish. Otherwise go back to select correct options and
finally chose Finish.

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Insert the test bench stimulus code:

Change the View in Design section from Implementation to Simulation.

Select the test bench file and double click Simulate Behavioral Model in the Process section:

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This will flush information in the Console section and will finally open the ISim, the Integrated Simulator.
Analyze the simulation results in the waveform window.

Waveform Window

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Make yourself familiar with the Simulator.

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Full adder using half adder instances:

Now, a full adder will be created by using instances of the half adders just created. This will be gate level
modeling. Also, instead of using the wizards input/output, the Inputs and outputs will be written manually in
the file.

Add New Source:

Xilinx Tool Bar  Project  New Source
OR, RtClick Chip  New Source

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Next Window will be skipped:

Verify the Summary.

If some changes required go back otherwise Click Finish.

This time, there are no ports:

Complete the design by writing the code for the full adder:

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In the design full adder is named full_adder_gl. It is easy to understand later without opening the .v file that it
is a full adder with gate level modeling.

Following full adder uses place instantiation. Named instantiation is strongly recommended.

Recommended coding style:

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Make sure that the top module is the correct module that supposed to be top. Since half adders (half_adder_dfl)
combine to make a full adder (full_adder_gl) higher level, full adder must be the top module till this design. If
the full adder is further used to make a 4 bit ripple carry adder, the 4 bit carry adder would be the top module

Check Syntax:
Make sure the correct source/module is selected and run the syntax check.

Check to see any syntax errors.

Correct the code until it is syntactically clean. Run the check until successful.

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Run the Simulation:

Make a test bench code for the full adder and run the simulation. Make sure that the test bench is associated
with the correct module (right click the module full adder and then add the new source). Give test fixture a
name full_adder_gl_tw1.

You may insert the stimulus in the test fixture file as:
#100 a=0; b=1;
#100 a=1; b=0;
#100 a=1; b=1;

Simulation Results:
Check to see the simulation results similar to the one shown:

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4 Bit Ripple Carry Adder:

Now it is time to design a ripple carry adder using 4 instances of full adders. Now, the 4 bit RCA will be the top

This time, there will be a slight change in the Source creation. Although the RCA could have been made using
the same New Source. This time instead of New Source an existing source will be added.
Create a .v file, adder_4bit_rca.v using the text editor as you would in the tool. This file must exist before
proceeding further as it has to be browsed and added. So, place this file preferably in the working directory
that is, where the project is (eg. "E:/xilinx_proj/adder_sample/).

Add Source:
Project  Add Source

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The code is:

module adder_4bit_rca ( S,CO,A,B,CI);
output [3:0] S;

[3:0] A,B;


wc1, wc2, wc3;

full_adder_gl fa0(.s(S[0]),.co(wc1)
full_adder_gl fa1(.s(S[1]),.co(wc2)
full_adder_gl fa2(.s(S[2]),.co(wc3)
full_adder_gl fa3(.s(S[3]),.co(CO)



Run Check Syntax and fix the code until syntactically clean.

Recommended coding style:

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Now the Hierarchy looks something like this:

Look at the hierarchy and understand it.

Run the Simulation:

Now make a test bench and rerun the simulation.
Sample test bench stimulus:

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The simulation seems correct.

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For synthesis and rest of the flow Implementation tab must be selected and only the top module is
synthesized. Selecting the top module in Implementation tab will bring the implement flow options.

6. User Constraint:

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This may take a while and opens PlanAhead . Close the welcome screen and select NO when asked for

From the I/O ports section select the ports one by one and fill in the site field (refer the FPGA board manual for

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For Nexys 2 FPGA kit reference manual the locations filled in the port properties.

Make sure to save the plan. After save, the design can be synthesized. PlanAhead may be closed after saving if
not required.

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Go back to the Project Navigator Window aka ISE.

Constraint file is .ucf file. After creating and saving the port plan in PlanAhead the file adder_4bit_rca.ucf
should be added and associated to the project files automatically. Verify that adder_4bit_rca.ucf is added
under hierarchy in the Design Section.

7. Synthesis:
The RTL can be synthesized now. Xilinx Synthesis Tool (XST) will be used for the synthesis.

Double Click Synthesize XST to synthesize the design.

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View RTL Schematic:

Double Click View RTL Schematic,

Double Click inside grey box to see the details (go further down the hierarchy).
RTL Schematic shows the resulting logic blocks and the connections between them.

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View Technology Schematic:

Double Click View Technology Schematic,

The Technology schematic shows what exactly is going to be implemented on the FPGA.

View Summary and Reports:

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Double Click Implement Design.

Once Completed, Implement Design will have a tick mark and this can be checked in the console as well.

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Generate Programming File:

Right Click Generate Programming File 

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Design Entry (Implementation mode):

a) New Project (only once every new project)
Project  New SourceVerilog Module  give name Next  Next Finish.
b) Design Entry using Verilog (Verilog module) DU (Design Unit)
Write the verilog code for the design and save.
c) Syntax Check:
SOURCE: Select correct file.
PROCESS: Synthesize XST Double Click Check Syntax.


Simulation (Behavioral Simulation mode):

a) TB (Test bench) for the DU.
Project  New SourceVerilog Test Fixture  give name Next  Next Finish.
b) Edit the test fixture file by adding the appropriate stimulus.
SOURCE: Select correct file.
PROCESS: Xilinx ISE Simulator Double Click Simulate Behavioral Model .


Assign FPGA component locations to the pins in DU(Implementation mode):

SOURCE: Select the top module.
PROCESS: User Constraints Double Click Floor Plan IO Pre-Synthesis

Assign appropriate locations to the pins in module and save. Go back to the ISE WINDOW.


Synthesis (Implementation mode):

SOURCE: Select the top module.
PROCESS: Double Click Synthesize XST.


Implementation-translate, map, place & route (Implementation mode):

PROCESS: Double Click Implement Design.


Generate Program File (Implementation mode):

***Skip step 6. a) if programming on-board PROM.
a) Right Click Generate Programming File  Properties  Category=Startup Options 
FPGA Start-Up Clock = JTAG Clock  OK.
b) Double Click Generate Programming File.


Programming the FPGA using Adept:

a) Connect the FPGA kit with the PC via an appropriate USB connector.
b) Switch the FPGA kit ON (Red(Power) LED will glow).
c) Windows Start Button  All Programs  Digilent  Adept  Adept.

If the FPGA kit is powered ON, connected to the PC and the Digilents USB cable drivers are installed the Adept
programmer window will auto recognize the connected FPGA kit and will show digilents device name (such as
Nexsys2 or Basys2) under Connect:.

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Also, the programming options will be available for: 1. FPGA. 2. PROM.

For FPGA: (make sure the jumper is at USB/PC )
(The programming information will be lost at power OFF and the FPGA has to be re-programmed at every
power ON and OFF so, it is a volatile programming. To retain the programming information so that it is autoloaded at every start-up, choose to program the on-board PROM)
a) Click Browse (the one next to FPGA tab)  locate the bit file generated by ISE (will have same
name as the top module and will be located in the project directory). If there is a .bit at the location
it will show.
b) Select the bit file  Click Open  Program (the one next to FPGA section).


Adept will report Program Successful.

For PROM: (make sure the jumper is at PROM/ROM)

(The programming information is retained and is auto-loaded at every start-up)

Click Browse (the one next to PROM tab)  locate the bit file generated by ISE (will have same
name as the top module and will be located in the project directory). If there is a .bit at the location
it will show.

b) Select the bit file  Click Open  Program (the one next to PROM section).


Adept will report Program Successful.


Check that a yellow LED on the FPGA kit, glows. This indicates the FPGA has been programmed.
Analyze/Observe the working of the design DU.

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