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KL University, Guntur

Academic Year: 2015 16, VII Semester


Branch: ECE Course Title: Computer Organization
Course Code : 13 EM 201
Date of Examination: 06-8-2015
Max. Marks: 05 M

Assignment Test
1. (a) Design a block diagram that implements the following statements:
x+yz: AR AR+BR, Where AR and BR are 2 n-bit registers and x, y and z are
control variables. Include the logic gates for the control functions.
(Computer system architecture by M.Morris Mano, third edition, page no: 122, problem no: 4.8)
(b) Construct the hardware that implements the following statement. Include the logic
gates for the control function and a block diagram for the binary counter with count
enable input.
xyT0 + T1 +y'T2: AR AR+ 1
(Computer system architecture by M.Morris Mano, third edition, page no: 122, problem no: 4.9)
2. (i) A computer uses a memory unit with 256 K words of 32 bit each a binary instruction
code is stored in one word of memory. The instruction has four parts; an indirect bit, an
operation code, a register code part to specify one of 64 registers and an address part.
(a) How many bits are there in the operation code the register code part and address part
(b) Draw the instruction word format and indicate the number of bits in each part.
(c) How many bits are there in the data and the address inputs of the memory?
(Computer system architecture by M.Morris Mano, third edition, page no: 169)
(ii)What is the difference between a direct and an indirect address instruction? How many
references to memory are needed for each type of instruction to bring an operand into a
processor register?
(Computer system architecture by M.Morris Mano, third edition, page no: 169)
3. How a common bus system will be connected to the computer registers and explain the
control operation related to the bus system
(Computer system architecture by M.Morris Mano, third edition, page no: 132)
4. Derive a combinational circuit that selects and generates any of 8 logical operations listed
below

(Computer system architecture by M.Morris Mano, third edition, page no: 123,problem no:4.16)

5. The outputs of 4 registers R0, R1, R2 and R3 are connected through 4-to-1-line
multiplexer to the inputs of 5th register R5. Each register is 8bit long. The required transfer
are dedicated by four timing variables T0 through T3 as follows
T0: R5 R0
T1: R5R1
T2: R5 R2
T3: R5 R3
The timing variables are mutually exclusive, which means that only one variable is equal
to 1 at any given time, while the other three are equal to zero. Draw a block diagram
showing the hardware implementation of the register transfers. Include the connections
necessary from the four timing variables to the selection inputs of the multiplexers and to
the load input of register R5.
(Computer system architecture by M.Morris Mano, third edition, page no: 121, Problem
4.2)
6. Design an arithmetic circuit with one selection variable S and two n-bit data inputs A and
B. the circuit generates the following four arithmetic operations I conjunction with the input
carry Cin. Draw the logic diagram for the first two stages
S
0
1

Cin = 0
D=A+B (add)
D=A-1 (decrement)

Cin=1
D=A+1 (Increment)
D=A+B+1 (Subtract)

(Computer system architecture by M.Morris Mano, third edition, page no: 123, Problem
4.15)