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MOSFET Operation

Day 11-12
ECE3030
Jeff Davis

CMOS Transistors!
(Complementary MOSFET)
p-channel MOSFET
acts like normally
closed switches
VDD
b

a

z’

z

a

n-channel MOSFET
acts like normally
open switches

b
GRD

2

nMOS (or nFET) Transistor!
(Switch level model)
n-channel MOSFET acts like normally open switches
gate voltage = LOW
drain
drain

source

gate

source

gate voltage = HIGH

drain

source

3

pMOS (or pFET) Transistor! (Switch level model) p-channel MOSFET acts like normally closed switches gate voltage = LOW drain source drain gate gate voltage = HIGH source drain source 4 .

channel n+ n+ S(emiconductor) p 5 .A new device: MOSFET! glass (silicon dioxide) Gate Source Drain M(etal) silicon wafer surface O(xide) Add lots phosphorus to source and drain junctions.

Band Diagram ACROSS the Channel Gate Source Drain x channel (in equilibrium) Source channel EF Drain EC Ev x .

Apply Voltage Across Drain and Source Vdd Vdd Drain Gate + VDS Source gate voltage = LOW .

Band Diagram Long Channel Device VG = 0 Unbiased Bias Junction Ec Ev Unbiased Junction VDS = 0 .

Band Diagram Long Channel Device VG = 0 Unbiased Bias Junction Ec Unbiased Junction VDS = 0 VDS = small voltage Ev .

Band Diagram Long Channel Device VG = 0 Unbiased Bias Junction Ec Unbiased Junction VDS = 0 VDS = small voltage Ev VDS = large voltage .

Leakage Currents VG = 0 Unbiased Bias Junction Unbiased Junction Ec - VDS = 0 VDS = small voltage Ev Drain-Induce Barrier Lowering (DIBL) can occur on the source junction as the drain junction gets closer to the source! VDS = large voltage pn junction leakage at reverse bias drain junction .

.DIBL with 45nm Devices Lau.” Microelectronics Reliability. vol. 49 (2009)p.”Drain current saturation at high drain voltage due to pinch off instead of velocity saturation in sub-100nm metaloxide-semiconductor transistors. 1-7.

Band Diagrams for MOSFET .

Simultaneous View of Both Directions .

MOS Capacitor M(etal) O(xide) S(emiconductor) n+ n+ 2.2 things we must understand! 1. MOSFET Channel Conduction 15 .

MOS Capacitor Gate voltage VG Metal “Gate” Insulator Semiconductor Substrate grounded! 16 .

Example Calculation Assuming for the moment that the semiconductor acts like a good conductor. L = 180nm 180nm Technology VDD = 1.236[ fF ] gate capacitance estimation .8V L = 180nm xox = 5nm xox = 5nm C ox = x ox O(xide) Z = width S(emiconductor) Special Parameter.903e − 7) *10 * (180e − 7cm)(180e − 7cm) C gate = 2. Cgate C gate = Cox ZL = (6.903e − 7[F /cm 2 ] capacitance per unit area! Total Capacitance.236e − 15[F ] = 2. what is the capacitance of a MOS capacitor that has a gate length of 180nm and a transistor width that is 10x the length.85e − 14[F /cm]) 5e − 7[cm] C ox = 6. Assume that the oxide thickness is 5nm.9)(8. Cox K SiO2 ε o M(etal) = (3.

Work Function/Affinity
Vacuum Level

Electron Affinity

ΦM = work function of the metal
ΦS = work function of the semiconductor
18

MOS Materials Capacitor

19

MOS Capacitor
Assumption of this discussion

ΦM = ΦS

20

MOS Capacitor Under Bias 21 .

e.e.e.e- n = e(Fn − Ei )/ kT p=e (Ei − Fp )/ kT 22 .e.e.e.e.e.e.e.e.Accumulation VG > 0 with n-type substrate These are referred to as quasi-fermi levels! VG n Accumulation of MAJORITY carriers! M(etal) O(xide) e.e.

Depletion VG < 0 for n-type substrate Depletion region forms at surface of semiconductor! 23 .

Inversion VG < VT for n-type substrate Note that VT is negative for this case! pinterface = ND n = e(Fn − Ei )/ kT p=e (Ei − Fp )/ kT Inversion layer of minority carriers (holes) is created at surface! 24 .

Strong Inversion VG << VT for n-type substrate n = e(Fn − Ei )/ kT p=e The number of minority carriers (holes) at surface is increased significantly! (Ei − Fp )/ kT 25 .

Bias Types for P-type Material ACCUMULATION DEPLETION INVERSION 26 .

1 φ F = [Ei − BULK − EF ] q φS = Reference taken at the bulk! 27 .Surface Potential φ(x) = electrostatic potential inside the semiconductor at a depth x 1 φ (x ) = [Ei − BULK − Ei (x )] ≡ electrostatic potential q and P-type Example 1 [Ei − BULK − Ei− INTERFACE ]≡ surface potential q along with.

φ s = 2φ F 28 .Condition for “Threshold Voltage” Surface potential that gives a concentration at the Si/SiO2 interface that is the same as the concentration in the bulk.

Condition for “Threshold Voltage” p BULK = ni e (Ei− BULK − EF ) kT = NA (EF − Ei− BULK ) and n BULK = ni e  kT  N A  ln  for a p-type semiconductor    q  ni  φF =  − kT ln  N D  for a n-type semiconductor  q  n  i  kT = ND 29 .

2885V .45e10cm φ F = 0. N A = 1015 cm −3 Solving for the Fermi potential gives the following: φF = kT N ln( A ) q ni (1.45e10 cm-3.38e − 23 J/K)(300 K) 1015 cm-3 φF = ln( ) -3 1. We know by definition that the channel is p doped because it is an nFET.6e −19C 1.Example Calculation Find the Fermi potential in the body of the n-channel transistor assuming that the channel doping concentration is 1015 cm-3. Assume the room temperature intrinsic carrier concentration is given by 1.

φ s = 2φ F From the previous example we can know that the Fermi potential in the body is: φ F = 0.2885V φ s = 2(0.577 V .Example Calculation For the previous example how much band bending do we need to have to reach the threshold condition? More specifically what is the surface potential at threshold? We know the threshold condition is set when the surface potential is twice the Fermi potential in the “body” of the transistor.2885) = 0.

What is the GATE voltage that gives this surface potential! φ s = 2φ F .

Surface Potential and Gate Voltage Relationship VG=φoxide+φS Potential drop across oxide Potential drop across the bulk (which is surface potential) 33 .

...........What about voltage drop across the oxide? VG=Φoxide+φS Q=CV Φ oxide QB ZL = C ox ZL M(etal) O(xide) ......- Z = transistor width L = transistor length Depletion region is formed first! 34 ..

...) VG = φs + φoxide Remember this is the surface potential! C ox φoxide K SiO2ε o = x ox Q=CV QB qN AW = = Cox Cox M(etal) O(xide) W ......- xox W= 2K S ε oφ s qN A This is an expression for the width of the depletion region! 35 ......What is the relationship between surface potential and gate voltage! (Note that this assumes FREE inversion charge is much less than FIXED charge in channel.....

8715 microns .577 V The width of the depletion region at threshold is given by: W = 2 * 11.Example Calculation What is the width of the depletion region when the surface potential is at the threshold condition? Assume the doping in the channel is 1015 cm-3 Assume that the KSiO2= 3. W= 2K S ε oφ s qN A From the previous example we can know that the surface potential at “threshold” is: φ s = 2(0. and εo = 8.9.9 * 8.85e − 14 * 0.2885) = 0.577 1.6e − 19 * 1015 W = 8. KS = 11.9.85e-14 F/cm.715e − 5 cm = 0.

What is the relationship between surface potential and gate voltage! 37 .

What is the relationship between surface potential and gate voltage! 2qN A K s ε oφ s VG = φ s + xxoox K SiO2ε o VG φ Threshold voltage!!! s = 2φ F 2qN A K s ε o 2φ F = VT = 2φ F + xxoox K SiO2ε o 2kT  N A  2φ F = ln  q  ni  p-type 38 .

596[V ] . We have already calculated the Fermi potential for this doping to be: φ F = 0.85e −14) VT = 0.2885) VT = 2(0.85e −14)2(0. Assume 180nm technology specifications that have been outlined in previous graphs.9.02011 = 0. Assume the doping in the channel is 1015 cm-3 Assume that the KSiO2= 3.6e − 19)(1015 )(11.9.2885V The estimation of the threshold voltage for this case is: 2qN A K sε o 2φ F VT = 2φ F + x ox K SiO2 ε o 2(1.9)(8. KS = 11. and εo = 8.Example Calculation Calculate the threshold voltage for an nFET.85e-14 F/cm.576 + 0.2885) + 5e − 7[cm] (3.8)(8.

Threshold Voltage Expressions for nFET and pFET VT = 2φ F + εS C ox 2qN A (2φ F ) (for n .channel devices) εS VT = 2φ F − εS C ox 2qN D (− 2φ F ) (for p .channel devices) εS where. C ox = ε ox xox is the oxide capacitance per unit area ε S = K Sε o ε ox = K SiO2 ε o 40 .

Qualitative Description MOSFET Current 41 .

” 42 . n-channel MOSFET = “nFET” or “nMOS transistor” Change conductivity of channel region “Control by the GATE voltage is achieved by modulating the CONDUCTIVITY of the semiconductor region just below the gate.MOS Transistor Qualitative Description Electron flow from “Source” to “Drain” is controlled by the “Gate” voltage.

N-channel MOS Transistor Qualitative Description MOSFETs WON’T WORK IN ACCUMULATION! VGS < 0 (accumulation) “The source to drain path consists of two back to back diodes.E. One of these diodes is always reverse biased regardless of the drain voltage (I. VDS) polarity… holes won’t flow! “ P-type .

” High 〉 due to Depletion For ANY value of VDS: 44 .N-channel MOS Transistor Qualitative Description 0<VGS <VT (depletion  “CUTOFF”) “There is a deficit of electrons and holes making the channel very highly resistive. => No Drain current can flow.

type region.N-channel MOS Transistor Qualitative Description VDS = 0 VGS > VT “An induced n.” Inversion layer (n-type) P-type 45 . an “inversion layer”. forms in the channel and “electrically connects” the source and drain.

depends linearly on the DRAIN voltage VD. this current.type region allows current to flow between the source and drain. This mode of operation is called the linear or “triode”* region. ID.N-channel MOS Transistor Qualitative Description Small positive VDS VGS > VT(continued): “The induced n. The induced channel acts like a simple resistor.” Inversion layer (n-type) P-type 46 . Thus.

N-channel MOS Transistor Qualitative Description Small positive VDS VGS > VT(continued): “Drain current verses drain voltage when in the linear or “triode”* region.” Linear region 47 .

48 .N-channel MOS Transistor Qualitative Description Reduced electron concentration in the Inversion layer near the drain VGS > VT P-type Leads to current starting to roll off for larger VDS.

N-channel MOS Transistor Qualitative Description Channel Conductivity starts to pinch off near the drain! Saturation region Linear Region This occurs when VG .VD = VT IDsat VDsat = saturation voltage = VGS-VT 49 .

Channel changes as we increase VDS! (Assume VG is greater than the threshold voltage) VDS = 0 VDS < VD.SAT VDS =VD.SAT VDS > VD.SAT .

ID-VDS curves for various VGS: VDsat depends on VG 51 .MOS Transistor Qualitative Description Finally.

Quantitative Current Model! 52 .

Effective Surface Mobility Surface scattering REDUCES Mobility! BULK VALUE µ n = 1350 Average Surface VALUE µ n = 200 53 .

Quick Estimation .

Inversion Charge Estimation QI = Cox (VGS − VT ) Below threshold applied voltage produces BULK charge NOT free charge! L .

QI = Cox (VGS − VT ) L I= Charge in Channel time to move charge out of channel C ox (VGS − VT )ZL I= ∆t L vd = = µE field ∆t Z I = µ C ox (VGS − VT )VDS L L2 ∆t = µVdd E field Vdd ≈ L .

VT Z (VGS − VT )2 L VDS 57 .“Zeroth Order” Capacitor Current Model IDS Saturation region Linear region I ≈ Cox µ Z (VGS − VT )VDS L I ≈ Cox µ VDS = VGS .

Is there a better model? 58 .

Observation: Inversion Charge is not always UNIFORM in Channel VDS = 0 VDS < VD.SAT VDS =VD.SAT .

Inversion Charge is not Uniform! Source MOS Capacitor ( QN ≅ Cox VGS −VT ) for VGS ≥ VT Neglect the depletion region charge Drain MOS Transistor ( QN ≅ Cox VGS − VT − ϕ ) for VGS ≥ VT 60 .

First Order Square Law Model – LINEAR REGION Z µn ID = L Z µn ID = L ∫ φ = VDS ∫ φ = VDS φ= 0 φ= 0 QN dφ Cox (VG − VT − φ )dφ 2  Z µ nCox  VDS ID = (VGS − VT )VDS −   L  2  0 ≤ VDS ≤ VDsat and VGS ≥ VT This is known as the “square law” describing the Current-Voltage characteristics in the “Linear” or “Triode” region. 61 .

( ) QN (y = L) ≅ Cox VGS −VT −VDsat = 0 or VGS −VT = VDsat Thus.First Order Square Law Model – SATURATION REGION For VDS>VDsat I D = I Dsat 2  Z µ nCox  VDsat = (VGS − VT )VDsat −  L  2  VDsat ≤ VDS But. I D = I Dsat = Z µ nCox  2  V − V ( ) GS T  2L  VDsat ≤ VDS 62 .

MOS Transistor I-V Derivation 2  Z µ nCox  VDS ID = V − V V − ( ) GS T DS L  2  0 ≤ VDS ≤ VDsat and VGS ≥ VT I D = I Dsat = Z µ nCox  2 VGS − VT )  (  2L  VDsat ≤ VDS V Dsat = VGS − VT 63 .

8 is greater than 0.319e − 4[ A] = 0.903e − 7(1.9 −  2   I D = 9.6 therefore NOT in cutoff! VD.2V VDS = 0.SAT = VGS − VT = 1.8 − 0. linear region. VGS > VT 1. or saturation. Also assume that the surface mobility is 200 cm2/Vs.9319mA . and the transistor width is 10x the transistor length.9 is less than VD.9) 2  I D = 10 * 200 * 6.8 − 0. First we must consider the whether the device is in cutoff.SAT = linear region! Now we can use the appropriate formula! 2  Z µ nCox  VDS ID = (VGS − VT )VDS −  L  2  0 ≤ VDS ≤ VDsat and VGS ≥ VT  (0.6 = 1.6)0. Assume that the VGS = VDD and VDS = VDD/2.Example Calculation Calculate the current through the MOSFET assuming that the threshold voltage is 0.6V and the rest of the parameters correspond to 180nm technology.

or saturation.6 therefore NOT in cutoff! VD.6) I D = 9.SAT = VGS − VT = 1.8*VDD.9940[mA] ] .940e − 4[ A] = 0.8 is greater than 0.8*1.6V and the rest of the parameters correspond to 180nm technology.44 is greater than VD.6 = 1. and the transistor width is 10x the transistor length. linear region.8 = 1. Assume that the VGS = VDD and VDS = 0. VGS > VT 1.5* 200 * 6.8 − 0. First we must consider the whether the device is in cutoff.SAT = saturation region! Now we can use the appropriate formula! I D = I Dsat = Z µ n Cox  2 VGS − VT )  (  2L  VDsat ≤ VDS [ 2 I D = 10 * 0. Also assume that the surface mobility is 200 cm2/Vs.2V VDS = 0.Example Calculation Calculate the current through the MOSFET assuming that the threshold voltage is 0.8 − 0.903e − 7 (1.

or saturation. Assume that the VGS = 0.sub = I x (1− e VDS kT / q (VGS −VT ) )e − S = I x (1− e VDS kT / q −VT )e S VGS =0 S = subthreshold slope Ix= parameter that is proportional to device width (Z) .8*VDD.Example Calculation Calculate the current through the MOSFET assuming that the threshold voltage is 0. Also assume that the surface mobility is 200 cm2/Vs.18 is less than 0. First we must consider the whether the device is in cutoff.1 V and VDS = 0.6 therefore in cutoff! ID ≈ 0 A more accurate answer is that that there is leakage! Notice dependence below! − I D.6V and the rest of the parameters correspond to 180nm technology. VGS > VT 0. and the transistor width is 10x the transistor length. linear region.

Subthreshold Leakage Currents A more accurate answer is that that there is leakage! Notice dependence below! − I D.sub = I x (1− e VDS kT / q (VGS −VT ) )e − S = I x (1− e VDS kT / q −VT )e S VGS =0 S = subthreshold slope exponential dependence on threshold voltage Ix= parameter that is proportional to device width (Z) Conclusion Subthreshold current ∝ Z Subthreshold current ∝ e − VT S .

the potential across channel stays as (VGS-VTn) All excess voltage is across pinch off region 68 . “pinch-off” region grows by ⊗L ! As VDS grows.Channel Length Modulation Effect For VDS > Vdsat = VGS-VTn.

Channel Length Modulation Effect Channel Length Modulation I D = I Dsat Z µ nCox  2 = (VGS − VT )  (1 + λ VDS )  2L Channel Length Modulation Parameter VDsat ≤ VDS 69 .

Current Equations NMOS Regardless of Mode K n = K n' PMOS W W W W = µ n C ox (Note : W = Z in Pierret) K p = K p' = µ p Cox L L L L (Note: W = Z in Pierret) Cutoff i DS = 0 Linear iDS 2  Z µ n Cox  vDS = (vGS − VTN )vDS −   L  2  vGS − VTN ≥ vDS ≥ 0 Saturation iDS = VT for Enhancement Mode for vGS ≤ VTN Z µ nCox  (vGS − VTN )2  (1 + λ vDS )  2L for vDS ≥ vGS − VTN ≥ 0 VTN > 0 iSD = 0 iSD iSD = for vSG ≤ −VTP 2  Z µ nCox  vSD = vSG − VTP )vSD − (  L  2  vSG + VTP ≥ vSD ≥ 0 Z µ pCox (v − V )2  (1 + λ v ) SG TP SD  2L  for vSD ≥ vSG + VTP ≥ 0 VTP < 0 70 .