Engineering Procedure

Signalling

CRN SC 023
DESIGN OF MICROLOK II
INTERLOCKINGS
Version 2.1
Issued March 2015

Owner:
Approved by: Stewart Rendell
Authorised by: James Zeaiter
Disclaimer. This document was prepared for use on the CRN Network only. John Holland Rail Pty Ltd
makes no warranties, express or implied, that compliance with the contents of this document shall be
sufficient to ensure safe systems or work or operation. It is the document user’s sole responsibility to
ensure that the copy of the document it is viewing is the current version of the document as in use by
JHR. JHR accepts no liability whatsoever in relation to the use of this document by any party, and JHR
excludes any liability which arises in any manner by the use of this document.
Copyright. The information in this document is protected by Copyright and no part of this document
may be reproduced, altered, stored or transmitted by any person without the prior consent of JHR.

UNCONTROLLED WHEN PRINTED

Page 1 of 79

CRN Engineering Procedure - Signalling
Design of Microlok II Interlockings

CRN SC 023

Document control
Revision

Date of Approval

Summary of change

1.3

October 2006

RIC Standard SC 05 43 00 00 SP Version 1.3 October 2006.

1.0

June 2011

Conversion to CRN Signalling Standard CRN SC 023.

2.0

May 2014

Major update to include of missing sections and removal of Dual
Hot Stand-by arrangements

2.1

March 2015

Update Elsafe immunisation module codes from 216640 to 216643

Summary of changes from previous version
Section

Summary of change

2.3.2

Update Elsafe immunisation module reference from 216640 to 216643

2.3.3

Update Elsafe immunisation module reference from 216640 to 216643

2.3.4

Update Elsafe immunisation module reference from 216640 to 216643

2.10.5

Update Elsafe immunisation module reference from 216640 to 216643

© JHR
Issued March 2015

UNCONTROLLED WHEN PRINTED

Page 2 of 79
Version 2.1

CRN Engineering Procedure - Signalling
Design of Microlok II Interlockings

CRN SC 023

Contents
1
2

Reference Documents ............................................................................................................................. 6
System Configuration .............................................................................................................................. 6
2.1
General .......................................................................................................................................... 6
2.2
Design Goals ................................................................................................................................. 7
2.2.1 High Traffic Areas .................................................................................................................. 7
2.2.1.1
2.2.1.2

Definition ..................................................................................................................................... 7
Goals .......................................................................................................................................... 7

2.2.2 General Traffic Areas ............................................................................................................ 7
2.2.2.1
2.2.2.2

Definition ..................................................................................................................................... 7
Goals .......................................................................................................................................... 7

2.2.3 Low Traffic Areas ................................................................................................................... 8
2.2.3.1
2.2.3.2

Definitions ................................................................................................................................... 8
Goals .......................................................................................................................................... 8

2.3

Power Supply Configuration .......................................................................................................... 8
2.3.1 General .................................................................................................................................. 8
2.3.2 High Traffic Areas .................................................................................................................. 8
2.3.3 General Traffic Areas ............................................................................................................ 9
2.3.4 Low Traffic Areas ................................................................................................................... 9
2.4
Interlocking Equipment Configuration ......................................................................................... 10
2.4.1 High Traffic Areas ................................................................................................................ 10
2.4.2 General Traffic Areas .......................................................................................................... 10
2.4.3 Low Traffic Areas ................................................................................................................. 10
2.4.4 Connection to Adjacent Interlockings .................................................................................. 10
2.5
Control System Communication Link Configuration ................................................................... 11
2.5.1 General ................................................................................................................................ 11
2.5.2 High Traffic Areas ................................................................................................................ 11
2.5.3 General Traffic Areas .......................................................................................................... 11
2.5.4 Low Traffic Areas ................................................................................................................. 11
2.6
Safety System Communication Link Configuration ..................................................................... 11
2.6.1 General ................................................................................................................................ 11
2.6.2 High Traffic Areas ................................................................................................................ 12
2.6.3 General Traffic Areas .......................................................................................................... 12
2.6.4 Low Traffic Areas ................................................................................................................. 12
2.7
Equipment Housing And Cable Route Configuration .................................................................. 12
2.7.1 General ................................................................................................................................ 12
2.7.2 High Traffic Areas ................................................................................................................ 13
2.7.3 General Traffic Areas .......................................................................................................... 13
2.7.4 Low Traffic Areas ................................................................................................................. 13
2.8
Microlok Specific Configuration Issues ....................................................................................... 13
2.8.1 General ................................................................................................................................ 13
2.8.2 Approved Microlok II Modules ............................................................................................. 15
2.8.3 Timers in High Traffic Areas ................................................................................................ 17
2.8.4 Timers in General Traffic Areas ........................................................................................... 17
2.8.5 Timers in Low Traffic Areas ................................................................................................. 17
2.8.6 Microlok Interlocking Simulator Systems (MISS) ................................................................ 17
2.9
Microlok Platform Safety Application Guidelines ........................................................................ 17
2.10
Track Side Equipment Configuration .......................................................................................... 20
2.10.1 Signals ................................................................................................................................. 20
2.10.1.1
2.10.1.2

Direct Control by Microlok II .................................................................................................... 20
Relay Control .......................................................................................................................... 21

2.10.2 Track Circuits ....................................................................................................................... 21
2.10.3 Microtrax Coded Track Circuits ........................................................................................... 21
2.10.4 Relay Noise Suppression .................................................................................................... 22
2.10.5 Microlok II Input Circuits External to the Location ............................................................... 22
2.11
Cables and Wiring ....................................................................................................................... 23

© JHR
Issued March 2015

UNCONTROLLED WHEN PRINTED

Page 3 of 79
Version 2.1

...................................................5..........4....................................5......................................................................................2 Leased Line Settings ...............................6 Wiring .. 33 Application Logic Design ........1.................................................. 26 3..........1 Colour Coding ..................................1 ........2 3...........................................................4..............................................................4 Conversion Between RS232 and RS485 ....... 26 3......................... 35 4.......................... 32 Dial-up Settings ...........2 Design Process .5 Boolean Bits ...............................2...............................................................1.........3.................11.....2................... 26 Slave Settings ..............1...............................11................................................................2 Fibre Optic Links .................................................................................. 24 2............................................3 Naming Conventions ..................... 38 4........ 26 3...................................................................................................................................................................................................................................................................2..............5..........................3 Elements of the OCS Philosophy ............................................................2 2.....................11.................. 38 4.................................. 37 4.................... 27 3. 35 4........4 Elements of the NX Philosophy ............5.......5..........................................................................................................................................................................................2....................... 34 4.5............................................ 36 4..... 29 3........................... 26 Distance for Single Mode Fibre...............5..........5 Fibre Optics ...........................................................4................ 31 3......................... 30 3...............................................................5 2...............1 3............5....................................................Signalling Design of Microlok II Interlockings CRN SC 023 2................................................ 34 4.................................4.................... 25 Cable ...............................5....1 2.... 33 4.................................6 2............7 Log Bits ........ 27 3.......... 38 © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 4 of 79 Version 2...................... 26 3.........................3 Circuits .......................................................................................................................2 Master settings ...... 35 4......................................................................................................1 RS232 Control Lines .......................................................11....................2...................3 2..... 29 3..........................................................................1.....3 4 Control Line States ...............................................3.....................2 Address Allocation ............................1 3........ 23 2............................ 30 3.................................................................................................5..........3 System Limitations ..........2 Master ........ 32 3......................................... 34 4.............................................................................. 30 3..... 37 4........................... 26 Distance for Multimode Fibre ........2.........................................3 Analogue Modems ..........................4 Circuits .........................................................................................11.......... 33 3.................................................................................. 37 4...........................................5......................................................................................3............................................ 28 Exicom 396 Modem Settings .........................2.................................................................................................................................. 31 3.................................................4 Standardisation of OCS Control of Interlockings ....1..........................5...........................3.......................... 26 Fibre Optic Modems ..........11........................1.................................6.............................................................................2 Applicability .........................................................................2.............................................................................. 33 4....7 3 General ........... 37 4................................2 Master Settings ...............................................................................................................................................1 Background.................1.........................................................................6.....2 RS422/RS485 Control .....................6 Timer Bits ..........................................................................................11...................................... 36 4.................................................. 31 3.............................................................................................5 Conversion Between RS485 and RS232 ..................................................................................5..4 Interface Section .................................. 25 Patch Leads .....1..........2..........1 Slave ... 28 3.......................................................................................5 General Guidelines .........CRN Engineering Procedure .........................................................5 Changes to Interlocking Philosophy ................... 25 Fibre Management Enclosure ...................................................................11........ 25 2......... 24 2......................................................................................................11................ 26 Serial Link Communications ......................................................................................................................................................................................6 Further Enhancements to the Interlocking Philosophy ........... 29 Genisys Links (Control System Link) .4................................................................. 38 4........ 27 Slave Settings ................................3 3.......1 Introduction .............................................................................................................................3 Internal Wire .... 24 2.1...................6 Modem Configuration ...............................................................3...4........................................2 General Multi-Core Cable ...............................................................1 3.............................................................................5..........4 2...............................................................................................3 RS423 Control ...................... 33 3.........5 Wiring ....1................................11........................................1 General ..........................................................................................................11...... 31 3..........................................................1.... 33 3.....1 Program Title ..............11............4 Heavy Duty Cable ..........................................................................................................................................................................1 Vital Serial Links .2..........................3................................................ 34 4........................................

........... 52 5...............................................................................5..................................1 N12 Connections and Vital Output Cards .............................5.............................................................1................................... 50 5....................2 5........................9 Constants .................5.........................................................................11 Vital Serial Ports .................................................................2...... 39 4..................23 System Clock ................................2..................................................................2.............................................................5........................5...........3 6 7 CRN SC 023 Isolated External Supplies .............................................................. 52 5..................CRN Engineering Procedure ........................2....................................................................................... 43 4.5................ 41 4.... 50 5...... 50 5............................................................21 Points .................................. Single-sided Installations ........................................................2........................................................................................ 43 4.....17 Vital Blocking ............ 40 4..............5..........................1 Microlok II Design Configuration and Settings ..2 Microlok II Power Consumption ......................................................................... 43 4...............1 Arrangements of Cards in Card Files ......................2................................1.........................................1...............16 Coded Track Circuits ...... 49 4.............2 Power Supply Card .....................................................................1 5...................................... 51 External Power Supply .........................2 5......................................................... 40 4....................................5....................................5.............................................. 49 Circuit Design ..........2.................................................................................................................19 Tracks . 44 4.......5..5..............................................................................1................................................... 43 4.................................5.................... 52 Setting To Work ................................20 Signals .....15 Lamp Driven Signals ....................................................14 Logic Queue Overflow .........................................................5...........................8 Boolean Logic .......................................................... 46 4.........................................................22 Ground Frames.................................5.................................................................................................................................................................................................. 53 Appendix A .......................................10 Conditional Power Supply Logic ...............................................13 Revision Number Verification ..........5.... 55 © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 5 of 79 Version 2..............1..............................Typical Circuits .................. 52 Larger........... 40 4.......................1 .......................................... 43 4...............................1 5................................ 51 Circuit Design Hazards....... 42 4.....................................................................................................................................................1.............18 Level Crossings ......................................5.2 Output Card Faults ...Signalling Design of Microlok II Interlockings 5 4..................................................1............ Single-sided Installations ................................................................................... 52 Small.......................................................... 40 4..12 Program Verification Logic ... 51 5........ 52 5..............................................................

2 System Configuration 2. Trouble Shooting and Maintenance SM-6800C Microlok II System Application Logic Programming Guide SM-6800D Microlok II Programmable Controller Platform Safety Application Issues Microlok II Application Logic Comparison Tool SM-8584 Microlok.Signalling Design of Microlok II Interlockings 1 CRN SC 023 Reference Documents The following documents provide supporting information or referenced information to that provided by this document.The Microlok II manuals. Microlok Data Design and Factory Acceptance Test CRN SQ 001 .1 General This section details a set of design goals and methods of achieving the design goals when designing the system configuration for particular installations. US&S Documents Microlok II System Description SM-6800A Microlok II Hardware Installation SM-6800B Microlok II System Start up. .The CRN Signalling Engineering Standards.29 Signals Power Designs CRN SQ 001 .27 Checking of Microlok Circuit and Data Designs CRN SQ 001 . Microtrax. Surge protection Installation Guideline Ancillary Equipment Temperature rating Installation Guideline LED signals controlled by relay circuits Design Guideline CRN Engineering Standards The Principal Signal Engineer upon request may provide the CRN documents.1 .Signalling design quality procedures.Signalling design guidelines. The signalling system configuration must comply with: . Genisys – Circuit Design Application Notes CRN Documents Microlok File Control. .14 Re-Testing of Microlok Data CRN SQ 001 .CRN Engineering Procedure .51 Proposal for Standard Specification alterations to address issues with 415V signalling power distribution. © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 6 of 79 Version 2. .

Clearly identified safety requirements and how they are achieved.1.Common mode failure risks are identified and managed in some way. .1 Definition General traffic areas are unidirectional Signalling with Headway Designs of less than 10 minutes or Bi-direction Signalling with Headway designs of less than 15 minutes.2.Choose equipment with demonstrated level of reliability.Signalling Design of Microlok II Interlockings 2.2. .Provide duplication for items that could cause a whole interlocking area to fail.The time delay from power on to the system being fully operational shall be less than 5 minutes. .All new works or alterations within the duplicated part of the system can be undertaken and tested without operational impact except for the final commissioning activities. .Provide facilities to permit disconnection of signalling equipment as per the Microlok Computer Based Interlocking Signalling Maintenance Procedure CRN SP 037.1 Definition CRN SC 023 High traffic areas are unidirectional Signalling with Headway Designs of less than 4 minutes or Bi-direction Signalling with Headway designs of less than 7 minutes in the normal running direction.Duplicated parts of the system are able to be isolated and have corrective action completed without disruption to train operations. .Provide a power supply system with two independent sources of supply that will also withstand loss of all incoming power for at least 10 minutes.Common mode failure risks are identified and have a design solution implemented to address the risk.All failures within the duplicated system to generate an alarm or warning or be revealed by maintenance task. 2.1 . . .2 Design Goals 2. Some ancillary equipment may require supply breaks to be less than 20mS. .2.2.Provide a power supply system that ensures breaks in supply to equipment are normally less than that required to disrupt the normal operation of the equipment.Design to ensure a single failure does not fail more than 2 signals on each line in each direction or have a fallback operational mode that can reduce the impact to equivalent to 2 failed signals in each direction. . which do not come within the High traffic area definition.Provide duplication so that each single failure point will not cause more than one signalling object to fail except for items that can be demonstrated as "unlikely to fail within the expected life of the system".2 General Traffic Areas 2.CRN Engineering Procedure .Design to ensure independence of each line or minimise impact on adjacent lines.Provide duplication for items that may require more than one maintenance team involved in corrective action or will take more than 2 hours to repair. 2.2.2. © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 7 of 79 Version 2.2 Goals .2. .1 High Traffic Areas 2.2.1. .2 Goals . . which are minimised. . . .Clearly identified safety and reliability requirements and how they are achieved. 2.

2. . higher than 120V).3.Provide facilities to permit disconnection of signalling equipment as per the Microlok Computer Based Interlocking Signalling Maintenance Procedure CRN SP 037.Choose equipment with demonstrated level of reliability.The time delay from power on to the system being fully operational shall be less than 5 minutes.1 .Design to minimise single point failures that can impact on multiple lines. Normal and emergency supplies must be provided independently from the electricity grid. Power distribution should be at extended voltage (that is. with a standalone power supply capacity of 10 minutes or more. © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 8 of 79 Version 2.All failures within the duplicated system to generate an alarm or warning or be revealed by a maintenance task.2. Components that are likely to fail within the life of the installation are to have redundant facilities as part of the design.1 General Power load calculations are to be as per Signal Design quality procedure CRN SQ 001 .2. .Provide duplication for items that may require more than one maintenance team involved in corrective action.CRN Engineering Procedure .3.Duplicated parts of the system are able to be isolated and have corrective action completed without disruption to train operations. .Choose equipment with demonstrated level of reliability. Full galvanic isolation is required between each signalling location. .3 Power Supply Configuration 2.Signalling Design of Microlok II Interlockings CRN SC 023 .Clearly identified safety requirements and how they are achieved.51 Signals Power Design.2 Goals .Design to ensure a single failure does not fail more than 2 signals on each line in each direction or have a fallback operational mode that can reduce the impact to equivalent to 2 failed signals in each direction. under normal circumstances.The time delay from power on to the system being fully operational shall be less than 5 minutes.3.Provide a power supply system that ensures breaks in supply to equipment are normally less than that required to disrupt the normal operation of the equipment.Provide facilities to permit disconnection of signalling equipment as per the Microlok Computer Based Interlocking Signalling Maintenance Procedure CRN SP 037. . 2. . 2.1 Definitions Low traffic areas are all other areas that the High traffic and General traffic definitions do not apply. . . and design to provide breaks of less than 10mS.3 Low Traffic Areas 2. . 2.3. 2.Provide a power supply system with two independent sources of supply that will also withstand loss of all incoming power for at least 1 minute. .Provide a power supply system that will prevent a loss of power that will delay more than one train.2 High Traffic Areas Provide redundant supplies. . . .

2. The Microlok II 12V supply is to be battery backed up as per the Microlok II manuals. In some cases.3. Solar power designs must have a minimum of 7 days autonomy. 2. The power system must detect “brown outs” in the normal supply and then use the other supply.000 hours. The Normal supply must be provided from the electricity grid and a railway supply is preferred.3 General Traffic Areas Supply breaks of up to 30 seconds can be tolerated but should normally be less than 0. Choose approved DC power supplies with a Mean Time Between Failures (MTBF) of greater than 100. not all equipment may be provided with emergency supply (e. Normal supply can be from electricity grid or solar power. un-regulated DC power supplies may be used for external inputs provided that Elsafe immunisation modules (216643) are fitted at the Microlok II inputs. © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 9 of 79 Version 2.g. A standalone power supply capacity of 1 minute or more must be provided.000 hours for those DC supplies that do not have redundancy. The power system must detect “brown outs” in the normal supply and then use the other supply. The emergency supply may alternatively be automatically provided by generator. which may use nonredundant supplies as per normal practice for DC supplies that will cause an immediate failure. or battery with an 8 hour endurance minimum. however interlocking equipment must remain functional when operating from the emergency supply.CRN Engineering Procedure .Signalling Design of Microlok II Interlockings CRN SC 023 The power system must detect “brown outs” in the normal supply and then use the other supply. un-regulated DC power supplies may be used for external inputs provided that Elsafe immunisation modules (216643) are fitted at the Microlok II inputs. However existing unfiltered. Normal and emergency supplies must be provided from independent sources.1 . point machines). N+1 redundancy is required for all DC supplies other than track circuits. The Microlok II 12V supply is to be battery backed up as per the Microlok II manuals. Outside the electrified area the emergency supply may be provided by a motor generator. However existing unfiltered. The emergency supply should usually be provided from the electricity grid. DC power supplies are to be filtered and regulated. which may use nonredundant DC supplies as per normal practice. or battery with a 12 hour endurance minimum.1 seconds and occur less than once per 3 month period. DC power supplies are to be filtered and regulated.4 Low Traffic Areas Supply breaks of up to 60 seconds can be tolerated but should normally be less than 10 seconds and occur less than once per month. N+1 redundancy is required for all DC supplies other than track circuits. Choose approved power supplies with an MTBF of greater than 100. No redundancy is required for DC supplies.3.

The non-preferred connection to an adjacent Microlok interlocking is via vital serial links from Slave Microloks at adjacent locations.4. however would be permitted where such failures can be shown to be of an impact that fails not more than 2 signals on each track. Direct drive to LED signal lights is not normally permitted as this can cause the failure of the interlocking equipment due to failures of the LED module. Inputs from external equipment are commoned and wired to both Interlockings and OR’d together in the interlocking data. Individual interlockings may be split vertically if required due to processing constraints. and the lower will process the outputs and comparisons for synchronisation. 2.4.4.4 Connection to Adjacent Interlockings The preferred connection to an adjacent Microlok interlocking is via vital serial links. Interlocking equipment used to interface to track-side equipment does not need to be duplicated.3 Low Traffic Areas The interlocking equipment does not require redundancy for availability. un-regulated DC power supplies may be used for external inputs provided that Elsafe immunisation modules (216643) are fitted at the Microlok II inputs. Disconnection facilities must be provided for testing of new works and alterations without any impact on the operation of the railway. © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 10 of 79 Version 2. The interface between a Microlok II interlocking and another type of interlocking is via relay style interface circuits. 2. The upper Microlok will process the inputs and interlocking controls to the system. 2. stop “back feeds” ).1 High Traffic Areas Fully redundant interlocking equipment with non–duplicated external circuits in a hot standby configuration is required. The interlocking design must provide a method to permit disconnection as per the Microlok Computer Based Interlocking Signalling Maintenance Procedure CRN SP 037. However existing unfiltered.1 . Outputs are OR’d together via facilities to prevent the failure of one system affecting the loads (i. and the lower will process the outputs and comparisons for synchronisation. Direct drive of LED signal lights is permitted. Individual interlockings may be split vertically if required due to processing constraints.Signalling Design of Microlok II Interlockings CRN SC 023 DC power supplies are to be filtered and regulated. The upper Microlok will process the inputs and interlocking controls to the system. The Microlok II 12V supply is to be battery backed up as per the Microlok II manuals.2 General Traffic Areas Main interlocking equipment is duplicated in a hot standby configuration. making a slave Microlok II location as a slave of both interlocking masters. 2.e.4.4 Interlocking Equipment Configuration 2.CRN Engineering Procedure . Direct drive to LED signal lights is currently not permitted as this has the potential to cause the common mode failure of the interlocking equipment.

The communications equipment must use a secure power supply.5. Opto-isolators. 8 data bit. If the secondary link is not normally in use then it must be brought into operation automatically. with a point to point link back to the Control System. The secondary link must automatically re-establish if it fails whilst in service. a primary and a secondary. no parity. The secondary link does not need to be in constant use. 1 stop bit. 8 data bit.5.3 General Traffic Areas Two communication links are to be provided.5. 2. Only point-to-point 9600 or 19200 bps. with diverse paths are to be provided. The communications links must not be disrupted for more than 15 seconds due to power supply disruptions. no parity. Point to point 19200.5. Communications links must have galvanic isolation between the interlocking equipment and any external circuits. 9600 or 1200bps asynchronous.4 Low Traffic Areas A single communication link is required with an MTBF of greater than 2 years.1 . 1 start bit. 8 data bit. The secondary link must be mostly via diverse path to the primary link. full duplex links are preferred but Multi-drop 9600bps or 1200bps links may be used when point-to-point links are impractical.2 High Traffic Areas Two fully redundant communication links in constant use. Point to point 9600 or 19200 bps asynchronous.6. full duplex links should be used for main interlockings. Some communications equipment provides galvanic isolation.6 Safety System Communication Link Configuration 2. 2.CRN Engineering Procedure . Non-continuous secondary links must automatically disconnect after more than 90 seconds of correct operation of the primary link. 1 stop bit.5 Control System Communication Link Configuration 2.1 General Safety communication links must not have any buffering or “store and forward” provided in the communications equipment between the Microlok II equipment as per the requirements set out in the Microlok II Platform Safety Application Guidelines. asynchronous. 1 stop bit. Multi-drop arrangements using Fibre Optic Modems for in-section signalling locations are acceptable.1 General CRN SC 023 Received data may need to be conditioned by the link status as the bit states are maintained when the link fails. or transformers are normally used to provide galvanic isolation. The operation of the secondary link does not need to be automated. no parity. The communications links must not be disrupted for more than 30 seconds due to power supply disruptions. 2. © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 11 of 79 Version 2. full duplex links are preferred but Multi-drop 9600bps links may be used when point-to-point links are impractical. with less than a 90 second disruption to operations. 2. The communications links must not be disrupted for more than 60 seconds due to power supply disruptions. A secondary link is desirable. The communications equipment must use a secure no-break power supply.Signalling Design of Microlok II Interlockings 2. 1 start bit. 1 start bit. The communications equipment should use a secure power supply.

No more than 10 slave addresses are to be used on one link. Opto-isolators or transformers are normally used to provide galvanic isolation.6. Particular configuration details are set out in the section on Serial links.1 . Some communications equipment provides galvanic isolation. Multi-drop links for slaves in more than 5 separate locations must have a loop arrangement with a redundant link.4 Low Traffic Areas No redundancy for availability is required. or cable failure shall cause an operational impact on the railway.3 General Traffic Areas Single equipment or cable failure can cause an operational impact on the railway. otherwise Fibre Optic Modem (FOMs) units would be used. or analogue modems are provided as part of the signalling installation. The poll cycle time must be less than 2 seconds. This results in a poll cycle time of about 1080mS for the link at about 90ms per slave at 19200bps using Fibre Optic Modems. Multi-drop links for slaves in more than 9 separate locations must have a loop arrangement with a redundant link. otherwise Fibre Optic Modem (FOMs) units would be used. Facilities must be provided so that the Signalling maintenance personnel can correct the failure without other assistance. Fibre Optic communications links must be used. No more than 12 slave addresses are to be used on one link. Fibre Optic communications links should be used for complete new installations. 2. Single equipment or cable failure may cause an operational impact on the railway. 2.6. Communications links must have galvanic isolation between the interlocking equipment and any external circuits.1 General Equipment housings and cable routes must comply with specification alterations identified in the Proposal for Standard Specification alterations to address issues with 415V signalling power © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 12 of 79 Version 2. 2.2 High Traffic Areas No single equipment. Duplicated point to point links do not require a diverse link but they must have some physical diversity in the links.CRN Engineering Procedure . This results in a poll cycle time of about 900mS for the link at about 90ms per slave at 19200bps using Fibre Optic Modems. Typically Diversity Link Controllers (DLCs) would be used in this case.6.Signalling Design of Microlok II Interlockings CRN SC 023 Typically “dark fibre” or a copper pair is provided and the approved Fibre Optic Modem arrangements.7 Equipment Housing And Cable Route Configuration 2. Duplicated point to point links do not require a diverse link but they must have some physical diversity in the links. Typically Diversity Link Controllers (DLCs) would be used in this case. Fibre Optic communications links must be used. 2.7. Modem links using copper cables are acceptable when new cable routes are not being provided.

2 High Traffic Areas A well as complying with the CRN Signalling Engineering standards requirements for protecting against fire damage and stopping the spread of fire.1 . and the Ancillary Equipment Temperature rating Installation guideline.8 Microlok Specific Configuration Issues 2.Protection of the location from damage. Duplicate cables or diverse cables must be physically separated or have appropriate physical protection so that it is improbable that both cables are damaged in the one incident.Layout of equipment for temperature effects.7. Sighting of any location must consider: .Layout of equipment and wiring for minimise coupling of electrical noise onto sensitive circuits. .Segregation for wiring and equipment for surge protection. the limiting of fire damage should be considered in the design. Location layout must provide: .7. Passive fire protection should be provided so that cable routes can withstand an external fire without irreparable damage as per the Environmental Conditions CRN SE 002. 2. . using a method of shade structures or “double skinning” and adequate ventilation. .Damage due to High voltage power faults.Surge damage risk. 2.CRN Engineering Procedure . 2.7.1 General Microlok application data must not use Look-up tables without a specific design guideline being approved for the particular use.4 Low Traffic Areas There are no additional requirements for Low traffic areas.3 General Traffic Areas Passive fire protection should be provided so that cable routes can withstand an external fire without irreparable damage as per the Environmental Conditions CRN SE 002. . A re-enterable cable route is required.Fire risk. Surge protection installation guideline.Signalling Design of Microlok II Interlockings CRN SC 023 distribution. . . . © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 13 of 79 Version 2. Cables that can introduce significant surges must not be placed in close proximity to other cables prior to having passed through some surge protection.Layout of equipment for ease of maintenance. Routing of cable routes is to consider surge protection issues and proximity to High Voltage Earths for Earth Potential Rise (EPR) issues.1 in 100 year flooding.8. 2. Passive temperature control is required on all locations.

The DELAY_RESET default setting is 100mS. It is not necessary to fail a coded track circuit on loss of the CPS. Timers less than 24 seconds can be delayed by more than 10% of their value. It should not normally be changed.STATUS to become false. Vital serial links are to be disabled by the loss of the CPS.ERROR bit. All direct vital output circuits must be powered via a contact of the VCOR or a repeat of the VCOR. This shall include the CONFIGURE. This may cause problems with timers used for speed control. It may be set at any value in the provided range to address a particular problem.RESET system bits are not to be set by the application logic. The SELECTIVE. It may be set to no more than 4 seconds to address the problem.SHUTDOWN bits for the boards are not to be set by the application logic. Consideration must be given to the impact of delays when using timers of less than 24 seconds. QUICK. The LOGIC_TIMEOUT default setting of 2 seconds must be used unless there is a specific problem. The KILL system bit should be used instead. If this is not satisfactory then other solutions must be found.CRN Engineering Procedure .STATUS system bit. The RESET. External signalling circuits driven by Microlok Outputs must not have “stick” paths without a design review to confirm that short duration “false” outputs do not cause a hazard. Safety critical faults detected by the application logic must set the KILL system bit.1 . however action is to be taken to ensure that track codes are not able to allow a potential safety hazard due to the event that caused the CPS. © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 14 of 79 Version 2.Signalling Design of Microlok II Interlockings CRN SC 023 Microlok application data must not use Numeric blocks for purposes other than for configuration control without a specific design guideline being approved for the particular use.STATUS system bit.

1 .2 CRN SC 023 Approved Microlok II Modules Part No.CRN Engineering Procedure .8. Description Permitted for High Traffic use Permitted for General Traffic use Permitted for Low Traffic use Notes N17061301 Central Processing Unit    1 & 11 N800101-001 Microlok II Executive Software Version 8. 8 Vital Input (12)   Permitted but not preferred N17062701 Non Vital Isolated Output Card    N17063701 Non Vital Isolated Input Card    N4519100701 MicroTrax Coded Track Circuit PCBs    9 N17001102 Output Isolation Module (50V)    10 J7031050107 4MB FLASH Card    11 N322500-701 VCOR relay    © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 15 of 79 Version 2.50    2 N800102-001 MicroLok II Development System Version 8.Signalling Design of Microlok II Interlockings 2.50    3 N16661203 Power Supply    4 N4519107501 CPS    N17060101 Vital Lamp Driver Card N17060501 Standard Vital Output (12V) N17066801 Second Generation Standard Vital Output (12V) N17061001  Limited Usage  5    6 & 15    15 Vital Input (12V)  Limited Usage  7 N17061003 Vital Input (50V)    7 N17061501 Non Vital Non Isolated Input and Output Card Limited usage Limited usage  8 N17061601 Standard 8 Vital Output.

2.50. Where future stages will require additional outputs. launched by Ansaldo STS as a direct replacement for the old N16660301. Spare inputs may be wired to interface terminals if required for future stages. This may eliminate the need for external power supplies in some projects.1 .01. spare outputs may be wired to interface terminals. one spare serial port on masters is to be wired out to interface terminals or a suitable connector. Version 8. Includes the Compiler. Previously approved Executive Versions 3. 4. Where available. © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 16 of 79 Version 2. 3. This is the Enhanced Power Supply card. 7. Spare outputs shall preferably be left unwired. The Enhanced card has higher current capacities compared to the old card: 5VDC @ 5A (up from 3A).2. 3. removable diode plugs are acceptable disconnection points. 5. and such outputs must be terminated with 220R 1W resistors. 6. Reverse Compiler and Comparison Tool as well as Microlok II Development System.4. 4. When using the Power Calculation tool in the Microlok Tools software. Spare outputs may be wired to interface terminals.1 are approved for minor alterations at existing locations but are not to be used on new installations. Major alterations should upgrade to V8.Signalling Design of Microlok II Interlockings CRN SC 023 PN150B (6FBSTD) 400 ohm N322505-701 VCOR relay PN150HD (4FBHD/2FBSTD) 400 ohm    12 N4513760302 Plug-in base for PN150B & PN-150HD relays    13 N16902101 General purpose card file    14 N16905301 Dual card file    14 & 16 N18003901 Half box card file    14 N4518502902 1-wide blank front panel    N4518592901 2-wide blank front panel    Notes 1.CRN Engineering Procedure . -12VDC @ 2A (up from 1A).1 (and earlier) calculators do not allow for the higher capacity of the Enhanced Power Supply. If the usage is limited then use of the card is permitted based on failure impact meeting the design goals. All lamps outputs are to meet the requirements for disconnection as per the Microlok Computer Based Interlocking Signalling Maintenance Procedure.5 Tools show current loads for both versions of the Power Supply card. +12VDC @ 1A (unchanged). For locations with duplicated outputs. and 5. All outputs that are wired are to be wired via a disconnect terminal (between the Microlok and the relay or other output load) to permit disconnection as per the “Disconnection of Signalling Apparatus” Signalling Maintenance Procedure. designers should note that version 5.

The output circuits should use A17. Chapter 2 of SM-6800G covers wiring issues for vital output cards. which are addressed in the typical circuits section of this CRN document.4 Misc.2.9 Microlok Platform Safety Application Guidelines Personnel working with Microlok II should be familiar with the document Microlok II Application Guidelines (Ansaldo STS SM-6800G). To do so would reduce the benefit of duplication – a fault on the backplane of one side requires that both sides be shut down to replace the card file. Care is required in allocating the N12 connections. A29 as the N12 connections. When using the Power Calculation tool. 12. 2. 10. note that the second generation OUT16 card draws approximately twice the current of the original OUT16 card. 2. A25. 15. C3.6 Microlok Interlocking Simulator Systems (MISS) Testing of the interlocking shall be performed on a Microlok Interlocking Simulation system. 16. 14. communications links. 2. The second generation standard output is preferred for new designs.5 Timers in Low Traffic Areas Based on the lower expected rail traffic conditions Timers set for less than 6 seconds must be reviewed to determine that they will not cause an operational impact or safety hazard if they are delayed by more than 10%. Use the M451142-2702 contact springs associated with this relay base.2.8. Top PCMCIA Programming Voltage on JMP28 set to program and the Flash Programming Voltage on JMP30 . C13.4 Timers in General Traffic Areas Based on the lower expected rail traffic conditions Timers set for less than 12 seconds must be reviewed to determine that they will not cause an operational impact or safety hazard if they are delayed by more than 10%. A21. 13. which is to be configured in accordance with TMGG 1232 Microlok Interlocking simulation System (MISS) Design Guidelines. The isolation module should be provided with 15V power to ensure the output voltage is adequate. 11. This module is for use in permitted non-electrified areas only.3 Timers in High Traffic Areas Timers set for less than 24 seconds must be reviewed to determine that they will not cause an operational impact or safety hazard if they are delayed by more than 10%.set to 5 volts. The application data is to contain 75% of the actual track length or a value set by the Engineer certifying the track as the default. The input circuits should use A13. This is to ensure that MISS files are suitably controlled and that the trackside screens and control screen may be directly used for the replay and local control.1 .Signalling Design of Microlok II Interlockings CRN SC 023 8. Used in conjunction with Vital Lamp Driver Card. This includes items detailed in Ansaldo STS document SM-6800B Section 4. 2. 9. All OUT16 modules at a location are to be the same type. The Dual Card File (also referred to as Split Card File) is not to be used to house both 'sides' of a duplicated installation. Reply and Emergency Control software.3 PCB Interface Cable Assembly Components and Tools as well as Sections 4. Cardfile Installation Parts as limited by this specification.8. C12 as the N12 connections. if required. © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 17 of 79 Version 2.CRN Engineering Procedure . 2. Microlok data.8.8. and MISS facilities and files shall be in accordance with QSDP 71 Application of MISS.

1 . highlight behavioural aspects of the Microlok hardware and software systems which may affect safety of the interlocking. The issues identified in the Microlok II Platform Safety Application issues have been considered and addressed as follows: © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 18 of 79 Version 2.CRN Engineering Procedure .Signalling Design of Microlok II Interlockings CRN SC 023 Chapter 3 of SM-6800G. and its predecessor Microlok II Programmable Controller Platform Safety Application Issues (ML2-RS-007).

33. 49. and Verification on each design. Review. 42 CRN Signalling Engineering Standards. 7.CRN Engineering Procedure . and Verification on each design. 29. 25 Addressed by this document. and Verification on each design. and Verification on each design.1 . 37. 32. © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 19 of 79 Version 2. 14 Addressed by this document.27 to verify the application image 3 Addressed by Microlok Computer Based Interlocking Signalling Maintenance Procedure CRN SP 037 4. Review. 27 Design. 11 CRN Signalling Engineering Standards. 17 Addressed by Microlok Computer Based Interlocking Signalling Maintenance Procedure CRN SP 037. Review. 16 Addressed by this document. 18 Signal Design Quality Procedure CRN SQ 001 . 10 Addressed by this document. 38. 26 Signalling Maintenance Procedure for MircoTrax. 23 Addressed by this document. 31. 13. 44. 51 Addressed by this document. 45 Addressed by this document. 47 CRN Signalling Engineering Standards. and advice from US&S that the Microlok Executive software checks the Boolean logic trigger list as part of the start-up safety checks. 48. and Verification on each design. Review. 5 Addressed by this document. 46 Addressed by Microlok Computer Based Interlocking Signalling Maintenance Procedure CRN SP 037 . 36 Addressed by this document. Review. 20. and Verification on each design. 22. 34. 39 CRN Signalling Engineering Standards. 28. and CRN SQ 001 . 50. 24 Design. 15 Design.Signalling Design of Microlok II Interlockings CRN SC 023 Issue Treatment 1. 43. 30.29 19 Design. 21. 2 Signal Design Quality Procedure CRN SQ 001 .14. 9 CRN Signalling Engineering Standards. 12 Design. 6 Design. 35. Review. 40 Addressed by Microlok Computer Based Interlocking Signalling Maintenance Procedure CRN SP 037 41. 8 CRN Signalling Engineering Standards.

Up to 110m cable distance using 1.5mm 2 of twisted pair cable using regulated 16. and Verification on each design.2V lamp supply. 68. DC signal light requires a 10R.Up to 110m cable distance using 1. . . The Mark 2 Outdoor 127mm. 61 CRN Signalling Engineering Standards. Review. 56 Design. DC signal light requires a 15R.Up to 340m cable distance using 4mm 2 of twisted pair cable using regulated 16. . . 25W WH25 series resistor fitted in the signal head when operated using a regulated 16.27 to verify the application image 63. 65. 67. DC signal light requires a 12R. The Mark 2 Outdoor 212mm.Up to 20m cable distance using 1. 54.14. and CRN SQ 001 . 58.6V battery supply as the lamp voltage. 25W WH25 series resistor fitted in the signal head when operated using an un-regulated 13.1 Signals 2. 59 Addressed by this document.2V lamp voltage.10.2V lamp supply.2V lamp voltage.10 Track Side Equipment Configuration 2.5mm2 of twisted pair cable using 13.CRN Engineering Procedure .6V battery supply as the lamp voltage.Up to 340m cable distance using 4mm2 of twisted pair cable using regulated 16.Signalling Design of Microlok II Interlockings CRN SC 023 Issue Treatment 52.10.1 . Review.2V lamp voltage. 2. 57. and Verification on each design. 69 Design. 53.1 Direct Control by Microlok II Aldridge Not currently approved for direct drive by Microlok II Vital Lamp Driver card.6V battery supply. The Mark 2 Outdoor 127mm.6V battery supply. DC signal light requires a 24R. United The Mark 2 Outdoor 212mm. . 60. 64.5mm2 of twisted pair cable using 13. 25W WH25 series resistor fitted in the signal head when operated using a regulated 16. 25W WH25 series resistor fitted in the signal head when operated using an un-regulated 13. .Up to 60m cable distance using 4mm 2 of twisted pair cable using 13.2V lamp voltage. 70 Addressed by this document.Up to 40m cable distance using 1.6V battery supply as the lamp voltage.1. 55. 66.5mm 2 of twisted pair cable using regulated 16. © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 20 of 79 Version 2. 62 Signal Design Quality Procedure CRN SQ 001 . .

© JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 21 of 79 Version 2. .5mm 2 of twisted pair cable using regulated 16. CRN SC 023 of twisted pair cable using 13. 212mm signal light requires a 15R.5mm2 of twisted pair cable using 13. 2. .Up to 160m cable distance using 1.2V lamp voltage.Up to 110m cable distance using 4mm 2 supply as the lamp voltage. 2.Up to 55m cable distance using 1.1 .6V battery supply as the lamp voltage.Up to 160m cable distance using 1. . or 150m of 4mm 2 twisted pair cable unless a technical review is performed which determines an acceptable feed length for the particular Coded track circuit.Up to 340m cable distance using 4mm 2 of twisted pair cable using regulated 16. 25W WH25 series resistor fitted in the signal head. .5mm 2 twisted pair cable. 25W WH25 series resistor fitted in the signal head. . . of twisted pair cable using 13.6V battery supply as the lamp voltage. .2V lamp voltage. 2.6V battery supply as the lamp voltage.Up to 110m cable distance using 1.10. .2V lamp voltage.Up to 450m cable distance using 4mm 2 of twisted pair cable using regulated 16.6V battery The TR3 501 series tunnel or outdoor 127mm signal light requires a 10R. .6V battery The DC LED stencil indicator requires a 10R.Up to 20m cable distance using 1.6V battery Relay Control Relay control of LED signals must be as per the LED signals controlled by relay circuits Design Guideline.CRN Engineering Procedure .Up to 450m cable distance using 4mm 2 of twisted pair cable using regulated 16.2V lamp voltage.10. Westinghouse The RM4 series outdoor. .Up to 40m cable distance using 1. .2 of twisted pair cable using 13.Up to 160m cable distance using 4mm 2 supply as the lamp voltage.Up to 60m cable distance using 4mm 2 of twisted pair cable using 13.10.Signalling Design of Microlok II Interlockings . .5mm 2 of twisted pair cable using regulated 16. 50W WH50 series resistor fitted in the signal head.5mm 2 of twisted pair cable using 13.2V lamp voltage.Up to 110m cable distance using 4mm 2 supply as the lamp voltage.5mm 2 of twisted pair cable using 13. track interface unit must be less than 50m of 1.3 Microtrax Coded Track Circuits The cable from the location to the Microtrax Coded track.2 Track Circuits Track circuit limits are as per the CRN Signalling Engineering Standards.5mm 2 of twisted pair cable using regulated 16.6V battery supply as the lamp voltage.1.2V lamp voltage.

This method is suitable for 12VDC. 50VDC relays. 2. 24VDC. They may be used for 120VAC relays but this will operate the RC snubber at close to its 0. The surge protection arrangement must consider 50Hz Earth Potential Rise (EPR) faults if both ends of the circuit are not at the same location. The recommendation in Microlok II manual SM-6400B to use Transorbs is not preferred. The track interface panel must have RSA disconnect links on the connections to the rails to allow for disconnection as per Microlok Computer Based Interlocking Signalling Maintenance Procedure CRN SP 037 and Microtrax Signalling Maintenance Procedure CRN SP 036. AC Immunising modules on the inputs. and 210-370 with a fixing tab that can be secured under the bottom screw of a Q relay base. They are available from RS Components as stock number 210-364 for free wiring.4 Relay Noise Suppression Relays generate electrical noise when they are de-energised. this will normally be for an AC circuit. All relays at a location with Microlok II are to be snubbed or the Microlok II segregated from the source of the electrical noise.5 Microlok II Input Circuits External to the Location Microlok II inputs that are wired external to the equipment location require immunity from sources of 50Hz AC.10. and Microlok II Isolation modules or relays on the outputs and physical separation.25 ohm test shunt is used in certifying the Microtrax Coded Tracks. and 50VDC relays only and it may not be suitable for polarised circuits. as these units have been found to be un-reliable.1uF plus 100R) fitted across the coil. Relays that are controlled by a circuit that is not exclusively within the location housing the relay are snubbed with a Contact suppressor (RC snubber 0. A 0. The importance of the loop resistance increases as the length of the track increases. 24VDC. © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 22 of 79 Version 2. and general electrical noise as well as surges due to lightning. A 0R22 resistor in the track interface unit is typically fitted in the trackside of the Track Interface unit to decrease the shunting sensitivity to at least 0.CRN Engineering Procedure . This electrical noise can interfere with electronic or computerised equipment like the Microlok II. These units are suitable for 12VDC. The preferred method of segregation is by the use of twisted pair wiring.10. Fitting the diode across the relay coil means that the relay cannot be AC immune. Circuits that are wholly within a tunnel and do not travel within 100m of the tunnel portal do not require the surge protection. Two methods are currently accepted for provision of immunity from any source of interference for circuits external to the location. Relays that are controlled by a circuit that is exclusively within the location housing the relay are snubbed with a 1N4007 diode fitted in the reverse direction across the coil. In some cases a resistor can also be used for snubbing purposes.25 ohms.Signalling Design of Microlok II Interlockings CRN SC 023 Microtrax Coded track circuits shunting sensitivity is affected by the loop resistance of the cable from the location to the trackside interface unit. Relays directly driven by Microlok II must be snubbed.1 . Traction currents.5W power rating. 2.

That the cumulative length of cable route that is within 3m of traction return rails or traction supply wire is less than 100m. Acceptable external circuit lengths for the 50V input card is 3.Power cables that provide power to a load that is more than 10KVA and run parallel to the cable for more than 100m are separated by at least 300mm from the cable. . and black as the Positive or Active side of the circuit. The Power supply wiring colour code is red for positive DC.CRN Engineering Procedure .Signalling Design of Microlok II Interlockings CRN SC 023 Method 1 Use Dekoron twisted pair cable and twisted pair wiring with double cut circuits.000m of wire length. and line to earth) at any external entry or exit to the equipment location. Paired cables or wires for control wirings will normally have black and white as a pair.000m double cut Method 1 circuit length or 8. 2.1 Colour Coding Generally black wire is used for permanent control wiring. and Blue for un-earthed AC. The Elsafe immunisation module (216643) provides about 25dB attenuation at 50Hz.11 Cables and Wiring 2. Note that there cannot be two Elsafe immunisation modules (216643) in series in a circuit for dual Microlok II inputs as there would be a series voltage drop of about 30V across the Elsafe immunisation modules. Twisted pair wiring using the Dekoron cable as per Method 1 may be used. ensuring that the twisted pair is maintained throughout the whole circuit. The holdover voltage for the arrestor must be greater than 75 volts. Black for Negative DC. Some paired cables or wires for control wirings have red and black pairs. and provide a 3 mode surge arrestor (line to line. If the given conditions are not met then the circuit must be treated as per Method 2. The white is to be used for the negative or neutral side of the circuit. © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 23 of 79 Version 2. Method 2 (Only permitted for 50V circuits) Use traditional signalling cable or wire and Elsafe Immunisation module (216643) near to the Microlok II input. .Non-twisted cable and wiring does not exceed 3m circuit length.000m double cut Method 2 circuit length or 6. and the red as the positive or active side of the circuit. In this case an Elsafe Gas arrestor (290V) module (216680) is provided at the feed point of the circuit. The black is used for the negative or neutral side of the circuit.11. A surge arrestor based on a 290V three terminal ceramic arrestor is considered suitable. Acceptable external circuit lengths for the 50V input card is 4. Given: .000m of wire length.1 . Acceptable external circuit lengths for the 12V input card is 400m double cut Method 1 circuit length or 800m of wire length.

and Q relay crimps.11. use black 19/34 AWG. The wire is 19/29 AWG.CRN Engineering Procedure .11.3 Internal Wire Safety critical wiring in Location cases and Relay Rooms where a Computer Based Interlocking system is being used must use Mil-W-22759-16-16 wire due to problems with the thickness of insulation and the possibility of leaking plasticiser from the standard internal wire as specified in CRN Engineering Standard CRN SE 035 Cables for Railway Signalling Applications. It is suitable for terminations in general terminals. For 48 way connectors. 09-06-000-8481 crimps for the 24 AWG Cat 5 cable. The Microlok II CPU 48 way connectors will need connections for serial links. The 96 way connector for the Microlok II non-vital card has insufficient space to use the 1. Circuit currents should not normally exceed 6 amps. 1. 0.11. Use Harting Part No. 09-06-0008484 crimps for the 0. 2. Use Harting Part No.4 Heavy Duty Cable © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 24 of 79 Version 2.8 ohms/km. Use Harting Part No.1 .2 CRN SC 023 General Multi-Core Cable CBI interface applications may use Olex Dekoron Instrumentation cable or a similarly specified cable with an overall screen for signalling inputs and outputs The standard cables are twisted pair cables and need to be used as pairs to provide immunity to electrical noise and interference. Other suppliers may be available. The wire is also available as black and white twisted pair. part number Mil-W-22759-16-22-000. Part Mil-W-22759-16-16-0+9 twisted at greater than 15 twists per metre. 2. This is based on the US Military Standard Mil-W-22759-16-16-000. which has good properties for physical abuse during installation. The wire is available from Cambridge Technologies as part number 16-ACFZ-1929.23mm2 wire so 19/34 AWG. This wire is insulated using extruded ETFE.4mm 2 wire. These cables are permitted for use at voltages up to 130VAC or 150VDC.4mm 2 wire is to be used for the 96 way connector output card. use twisted pair black & white cable 19/29 AWG. 09-06-000-8482 crimps for the 1.4 mm 2 wire. which is half the Manufacture’s rated current. and in service. 1. Refer to “CRN SE 035 – Cables for Railway Signalling Applications” for cable specifications.23mm 2 wire.23mm 2 at 15.23 mm 2 wires. Typically 24 AWG Cat 5 cable is used. the 48 way connectors for the Microlok II cardfile. It is rated for 600 volts and 150oC. For 96 way connectors.Signalling Design of Microlok II Interlockings 2. 0. This wire may be used for safety critical circuits up to and including 120VAC.

Normally ST or FC connectors are used. MOD). with a loss of less than 3.1 General Multi-mode fibre optic installations are preferred as they are more tolerant to poor environment conditions. 2. Single-mode fibre optic installations are to have a separate approval for each installation.5/125 micrometer.1 . suitable for a minimum of 16 fibres. and termite resistant. or ducts.5 Fibre Optics 2. Fibre Optic cable is to be outdoors type suitable for direct burial.11. 100% Insertion Loss (light source and power meter) testing of all terminated fibres must be performed in both directions at 850nm for multimode cables. The multi-mode optical fibre cables shall have a graded-index of 62.5.2 Cable Fibre Optic installation must be in accordance to AS/NZS-3080:2013 Information technology Generic cabling for customer premises (ISO/IEC 11801:2011.11. © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 25 of 79 Version 2.Signalling Design of Microlok II Interlockings CRN SC 023 Cable with larger conductors cable can be used for lamp drive circuits and coded track circuits.11.5. 2.5dB/Km at 850nm. 2. Refer to “CRN SE 035 – Cables for Railway Signalling Applications” for cable specifications.CRN Engineering Procedure .5. OTDR tests shall be performed at wavelength used by the Fibre Optic Modems.11.3 Fibre Management Enclosure Terminate Fibre Optic cables in rack mount termination enclosure with patch panel.

The application logic must check the additional address and not accept any data unless the address matches the normal address and the additional address.1 General All Microlok II vital serial links at each individual site.DELAY: STALE.1 Master Settings LINK: ADJUSTABLE ENABLE: PROTOCOL: FIXED PORT: ADJUSTABLE BAUD: ADJUSTABLE KEY. Fibre Optic modems in normal use have ST connectors. ST to ST.5. and port 4 having the lowest priority. Normally the priority of the serial ports will not impact on the design.5. and the CPU is expected to be heavily loaded.1 .DELAY: KEY.1 Vital Serial Links 3.DATA. however if all links are in use. and within each section of the cable route. 4:SEC. 3. Both single mode and multi-mode versions have been approved.5.11. It is current practice to power the OSD136 from 5VDC via the DB25 connector where practical to reduce the operating temperature of the Fibre Optic Modem. 2. 19200.ON.CRN Engineering Procedure .6 Distance for Multimode Fibre Designs should limit the segments between OSD136 Multimode modems to a maximum of 5 Km of fibre optic cable after allowing for losses in connectors etc.POINT: © JHR Issued March 2015 COMMx 1 MICROLOK.11.7 Distance for Single Mode Fibre Designs should limit the segments between OSD136 single modems to a maximum of 40 Km of fibre optic cable after allowing for losses in connectors etc.2 Fibre Optic Links These settings are for configurations using Fibre Optic Modems.Signalling Design of Microlok II Interlockings 2. 1.4 CRN SC 023 Patch Leads Patch leads are normally Multimode. it is preferred to allocate the vital links as the lower port numbers.11. must have a unique serial link address unless they must have identical data because they are individual links of a duplicated link arrangement.1.OFF.11. Duplex.5 Fibre Optic Modems Currently the only approved Fibre Optic Modem is the OSD136 from Optical Systems Design. 3 Serial Link Communications 3.1. 2. 12.1. UNCONTROLLED WHEN PRINTED Page 26 of 79 Version 2. The Microlok II serial ports have different priorities. 30. 2.TIMEOUT: POINT. or FC to ST for connection to Fibre Optic modems. port 1 having the highest priority.5.MASTER x. If a Microlok II vital serial link is to operate over cabling or communications multiplexing equipment that extends beyond the trackside signalling cables then an additional 8 bit address must be embedded into the vital serial link data.2. 3.

DATA.INTERVAL is normally left at the default and should only be adjusted in response to a particular problem. The Exicom 396 modem is approved for Microlok 2 vital serial links.3. STALE. ADJUSTABLE KEY. POLLING. 19200. 0:MSEC.DATA.DATA.TIMEOUT: ADDRESS: ADJUSTABLE ENABLE: COMMx 1 MICROLOK.DELAY: 280.DATA. © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 27 of 79 Version 2.OFF.1. 3.1 .DELAY: KEY. It may be decreased or increased to a maximum of 6 seconds to address particular application issues.ON.POINT: 1.1.TIMEOUT should not be changed from the default of 4 seconds. Most modems are not suitable. It should not be set above 200mS. It may be increased to a maximum of 6 seconds to address particular problems.ON.Signalling Design of Microlok II Interlockings CRN SC 023 ADJUSTABLE MASTER. It may be increased to a maximum of 6 seconds to address particular problems.2. 1. 3. ADJUSTABLE BAUD: 9600.TIMEOUT should not be changed from the default of 4 seconds.DELAY: STALE. 4:SEC. Typically at 9600 bps the carrier startup time is less than 30mS.3 Analogue Modems Modems must have controlled carrier with a carrier startup time of less than 280 bit times.TIMEOUT: 250:MSEC.TIMEOUT: POINT. xx 1 STALE.DATA. The Dataplex 210 short haul modem specifications are suitable.CRN Engineering Procedure .OFF.POINT: INTERBYTE. POINT. 3. 30.TIMEOUT should be set at 250mS and may be increased to 500mS to address particular problems.1 Master settings LINK: COMMx ADJUSTABLE ENABLE: 1 PROTOCOL: MICROLOK. ADDRESS: ADJUSTABLE ENABLE: xx 1 STALE. STALE.INTERVAL is normally left at the default and should only be adjusted in response to a particular problem.1.SLAVE x.TIMEOUT default is 4 seconds. POLLING.2 Slave Settings LINK: ADJUSTABLE ENABLE: PROTOCOL: FIXED PORT: ADJUSTABLE BAUD: ADJUSTABLE KEY. ADJUSTABLE MASTER. ADDRESS: ADJUSTABLE ENABLE: xx 1 MASTER. It should not be set above 200mS.TIMEOUT: 4:SEC. ADJUSTABLE KEY. 12.TIMEOUT: 100:MSEC. however the modem has not been tested at the time of writing.DELAY: 20.MASTER FIXED PORT: 4.

DATA.Switch 3/2 OFF Don't care .Switch 2/5 OFF No retrain . . .Switch 2/6 OFF not used for this mode.Switch 3/3 OFF No link amplitude equalizer. B removed. 3. 10 bits/Character.Switch 2/2 OFF Point to Point.Switch 3/1 OFF Don't Care .Switch 1/2 ON Don't Care Primary rate.2 CRN SC 023 Slave Settings LINK: ADJUSTABLE ENABLE: PROTOCOL: FIXED PORT: ADJUSTABLE BAUD: ADJUSTABLE KEY.Switch 3/5 OFF No cable equalizer. D Removed for 4 Wire .1. . Link K out.Switch 1/8 OFF Link L installed.29 Fast Train Don't Care .Switch 1/7 OFF -26dbm receive .3.OFF. . Internal clock . . © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 28 of 79 Version 2.ON.Switch 2/1 ON Link D installed. 9600.Switch 2/4 OFF No RTS delay . .POINT is set to 1 unless multi-drop analogue modems are used. 9600bps.29 fast train. 280. Link C out for 2 wire or Half duplex.Links N installed. ADDRESS: ADJUSTABLE ENABLE: xx 1 POINT. M removed Pin 9 isolated .Switch 1/4 ON . 1. Asynchronous. 4:SEC. Baud is set to 9600 unless a particular modem’s limitations require a lower speed.DELAY: ADJUSTABLE KEY.Switch 2/7 OFF not used for this mode.Switch 1/6 OFF -10dbm .1.3 Exicom 396 Modem Settings The modem needs to be configured for V.Links R installed. Link C Installed.Switch 2/3 OFF No squelch .TIMEOUT: ADJUSTABLE POINT. P removed Pin 10 isolated . 600 ohm receiver. . 4 wire communication links are preferred.Switch 2/8 OFF not used for this mode.1 .CRN Engineering Procedure .3. . and T Don't Care . The modem can use 4 wire or 2 wire communication links. Half Duplex.Switch 1/5 OFF V.Signalling Design of Microlok II Interlockings 3.POINT: COMMx 1 MICROLOK.Switch 1/1 ON Links S.Links A installed.Switch 1/3 ON . 20. .DELAY: ADJUSTABLE STALE.Switches 3/4 OFF No receive delay equalizer.SLAVE x.

Configuration Design to provide a received signal levels to modems of at least 10dB above the minimum modems receive level. .6 Wiring Category 5 (CAT5) telecommunications cable using 24 AWG wire may be used for RS485 wiring within the location or building.Switch 3/7 OFF No digital delay equalizer.1.Switch 3/8 ON Ccts 140. 3.1 .4 Circuits . .1.Switch 4/2 FF .Modem DTR: Line should be held in the ON state for analogue modems. . The Alfatron A440 is used because it provides the RTS. The twisted pair ETFE Teflon internal wire may be used for RS485 wiring for distances up to 5 metres.RX: Wire to Communications device or other Microlok port TX of the Microlok port. and DCD control links as well as the TXD. © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 29 of 79 Version 2.Switch 4/3 OFF Async timing at Basic tolerance. . but may be left unused for Fibre Optic Modem. 3. 6 although document implies 2/3 is expected. Careful consideration is required in the choice of power arrangements for the Alfatron A440 and other serial communications equipment to ensure the installation is not exposed to surges via the serial communications link.DCD: Wire to Communications device or other Microlok port RTS of the Microlok port. 3. . .605 Plug terminals 4W TX 2.TX: Wire to Communications device or other Microlok port RX of the Microlok port. Links E installed.Signalling Design of Microlok II Interlockings CRN SC 023 . .CRN Engineering Procedure . F removed. . and RXD.Switch 3/6 OFF No cable equalizer.Switch 4/4 ON Asynchronous . Typically 5 km between modems is easily achieved.CTS: Hold in the OFF state. . H removed. 3. CAT5 telecommunications cable using 24 AWG wire may be used for RS232 wiring within the location or building to a maximum length of 5 metres. and RX 4. 6. RS232 wiring up to 15 metres is permitted using shielded cable designed for RS232 applications. & 141 disabled.Switch 4/1 OFF 10 bits per character.1. E-link removed Signal ground isolated from protective ground. .RTS: Wire to Communications device or other Microlok port DCD of the Microlok port. The Alfatron A440 does not provide galvanic isolation. . Links G installed.5 Conversion Between RS485 and RS232 The Alfatron A440 RS232-RS422 converter is approved for use on Microlok Vital Serial Links.2W TX/RX 4.

or .MASTER x.CRN Engineering Procedure . ADDRESS: ADJUSTABLE ENABLE: xxx 1 Note: Where a dual hot standby interlocking is used.MODE: ADJUSTABLE MASTER.1 . 15:SEC.TIMEOUT must not be set to more than 2 seconds.TIMEOUT: ADJUSTABLE CARRIER. and 1 stop bit with speed (in order of preference) of 19200 or 9600 bps.19200. CONSTANT. or . LINK: ADJUSTABLE ENABLE: PROTOCOL: FIXED PORT: ADJUSTABLE BAUD: ADJUSTABLE STALE. External switching between primary and secondary links can be performed by Black box SW111AE RS232 Fallback switch.SLAVE x. The settings shown are for the panel interface communicating with a single-sided interlocking master.2.Full duplex leased line modems at 19200 or 9600 bps.POINT: COMMx 1 GENISYS.DATA.A full duplex Telstra DDS (Direct Data Service) operating at 19200 or 9600 bps.A full duplex.POINT: COMMx 1 GENISYS. CONSTANT. 9600 bps. 300:MSEC. STALE. ADDRESS: ADJUSTABLE ENABLE: xxx 1 Master The Master Genisys arrangement would only be used where a Microlok is acting as the control system. 1. And the secondary link is: . 19200.2 CRN SC 023 Genisys Links (Control System Link) Genisys requires an asynchronous communications link with 8 data bits.DATA. 15:SEC. 1.Signalling Design of Microlok II Interlockings 3. 1 start bit. © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 30 of 79 Version 2. 1200 bps may be used if a reliable connection cannot be established at 9600 bps. Depending on the configuration the primary link is: .2 LINK: ADJUSTABLE ENABLE: PROTOCOL: FIXED PORT: ADJUSTABLE BAUD: ADJUSTABLE STALE. 3.TIMEOUT: ADJUSTABLE POINT. 19200.Dial-up modems set for full duplex. no parity.DATA. a push-button panel with a Microlok providing the non-vital interface between the panel and the interlocking.2. Where the communications line quality is low. in order for the hot standby changeover to work. for example.TIMEOUT: ADJUSTABLE CARRIER.MODE: ADJUSTABLE POINT. 3. or 9600 bps leased line modems.1 Slave These settings are for Genisys slaves of either ATRICS or Phoenix Control System masters using point to point direct connections or Modems.

2.Signalling Design of Microlok II Interlockings 3. ensuring that the modem works even if the 120V supply is lost. RS232 wiring up to 15 metres is permitted using shielded cable designed for RS232 applications. . including: . The twisted pair ETFE Teflon internal wire may be used for RS485 wiring for distances up to 5 metres. including the power supply connection.4 Conversion Between RS232 and RS485 The Adam 4520 RS232-RS485 converter is approved for use in Genisys Serial Links. 3. 10 bit.3 CRN SC 023 Circuits .Modem DTR: Should normally be held ON. . The Adam 4520 is normally left in its default settings of 9600bps. . . the watchdog will reset the modem enabling communications to be restored automatically. 3.2.CRN Engineering Procedure .Modem RTS: Should normally be held ON. software.TX: Wire to Communications device or other Microlok port RX.2. CAT5 telecommunications cable using 24 AWG wire may be used for RS232 wiring within the location or building to a maximum length of 5 metres.Low supply voltage . In the event of internal fault. . The modem also provides DIP switches which can be used to set many of the operating parameters of the modem without requiring a computer to initialise the AT commands.CTS: Hold in the OFF state . 3.2.1 . The preferred use is for the Adam 4520 to be powered from the Microlok II B12/N12 supply. . and the RS485 side is connected to the Microlok II serial port. and no step-up transformer is required.RTS: Normally leave disconnected unless using Multi-drop communications or Halfduplex modems.Full galvanic isolation of all ports.6 Modem Configuration The modem currently preferred for the non-vital link is the Westermo TD-35LV. © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 31 of 79 Version 2.DCD: Wire to Communications device or hold in the ON state. and power supply. . The RTS line on the RS232 interface must be held ON.5 Wiring CAT5 telecommunications cable using 24 AWG wire may be used for RS485 wiring within the location or building. The Adam 4520 provides galvanic isolation on the serial link. The TD-35 is designed for industrial use and incorporates several features to facilitate reliable operation.can be powered directly from the battery-backed 12V Microlok supply.Watchdog function monitoring hardware. Refer to the TD-35 manual for the location of the switch groups in the modem.RX: Wire to Communications device or other Microlok port TX.

8 off SW2 1 . A computer must be used to configure the dialling settings for the modem using the command string AT&A1&B1&D3S0=0&Z0=n (where n is the phone number the modem is to dial). 3 ON. 1 . 4 off (19200 baud) OR 1 off.2. 7 ON (4-wire mode for leased line) 8 off. The modem at the control system end must be configured by computer with the command string AT&A1S0=2. 2-wire mode may be used by setting SW4-7 off.3 ON.4 ON (automatic line speed) 5 . 4 off (9600 baud) 5 . 4 . A fallback switch will detect failure of the primary link. all of the modem configuration can be achieved by use of the switches. 5 .6 ON.2 off (PSTN dial-up) 3 . and trigger the modem to dial by asserting the DTR line to the modem. The telecommunications service provider should be contacted to arrange to have the problems investigated and corrected. No parity) 8 off (1 Stop bit) 1 . No parity) 8 off (1 Stop bit). 4 off (9600 baud). 2 .6.8 off For dial-up operation. 2 ON (Leased line calling) 3 .CRN Engineering Procedure .4 ON (automatic line speed) 5 .6 off.2 off. and changing the telephone line connections appropriately.3 ON. the interlocking end will normally be the dialling modem. SW3 SW4 1 .8 off (sets commonly used AT parameters) 1 .6 ON. 3 ON. For leased line operation.2.1 CRN SC 023 Leased Line Settings Switch Group SW1 Genisys Master End Genisys Slave End 1 . When using the modems on a leased line.8 off 1 . 4-wire is preferred. the maintenance instruction must also include a warning to ensure the Microlok is disconnected from the modem before a computer is connected to the modem. Instructions should be provided in the circuit book and the maintenance instructions. 7 off (8 data bits. and generally only in lower-traffic areas where the disruption caused by the loss of interlocking control will be minimal. 4 . Because the TD-35 has two connection options for the RS-232 port. © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 32 of 79 Version 2.2 ON (Leased line answering) 1 off.3 ON. Where problems are experienced. 2 . 4 off (19200 baud) OR 1 off.1 . 7 off (8 data bits.6.8 off (sets commonly used AT parameters).Signalling Design of Microlok II Interlockings 3. 3.2 Dial-up Settings Normally a dial-up link will only be used as the secondary link. Switch Group SW1 SW2 SW3 SW4 Genisys Master End Genisys Slave End 1 .2 off.3 ON.

. 3.1 Introduction The Microlok II development system tools are to be used to develop and compile an application logic program. .3.1 RS232 Control Lines . SM-6800D manual. . +ve terminal to +5V. and upload the application program to the Microlok II central processing unit (CPU) card.29: Checking of Microlok Circuits and Data Designs.Signalling Design of Microlok II Interlockings CRN SC 023 Modem AT commands used: &A1 Ignore characters from the computer / Microlok during the call establishment phase.3. CRN SQ 001 .ON state for control lines is +6V. +ve terminal to 0V.CRN Engineering Procedure .OFF state for control lines is –12V. &Z0=n Store the phone number n in phone number memory 0 3. Note that the link setting for port 3 is normally set for RS232 so although port 3 is described as RS423 it is normally configured as a RS232 port. Typical examples of these are: © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 33 of 79 Version 2.OFF state for control lines are –ve terminal to 0V. reference should be made to the US&S Microlok II System Application Logic Programming Guide. 3. debug the program.14: Microlok File Control. and the features that are part of current relay design methods which are not essential or necessary for the satisfactory operation of computer based interlockings and non-vital equipment.3.1 . Microlok Data Design and Factory Acceptance Testing.ON state for control lines are –ve terminal to +5V. 4 Application Logic Design 4. &B1 Dial the stored number when DTR line rises. It is important to note all the features that can be programmed into the Microlok II system but are not or cannot be part of current relay design methodology. For the comprehensive procedures to create the complete Microlok II application program.27: Retesting of Microlok Data. &D3 Perform soft reset when DTR line falls.OFF state for control lines is –6V. S0=x Auto-answer after x rings (zero disables auto answer).3 RS423 Control .3 Control Line States 3.2 RS422/RS485 Control . The application logic is to be designed in accordance with the Signal Design Quality Procedures CRN SQ 001 . In general the application logic is based on or derived from the Signalling Circuit Design Standards.ON state for control lines is +12V. CRN SQ 001 . Design Engineers are to ensure the application logic is produced utilising the current approved Microlok II development tools and compilation software.

The application logic is created utilising a standard text editor to create the data file.The compiled application source file may be uploaded to the appropriate Microlok II cardfile installation utilising the Microlok II Maintenance Tools program. 4.ASSIGN statements and the timer bits. vital and non-vital I/O requirements. and all required interlocking logic.Signalling Design of Microlok II Interlockings CRN SC 023 .The Design Engineer identifies the system configuration requirements such as the Microlok II circuit boards to be used.ASSIGN statements.3 System Limitations . tables.4. per address may be defined for transmission over a non-vital serial link.A maximun of 512 data bit inputs and 512 data bit outputs. .A maximum of 499 statements can be awaiting execution at any time on each of the execution queues for ASSIGN and NV. . and alternative configurations may need to be considered.4 Standardisation of OCS Control of Interlockings 4. . (Genisys Protocol) 4. . or the number of defined bits exceeds 3500. .There is a combined limit on the number of timers. the sytem may become heavily loaded. © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 34 of 79 Version 2. . as well as any errors detected in the source file. Designers will need to pay particular attention during testing to ensure that the system will be stable. per address may be defined for transmission over a vital serial link.A single ASSIGN or NV.2 Design Process The following steps should be followed when producing Microlok II application designs. .Specific maintenance indications and diagnostics. .1 Background Entrance – exit style interlockings in NSW have developed over the years and have a number of features and constraints in the design.ASSIGN statement may assign to no more than 32 bits.A bit used in the output list of an assign statement may trigger no more than 50 assignments. or coded outputs.Replication of magnetically latched relays in principle.Timing and indication features that would be an expensive addition to conventional systems. 4. This file is given a filename extension of “ml2” . . Where the number of assign statements exceeds 3000.1 . The compilation software produces an application source file (mlp extension) and a listing file (mll extension). . tables. .CRN Engineering Procedure . This includes the total number of ASSIGN and NV.The Microlok II logic compilation software is to be used to process the completed application logic data file. . system interconnects.A maximun of 128 data bit inputs and 128 data bit outputs. It is recommended that NOTEPAD+ be used for this purpose. (Microlok Protocol) . blocks.Removal of back contact proving for relay down proving purposes only. and numeric blocks that may be defined. The listing file contains a summary of the application program.Removal or addition of relay features not relevant to ‘software’ relays. this limit is 399.There can be no more than 4095 assign statements in the Boolean Logic section.The application logic file may need to be corrected using the text editor and run through the compiler again. .

CRN Engineering Procedure . . mode failure releasing locking in the face of a train.Control System commands are pulsed. the NX style of circuit philosophy is to be largely replaced with the OCS style.Shunting requires the signaller to manually cancel the route as the auto normalising does not operate when the berth track is occupied. and thermal approach locking release timers. the ALSJR timer is used to normalise routes.4.Drop track circuit releasing in Approach Sticks for shunts only. For new works. The following features are typical: . © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 35 of 79 Version 2. which required an (N)R function. .4.Machine in Use/Finish function to advise the signaller of the status of the commence and finish of each route.Availability functions for point sequencing. It may not be directly applicable to existing installations where an NX control panel is retained.2 Applicability This is applicable to new Microlok interlocking projects that interface to both ATRICS or Phoenix and should be generally applicable to all control systems.Signalling Design of Microlok II Interlockings CRN SC 023 Some of these have resulted from a system that was developed from using magnetically latched RLR relays for signal routes. . . .1 . The operational implications of this arrangement include: . 4. 4.TZR/NR functions for automatic normalising that protect against a common.Locking arrangements that did not require point sequencing for overlap maintenance as a result of the simple layouts.Non storage of point controls individually applied to each set of points. . . .When shunting on main aspects. and present a more appropriate interface to the present control system. .Route normalisation calls initiated on the ‘A’ track down. .3 Elements of the OCS Philosophy The original OCS type installations had the following features: . improve operational flexibility.Can only set one route at a time. and circuits using direct button interfaces on the control panel.Track down releasing of Approach Locking. . 4.4 Elements of the NX Philosophy Entrance exit systems are generally used only in the larger interlockings and are the usual form of interlocking in the metropolitan area.It is not possible to maintain a route set if the ‘A’ track is failed. This will simplify the data design.An RSR relay (Non-vital) that incorporated the lever stick function. although existing relay based systems could be modified to provide this approach. .A restriction of being able to only set one route at a time. The operational implications of these arrangements include: .4.Non storage of points implemented through the ‘one shot’ route setting command requiring points to be free or available at the time of setting.

A consistent and identical interface for ATRICS and Phoenix. . 4. The route would then cancel when the train has fully passed the signal.Route normalisation to be initiated by the ‘A’ track dropping the RSR.It is (usually but not always) possible to set routes over track failures.4. 4. the following techniques are available: 1.Ability to set non-conflicting routes simultaneously. In some cases.Point sequencing will operate as per the current NX relay interlockings. .4. during shunting.6 Further Enhancements to the Interlocking Philosophy Generally.An RSR be provided for route setting and normalisation. approach locking time releasing will be required. the operational disadvantages are not considered to adversely affect train operation or system operation. It would only be possible to set the route when the train has occupied the berth track with the ‘A’ UNCONTROLLED WHEN PRINTED Page 36 of 79 Version 2.It will not be possible to set a route (especially a shunt route) if the ‘A’ track is failed.CRN Engineering Procedure . .1 . possibly delaying route cancellation. . .The RSR not to stick if the NLR does not drop at time of setting.Because the route normalisation is initiated by the ‘A’ track dropping the RSR. The technical and operational implications of this arrangement are: .The non-storage feature to be retained using the UJZR function inherent in the way Microlok Booleans provide for the NLR. In this case.Data to provide for separate main (120s) and subsidiary shunt (60s) approach locking release times and approach stick relays be provided to simplify current approach locking data.Considerably simplified route normalising data without loss of safety integrity.In some areas. which will reduce data design time and simplify the checking process. without signaller intervention required by cancelling the route. (Note: The Control System must prevent the issue of simultaneous calls on conflicting routes to prevent possible lockouts occurring in the interlocking) . .Consistent route normalisation when the signal is passed irrespective of whether the approach tracks remain occupied.Signalling Design of Microlok II Interlockings CRN SC 023 . . (Phoenix may not utilise all the indication bits). . . © JHR Issued March 2015 Using the berth track down in lieu of or in parallel with the ‘A’ track to hold the RSR. droptrack releasing has to be modified to minimise the risk of a single failure normalising the route prematurely. (However the track replacement in the RSR can be omitted for non-track controlled signals) .The following functions to be removed: o Ring circuit o Commence and Finish relay o Machine in Use relay o NR o SR A modified TZR is used in the new approach locking release arrangements.5 Changes to Interlocking Philosophy The following changes to the current standard NX interlocking will occur: . . it may be an operational requirement to be able to set a route when the ‘A ‘ track is occupied.

Signalling Design of Microlok II Interlockings CRN SC 023 track down. Phoenix Implementation Within Phoenix systems there is no necessity to prove the route NLR down in the RSR stick path. shunt route checking data should include the ‘A’ track. Typically.3 Naming Conventions Where possible bit names are to be kept the same as those used in conventional relay interlockings. the address allocated to the control system serial link is the same address allocated as the interlocking address number. Pending this facility being introduced. In configurations where one ‘Master” Microlok II interlocking is communicating with multiple ‘slave’ cardfile locations an interlocking address number is also to be provided.1 . Reference should be made to the Hot Standby Arrangements document in the appendix for how the address numbers are utilised in the application logic design in this instance. This name is to be consistent with the signalling location that the interlocking is to be installed. This arrangement could be universally applied. The Microlok II Boolean logic also follows a ‘break’ before ‘make’ rule. by using an additional button similar to the Emergency Shunt Function button). 4. The same method could also be used for auto-re-clearing of main routes. Allocation of the address is made through the Microlok Address Register in the Signal Design Office. Using ATRICS or Phoenix and maintaining the control system call until the signaller manually cancels the route (this could be performed.5 General Guidelines The Microlok II Boolean logic section of the program does not execute in the same manner as a typical computer program.5. and would provide for a more consistent user interface. 4.ASSIGN statements that need to be re-evaluated based on changes. © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 37 of 79 Version 2.2 Address Allocation Every Microlok II cardfile is to be provided with an address number.1 Program Title Every Microlok II program is to be provided with a title name. 4. and future upgrades of ATRICS only would then be able to retrospectively introduce this facility. 4.5. Option 2 is preferred as it results in the data design not requiring any modification from standard. Option 2 would permit the design of interlockings to a consistent standard.CRN Engineering Procedure . This arrangement would not be universally applied and hence signallers may have difficulty in knowing which routes had this facility. The route availability for the shunt signal (but not the ESF) in the control system will need to include the 'A' track to prevent the signal momentarily clearing and replacing during route calls with the 'A' track occupied. This number must be unique to the area or region to which that cardfile is to be installed. Deliberate signaller selection to clear a shunt signal without first track replacement is a requirement of the Emergency Shunt Function. A Microlok II program only executes those ASSIGN or NV. as the route set indications are produced by the Phoenix itself and an out of correspondence between the RSR and RUR would be seen as a failure prompting the signaller to cancel and reset the route.5. 2.

LINK_3. As a minimum.ENABLED. LINK_3.5 Boolean Bits Any bits that are assigned to a function that is exclusively used within the application logic and is not defined as either an input or output bit in the interface section is defined as a Boolean bit. It is also necessary to log some of the internal system bits. So. a snapshot is logged.FULL.LARGE. slow to drop. Snapshots are logged when "too many" bits change at the same time.7 Log Bits The Microlok II includes a built in event recorder. they are logged individually. the bits to be logged are: . if 300 bits are being logged. All timers may be defined as “adjustable” excluding those used for safety critical purposes.5.ENABLE. Upon further investigation. As a general rule.Status. 4. CPS. the trailing ‘R’ (denoting ‘relay’) is not required on data names. For large applications.Signalling Design of Microlok II Interlockings CRN SC 023 Bits defined in the interface section as inputs or outputs for a serial link are usually prefixed with the serial port number. or both. In a typical program.OK.4 Interface Section The interface section defines all of the local and serial I/O bits for the Microlok II cardfile.All outputs (except flashing. Reference should also be made to the relevant Microlok II manual to ensure reserved words and system bit names are not used.5. for example: 3_100MA_HR. pulsing or toggled outputs) © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 38 of 79 Version 2.33. (serial link bits for port 3. address 33) . inclusive of the following: .CRN Engineering Procedure . KILL.6 Timer Bits Defining timer bits is equivalent to making relays slow to pick.RESET. LOG. US&S have received reports about the event logger causing a load on the system. the system always makes sure that at least 1 snapshot is present in the log. Care must be taken to ensure any bits that flash or pulse are not logged. they have found that the user has specified every bit to be logged in the system data. a Boolean bit is equivalent to a relay coil that is not an input or output.STATUS. (There are 4 physical serial ports available) 4. If 55 bits change at the same time.5.RESET. 4. Any of the bits used in the program can be logged.All inputs (vital and non-vital) . this can cause a loading problem. It may be noticed that the Microlok performance seems to slow down on occasions. 4. with a minimum of 50 and a maximum of 100. Too many is defined as the "total number of bits being logged" divided by 5. QUICK.5. this may be when the system is writing a "snapshot" to the log. Up to 6 serial links may be declared in an application program although only 4 may be enabled at any one time. LOG. if more than 60 (300/5) bits change at the same time. CPS. Also.1 . Any Boolean bit or output bit can be given timing characteristics. LOG.

consideration should be given to breaking up the data so that it is more readable. As a general rule logging of all internal variables is not required. ^. &. AND Boolean AND OR Boolean OR XOR Boolean XOR +. @. they should be used to ensure designers and checkers have a clear understanding of the way the Boolean will function. !. 4. Comments are notes which would add clarity to the data reader and are ignored by the compiler. The operators used in the Boolean expressions in order from highest to lowest precedence are as follows: ~.1 . Comments Comments can be placed almost anywhere within the program. © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 39 of 79 Version 2. and using parenthesis may change operator precedence. however if there is any doubt with complex ‘or’ statements. NOT Boolean NOT *.ASSIGN (or) NV. pulsing or toggled outputs are to be logged.CRN Engineering Procedure .ASSIGN <Boolean expression> TO <bit>.8 Boolean Logic The basic format of an assign statement is: .Signalling Design of Microlok II Interlockings CRN SC 023 . Liberal use of comments are encouraged to make the program easier to understand.5.Any internal bit that may give a concise report of an event. Parenthesis should be kept to a minimum. Internal bits that initiate flashing. Operators of the same precedence are evaluated from left to right. Where data constructs have a number of complex parallel paths.

STATUS TO LINK_3.ENABLE is used in the control of the VCOR relay.9 CRN SC 023 Constants Constants that are to be used in the program are to be defined.STATUS TO LED.10 Conditional Power Supply Logic The internal system bit. Typically this is done as follows: CONSTANTS BOOLEAN TRUE = 1. This logic also ensures the version of the compilation software is verified to the executive version of software loaded into the Microlok II CPU card.ENABLE. If the incorrect numbers are entered at this time the Microlok II unit will shutdown due to the internal system bit “KILL” becoming true. program verification logic has been developed.DISABLE.5.5. Note that “KILLZ” is a Boolean bit. Data having inputs from Genisys serial links should have a comms link status bit included so that Genisys bits that freeze on link failure or disconnection will not affect system operation.12 ASSIGN LINK_3. for example LINK_3. 4.CRN Engineering Procedure .5. UNCONTROLLED WHEN PRINTED Page 40 of 79 Version 2.STATUS TO LINK_3. Typically this is done as follows: ASSIGN 4. NV. these ports are to be disabled should the Microlok II cardfile CPS status be down. The LEDs on the front of the Microlok II CPU card are also generally utilised to indicate to the Maintenance staff the status of serial links. CPS.33. The program verification logic and User Numeric are as follows: USER NUMERIC ADDRESS_NUMBER : © JHR Issued March 2015 "Set Address Number" . Program Verification Logic In order to ensure the correct version of application logic is uploaded into the Microlok II cardfile location.Signalling Design of Microlok II Interlockings 4. Vital Serial Ports Where serial port configurations exist that utilise the vital “MICROLOK” protocol.33. The statements listed in the User Numeric section of the program work in conjunction with the program verification logic to ensure the correct numbers are entered during the modification of the system configuration settings. if paired internally with a backup or duplicated link.1 . Where serial links are in use there may be a requirement to prove the link is operational before allowing certain bits to become true.ASSIGN LINK_3. FALSE = 0. Typically this is done as follows: // SERIAL LINK MONITORING LOGIC 4.11 TRUE TO CPS. for example input control bits received over a non-vital link. Typically this is done as follows: ASSIGN ~CPS. as long as all diagnostics are passed the VCOR relay will always pick.3. Where this function is required a Boolean bit may be defined with a name particular to that serial link.5.

An example of revision verification logic is as follows: //REVISION NUMBER VERIFICATION LOGIC ASSIGN ~DUAL_LINK_OK + (I2_REVISION_BIT1 * REVISION_BIT1) + (~I2_REVISION_BIT1 * ~REVISION_BIT1) TO REVISION_BIT1_OK. KILLZ + CONFIGURE. © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 41 of 79 Version 2.13 Revision Number Verification Where the Microlok II application logic has been produced for the MASTER interlocking of a Hot Standby configuration revision verification logic is to be provided.Signalling Design of Microlok II Interlockings REVISION_NUMBER : EXECUTIVE_VERSION: ASSIGN CRN SC 023 "Set Revision Number" . //Convert the decimal "REVISION" number to a binary number //Note_ Additional statements are required should the REVISION number be greater than 15. ASSIGN ~DUAL_LINK_OK + (I2_REVISION_BIT3 * REVISION_BIT3) + (~I2_REVISION_BIT3 * ~REVISION_BIT3) TO REVISION_BIT3_OK. The logic converts the revision number into a 4 digit binary number. ASSIGN KILLZ + ~REVISION_NUMBER_OK + CONFIGURE. ASSIGN REVISION_BIT1_OK * REVISION_BIT2_OK * REVISION_BIT3_OK * REVISION_BIT4_OK TO REVISION_NUMBER_OK. If the two compared numbers are not identical the internal system bit “KILL” will be made true causing the Microlok cardfile to shutdown. END LOGIC NUMERIC BEGIN //PROGRAM VERIFICATION LOGIC BLOCK 1 TRIGGERS ON CPS. which is then passed through the dual link of the Hot Standby configuration and compared with the revision number of the other interlocking.ERROR TO KILL.ENABLE AND STALE AFTER 0:SEC.ERROR TO KILL. END BLOCK END NUMERIC 4. ASSIGN (ADDRESS_NUMBER <> 89) OR (REVISION_NUMBER <> 5) OR (EXECUTIVE_VERSION <> 510) TO KILLZ.ENABLE AND STALE AFTER 0:SEC. END LOGIC NUMERIC BEGIN //PROGRAM VERIFICATION LOGIC BLOCK 1 TRIGGERS ON CPS.1 . IF ((REVISION_NUMBER/1 % 2) = 1) THEN ASSIGN TRUE TO REVISION_BIT1. ASSIGN ~DUAL_LINK_OK + (I2_REVISION_BIT4 * REVISION_BIT4) + (~I2_REVISION_BIT4 * ~REVISION_BIT4) TO REVISION_BIT4_OK.5. ASSIGN ~DUAL_LINK_OK + (I2_REVISION_BIT2 * REVISION_BIT2) + (~I2_REVISION_BIT2 * ~REVISION_BIT2) TO REVISION_BIT2_OK. "Set Executive Version" .CRN Engineering Procedure . This logic is to be produced to ensure identical data is uploaded into both of the two MASTER interlocking cardfiles.

CLEAR=0:SEC.DISABLE. resulting in all the bits received by the healthy master on the dual link dropping out simultaneously.CRN Engineering Procedure . All bits received for output comparison are already made slow to drop to ensure that the B_BYPASS bit can pick before the comparisons fail.DISABLE.DISABLE. CLEAR=2500:MSEC. Inputs from slaves may be staggered by applying different timers to the address verification bits: ADJUSTABLE ADJUSTABLE ADJUSTABLE SP25_ADDRESS: SET=500:MSEC SP23_ADDRESS: SET=1000:MSEC SP5_ADDRESS: SET=1500:MSEC CLEAR=0:SEC. This is addressed in the Dual Hot Standby Arrangements in Appendix B. the up signal control bits received on the dual link for output comparison are made 0.5 seconds slower to drop than other output comparison bits.STATUS + ~VSL1JR LINK ASSIGN ~VSL4JR VITAL LINK ASSIGN ASSIGN CLEAR=0:SEC. CLEAR=2500:MSEC. TO COMM1. % 2) = 1) THEN ASSIGN TRUE TO REVISION_BIT3. <> 10) OR (REVISION_NUMBER <> 13) OR 510) TO KILLZ. To overcome this scenario delays may be provided to the establishment of serial links. //VITAL TO COMM4. CLEAR=2500:MSEC. CLEAR=2500:MSEC. To overcome this.14 Logic Queue Overflow Where too many assign statements have been triggered for execution at one time a Microlok II shutdown may occur due to a logic queue overflow error. CLEAR=0:SEC. particularly where multiple serial links are provided.5. % 2) = 1) THEN ASSIGN TRUE TO REVISION_BIT4. //NON- CPS. //VITAL TO COMM2. CLEAR=2000:MSEC.1 . TO VSL4JR. This situation may arise at start up when serial links are established and multiple inputs are set at the same time. B33M_HR: B33S_HR: B38MA_HR: B38SA_HR: B38MB_HR: B38SB_HR: © JHR Issued March 2015 SET=0:SEC SET=0:SEC SET=0:SEC SET=0:SEC SET=0:SEC SET=0:SEC CLEAR=2000:MSEC. UNCONTROLLED WHEN PRINTED Page 42 of 79 Version 2. CLEAR=0:SEC. A similar situation may occur when one side fails.Signalling Design of Microlok II Interlockings END IF IF ((REVISION_NUMBER/2 END IF IF ((REVISION_NUMBER/4 END IF IF ((REVISION_NUMBER/8 END IF ASSIGN (ADDRESS_NUMBER (EXECUTIVE_VERSION <> CRN SC 023 % 2) = 1) THEN ASSIGN TRUE TO REVISION_BIT2. END BLOCK END NUMERIC 4.STATUS + ~VSL1JR LINK ASSIGN ~CPS.ENABLE + VSL4JR TO VSL1JR. An example of this application logic is as follows: TIMER BITS ADJUSTABLE ADJUSTABLE VSL1JR: SET=40:SEC VSL4JR: SET=20:SEC ASSIGN ~CPS.ENABLE + VSL1JR CPS.

4. both in terms of the communications and the track shunt / shunt clearing times. Each message cycle (master send.OUT TO 3_DGE.CRN Engineering Procedure .  Crossing control outputs are to be preferably qualified by physical contacts of all track circuits within the control area. this is to prevent crossing operation upon cardfile shutdown unless a train is present. 4. and up to 18 seconds to show clear after the shunt is removed.5.1 .16 Coded Track Circuits MicroTrax coded track circuits provide 22 codes for application communication between ends.5. which requires two missed messages. and when two or more codes are simultaneously activated by the application logic.OUT * (~3_DR + 3_DGE_LAMP. Designers need to be aware of this and ensure that higher-priority codes do not convey contradictory information to lower priority codes which may be validly active at the same time. This however allows use of the 'Sleep' code for other application purposes. slave respond) is approximately 6 seconds. so may take up to 12 seconds. the user application must put the unit to sleep. but most messages need to be initially received twice.18 Level Crossings Where Microlok provides for control of level crossings. Shunt is actually determined by failure of communications. Designers also need to take into account the inherent delays of coded tracks. Where level crossing operation is interfaced to controls in other interlockings.  Master emergency Switch controls shall be applied external to the Microlok. the lamp may light if driven. Microlok does not inhibit a lamp it has detected as failed. Each code has a unique priority level. To prevent this. a suitable handshaking arrangement between the systems shall be implemented to ensure that timing delays between events does not create the possibility of irregular operation.OUT) TO 3_HGE. only the highest-priority code will be transmitted. Note that the 'Sleep' code does not put the unit to sleep. it is important that the following circuit configurations apply:  Boom delay shall be applied external to the Microlok. or to traffic lights. ASSIGN 3_DR * ~3_DGE_LAMP.Signalling Design of Microlok II Interlockings 4. then continuously two out of three. As a shut-down of the cardfile will remove all outputs. as part of the security of the protocol (there are two “fast” codes for special purposes). and also for booking out signals. if required.17 Vital Blocking This section has been left intentionally blank.5. the testing parameters may allow a lamp to be declared failed when in fact a circuit fault is presenting a higher than expected resistance. However. 4. and in the event of such a circuit failure.5. which is often used to maintain lower aspects if the higher aspect lamp is failed.19 Tracks © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 43 of 79 Version 2. 4. the lamp failure bit is proved down in the lamp output assignment.5.15 CRN SC 023 Lamp Driven Signals Lamp driver cards provide “cold” filament proving of lamps. consideration needs to be provided for failure modes that may impact the level crossing. ASSIGN 3_HR * ~3_HGE_LAMP.

As some track circuits are inherently slow to operate. The following table provides details of the inherent slow to pick functionality in the track circuit equipment and the consequential input delay to be applied in the CBI: Track Circuit Type 4.4 Westinghouse FS2600 1 2 TD4 0 3 Signals TZR. a consistent 3 second delay will have been universally applied.6 1. The SR and NR functions are not required where the application logic is designed with an RSR function as per OCS type interlockings. there is protection against track bobbing prematurely releasing the interlocking. By the application of a consistent time delay to track circuit operation.CRN Engineering Procedure .1 . 3_UNR + (~3M_NLR + ~3S_NLR) * ~3M_RSR * ~3S_RSR * 3_NR + 3_TZR * 1CT * 3_ALSR TO 3_NR. a new form of TZR function is used as part of the drop-track release of approach locking: ASSIGN ~3SA_RSR * ~3SB_RSR * (~3AT * ((3BT * 101_NLR) + (3XT * 101_RLR)) + 3_TZR * ((~3BT * 101_NLR) + (~3XT * 101_RLR))) TO 3_TZR. The concept is that by the time a track circuit clear indication is given to the interlocking. In CBI interlockings it becomes much easier to be able to provide time delays which present a more consistent time sequence of track circuit operation to the interlocking.Signalling Design of Microlok II Interlockings CRN SC 023 In general all track inputs are to be provided with a slow to pick timing function. the CBI input delays may be varied to complement these times and achieve a consistent 3 seconds.4 Westinghouse DPU 1. In NX style interlockings these functions are as per typical relay circuits as shown following: ASSIGN ASSIGN ASSIGN ~3AT * (~1CT + 3_TZR) TO 3_TZR.6 1. © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 44 of 79 Version 2.20 Track Circuit Inherent Delay CBI Input Delay DC 0 3 AC 0 3 Jeumont 0 3 CSEE 2 1 CSEE DPU 2 1 ML 2 1 Westinghouse FS2500 1. RSR The RSR function is as per typical OCS type interlockings and ensures the auto normalisation of the signal route through the occupation of the ‘A’ track past the signal.5. 48AT * (3M_NLR * 3S_NLR + 3_NR + 3_SR) TO 3_SR. This TZR is provided to minimise the risk of undesired release of approach locking simultaneously with route normalisation under certain failure scenarios. SR. and NR In an OCS interlocking.

The output HR relay function is to include this intermediate function and the train stop VRR input bit. This function is required as part of the logic for simulation of the magnetically latched NLR relay. ALSR / ALSJR The ALSR function is as per standard relay circuits with the exception of two timing release paths. A new release path based on the new TZR function is used instead. This bit is also provided to the Control System as a route availability bit.Signalling Design of Microlok II Interlockings CRN SC 023 Where the application is not to be designed as per OCS type interlockings the RSR bit is to be included in series with the UJZR in the stick path of the RUR function. © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 45 of 79 Version 2. Where the Microlok II configuration requires a Hot Standby arrangement reference should also be made to the ‘Dual Hot Standby Arrangements’ document found in the appendix. (via the UJZR) As per typical relay circuits the NLR function is utilised to prove the signal is normal and when down will not become true unless the signal is normal and free of approach locking. RUR The RUR function will become true through the route setting control bit (RSR) being set and with the route proven to be free to set via the UJZR bit. NLR The NLR function is held true unless the route is free to set. HR The HR function is typically an output bit. For main line routes the HR function will require an intermediate function where train stops are provided. RUZR The RUZR function proves the required opposing locking is normal and that all necessary points are locked in the required position or free to be moved. If a POJR is required to be provided in any ALSR release path then a power off (POR) vital input will be required and assigned to a POJR timing function of 30 seconds slow to set. Note that the UJZR function is given a slow to drop (clear) timing function of 1 second to ensure the RUR will have time to become true and stick up before the UJZR drops. which continuously monitors the status of the locking. Following is an example of typical application logic for a signal and one of the signal routes. as a single failure could both drop the RSR and release the approach locking. Note the stick path around the UJZR bit. Those functions shown that were not previously covered above are designed as per typical relay circuit standards. //========================================================3 SIGNAL ASSIGN ~3M_UCR * ~3S_UCR * 3VNR * ~3M_HR * ~3S_HR * 3NGP TO 3_NGPR. Where the application is designed in line with OCS type interlocking the two-drop-track release path is not to be provided.1 . The main and shunt routes may have separate ALSJR timing functions as specified in the control tables. This function has been created for use in the UJZR and RUR functions and avoids the need to duplicate the information. This function is provided as an interlocking safeguard.CRN Engineering Procedure . UJZR The UJZR function may be referred to as a route free to set expression.

ASSIGN 3M_RUZR * ~3M_RSR TO 3M_UJZR.Signalling Design of Microlok II Interlockings ASSIGN 3RGK. The WJZR function can be regarded as a point free to move function. ASSIGN (3_ALSR + 3M_NLR) * ((3AT + 102_RWKR) * 3BT * 3CT + 3M_USR + 3CTJR + 3BCTJR) TO 3M_USR. ASSIGN 3M_HR * 3M_HP * 9A_HP * 9VRR TO 3M_HDR. which continuously monitors the status of either the normal or reverse locking depending which way the points are currently laying and the local tracks clear. ASSIGN 3AT * 3BT * 3CT * 9AT * (9BT + 103_RWKR) * 101_NLKPR * (103_NWKR + (16M_USR * 14AT)) * 3M_RUR TO 3M_UCR. WLZSR © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 46 of 79 Version 2. WJZR The WJZR function is provided as an interlocking safeguard. //----------------------------------------------------------- 4. ASSIGN 3M_HDR * 3M_HDP * (9A_HDP + 9A_DP) TO 3MA_DR.21 Points The point setting and point locking functions are separate in the application logic design.5. ASSIGN 3S_NLR * 6SB_NLR * ((16M_NLR * 16M_USR) + 103_NLR + 103_WJZR) * (101_NLR + 101_WJZR) TO 3M_RUZR.1 . ASSIGN 3_NGPR TO 3M_ALSJR. The point setting functions NZ and RZ include all the setting conditions to call the points normal or reverse respectively. ASSIGN ~3M_USR * ~3CTJR * 9A_VCSR * ~3_NGPR * ~3_ALSR * ~3M_ALSJR * 3M_UCR TO 3M_HR. //60” //=======================================================3(M) ROUTE ASSIGN ~3_UNR * (3M_URR + (3AT * ~3M_NLR * 3M_RSR)) TO 3M_RSR.3CT + 1_ALSR) * 1AT) + 3M_NLR) * 1BT * 1CT) TO 3_ALSR. //120” ASSIGN 3_NGPR TO 3S_ALSJR.CRN Engineering Procedure . CRN SC 023 3MHP + 3SHP TO ASSIGN 3_NGPR * (3_ALSR + ((3M_ALSJR + 3M_NLR) * 3S_ALSJR) + (~3AT * 3M_NLR * POJR) + (3AT * 3_TZR * POJR) + (((260. ASSIGN 3M_RUZR * 3M_RSR * ~3M_NLR * (3M_UJZR + 3M_RUR) TO 3M_RUR. including the direct point ‘key’ calls. ASSIGN (3_ALSR + 3M_NLR) * (~3M_RSR + ~3M_UJZR * 3M_NLR) * ~3M_RUR TO 3M_NLR. Note the WJZR is to have a slow to clear timing function of 500 ms and a slow to set timing function of 1 second.

EP points will utilise EOL push buttons and require modified data functions. The isolating relay (IR) function is used to provide an independent over lock on the points by electrically isolating them and also incorporates the points transit function WTJR. The WLZSR function would be down at start up and then permanently true once either of the point locking functions have been established. the points NLR or RLR function will become true allowing the points to move. holding up the NLR or RLR unless the points WJZR function is true. or push button operated points. The WTJR is not to time unless conditions permit the IR to be energised. If the points have not operated and reached the required position within 10 seconds of the IR energising then the WTJR function will become true and the external IR will drop cutting power to the points.1 . Occupation of local track circuits or operation of the EOL are to reset the WTJR. via the points NZ or RZ control bit and the points are free to move. POINTS CONTROL The following description applies to electrically operated points. NLR / RLR In conjunction with the points WJZR function the NLR and RLR functions simulate the operation of the magnetically latched relay. Note that the WCZJR is to have a slow to set timing function of 15 seconds. The points will remain locked. the NLR function would also need to be modified. A separate input into the Microlok II is to be provided for the ESML / EOL. When a point call is not usually present such as in an automatic crossing loop. If the points NLR function is true then the output bit NWR will call the points normal subject to any further control conditions applied via the IR. Loss of the ESML / EOL input will also cause loss of detection. RWR and IR. To cover the situation where no detection is present during start up the WLZSR is used in the WJZR function to call the points normal in conjunction with the points NR control bit.CRN Engineering Procedure . If the points RLR function is true then the output bit RWR will call the points normal subject to any further control conditions applied via the IR. When a point call is made. If the points were lying reverse they would drive normal. If at any time the handle is removed then the IR will be de-energised cutting power to the points. The energisation of the IR enables the points to operate to the position required via either the NWR or RWR being energised. Points are controlled using three output bits to drive three relays. These output bits and relays are designated NWR. (NWKR and RWKR) © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 47 of 79 Version 2. ( ~WLZSR * ~ RKR would be required to qualify the NZ bit in the points NLR function) WCZJR In circumstances other than start up where both the points NLR and RLR functions may be down the WCZJR function is used to set either the NLR or RLR function in line with the detection.Signalling Design of Microlok II Interlockings CRN SC 023 The WLZSR function provides a one shot feature during the initial start up period of the interlocking to allow the point lock relays to initialise in line with the point detection. (Which would need to be true). The WTJR is to have an adjustable slow to set timing function of 10 seconds. Until the point lock relays have been initialised it is not possible to drive the points.

* 1M_USR * 3M_NLR * 3S_NLR * 6SB_NLR * + 8BT) * 101_NLR * ~101_RR) + 6SA_NLR * + 1CT) * ~101_NR + ~101_WLZSR))) * 101_CZ TO (101_NLR + 101_RLR + 101_WLZSR) TO 101_WLZSR. These input bits are designated NKR and RKR and are to be provided separately for each end of a set of points. ASSIGN ASSIGN 101_CR 3AT * 8AT ((1M_NLR * (14MB_USR2 (6MA_NLR * (14MB_USR2 (101_RLR * 101_WJZR. Where the Microlok II configuration requires a Hot Standby arrangement reference should also be made to the ‘Dual Hot Standby Arrangements’ document found in the appendix. ASSIGN 101_RLR TO 101_RWR.//15” TO ASSIGN (101_NZ * 101_WJZR + 101_NLR) * ~101_RLR * (~101_RZ + ~101_WJZR * 101_NLR) + (~101_WLZSR + 101_WCZJR) * 101_NKR * ~101_RKR * ~101_RLR * ~101_NLR TO 101_NLR. Two further detection and locking functions are to be provided and are designated NLKPR and RLKPR and these are used for interlocking logic conditions in which the WJZR is required true. ASSIGN 101A_NK * 101B_NK * ~101A_RK * ~101B_RK TO 101_NKR.CRN Engineering Procedure . ASSIGN ((6MA_RUR + 6SA_RUR) * 101_CZ + 101_RR) * ~101_NZ TO 101_RZ. Following is an example of typical application logic for a set of points. They are associated with the points control logic in addition to driving the secondary detection. Loss of this input will cause a loss of detection. The NKR and RKR input functions are to be crossed proved in each other. © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 48 of 79 Version 2. Those functions shown that were not previously covered above are designed as per typical relay circuit standards. ASSIGN (101_RZ * 101_WJZR + 101_RLR) * ~101_NLR * (~101_NZ + ~101_WJZR * 101_RLR) + (~101_WLZSR + 101_WCZJR) * 101_RKR * ~101_NKR * ~101_NLR * ~101_RLR TO 101_RLR. //=======================================================101 POINTS ASSIGN ((1M_RUR + 3M_RUR + 3S_RUR + 6SB_RUR) * 101_CZ + 101_NR) * ~101_RZ TO 101_NZ.//1” ASSIGN TO 101_CZ.1 . ASSIGN 101_NLR TO 101_NWR. (NWKR and RWKR) Points are detected using two input bits to provide the primary detection functions. Two secondary detection functions are to be provided and are designated NWKR and RWKR and are used for interlocking logic conditions in which the WJZR is not required to be down. ASSIGN 101A_RK * 101B_RK * ~101A_NK * ~101B_NK TO 101_RKR. ASSIGN 101_WLZSR * ~101_NLR * ~101_RLR * 101_CZ 101_WCZJR.Signalling Design of Microlok II Interlockings CRN SC 023 The external IR relays are down proved as inputs into the Microlok II cardfile.

ASSIGN ~101_WJZR * 101_RWKR * ~101_NLKPR TO 101_RLKPR. and further. ASSIGN 20_NZR TO 20_NKR. As © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 49 of 79 Version 2. The peer-to-peer protocol allows timestamps to be attached to communications.1 . //----------------------------------------------------------------- 4. particularly when trying to align logs from different CPUs where the clocks have drifted independently. ASSIGN 20_RWZR * ~20RR TO 20_WJZR.5. ASSIGN 101_NKR * 101_NLR * ~101_RKR * ~101_IR * 101_IZ * 101_EOL TO 101_NWKR. used primarily for timestamping of log entries. ASSIGN 20_RLR * ~20_NR * 19_RWKR TO RELSW_D_REV.CRN Engineering Procedure . ASSIGN 3SB_NLR * (46M_NLR + 20_RLR) * (19_RLR + 19_WJZR * 20_SR)TO 20_RWZR. ASSIGN (~20RR + ~20_WJZR * 20_NLR) * ~20_RLR * 3SA_NLR * (20NR * 20_NR + 20_NLR) TO 20_NLR. ASSIGN 20RR * (20_WJZR + 20_RLR) * 20_RWZR * ~20NR * ~20_NLR TO 20_RLR.23 System Clock Microlok II and Object Controllers include a ‘real time clock’. ASSIGN 20_RKR * 20_RLR * RELSW_D_REV * ~RELSW_D_CZR TO 20_RR.20 ASSIGN / 19_WJZR * (20_NR + 20_SR) TO 20_SR. clocks have been observed to drift beyond acceptable limits. ASSIGN 20_NKR * ~20_RLR * ~RELSW_D_REV * RELSW_D_CZR * ~4_FR_D_LPR * FR_D_EM_REP TO 20_NR.Signalling Design of Microlok II Interlockings CRN SC 023 ASSIGN (101_NLR * ~101_NKR + 101_RLR * ~101_RKR) * ~101_WTJR * 101_EOL * (6_ALSR * 3AT * 8AT + 101_IR) TO 101_IR.5. ASSIGN 101_RKR * 101_RLR * ~101_NKR * ~101_IR * 101_IZ * 101_EOL TO 101_RWKR. ASSIGN 20_RZR TO 20_RKR.//10” ASSIGN ~101_WJZR * 101_NWKR * ~101_RLKPR TO 101_NLKPR. The system clocks on all CPUs within an interlocking can therefore be synchronised. but it is prone to drift. but in between visits. ASSIGN (101_NWR * ~101_NKR + 101_RWR * ~101_RKR) * 101_EOL * 6_ALSR * 3AT * 8AT TO 101_WTJR. Maintenance instructions require maintainers to adjust the clock of each CPU at each scheduled maintenance visit. This makes fault and incident investigation very difficult.22 Ground Frames An example of the typical application logic for ground frames is as follows: //================================================ FRAME D . //----------------------------------------------------------- 4. allows that these timestamps can be used to update the clocks on remote CPUs.

Where adjacent Microlok interlockings have a communications interface. this may cause difficulty. At the receiving end. the Principal Engineer Signals may give approval.TIMEOUT: 4000:MSEC. the items are not absolutes. and if a preferable arrangement is proposed for a specific job. PEER. There may be advantages in installing these boards on the right hand side.SET. the timestamp will be transmitted with every data transmission. other cards should be installed as follows: .Coded Track Circuit Cards .CLOCK.Vital Outputs © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 50 of 79 Version 2. e. HEARTBEAT. With the communications defined thus.MASTER: 1. In many cases. CLOCK.SET will cause the flag to be set in all peer communications for which the CPU is CLOCK.1 . At the time master.1 Microlok II Design Configuration and Settings In order to provide consistency between applications the following guidelines are to be followed by designers. 5. but the slave CPU will only update its clock when a system flag is set in the message. through MP2 to slaves or through an interface slave to the adjacent interlocking.CPU . However where card files are considered for the installation of split card files. 5 Circuit Design 5.DATA.ADDRESS: 1809 ADJUSTABLE ENABLE: 1 STATION.1 Arrangements of Cards in Card Files Previous installations installed the CPU and Power Supply in the left most position of the card file. The interlocking master shall be the time master for an interlocking.STAMP: 1.INTERVAL: 1600:MSEC.STAMP should be zero at the time slave end. Where multiple addresses are used between a time master and any of its slaves. and all other slaves synchronising to that master. If the clock update is to be cascaded through one Microlok to others.Lamp Drivers .ADDRESS: 2001. setting the bit PEER.MASTER needs to be set in the peer-to-peer address definition at the time master end only. From the left hand side. the interlocking at the Sydney end may be used as the time source for the other interlocking(s) by the second interlocking master synchronising to the interface slave. synchronising only serves to ensure that all clocks within an interlocking are incorrect by the same amount.Signalling Design of Microlok II Interlockings CRN SC 023 there is at this stage no method to connect to an external timing source. this should only be included on one address.g. MII. To achieve synchronisation. to minimise the processing and communications overheads. the parameters TIME.STAMP and CLOCK.CLOCK. STALE.Power Supplies .CRN Engineering Procedure . Where the card file is likely to be filled to capacity. TIME. TIME. the update of the clock is invisible to the application. installation on the right hand side may be preferable.1.NAME: MJMP_MJ34.MASTER. then the application must send a bit to signal those units to set their PEER.

2. This allows you to assess the power consumption on each of the Microlok internal power supplies based on your design configuration. CPS card N451910-7501 is a double width card the same as the power supply card. 5. there may be inputs and outputs that are not wired. A UPS will usually be needed at the source of the new external supplies. The +12V supply is unchanged at 1 amp. Also. -12V. and there will usually be mutuallyexclusive combinations – some functions that cannot be on at the same time as others. For example. it becomes necessary to provide an external power supply.3. The wiring for this is shown in the US&S manuals in section 2. This can result in the power consumption being less than indicated. 5. +12V.Signalling Design of Microlok II Interlockings CRN SC 023 . The power supply card also drives the VCOR relay via a small DC-DC converter which is activated by the 250Hz CPS signal from the CPU. and 2 amps on the -12V supply. before using either “discounting” option.1.NV I/0 Cards . or CPU and input cards only) then the power supply card is not provided.CRN Engineering Procedure . but also into the CPS card. and the external power supply unit is connected to the Microlok by means of the terminals on the back of the cardfile behind slot 19. When using version 5. The version 8. a CPS card is required. values which exceed the listed capacity can be manually compared to the increased capacities of the new card: 5 amps on the +5V supply.1 .2 External Power Supply When the power consumption is beyond that which can be handled by the Power Supply card.50 includes facility to specify the number of simultaneous inputs ore outputs (as an average per card). the calculator in version 5.Code Interface Cards 5.1. and see the actual power requirements. © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 51 of 79 Version 2. CPU only.50 calculator shows both power supply cards and their capacities separately. This card provides the connection to the VCOR and also the 250Hz CPS signal to the CPU. No VCOR Required If the cardfile is being used in a situation where no VCOR relay is required (i. The calculator in Version 5. Version 8.1 of the 6800B manual and page 2-4. VCOR Required Where a VCOR is required because the cardfile contains output cards. some measure of analysis is required to estimate how many inputs and outputs can be on simultaneously for each location.1 Microlok II Power Consumption The Microlok II Development System (“Microlok Tools”) includes a cardfile power calculation tool.Vital Inputs . When this card is used the external power supply must be connected not only to the back plane terminals behind slot 19. and through on-board DC-DC converters provides multiple supply voltages for the cardfile: +5V.1. or lamp driver cards.10 assumes the worst case – all inputs and outputs on – so you may have to 'discount' and make allowance for the specifics of the particular arrangement.10 is based on power supply cards which have now been superseded.1.2 Power Supply Card The Power Supply Card receives a 12VDC inputs.2. However.10.e.

Where isolated converters are used.1 Isolated External Supplies At locations where cardfile load exceeds the capacity of the power supply card. As a result.Signalling Design of Microlok II Interlockings 5. However. If B12 is still connected to the power supply card. the VCOR is de-energised and outputs are thereby disabled.1.2. a train approaching that signal should already be travelling slowly. For signal aspect controls. the risk that this will result in an accident is extremely small. However. and so the driver should observe the signal return to stop before passing it. this leakage current may be sufficient to falsely energise multiple relays. an external power supply must be used.2. Single-sided Installations For small non-duplicated cardfiles with no more than two OUT16 cards. 5. the OUT16 cards are not to be connected directly to the location N12 bus. the 12V supply can “leak” through the OUT16 transistors through relay coils to N12. For most situations. and the VCOR will drop.2. The typical arrangement for this is a group of DCDC converters – one for each supply voltage. The preferred arrangement using Powerbox / Schaeffer “Eurocard” converters provides the necessary isolation. the N12 connections for the OUT16 cards are taken by two wires per card the N12 bus. circuits must be arranged to ensure that loads (relays or isolation modules) connected to output cards cannot become the only path for current to return to the N12 bus. Single-sided Installations At non-duplicated cardfiles with more than two OUT16 cards.CRN Engineering Procedure . If a © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 52 of 79 Version 2. If a signal at Stop falsely shows a clear indication. In this arrangement. or stopped. If the N12 is disconnected from the power supply card. 5. the relays have no negative connection for the B12 to leak to. the VCOR will drop. so cannot be energised. using two wires for each OUT16 card.1 .1. If all N12 connections to the cardfile are removed. 5.2.2.2 Small. If all N12 connections are disconnected from the cardfile. Various techniques apply depending on the local configuration.1 N12 Connections and Vital Output Cards CRN SC 023 The OUT16 vital output card takes 12V output supply through a contact of the Vital CutOff Relay (VCOR). All relays driven from an OUT16 are to have their coil negative connected to the corresponding Output PCB N12 bus. the hazard is eliminated. the transistors do not provide isolation between the cardfile backplane and the output loads. there may be up to 1 second between a fault occurring on output and the system detecting the fault and shutting down. noise-filtering facilities are also used to prevent momentary noise being detected as a critical fault. Additionally. the N12 supply is connected to the power supply card. and the relay coils do not provide a leakage path to N12.2 Circuit Design Hazards 5. All terminals connecting the cardfile to the N12 bus are to be non-disconnect type. 5. the train stop drive time exceeds the fault duration.1. All relays driven from an OUT16 are to have their coil negative connected to the corresponding Output PCB N12 bus. Depending on the configuration of a particular location. wire the N12 from non-disconnect terminals through a contact of VCOR to create an independent Output PCB N12 bus. and uses transistors (power FETs) to drive the output loads.2 Output Card Faults Microlok performs error-checking of vital hardware systems including the OUT16 cards.3 Larger. The N12 terminals of each OUT16 card are wired out to an independent Output PCB N12 bus. In the event of a critical fault. the cardfile will shut-down. To protect against this hazard.

Also check the VCOR has front contacts in use.Power is on. CRN circuits already incorporate defences:  cross-proving of the points normal and reverse control contactors  provision of the Isolating Relay. and the relay is biased. 008). they should be straight numeric values (e. except 2.4. which has to simultaneously energise with the points contactor.9. the train must be in a short range where the new indication can be seen.10. outputs 1 – 8 and outputs 9 – 16 may be treated as separate groups. There is no power on the coded track card. but the signal is passed before it returns to the correct state.1 . Ensure the dip switches or jumper pins on the card plugs are correctly set. and the isolating relay from the other. Boot up requires at least 11V to occur reliably.g.Signalling Design of Microlok II Interlockings CRN SC 023 restrictive indication steps to a less-restrictive indication. Even in this case though. © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 53 of 79 Version 2.System starts but CPS and VCOR do not pick. for the VCOR bus and card supplies.System boots. the following advice from the Microlok manufacturer is to be implemented for all new Microlok designs: 1. 1. lamp drive). but LED’s on coded track card light. While these provide strong protection against the incorrect operation of points.System will not accept version numbers with leading zeros (i.e.System starts.5. Check the main 12V supply and negative return to this card and condition of fuses and links . For points. .3. User configurable items are stored in the EEPROM on the CPU plug coupler.VCOR does not pick. and the control relays should be driven from one group. Output. the sighting distance and the overlap for the next signal are mitigating factors. and  track relay contacts in the external circuit of the isolating relay to prevent the points moving with a train in the immediate vicinity.11 etc). it becomes easy to identify. Note that the CPS delivers a greater negative than the N12 does.System boots and data is loaded. Check the VCOR negative pin is in. The Isolating Relay shall not be driven from the same output card as the points control relays. then fade away.2.7. but CPS light on the power supply card is on. . .CRN Engineering Procedure . Check that the VCOR supply to the cards is present (especially output and lamp driver cards).8. Check the supply voltage. . but the system will not accept the user configuration address and version number. Check the VCOR fuse. and the relay is wired correctly. Do not use leading zeros in version numbers. The following gives a description of those faults and the possible causes: .g. Check the error log using the Microlok Tools to narrow the fault to a specific card. Where a small location has only one output card. and that the crimps in the plug couplers are correct and pushed fully home. .6. but no signs of life. Check that the wiring from the EEPROM is correct and that the crimps are good and pushed well home in the plug. but CPS cycles and VCOR picks and drops until system locks out. 6 Setting To Work Experience with setting to work Microlok II systems has shown that many of the faults reoccur and having seen it before. Ensure all cards are powered where necessary (e.

1 .System still having problems and it is hard to isolate the fault. .System runs O. for LED drives only. Accept this mode and the ‘Tools’ programme should work ok. but output relays do not pick up. Where a modem is connected. You will probably need more than the manual specifies. ensure the data for the cards has “Adjustable” Enable rather than “Fixed”.System has had a critical error. The Microlok sees both outputs via the 2 relay coils.Signalling Design of Microlok II Interlockings CRN SC 023 .CRN Engineering Procedure . the system fails.K. A minimum of four should be provided. and more if a larger number of relays is installed. . . and then switch each on progressively. a Null Modem (crossed) cable is required.System works ok with signal lamps disconnected.When a negative pin on a relay output is pulled. With PC Link. Remember to Clear the CPS before attempting to run the system.K.K. but resets when the lamps are pinned up. Currents around 1A can cause problems. . .What cables do I need to connect things together? The laptop when connected to the CPU diagnostic port. The Microlok likes to see the correct lamp current being pulled.5A. © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 54 of 79 Version 2. Go into the ‘Reset’ menu then to ‘PC Link’ mode. The number quoted in the manual should be O. Ensure adequate negative return wires have been wired out of the card. Each output relay must have its own negative pin. and Non-Vital I/O card shows output LED’s O. Multiple output relays may have been looped on the negative side and a common pin used. Where Citect is connected to a CPU communications port. needs a special cable with 9 pin connectors. a standard RS232 (straight through) cable is required. Use the Tools programme to turn off (disable) all the cards. Details of the cable are in the Microlok manual. Check that the output current to the lamp is at least 1.

1 .Signalling Design of Microlok II Interlockings 7 CRN SC 023 Appendix A .Typical Circuits © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED Page 55 of 79 Version 2.CRN Engineering Procedure .

Signalling Design of Microlok II Interlockings © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED CRN SC 023 Page 56 of 79 Version 2.CRN Engineering Procedure .1 .

1 .CRN Engineering Procedure .Signalling Design of Microlok II Interlockings © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED CRN SC 023 Page 57 of 79 Version 2.

Signalling Design of Microlok II Interlockings © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED CRN SC 023 Page 58 of 79 Version 2.CRN Engineering Procedure .1 .

1 .CRN Engineering Procedure .Signalling Design of Microlok II Interlockings © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED CRN SC 023 Page 59 of 79 Version 2.

CRN Engineering Procedure .1 .Signalling Design of Microlok II Interlockings © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED CRN SC 023 Page 60 of 79 Version 2.

Signalling Design of Microlok II Interlockings © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED CRN SC 023 Page 61 of 79 Version 2.1 .CRN Engineering Procedure .

Signalling Design of Microlok II Interlockings © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED CRN SC 023 Page 62 of 79 Version 2.CRN Engineering Procedure .1 .

1 .Signalling Design of Microlok II Interlockings © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED CRN SC 023 Page 63 of 79 Version 2.CRN Engineering Procedure .

1 .CRN Engineering Procedure .Signalling Design of Microlok II Interlockings © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED CRN SC 023 Page 64 of 79 Version 2.

CRN Engineering Procedure - Signalling
Design of Microlok II Interlockings

CRN SC 023

WBS D84M - SINGLE RIGHT HAND

© JHR
Issued March 2015

UNCONTROLLED WHEN PRINTED

Page 65 of 79
Version 2.1

CRN Engineering Procedure - Signalling
Design of Microlok II Interlockings

© JHR
Issued March 2015

UNCONTROLLED WHEN PRINTED

CRN SC 023

Page 66 of 79
Version 2.1

CRN Engineering Procedure - Signalling
Design of Microlok II Interlockings

© JHR
Issued March 2015

UNCONTROLLED WHEN PRINTED

CRN SC 023

Page 67 of 79
Version 2.1

Signalling Design of Microlok II Interlockings © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED CRN SC 023 Page 68 of 79 Version 2.CRN Engineering Procedure .1 .

1 .Signalling Design of Microlok II Interlockings © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED CRN SC 023 Page 69 of 79 Version 2.CRN Engineering Procedure .

Signalling Design of Microlok II Interlockings © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED CRN SC 023 Page 70 of 79 Version 2.1 .CRN Engineering Procedure .

Signalling Design of Microlok II Interlockings © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED CRN SC 023 Page 71 of 79 Version 2.CRN Engineering Procedure .1 .

1 .Signalling Design of Microlok II Interlockings © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED CRN SC 023 Page 72 of 79 Version 2.CRN Engineering Procedure .

1 .CRN Engineering Procedure .Signalling Design of Microlok II Interlockings © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED CRN SC 023 Page 73 of 79 Version 2.

CRN Engineering Procedure .1 .Signalling Design of Microlok II Interlockings © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED CRN SC 023 Page 74 of 79 Version 2.

CRN Engineering Procedure .Signalling Design of Microlok II Interlockings © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED CRN SC 023 Page 75 of 79 Version 2.1 .

CRN Engineering Procedure .1 .Signalling Design of Microlok II Interlockings © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED CRN SC 023 Page 76 of 79 Version 2.

CRN Engineering Procedure .Signalling Design of Microlok II Interlockings © JHR Issued March 2015 UNCONTROLLED WHEN PRINTED CRN SC 023 Page 77 of 79 Version 2.1 .

CRN Engineering Procedure .1 UNCONTROLLED WHEN PRINTED .Signalling Design of Microlok II Interlockings CRN SC 023 © JHR Issued March 2015 Page 78 of 79 Version 2.

1 UNCONTROLLED WHEN PRINTED .Signalling Design of Microlok II Interlockings CRN SC 023 © JHR Issued March 2015 Page 79 of 79 Version 2.CRN Engineering Procedure .