.....question paper

© All Rights Reserved

3 views

.....question paper

© All Rights Reserved

- Flip Flops
- Xilinix Manual
- Coding and Synthesis With Verilog
- Counters _ Electronics Worksheet
- Implementation of Digital Lock Using Vhdl
- A Design Of A Low Power Delay Buffer Using Ring Counter Addressing Schemes
- Exp11 Counters (Part II)
- Basic Digital Logic 1
- 0203csit2
- Lect07 Race
- _Setup and Hold Time Violation_ _ Static Timing Analysis (STA) Basic (Part 3b) _VLSI Concepts
- All Sub Ques
- Plates
- ECE351(2)
- ECAD Lab Manual (ECAD and VLSI Lab)
- 74xx IC's
- 4 bit bcd adder (1)
- Work Sheet 3 Combinational Logic Circuit
- 3-Presentations COE 081 202 Counters and Registers
- SR Flip Flop Design With NOR and NAND Logic Gates

You are on page 1of 8

R07

Set No. 2

SWITCHING THOERY AND LOGIC DESIGN

Common to BME, ICE, E.COMP.E, E.CONT.E, EIE, EEE

Time: 3 hours

Max Marks: 80

Answer any FIVE Questions

All Questions carry equal marks

?????

1. (a) Differentiate between synchronous and asynchronous circuits.

(b) Design a 2 to 4 decoder using NAND gates

[8+8]

2. Draw an ASM chart for a synchronous sequential logic circuit which produces an

output THREE 1s if three or more consecutive 1s follow the last 0 output.

Design the data processing unit and a control unit for implementing the design.

[16]

(a) Conversion from Binary to decimal number

(b) Binary subtraction using 1s complement

(c) Binary subtraction using 2s complement

[16]

(b) Convert D flip flop to T flip flop.

5. Convert the following Mealy machine into a corresponding Moore machine.

PS

NS,Z

X=0 X=1

A C,0

B,0

B

A,1 D,0

C

B,1

A,1

D D,1 C,0

[8+8]

[16]

HIGH if and only if A and C inputs go HIGH. Draw the Truth table. Minimize the

Boolean function using K-map. Draw the circuit diagram.

[16]

7. Implement the following functions in a ROM. Specify the size of ROMs required to

implement the following functions

(a) Full adder

(b) Binary to BCD converter

[16]

8. (a) Convert the following SOP equation into its POS form.

G = XY0 Z + X0 YZ0

1

R07

Set No. 2

A0 C0 + ABC +AC0

?????

8+8]

R07

Set No. 4

SWITCHING THOERY AND LOGIC DESIGN

Common to BME, ICE, E.COMP.E, E.CONT.E, EIE, EEE

Time: 3 hours

Max Marks: 80

Answer any FIVE Questions

All Questions carry equal marks

?????

1. Draw an ASM chart for a synchronous sequential logic circuit which produces an

output THREE 1s if three or more consecutive 1s follow the last 0 output.

Design the data processing unit and a control unit for implementing the design.

[16]

2. (a) Differentiate synchronous and asynchronous circuits

(b) Design a 2 to 4 decoder using NAND gates

[8+8]

3. Implement the following functions in a ROM. Specify the size of ROMs required to

implement the following functions

(a) Full adder

(b) Binary to BCD converter

[16]

HIGH if and only if A and C inputs go HIGH. Draw the Truth table. Minimize the

Boolean function using K-map. Draw the circuit diagram.

[16]

5. Convert the following Mealy machine into a corresponding Moore machine.

PS

NS,Z

X=0 X=1

A C,0

B,0

B

A,1 D,0

C

B,1

A,1

D D,1 C,0

[16]

(a) Conversion from Binary to decimal number

(b) Binary subtraction using 1s complement

(c) Binary subtraction using 2s complement

(d) Conversion from gray to binary number

[16]

(b) Convert D flip flop to T flip flop.

8. (a) Convert the following SOP equation into its POS form.

G = XY0 Z + X0 YZ0

3

[8+8]

R07

Set No. 4

A0 C0 + ABC +AC0

?????

8+8]

R07

Set No. 1

SWITCHING THOERY AND LOGIC DESIGN

Common to BME, ICE, E.COMP.E, E.CONT.E, EIE, EEE

Time: 3 hours

Max Marks: 80

Answer any FIVE Questions

All Questions carry equal marks

?????

1. Design a combinational logic circuit with 4 inputs A, B, C, D. The output Y goes

HIGH if and only if A and C inputs go HIGH. Draw the Truth table. Minimize the

Boolean function using K-map. Draw the circuit diagram.

[16]

2. (a) Convert the following SOP equation into its POS form.

G = XY0 Z + X0 YZ0

(b) Reduce the following Boolean expressions to three literals.

A0 C0 + ABC +AC0

8+8]

(a) Conversion from Binary to decimal number

(b) Binary subtraction using 1s complement

(c) Binary subtraction using 2s complement

(d) Conversion from gray to binary number

[16]

(b) Design a 2 to 4 decoder using NAND gates

5. Convert the following Mealy machine into a corresponding Moore machine.

PS

NS,Z

X=0 X=1

A C,0

B,0

B

A,1 D,0

C

B,1

A,1

D D,1 C,0

[8+8]

[16]

(b) Convert D flip flop to T flip flop.

[8+8]

7. Draw an ASM chart for a synchronous sequential logic circuit which produces an

output THREE 1s if three or more consecutive 1s follow the last 0 output.

Design the data processing unit and a control unit for implementing the design.

[16]

8. Implement the following functions in a ROM. Specify the size of ROMs required to

implement the following functions

(a) Full adder

5

R07

Set No. 1

[16]

?????

R07

Set No. 3

SWITCHING THOERY AND LOGIC DESIGN

Common to BME, ICE, E.COMP.E, E.CONT.E, EIE, EEE

Time: 3 hours

Max Marks: 80

Answer any FIVE Questions

All Questions carry equal marks

?????

1. (a) Differentiate synchronous and asynchronous circuits

(b) Design a 2 to 4 decoder using NAND gates

[8+8]

2. Draw an ASM chart for a synchronous sequential logic circuit which produces an

output THREE 1s if three or more consecutive 1s follow the last 0 output.

Design the data processing unit and a control unit for implementing the design.

[16]

3. Explain the procedure for the following with an example

(a) Conversion from Binary to decimal number

(b) Binary subtraction using 1s complement

(c) Binary subtraction using 2s complement

(d) Conversion from gray to binary number

4. Convert the following Mealy machine into a corresponding Moore machine.

PS

NS,Z

X=0 X=1

A C,0

B,0

B

A,1 D,0

C

B,1

A,1

D D,1 C,0

[16]

[16]

(b) Convert D flip flop to T flip flop.

[8+8]

6. Implement the following functions in a ROM. Specify the size of ROMs required to

implement the following functions

(a) Full adder

(b) Binary to BCD converter

[16]

HIGH if and only if A and C inputs go HIGH. Draw the Truth table. Minimize the

Boolean function using K-map. Draw the circuit diagram.

[16]

8. (a) Convert the following SOP equation into its POS form.

G = XY0 Z + X0 YZ0

7

R07

Set No. 3

A0 C0 + ABC +AC0

?????

8+8]

- Flip FlopsUploaded byGaurav
- Xilinix ManualUploaded bysuarad
- Coding and Synthesis With VerilogUploaded bytrinaths
- Counters _ Electronics WorksheetUploaded bydeepakk_alpine
- Implementation of Digital Lock Using VhdlUploaded byVaibhav Tripathi
- A Design Of A Low Power Delay Buffer Using Ring Counter Addressing SchemesUploaded byeditor_ijtel
- Exp11 Counters (Part II)Uploaded byAbdAllah El Sheikh
- Basic Digital Logic 1Uploaded byCao Cường Nguyễn
- 0203csit2Uploaded byInternational journal of computer science and information Technology (IJCSIT)
- Lect07 RaceUploaded byAmod Aggarwal
- _Setup and Hold Time Violation_ _ Static Timing Analysis (STA) Basic (Part 3b) _VLSI ConceptsUploaded byRaghavendra Mattur
- All Sub QuesUploaded byMohammed Salman Khalander
- PlatesUploaded byCharles Ritter
- ECE351(2)Uploaded byujiee
- ECAD Lab Manual (ECAD and VLSI Lab)Uploaded bySwaminathan Kathirvel
- 74xx IC'sUploaded bykarthikeyan b
- 4 bit bcd adder (1)Uploaded byjitendra jha
- Work Sheet 3 Combinational Logic CircuitUploaded byMehrez Saafi
- 3-Presentations COE 081 202 Counters and RegistersUploaded bykstu1112
- SR Flip Flop Design With NOR and NAND Logic GatesUploaded byunknown
- Latches and Flip-FlopUploaded byJane
- Coding and Synthesis With VerilogUploaded byPawan Pareek
- mg_tutUploaded byHairil Hanif
- 14-SequentialAnalysisUploaded byAhmed Saad
- 80C32Uploaded byAnonymous JR1LSmN0s
- Wint05_exam2Uploaded byBruno Silva
- ee101_dgtl_4.pdfUploaded bySumanth Varma
- App NoteUploaded bySarah Strunk
- Data SheetUploaded byDidit Andhika Subrata
- NPCIL sample question paperUploaded byReky George

- algberaUploaded byVijay Kumar
- Project QuestionsUploaded byVijay Kumar
- SQL QueriesUploaded byAnkit Gupta
- IJVDCUploaded byVijay Kumar
- 30 UnixUploaded bybjsk2020
- paperUploaded byVijay Kumar
- askhareesh.com-PLSQL interview questions - part1.pdfUploaded byVijay Kumar
- intervewUploaded byVijay Kumar
- intervewUploaded byVijay Kumar
- intervewUploaded byVijay Kumar
- intervewUploaded byVijay Kumar
- Frequently used UNIX commands.pdfUploaded byVijay Kumar
- Abstr CtUploaded byVijay Kumar
- ....Quant Mock Test_2Uploaded byVijay Kumar
- 1quantUploaded byVijay Kumar
- Pay ScaleUploaded byVijay Kumar
- iris dipUploaded byVijay Kumar
- The Eyegaze Communication Syste1Uploaded byrahulrv
- Steg No GraphyUploaded byVijay Kumar
- AbstractsUploaded byVijay Kumar
- Signal Lab ManualUploaded byVijay Kumar
- CH5 Slides 001Uploaded byVijay Kumar
- NokiaUploaded byVijay Kumar

- ExceptionUploaded byPetros Xania
- X25650.pdfUploaded byroozbehxox
- Makefile for AIR Project14Uploaded byHoras
- Robocop yUploaded byJason Smith
- 301 to 400 Computer Fundamental MCQ QuestionsUploaded bylayyah2013
- 9100manual ProgramatorUploaded byDorynVarga
- Chapter QuestionsUploaded byChandan Kumar
- Need for Speed UndercoverUploaded byMohit Borakhade
- SAP HANA System High Availability LinuxUploaded byayushjohri
- ucs_vspex_vview53_2k.pdfUploaded byAjaj Abdelmajid
- Shorewall TutorialUploaded byMarco A. Salas
- Arinc653 Annex OverviewUploaded bykrsimha
- Simple Mod Bus Master ManualUploaded bytacho_inc41
- #CENSORED DOX: :#ANONYMOUS: HOW TO - Secure Ur Pc Surf Anonymous BLACKHAT Style!Uploaded byCensored News Now
- Laptop Syllabus With Pictures (1)Uploaded bypopusingh
- LTRT-54004 Mediant E-SBC SIP Trunking for Microsoft Lync 2013 Configuration NoteUploaded bykaz7878
- Adsl Usb ModemUploaded byklulaku
- 03) Working Model of a ComputerUploaded byRuffee Careem
- chainess dump_Mode.pdfUploaded byMamaru Nibret Desyalew
- EE450-Fall2011-HW-5Uploaded byAshish Mehta
- 300 115.Examcollection.premium.exam.164qUploaded byAbdel Rahman Jamil Alkhawaja
- Whats NewUploaded byDebjitDG
- Openstack Install Guide Yum TrunkUploaded bytecnocrate
- Configurable 8-Bit Microcontroller Ip Core as a Basis for Effective System on Chip ImplementationUploaded byPronadeep Bora
- Clive Ward CVUploaded byanon-957287
- J2ME Application ModelUploaded byYufeng Wang
- Rdmplus Getstart JavaUploaded byHarsh Kumar
- ICMP [Compatibility Mode].pdfUploaded byAkash Khyadi
- 2011.ijnm1Uploaded bybhvijaykumarn
- 8085_MicroprocessorUploaded byMohit Manaktala