Introduction Power Semiconductor Applications

Philips Semiconductors
CHAPTER 1
Introduction to Power Semiconductors
1.1 General
1.2 Power MOSFETS
1.3 High Voltage Bipolar Transistors
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Introduction Power Semiconductor Applications
Philips Semiconductors
General
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Introduction Power Semiconductor Applications
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1.1.1 An Introduction To Power Devices
Today’s mains-fed switching applications make use of a
wide variety of active power semiconductor switches. This
chapter considers therange of power devicesonthe market
today, making comparisons both in terms of their operation
and their general areas of application. The P-N diode will
be considered first since this is the basis of all active
switches. This will be followed by a look at both 3 layer and
4 layer switches.
Before looking at the switches let’s briefly consider the
various applications in which they are used. Virtually all
mains fed power applications switch a current through an
inductive load. This is the case even for resonant systems
where the operating point is usually on the "inductive" side
of the resonance curve. The voltage that the switch is
normally required to block is, in the majority of cases, one
or twotimes themaximumrectifiedinput voltagedepending
on the configuration used. Resonant applications are the
exception to this rule with higher voltages being generated
by the circuit. For 110-240 V mains, the required voltage
ratings for the switch can vary from 200 V to 1600 V.
Under normal operating conditions the off-state losses in
the switch are practically zero. For square wave systems,
the on-state losses (occurring during the on-time), are
primarily determinedby the on-state resistance which gives
rise to an on-state voltage drop, V
ON
. The (static) on-state
losses may be calculated from:
At the end of the "ON" time the switch is turned off. The
turn-off current is normally high which gives rise to a loss
dependent on the turn-off properties of the switch. The
process of turn-on will also involve a degree of power loss
so it is important not toneglect the turn-on properties either.
Most applications either involve a high turn-on current or
the current reaching its final value very quickly (high dI/dt).
The total dynamic power loss is proportional to both the
frequency and to the turn-on and turn-off energies.
The total losses are the sum of the on-state and dynamic
losses.
The balance of these losses is primarily determined by the
switch used. If the on-state loss dominates, operating
frequency will have little influence and the maximum
frequency of the device is limited only by its total delay time
(the sum of all its switching times). At the other extreme a
device whose on-state loss is negligible compared with the
switching loss, will be limited in frequency due to the
increasing dynamic losses.
Fig.1 Cross section of a silicon P-N diode
High frequency switching When considering frequency
limitation it is important to realise that the real issue is not
just the frequency, but also the minimum on-time required.
For example, an SMPS working at 100 kHz with an almost
constant output power, will have a pulse on-time t
P
of about
2-5µs. This canbe compared with ahigh performance UPS
working at 10 kHz with low distortion which also requires a
minimum on-time of 2 µs. Since the 10 kHz and 100 kHz
applications considered here, require similar short
on-times, both may be considered high frequency
applications.
Resonant systems have the advantage of relaxing turn-on
or turn-off or both. This however tends to be at the expense
of V-A product of the switch. The relaxed switching
conditions imply that in resonant systems switches can be
used at higher frequencies than in non resonant systems.
When evaluating switches this should be taken into
account.
P
N
CATHODE
ANODE
P
STATIC
· δ.V
ON
.I
ON
(1)
P
DYNAMIC
· f .(E
ON
+ E
OFF
) (2)
P
TOT
· δ.V
ON
.I
ON
+ f .(E
ON
+ E
OFF
) (3)
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Introduction Power Semiconductor Applications
Philips Semiconductors
Fig.2 Field distribution in the N
-
layer
E
HIGH RESISTIVITY
Thickness
E
Thickness
LOW RESITIVITY
E
INTERMEDIATE CASE
Thickness
Case 1 Case 2 Case 3
At higher values of throughput power, the physical size of
circuits increases and as a consequence, the stray
inductances will also tend to increase. Since the required
currents are higher, the energy stored in the stray
inductances rises significantly, which in turn means the
induced peak voltages also rise. As a result such
applications force the use of longer pulse times, to keep
losses down, and protection networks to limit overshoot or
networks to slow down switching speeds. In addition the
useof larger switches will also have consequences interms
of increasing the energy required to turn them on and off
and drive energy is very important.
So, apart from the voltage and current capabilities of
devices, it is necessary to consider static and dynamic
losses, driveenergy, dV/dt, dI/dt andSafeOperating Areas.
The silicon diode
Silicon is the semiconductor material used for all power
switching devices. Lightly doped N
-
silicon is usually taken
as the starting material. The resistance of this material
depends upon its resistivity, thickness and total area.
A resistor as such does not constitute an active switch, this
requires an extra step which is the addition of a P-layer.
The result is a diode of which a cross section is drawn in
Fig.1
The blocking diode
Since all active devices contain a diode it is worth
considering its structure in a little more detail. To achieve
the high blocking voltages required for active power
switches necessitates the presence of a thick N
-
layer. To
withstand a given voltage the N
-
layer must have the right
combination of thickness and resistivity. Some flexibility
exists as to what that combination is allowed to be, the
effects of varying the combination are described below.
Case 1: Wide N
-
layer and low resistivity
Figure 2 gives the field profile in the N
-
layer, assuming the
junction formed with the P layer is at the left. The maximum
field at the P-N junction is limited to 22 kV/cm by the
breakdown properties of the silicon. The field at the other
end is zero. The slope of the line is determined by the
resistivity. The total voltage across the N
-
layer is equal to
the area underneath the curve. Please note that increasing
the thickness of the device would not contribute to its
voltage capability in this instance. This is the normal field
profile when there is another P-layer at the back as in 4
layer devices (described later).
Case 2: Intermediate balance
In this case the higher resistivity material reduces the slope
of the profile. The field at the junction is the same so the
same blocking voltage capability (area under the profile)
can be achieved with a thinner device.
The very steep profile at the right hand side of the profile
indicates the presence of an N
+
layer which often required
to ensure a good electrical contact
Case 3: High resistivity material
With sufficiently high resistivity material a near horizontal
slopetothe electric field is obtained. It isthis scenariowhich
will give rise to the thinnest possible devices for the same
required breakdown voltage. Again an N
+
layer is required
at the back.
An optimum thickness and resistivity exists which will give
thelowest possibleresistancefor agivenvoltagecapability.
Both case 1 (very thick device) and case 3 (high resistivity)
give high resistances, the table belowshows the thickness
and resistivity combinations possible for a 1000 V diode.
R · ρ.
l
A
(4)
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Introduction Power Semiconductor Applications
Philips Semiconductors
The column named RA gives the resistance area product.
(A device thickness of less than 50 µm will never yield
1000 V and the same goes for a resistivity of less than
26 Ωcm.) The first specification is for the thinnest device
possibleand the last oneis for the thickest device, (required
when a P layer is present at the back). It can be seen that
thelowest resistanceis obtainedwith an intermediate value
of resistivity and material thickness.
Thickness Resistivity RA Comments
(µm) (Ωcm) Ωcm
2
50 80 0.400 case 3
60 34 0.204
65 30 0.195
70 27 0.189 min. R
75 26 0.195
80 26 0.208
90 26 0.234
100 26 0.260 case 1
To summarise, a designer of high voltage devices has only
a limited choice of material resistivity and thickness with
which to work. The lowest series resistance is obtained for
a material thickness and resistivity intermediate between
the possible extremes. This solution is the optimum for all
majority carrier devices such as the PowerMOSFET and
the J-FET where the on-resistance is uniquely defined by
the series resistance. Other devices make use of charge
storage effects to lower their on-state voltage.
Consequently to optimise switching performance in these
devices the best choice will be the thinnest layer such that
the volume of stored charge is kept to a minimum. Finally
asmentioned earlier, the design of a 4layer device requires
the thickest, low resistivity solution.
The forward biased diode
When a diode is forward biased, a forward current will flow.
Internallythis current will have twocomponents: anelectron
current which flows from the N layer to the P layer and a
hole current in the other direction. Both currents will
generate a charge in the opposite layer (indicated with Q
P
andQ
N
in Fig.3). The highest dopedregion will deliver most
of the current and generate most of the charge. Thus in a
P
+
N
-
diode the current will primarily be made up of holes
flowing from P to N and there will be a significant volume
of hole charge in the N
-
layer. This point is important when
discussing active devices: whenever a diode is forward
biased (suchas abase-emitter diode) therewill be a charge
stored in the lowest doped region.
Fig. 3 Diode in forward conduction
The exact volume of charge that will result is dependent
amongst other things on the minority carrier lifetime, τ.
Using platinum or gold doping or by irradiation techniques
the value of τ can be decreased. This has the effect of
reducing the volume of stored charge and causing it to
disappear more quickly at turn-off. A side effect is that the
resistivity will increase slightly.
Three Layer devices
The threebasic designs, which formthe basis for all derived
3layer devices, are given in Fig.4. It should be emphasised
herethat the discussionis restricted tohigh voltage devices
only as indicated in the first section. This means that all
relevant deviceswill haveavertical structure, characterised
by a wide N
-
-layer.
The figure shows how a three layer device can be formed
by adding an N type layer to the P-N diode structure. Two
back to back P-N diodes thus form the basis of the device,
where the P layer provides a means to control the current
when the device is in the on-state.
There are three ways to use this P-layer as a control
terminal. The first is to feed current into the terminal itself.
The current through the main terminals is nowproportional
to the drive current. This device is called a High Voltage
Transistor or HVT.
The second one is to have openings in the P-layer and
permit the main current to flow between them. When
reverse biasing the gate-source, a field is generated which
blocks the opening and pinches off the main current. This
device is known as the J-FET (junction FET) or SIT (Static
Induction Transistor).
P
CATHODE
ANODE
I
p
I
N
Q
P
Q
N
N
N
-
+
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Introduction Power Semiconductor Applications
Philips Semiconductors
Fig.4 The three basic three layer devices
P
N
EMITTER
COLLECTOR
-
N
BASE
P
N
SOURCE
DRAIN
-
N
GATE
P
N
SOURCE
DRAIN
-
N
GATE
BIPOLAR TRANSISTOR J-FET (SIT) MOS
N N N
The third version has an electrode (gate) placed very close
to the P-layer. The voltage on this gate pushes away the
holes in the P-area and attracts electrons to the surface
beneath the gate. A channel is thus formed between the
main terminals so current can flow. The well known name
for this device is MOS transistor.
In practice however, devices bear little resemblance to the
constructions of Fig.4. In virtually all cases a planar
construction is chosen i.e. the construction is such that one
main terminal (emitter or source) and the drive contact are
on the surface of the device. Each of the devices will now
be considered in some more detail.
The High Voltage Transistor (HVT)
The High Voltage Transistor uses a positive base current
to control the main collector current. The relation is:
I
C
= H
FE
* I
B
. Thebase driveforwardbiasesthebase emitter
P-N junction and charge (holes and electrons) will pass
through it. Now the base of a transistor is so thin that the
most of the electrons do not flow to the base but into the
collector - giving rise to a collector current. As explained
previously, the ratio between the holes and electrons
depend on the doping. So by correctly doping the base
emitter junction, the electron current can be made much
larger than the hole current, which means that I
C
can be
much larger than I
B
.
Whenenoughbase driveis providedit is possibletoforward
bias the base-collector P-N junction also. This has a
significant impact on the resistance of the N
-
layer; holes
nowinjected fromthe P type base constitute stored charge
causing a substantial reduction in on-state resistance,
much lower than predicted by equation 4. Under these
conditionsthecollector isaneffectiveextensionof thebase.
Unfortunately the base current required to maintain this
Fig.5 The HVT
condition causes the current gain to drop. For this reason
one cannot use a HVT at a very high current density
because then the gain would become impractically low.
The on-state voltage of an HVT will be considerably lower
than for a MOS or J-FET. This is its main advantage, but
the resulting charge stored in the N
-
layer has to be
delivered and also to be removed. This takes time and the
speed of a bipolar transistor is therefore not optimal. To
improve speed requires optimisation of a fine emitter
structure in the form of fingers or cells.
Both at turn-on and turn-off considerable losses may occur
unless care is taken to optimise drive conditions. At turn-on
a short peak base current is normally required. At turn-off
a negative base current is required and negative drive has
to be provided.
P
COLLECTOR
B B B E E
N
N
-
+
N+ N+
I
B
Electrons
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Introduction Power Semiconductor Applications
Philips Semiconductors
A serious limitation of the HVT is the occurrence of second
breakdownduring switchoff. The current contracts towards
the middle of the emitter fingers and the current density can
become very high. The RBSOAR (Reverse Bias Safe
Operating Area) graph specifies where the device can be
used safely. Device damage may result if the device is not
properly used and one normally needs a snubber (dV/dt
network) to protect the device. The price of such a snubber
is normally in the order of the price of the transistor itself.
In resonant applications it is possible to use the resonant
properties of the circuit to have a slow dV/dt.
So, the bipolar transistor has the advantage of a very low
forward voltage drop, at the cost of lower speed, a
considerable energy is required to drive it and there are
also limitations in the RBSOAR.
The J-FET.
The J-FET (Junction Field Effect Transistor) has a direct
resistance between the Source and the Drain via the
opening in the P-layer. When the gate-source voltage is
zero the device is on. Its on-resistance is determined by the
resistance of the silicon and no charge is present to make
the resistance lower as in the case of the bipolar transistor.
When a negative voltage is applied between Gate and
Source, a depletion layer is formed which pinches off the
current path. So, the current through the switch is
determined by the voltage on the gate. The drive energy is
low, it consists mainly of the charging and discharging of
the gate-source diode capacitance. This sort of device is
normally very fast.
Fig.6 The J-FET
Its main difficulty is the opening in the P-layer. In order to
speed up performance and increase current density, it is
necessary to make a number of openings and this implies
fine geometries which are difficult to manufacture. A
solution exists in having the P-layer effectively on the
surface, basically a diffused grid as shown in Fig.6.
Unfortunately the voltages now required to turn the device
off may be very large: it is not uncommon that a voltage of
25 V negative is needed. This is a major disadvantage
which, when combined with its "normally-on" property and
the difficulty to manufacture, means that this type of device
is not in mass production.
The MOS transistor.
The MOS (Metal Oxide Semiconductor) transistor is
normally off: a positive voltage is required to induce a
channel in the P-layer. When a positive voltage is applied
to the gate, electrons are attracted to the surface beneath
the gate area. In this way an "inverted" N-type layer is
forced in the P-material providing a current path between
drain and source.
Fig.7 The MOS transistor
Modern technology allows a planar structure with very
narrow cells as shown in Fig.7. The properties are quite
like the J-FET with the exception that the charge is now
across the (normally very thin) gate oxide. Charging and
discharging the gate oxide capacitance requires drive
currents when turning on and off. Switching speeds can
be controlled by controlling the amount of drive charge
during the switching interval. Unlike the J-FET it does not
require anegative voltagealthough anegative voltage may
help switch the device off quicker.
The MOSFET is the preferred device for higher frequency
switching sinceit combines fast speed, easy drive and wide
commercial availability.
DRAIN
S G
N
N
-
+
S
N+ N+
P P
DRAIN
G G G S S
P P P
N+ N+
N
N
-
+
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Introduction Power Semiconductor Applications
Philips Semiconductors
Refinements to the basic structure
A number of techniques are possible to improve upon
behaviour of the basic device.
First, the use of finer geometries can give lower on-state
voltages, speed up devices and extend their energy
handling capabilities. This has led to improved
"Generation 3" devices for bipolars and to lower R
DS(ON)
for
PowerMOS. Secondly, killing the lifetime τ in the device
can also yield improvements. For bipolar devices, this
positively effects the switching times. The gain, however,
will drop, and this sets a maximumto the amount of lifetime
killing. For MOS a lower value for τ yields the so-called
FREDFETs, with an intrinsic diode fast enough for many
half bridge applications such as in AC Motor Controllers.
The penalty here is that R
DS(ON)
is adversely effected
(slightly). Total losses, however, are decreased
considerably.
Four layer devices
The three basic designs from the previous section can be
extended with a P
+
-layer at the back, thereby generating
three basic Four Layer Devices. The addition of this extra
layer creates a PNP transistor from the P
+
-N
-
-P-layers. In
all casesthe 3layer NPNdevice will nowdeliver an electron
current into the back P
+
-layer which acts as an emitter. The
PNP transistor will thus become active which results in a
hole current flowing fromthe P
+
-layer into the high resistive
region. This in its turn will lead to a hole charge in the high
resistive region which lowers the on-state voltage
considerably, as outlined above for High Voltage
Transistors. Again, the penalty is in the switching times
which will increase.
All the devices with an added P
+
-layer at the back will inject
holes into the N
-
-layer. Since the P
+
-layer is much heavier
doped than the N
-
-layer, this hole current will be the major
contributor to the main current. This means that the charge
in the N
-
-layer, especially near the N
-
-P
+
-junction, will be
large. Under normal operation the hole current will be large
enough to influence the injection of electrons from the top
N
+
-layer. This results in extra electron current being
injected fromthe top, leading to extra hole current fromthe
back etc. This situation is represented in the schematic of
Fig.8.
An important point is latching. This happens when the
internal currents are such that we are not able to turn off
the device using the control electrode. The only way to turn
it off is by externally removing the current from the device.
The switching behaviour of all these devices is affected by
the behaviour of the PNP: as long as a current is flowing
through the device, the back will inject holes into the
N
-
-layer. This leads to switching tails which contribute
heavily to switching losses. The tail is strongly affected by
thelifetime τ andby the application of negative drive current
when possible. As previously explained, adjustment of the
lifetimeaffects the on-state voltage. Carefully adjusting the
lifetime τ will balance the on-state losses with the switching
losses.
All four layer devices showthis trade-off between switching
losses and on-state losses. When minimising switching
losses, the devices are optimised for high frequency
applications. When the on-state losses are lowest the
current density is normally highest, but the device is only
useful at low frequencies. So two variants of the four layer
device generally exist. In some cases intermediate speeds
are also useful as in the case of very high power GTOs.
The Thyristor
A thyristor (or SCR, Silicon Controlled Rectifier) is
essentially an HVT with an added P
+
-layer. The resulting
P
-
-N
-
-P
+
transistor is on when the whole device is on and
provides enough base current to the N
+
-P-N
-
transistor to
stay on. So after an initial kick-on, no further drive energy
is required.
Fig.8 Thyristor
The classical thyristor is thus a latching device. Its
construction is normally not very fine and as a result the
gate contact is too far away from the centre of the active
area to be able to switch it off. Also the current density is
muchhigher thaninabipolar transistor. The switchingtimes
however are very long. Its turn-on is hampered by its
structure since it takes quite a while for the whole crystal
to become active. This seriously limits its dI/dt.
Once a thyristor is on it will only turn-off after having zero
current for a fewmicroseconds. This is done by temporarily
forcing the current via a so-called commutation circuit.
P
ANODE
G G C
P
+
N
-
N
+
Ip2
Ip1
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Introduction Power Semiconductor Applications
Philips Semiconductors
The charge in the device originates from two sources: The
standard NPN transistor structure injects holes in the
N
-
-layer (I
P1
inFig.8) andthe PNPtransistor injects a charge
fromthe back (I
P2
in Fig.8). Therefore the total charge is big
and switching performance is very poor. Due to its slow
switching a normal thyristor is only suitable up to a fewkHz.
A major variation on the thyristor is the GTO(Gate Turn Off
Thyristor). This is a thyristor where the structure has been
tailoredtogivebetter speedbytechniquessuchas accurate
lifetime killing, fine finger or cell structures and "anode
shorts" (short circuiting P
+
and N
-
at the back in order to
decreasethecurrent gainof thePNPtransistor). As aresult,
theproduct of thegainof bothNPNandPNPisjust sufficient
to keep the GTO conductive. A negative gate current is
enough to sink the hole current from the PNP and turn the
device off.
Fig.9 The GTO
A GTO shows much improved switching behaviour but still
has the tail as described above. Lower power applications,
especially resonant systems, are particularly attractive for
the GTO because the turn-off losses are virtually zero.
The SITh
The SITh (Static Induction Thyristor) sometimes also
referredto as FCT(Field Controlled Thyristor) is essentially
a J-FET with an added P
+
back layer. In contrast to the
standard thyristor, charge is normally only injected fromthe
back, so the total amount of charge is limited. However, a
positive gate drive is possible which will reduce on-state
resistance.
Active extraction of charge via the gate contact is possible
and switching speeds may be reduced considerably by
applying an appropriate negative drive as in the case of an
HVT. As for theSITthe technological complexity isasevere
Fig.10 The SITh
drawback, as is its negative drive requirements.
Consequently mass production of this device is not
available yet.
The IGBT
An IGBT (Insulated Gate Bipolar Transistor) is an MOS
transistor with P
+
at the back. Charge is injected from the
back only, which limits the total amount of charge. Active
charge extraction is not possible, so the carrier lifetime τ
should be chosen carefully, since that determines the
switching losses. Again two ranges are available with both
fast and slow IGBTs.
Fig.11 The IGBT
ANODE
G G G C C
P P P
N+ N+
N
P
-
+
P
ANODE
G G G C C
N
P
-
+
N+ N+
N
+
N
+
COLLECTOR
E G
N
-
E
N+ N+
P P
P
+
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Introduction Power Semiconductor Applications
Philips Semiconductors
The speed of the fast IGBT is somewhat better than that of
a GTO because a similar technology is used to optimise
the IGBT but only the back P
+
-layer is responsible for the
charge.
The IGBT is gaining rapidly in popularity since its
manufacturing is similar to producing PowerMOS and an
increasing market availability exists. Although the latching
of IGBTswasseen asaproblem, modernoptimiseddevices
don’t suffer from latch-up in practical conditions.
Refinements to the basic structure
The refinements outlined for 3 layer devices also apply to
4 layer structures. In addition to these, an N
+
-layer may be
inserted between the P
+
and N
-
-layer. Without such a layer
the designer is limited in choice of starting material to Case
3 as explained in the diode section. Adding the extra
N
+
-layer allows another combination of resistivity and
thickness to be used, improving device performance. An
example of this is the ASCR, the Asymmetric SCR, which
is much faster than normal thyristors. The reverse blocking
capability, however, is now reduced to a value of 10-20 V.
Comparison of the Basic Devices.
It is important to consider the properties of devices
mentioned when choosing the optimum switch for a
particular application. Table 2 gives a survey of the
essential device properties of devices capable of
withstanding 1000 V. IGBTs have been classed in terms
of fast and slow devices, however only the fast GTO and
slow thyristor are represented. The fast devices are
optimised for speed, the slow devices are optimised for On
voltage.
Comments
Thistableisvalidfor 1000 Vdevices. Lower voltagedevices
will always perform better, higher voltage devices are
worse.
A dot means an average value in between "+" and "-"
The "(--)" for a thyristor means a "--" in cases where forced
commutation is used; in case of natural commutation it is
"+"
Most figures are for reference only: in exceptional cases
better performance has been achieved, but the figures
quoted represent the state of the art.
HVT J-FET MOS THY GTO IGBT IGBT Unit
slow fast
V(ON) 1 10 5 1.5 3 2 4 V
Positive Drive Requirement - + + + + + + + = Simple to
implement
Turn-Off requirement - - + (--) - + + + = Simple to
implement
Drive circuit complexity - . + (-) . + + - = complex
Technology Complexity + . . + - - - - = complex
Device Protection - . + + - - - + = Simple to
implement
Delay time (ts, tq) 2 0.1 0.1 5 1 2 0.5 µs
Switching Losses . ++ ++ -- - - . + = good
Current Density 50 12 20 200 100 50 50 A/cm
2
Max dv/dt (Vin = 0) 3 20 10 0.5 1.5 3 10 V/ns
dI/dt 1 10 10 1 0.3 10 10 A/ns
Vmax 1500 1000 1000 5000 4000 1000 1000 V
Imax 1000 10 100 5000 3000 400 400 A
Over Current factor 5 3 5 15 10 3 3
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Philips Semiconductors
Merged devices
Merged devices are the class of devices composed of two
or more of the above mentioned basic types. They don’t
offer any breakthrough in device performance. This is
understandable since the basic properties of the discussed
devices are not or are hardly effected. They may be
beneficial for the user though, primarily because they may
result in lower positive and/or negative drive requirements.
Darlingtons and BiMOS
A darlington consists of two bipolar transistors. The emitter
current of the first (the driver) forms the base current of the
output transistor. The advantages of darlingtons may be
summarised as follows. A darlington has a higher gain than
asingle transistor. It also switches faster because the input
transistor desaturates the output transistor and lower
switching losses are the result. However, the resulting
V
CE(sat)
is higher. The main issue, especially for higher
powers is the savings in drive energy. This means that
darlingtons can be used at considerably higher output
powers than standard transistors. Modern darlingtons in
high power packages can be used in 20 kHz motor drives
and power supplies.
A BiMOS consists of a MOS driver and a bipolar output
transistor. The positive drive is the same as MOS but
turn-off is generally not so good. Adding a"speed-up" diode
coupled with some negative drive improves things.
Fig.12 The MCT
MCT
MCT stands for MOS Controlled Thyristor. This device is
effectively a GTO with narrow tolerances, plus a P-MOS
transistor between gate and source (P
+
-N-P MOS, the left
hand gate in Fig.12) and an extra N-MOS to turn it on, the
N-P-N
-
-MOS shown underneath the right hand gate.
Wherethe GTOwouldlike tobeswitchedoff with anegative
gate, the internal GTO in an MCT can turn off by short
circuiting its gate-cathode, due to its fine structure. Its drive
therefore is like a MOS transistor and its behaviour similar
to a GTO. Looking closely at the device it is obvious that
aGTOusingsimilar finegeometries with asuitable external
drive can always perform better, at the cost of some drive
circuitry. The only plus point seems to be its ease of drive.
Application areas of the various devices
The following section gives an indication of where the
various devices are best placed in terms of applications. It
is possible for circuit designers to use various tricks to
integrate devices and systems in innovative manners,
applying devices far outside their ’normal’ operating
conditions. As an example, it is generally agreedthat above
100 kHz bipolars are too difficult to use. However, a
450 kHz converter using bipolars has been already
described in the literature.
As far as the maximum frequency is concerned a number
of arguments must be taken into account.
First the delay times, either occurring at turn-on or at
turn-off, will limit the maximum operating frequency. A
reasonable rule of thumb for this is f
MAX
= 3 / t
DELAY
. (There
is a danger here for confusion: switching times tend to
depend heavily on circuit conditions, drive of the device and
on current density. This may lead to a very optimistic or
pessimistic expectation and care should be taken to
consider reasonable conditions.)
Another factor istheswitchinglosseswhichareproportional
to the frequency. These power losses may be influenced
by optimising the drive or by the addition of external circuits
such as dV/dt or dI/dt networks. Alternatively the heatsink
size may be increased or one may choose to operate
devices at a lower current density in order to decrease
power losses. It isclear that thisargument isvery subjective.
A third point is manufacturability. The use of fine structures
for example, which improves switching performance, is
possible only for small silicon chip sizes: larger chips with
very fine MOS-like structures will suffer fromunacceptable
lowfactory yields. Therefore high power systems requiring
large chip areas are bound to be made with less fine
structures and will consequently be slower.
The operating current density of the device will influence
its physical size. A lowcurrent density device aimed at high
power systems would need a large outline which tends to
beexpensive. Largeoutlines alsoincreasethephysical size
of the circuit, which leads to bigger parasitic inductances
and associated problems.
ANODE
N
P
-
+
N
G C G
P+ P+
N N +
P
13
Introduction Power Semiconductor Applications
Philips Semiconductors
Fig.13 Comparison of device operating regions
10 MHz
1 MHz
100 kHz
10 kHz
1 kHz
100 Hz
100VA 1kVA 10kVA 100kVA 1MVA 10MVA 100MVA
DARLINGTONS HVT
R
E
S
O
N
A
N
T

S
Y
S
T
E
M
S
S
Q
U
A
R
E

W
A
V
E

S
Y
S
T
E
M
S
THYRISTOR
(fast)
(fast)-IGBT-(slow)
SITr SITh
MOS
GTO (slow)
High power systems will, because of the mechanical size,
be restricted in speed as explained earlier in the text . This
coincides well with the previously mentioned slower
character of higher power devices.
Last but not least it is necessary to take the application
topology into account. Resonant systems allow the use of
considerablyhigher frequencies, sinceswitchinglossesare
minimised. Square wave systems cause more losses in the
devices and thus restrict the maximumfrequency. To make
a comparison of devices and provide insight into which
powers are realistic for which devices we have to take all
the above mentioned criteria into account.
Figure 13 shows the optimumworking areas of the various
switching devices as a function of switchable power and
frequency. The switchable power is defined as I
AV
times
V
MAX
as seen by the device.
As an example, darlingtons will work at powers up to 1MVA
i.e. 1000 V devices will switch 1000 A. The frequency is
thenlimited to 2.5 kHz. At lower powers higher frequencies
can be achieved however above 50 kHz, darlingtons are
not expected to be used. One should use this table only as
guidance; usingspecial circuit techniques, darlingtonshave
actuallybeen used at higher frequencies. Clearly operation
at lower powers and frequencies is always possible.
Conclusions
The starting material for active devices aimed at high
voltageswitching aremade on siliconof which theminimum
resistivity and thickness are limited. This essentially
determines device performance, since all active switches
incorporate such a layer. Optimisation can be performed
for either minimum thickness, as required in the case of
HVTs, or for minimumresistance, as required for MOS and
J-FETs. The thickest variation(lowest resistivity) isrequired
in the case of some 4 layer devices.
Basically three ways exist to control current through the
devices: feeding a base current into a P-layer (transistor),
14
Introduction Power Semiconductor Applications
Philips Semiconductors
using a voltage to pinch-off the current through openings
in the P-layer (J-FET) and by applying a voltage onto a gate
which inverts the underlying P-layer (MOS).
The HVT is severely limited in operating frequency due to
its stored hole charge, but this at the same time allows a
greater current density and a lower on-state voltage. It also
requires more drive energy than both MOS and J-FET.
When we add a P
+
-layer at the back of the three basic three
layer devices we make three basic four layer devices. The
P
+
-layer produces a PNP transistor at the back which
exhibits hole storage. This leads to much improved current
densities and lower on-state losses, at the cost of switching
speed. The four layer devices can be optimised for low
on-state losses, in which case the switching will be poor,
or for fast switching, in which case the on-state voltage will
be high.
The properties of all six derived basic devices are
determined to a large extent by the design of the high
resistive area and can be optimised by applying
technological features in the devices such as lifetime killing
and fine geometries.
Resonant systems allowdevices to be used at much higher
frequencies due to the lower switching losses and the
minimum on-times which may be longer, compared to
square wave switching systems. Figure 13 gives the
expected maximum frequency and switching power for the
discusseddevices. Thedifferencefor squarewavesystems
and resonant systems is about a factor of 10.
15
Introduction Power Semiconductor Applications
Philips Semiconductors
Power MOSFET
17
Introduction Power Semiconductor Applications
Philips Semiconductors
1.2.1 PowerMOS Introduction
Device structure and fabrication
The idea of a vertical channel MOSFET has been known
since the 1930s but it was not until the mid 1970s that the
technology of diffusion, ion implantation and material
treatment had reached the level necessary to produce
DMOS on a commercial scale. The vertical diffusion
technique uses technology more commonly associated
with the manufacture of large scale integrated circuits than
with traditional power devices. Figure 1(a) shows the
vertical double implanted (DIMOS) channel structurewhich
is the basis for all Philips power MOSFET devices.
An N-channel PowerMOS transistor is fabricated on an
N
+
substrate with a drain metallization applied to its’
underside. Above the N
+
substrate is an N
-
epi layer, the
thickness and resistivity of which depends on the required
drain-source breakdown voltage. The channel structure,
formed froma double implant in to the surface epi material,
is laid down in a cellular pattern such that many thousands
of cells go to make a single transistor. The N
+
polysilicon
gatewhich is embeddedin an isolating silicon dioxidelayer,
is a single structure which runs between the cells across
the entire active region of the device. The source
metallization also covers the entire structure and thus
parallels all the individual transistor cells on the chip. The
layout of a typical lowvoltage chip is shown in Fig.1(b). The
polysilicon gate is contacted by bonding to the defined pad
area while the source wires are bonded directly to the
aluminium over the cell array. The back of the chip is
metallizedwith atriplelayer of titanium/nickel/silver andthis
enables the drain connection to be formed usinga standard
alloy bond process.
The active part of the device consists of many cells
connected in parallel to give a high current handling
capability wherethe current flowisvertical through the chip.
Cell density is determined by photolithographic tolerance
requirements in defining windows in the polysilicon and
gate-source oxide and also by the width of the polysilicon
track between adjacent cells. The optimum value for
polysilicon track width and hence cell density varies as a
function of device drain-source voltage rating, this is
explained in more detail further in the section. Typical cell
densitiesare 1.6 million cells per square inchfor lowvoltage
types and 350,000 cells per square inch for high voltage
types. The cell array is surrounded by an edge termination
structure to control the surface electric field distribution in
the device off-state.
Fig.1(a) Power MOSFET cell structure.
19
Introduction Power Semiconductor Applications
Philips Semiconductors
Fig.1(b) Plan view of a low voltage Power MOS chip
20
Introduction Power Semiconductor Applications
Philips Semiconductors
A cross-section through a single cell of the array is shown
in Fig.2. The channel length is approximately 1.5 microns
and is defined by the difference in the sideways diffusion
of the N
+
source and the P-body. Both these diffusions are
auto-aligned to the edge of the polysilicon gate during the
fabrication process. All diffusions are formed by ion
implantation followed by high temperature anneal/drive-in
to give good parameter reproducibility. The gate is
electrically isolated from the silicon by an 800 Angstrom
layer of gate oxide (for standard types, 500 Angstrom for
Logiclevel andfromthe overlyingaluminiumby athick layer
of phosphorus doped oxide. Windows are defined in the
latter oxide layer to enable the aluminium layer to contact
the N
+
source and the P
+
diffusion in the centre of each cell.
The P
+
diffusion provides a low resistance connection
between the P
-
body and ground potential, thus inhibiting
turn-on of the inherent parasitic NPN bipolar structure.
Fig.2 Cross-section of a single cell.
Device operation
Current flow in an enhancement mode power MOSFET is
controlled by the voltage applied between the gate and
source terminals. The P
-
body isolates the source anddrain
regions and forms two P-N junctions connected
back-to-back. With both the gate and source at zero volts
there is no source-drain current flow and the drain sits at
the positive supply voltage. The only current which can flow
from source to drain is the reverse leakage current.
As the gate voltage is gradually made more positive with
respect to the source, holes are repelled and a depleted
region of silicon is formed in the P
-
body below the
silicon-gate oxide interface. The silicon is now in a
’depleted’ state, but there is still no significant current flow
between the source and drain.
When the gate voltage is further increased a very thin layer
of electrons is formed at the interface between the P
-
body
and the gate oxide. This conductive N-type channel
enhanced by the positive gate-source voltage, nowpermits
current to flow from drain to source. The silicon in the P
-
body is referred to as being in an ’inverted’ state. A slight
increase in gate voltage will result in a very significant
increase in drain current and a corresponding rapid
decreasein drain voltage, assuminga normal resistive load
is present.
Eventually the drain current will be limited by the combined
resistances of the load resistor and the R
DS(ON)
of the
MOSFET. The MOSFET resistance reaches a minimum
when V
GS
= +10 volts (assuming a standard type).
Subsequently reducing the gate voltage to zero volts
reverses the above sequence of events. There are no
stored charge effects since power MOSFETS are majority
carrier devices.
Power MOSFET parameters
Threshold voltage
The threshold voltage is normally measured by connecting
thegate tothe drain andthen determiningthe voltagewhich
must be applied across the devices to achieve a drain
current of 1.0 mA. This method is simple to implement and
provides a ready indication of the point at which channel
inversion occurs in the device.
The P
-
body is formed by the implantation of boron through
the tapered edge of the polysilicon followed by an anneal
anddrive-in. The main factors controlling threshold voltage
are gate oxide thickness and peak surface concentration
in the channel, which is determined by the P-body implant
dose. To allow for slight process variation a window is
usually defined which is 2.1 to 4.0 volts for standard types
and 1.0 to 2.0 volts for logic level types.
Positive charges in the gate oxide, for example due to
sodium, can cause the threshold voltage to drift. To
minimise this effect it is essential that the gate oxide is
grown under ultra clean conditions. In addition the
polysilicon gate and phosphorus doped oxide layer provide
a good barrier to mobile ions such as sodium and thus help
to ensure good threshold voltage stability.
Drain-source on-state resistance
The overall drain-source resistance, R
DS(ON)
, of a power
MOSFET is composed of several elements, as shown in
Fig.3.
The relative contribution from each of the elements varies
with the drain-source voltage rating. For low voltage
devices the channel resistance is very important while for
N- EPI Layer
N+ Substrate
DRAIN
SOURCE
P- P-
P+
N+ N+
GATE
20 um
21
Introduction Power Semiconductor Applications
Philips Semiconductors
Fig.3 Power MOSFET components of R
DS(ON)
.
the high voltage devices the resistivity and thickness of the
epitaxial layer dominates. The properties of the various
resistive components will now be discussed:
Channel. The unit channel resistance is determined by the
channel length, gate oxide thickness, carrier mobility,
threshold voltage, and the actual gate voltage applied to
thedevice. The channel resistance for agiven gatevoltage
can be significantly reduced by lowering the thickness of
the gateoxide. This approach is used tofabricate the Logic
Level MOSFET transistors and enables a similar value
R
DS(ON)
to be achieved with only 5 volts applied to the gate.
Of course, the gate-source voltage rating must be reduced
to allow for the lower dielectric breakdown of the thinner
oxide layer.
The overall channel resistance of a device is inversely
proportional to channel width, determined by the total
periphery of the cell windows. Channel width is over
200 cmfor a 20 mm
2
lowvoltagechip. The overall channel
resistance can be significantly reduced by going to higher
cell densities, since the cell periphery per unit area is
reduced.
Accumulationlayer. The silicon interfaceunder the centre
of the gate track is ’accumulated’ when the gate is biased
abovethethresholdvoltage. Thisprovides alowresistance
path for the electrons when they leave the channel, prior to
entering the bulk silicon. This effect makes a significant
contribution towards reducing the overall R
DS(ON)
.
Parasitic JFET. After leaving the accumulation layer the
electrons flow vertically down between the cells into the
bulk of the silicon. Associated with each P-Njunction there
is a depletion region which, in the case of the high voltage
devices, extends several micronsintotheNepitaxial region,
even under zerobias conditions. Consequently the current
path for the electrons is restricted by this parasitic JFET
structure. The resistance of the JFET structure can be
reduced byincreasing the polysilicontrack width. However
this reduces the cell density. The need for compromise
leads to an optimumvalue for the polysilicon track width for
a given drain-source voltage rating. Since the zero-bias
depletion width is greater for low doped material, then a
wider polysilicon track width is used for high voltage chip
designs.
Spreading resistance. As the electrons move further into
the bulk of the silicon they are able to spread sideways and
flow under the cells. Eventually paths overlap under the
centre of each cell.
Epitaxial layer. The drain-source voltage rating
requirements determine the resistivity and thickness of the
epitaxial layer. For high voltage devices the resistance of
the epitaxial layer dominates the overall value of R
DS(ON)
.
Substrate. The resistance of the N
+
substrate is only
significant in the case of 50 V devices.
Wires and leads. In a completed device the wire and lead
resistances contribute a few milli-ohms to the overall
resistance.
For all the above components the actual level of resistance
is a function of the mobility of the current carrier. Since the
mobility of holes is much lower than that of electrons the
resistance of P-Channel MOSFETs is significantly higher
than that of N-Channel devices. For this reason P-Channel
types tend to be unattractive for most applications.
Drain-source breakdown voltage
The voltage blocking junction in the PowerMOS transistor
is formedbetween the P-body diffusion andthe N
-
epi layer.
For any P-N junction there exists a maximum theoretical
breakdown voltage, which is dependent on doping profiles
and material thickness. For the case of the N-channel
PowerMOS transistor nearly all the blocking voltage is
supported by the N
-
epi layer. The ability of the N
-
epi layer
tosupport voltageisafunctionof its resistivityandthickness
where both must increase to accommodate a higher
breakdown voltage. This has obvious consequences in
terms of drain-source resistance with R
DS(ON)
being
approximately proportional to B
VDSS
2.5
. It is therefore
important to design PowerMOS devices such that the
breakdown voltageis as close as possible to the theoretical
maximum otherwise thicker, higher resistivity material has
to be used. Computer models are used to investigate the
influence of cell design and layout on breakdown voltage.
Since these factors also influence the ’on-state’ and
switching performances a degree of compromise is
necessary.
To achieve a high percentage of the theoretical breakdown
maximum it is necessary to build edge structures around
the activearea of the device. Theseare designed to reduce
the electric fields which would otherwise be higher in these
regions and cause premature breakdown.
22
Introduction Power Semiconductor Applications
Philips Semiconductors
For low voltage devices this structure consists of a field
plate design, Fig.4. The plates reduce the electric field
intensity at the corner of the P
+
guard ring which surrounds
the active cell area, and spread the field laterally along the
surface of the device. The polysilicon gate is extended to
form the first field plate, whilst the aluminium source
metallization forms the second plate. The polysilicon
terminationplate which is shorted to the drain in the corners
of the chip (not shown on the diagram) operates as a
channel stopper. This prevents any accumulation of
positive charge at the surface of the epi layer and thus
improves stability. Aluminium overlaps the termination
plate and provides a complete electrostatic screen against
any external ionic charges, hence ensuring good stability
of blocking performance.
Fig.4 Field plate structure for low voltage devices.
For high voltage devices aset of floatingP
+
rings, see Fig.5,
is used to control the electric field distribution around the
device periphery. The number of rings in the structure
depends on the voltage rating of the device, eight rings are
used for a 1000 volt type such as the BUK456-1000A. A
three dimensional computer model enables the optimum
ringspacing tobedetermined sothat each ringexperiences
a similar field intensity as the structure approaches
avalanche breakdown. The rings are passivated with
polydox which acts as an electrostatic screen and prevents
external ionic charges inverting the lightly doped N
-
interface to form P
-
channels between the rings. The
polydox is coated with layers of silicon nitride and
phosphorus doped oxide.
All types have a final passivation layer of plasma nitride,
which acts as a further barrier to mobile charge and also
gives anti-scratch protection to the top surface.
Fig.5 Ring structure for high voltage devices.
Electrical characteristics
The DC characteristic
If a dc voltage source is connected across the drain and
source terminals of an N channel enhancement mode
MOSFET, with the positive terminal connected to the drain,
thefollowing characteristicscan beobserved. With the gate
to source voltage held below the threshold level negligible
current will flow when sweeping the drain source voltage
positive from zero. If the gate to source voltage is taken
above the threshold level, increasing the drain to source
voltage will cause current to flow in the drain. This current
will increase as the drain-source voltage is increased up to
a point known as the pinch off voltage. Increasing the
drain-source terminal voltage above this value will not
produce any significant increase in drain current.
The pinch off voltage arises from a rapid increase in
resistance which for any particular MOSFET will depend
on the combination of gate voltage and drain current. In its
simplest form, pinch off will occur when the ohmic drop
across the channel region directly beneath the gate
becomes comparable to the gate to source voltage. Any
further increase in drain current would now reduce the net
voltage across the gate oxide to a level which is no longer
sufficient to induce a channel. The channel is thus pinched
off at its edge furthest from the source N
+
(see Fig.6).
Atypical set of output characteristics is shown in Fig.7. The
two regions of operation either side of the pinch off voltage
can be seen clearly. The region at voltages lower than the
pinch off value is usually known as the ohmic region.
Saturation region is the term used to describe that part of
the characteristic above the pinch-off voltage. (NB This
definition of saturation is different to that used for bipolar
devices.)
N- EPI Layer
P+
N+
P-
LOPOX
LPCVD NITRIDE
POLYDOX
P+
P+ P+ P+
Source
Guard
Ring
Floating Guard Rings
N- EPI Layer
N+ Substrate
P+
P-
N+
Guard Ring
Polysilicon
Source
Metallization
Gate Ring Source Ring Polysilicon
Termination
Plate
(Source)
23
Introduction Power Semiconductor Applications
Philips Semiconductors
Fig.6 Pinch off in a Power MOSFET
Fig.7 A typical dc characteristic for an N-channel
enhancement mode MOSFET.
The switching characteristics
The switching characteristics of a Power MOSFET are
determined largely by the various capacitances inherent in
its’ structure. These are shown in Fig.8.
To turn the device on and off the capacitances have to be
charged and discharged, the rate at which this can be
achieved is dependent on the impedance and the current
sinking/sourcing capability of the drive circuit. Since it is
only the majority carriers that are involved in the conduction
process, MOSFETs do not suffer from the same storage
time problems which limit bipolar devices where minority
carriers have to be removed during turn-off. For most
applications therefore the switching times of the Power
Fig.8. The internal capacitances of a Power MOSFET.
MOSFET are limited only by the drive circuit and can be
very fast. Temperature has only a small effect on device
capacitances therefore switching times are independent of
temperature.
In Fig.9 typical gate-source and drain-source voltages for
a MOSFET switching current through a resistive load are
shown. The gate source capacitance needs to be charged
up to a threshold voltage of about 3 V before the MOSFET
begins toturn on. The time constant for this is C
GS
(R
DR
+R
G
)
and the time taken is called the turn-on delay time (t
D(ON)
).
As V
GS
starts to exceed the threshold voltage the MOSFET
begins to turn on and V
DS
begins to fall. C
GD
now needs to
be discharged as well as C
GS
being charged so the time
constant is increased and the gradient of V
GS
is reduced.
As V
DS
becomes less than V
GS
the value of C
GD
increases
sharply since it is depletion dependent. A plateau thus
occurs in the V
GS
characteristic as the drive current goes
into the charging of C
GD
.
VGS
10 V
Ohmic Drop
7 V
3 V Net Gate to Channel
10 V Gate to Channel
Polysilicon Gate
Gate Oxide
P-
Source
Channel
N-
Pinch Off
Id
+
D
S
G
Cgs
Cgd
Cds
0
VDS / V
ID / A BUK4y8-800A
20
15
10
5
0
4
5
6
4.5
5.5
10
10 20 30
VGS / V =
24
Introduction Power Semiconductor Applications
Philips Semiconductors
Fig.9. The switching waveforms for a MOSFET.
0 0.2 0.4 0.6 0.8 1 1.2
50
40
30
20
10
0
Time (Microseconds)
V
o
l
t
a
g
e

(
V
o
l
t
s
)
Drain-Source Voltage
Gate-Source Voltage
Turn-on Turn-off
When V
DS
has collapsed V
GS
continues to rise as overdrive
is applied. Gate overdrive is necessary to reduce the
on-resistanceof the MOSFETandthereby keep power loss
to a minimum.
To turn the MOSFET off the overdrive has first to be
removed. The charging path for C
GD
and C
DS
nowcontains
the load resistor (R
L
) and so the turn-off time will be
generally longer than the turn-on time.
The Safe Operating Area
Unlike bipolar devices Power MOSFETs do not suffer from
second breakdown phenomena when operated within their
voltagerating. Essentially therefore the safe operating area
of a Power MOSFET is determined only by the power
necessary to raise its junction temperature to the rated
maximum of 150 ˚C or 175 ˚C (which T
JMAX
depends on
package and voltage rating). Whether a MOSFET is being
operated safely with respect to thermal stress can thus be
determined directly from knowledge of the power function
applied and the thermal impedance characteristics.
Asafeoperatingareacalculatedassumingamountingbase
temperature of 25 ˚C is shown in Fig.10 for a BUK438-800
device. This plot shows the constant power curves for a
variety of pulse durations ranging from dc to 10 µs. These
curves represent the power levels which will raise T
j
up to
the maximum rating. Clearly for mounting base
temperatures higher than 25 ˚C the safe operating area is
smaller. In addition it is not usually desirable to operate the
25
Introduction Power Semiconductor Applications
Philips Semiconductors
device at its T
JMAX
rating. These factors can be taken into
account quite simply where maximum power capability for
a particular application is calculated from:
T
j
is the desired operating junction temperature (must be
less than T
jmax
)
T
mb
is the mounting base temperature
Z
th
is the thermal impedance taken from the data curves
The safe operating areais boundedby a peak pulse current
limit and a maximum voltage. The peak pulse current is
based on a current above which internal connections may
be damaged. The maximumvoltage is an upper limit above
which the device may go into avalanche breakdown.
Fig.10. The Safe Operating Area of the BUK438-800.
In a real application the case temperature will be greater
than 25 ˚C because of the finite thermal impedance of
practical heatsinks. Alsoajunctiontemperatureof between
80 ˚C and 125 ˚C would be preferable since this improves
reliability. If a nominal junction temperature of 80 ˚C
instead of 150 ˚C is used then the ability of the MOSFET
to withstand current spikes is improved.
Causes of Power Loss
There are four main causes of power dissipation in
MOSFETs.
Conductionlosses - The conduction losses (P
C
) are given
by equation (1).
It is important to note that the on-resistance of the MOSFET
when it is operated in the Ohmic region is dependent on
the junction temperature. On-resistance roughly doubles
between 25 ˚C and 150 ˚C, the exact characteristics are
shown in the data sheets for each device.
Switching losses - When a MOSFET is turned on or off it
carries a large current and sustains a large voltage at the
same time. There is therefore a large power dissipation
during the switching interval. Switching losses are
negligible at low frequencies but are dominant at high
frequencies. The cross-over frequency depends on the
circuit configuration. For reasons explained in the section
on switching characteristics, a MOSFET usually turns off
more slowly than it turns on so the losses at turn-off will be
larger thanat turn-on. Switchinglosses arevery dependent
on circuit configuration since the turn-off time is affected by
the load impedance.
Turn-off losses may be reduced by the use of snubber
components connectedacross the MOSFETwhich limit the
rate of rise of voltage. Inductors can beconnected in series
withthe MOSFETtolimit the rate of rise of current at turn-on
and reduce turn-on losses. With resonant loads switching
can take place at zero crossing of voltage or current so
switching losses are very much reduced.
Diode losses - These losses only occur in circuits which
make use of the antiparallel diode inherent in the MOSFET
structure. A good approximation to the dissipation in the
diode is the product of the diode voltage drop which is
typically less than 1.5 V and the average current carried by
the diode. Diode conduction can be useful in such circuits
as pulse width modulated circuits used for motor control, in
somestepper motor drive circuits and in voltage fed circuits
feeding a series resonant load.
Gate losses - The losses in the gate are given in equation
2whereR
G
istheinternal gateresistance, R
DR
istheexternal
drive resistance, V
GSD
is the gate drive voltage and C
IP
is
the capacitance seen at the input to the gate of the
MOSFET.
The input capacitance varies greatly with the gate drain
voltage so the expression in equation 3 is more useful.
(3)
Where Q
G
is the peak gate charge.
Parallel Operation
If power requirements exceed those of available devices
thenincreasedpower levelscan beachieved by parallelling
devices. Parallelling of devices is made easier using
P
max
·
(T
j
− T
mb
)
Z
th
10 1000
VDS / V
ID / A
100
10
1
0.1
100 us
1 ms
10 ms
R
D
S
(
O
N
)

=

V
D
S
/
I
D
100 ms
DC
10 us
tp =
BUK438-800
100
A
B
P
G
·
C
IP
.V
GSD
2
.f .R
G
(R
G
+ R
DR
)
(2)
P
G
·
Q
G
.V
GSD
.f .R
G
(R
G
+ R
DR
)
(3)
P
C
· I
D
2
.R
DS(ON)
(1)
26
Introduction Power Semiconductor Applications
Philips Semiconductors
MOSFETs because they have a positive temperature
coefficient of resistance. If oneparallelledMOSFETcarries
more current than the others it becomes hotter. This
causes the on-resistance of that particular device to
become greater than that of the others and so the current
in it reduces. This mechanism opposes thermal runaway
in one of the devices. The positive temperature coefficient
also helps to prevent hot spots within the MOSFET itself.
Applications of Power MOSFETs
Power MOSFETs are ideally suited for use in many
applications, some of which are listed below. Further
information on the major applications is presented in
subsequent chapters.
Chapter 2: Switched mode power supplies (SMPS)
Chapter 3: Variable speed motor control.
Chapter 5: Automotive switching applications.
Conclusions
It can be seen that the operation of the Power MOSFET is
relatively easy to understand. The advantages of fast
switching times, ease of parallelling and low drive power
requirements make the device attractive for use in many
applications.
27
Introduction Power Semiconductor Applications
Philips Semiconductors
1.2.2 Understanding Power MOSFET Switching Behaviour
Power MOSFETs are well known for their ease of drive and
fast switching behaviour. Being majority carrier devices
means they are free of the charge storage effects which
inhibit the switching performance of bipolar products. How
fast a Power MOSFET will switch is determined by the
speed at which its internal capacitances can be charged
and discharged by the drive circuit. MOSFET switching
times are often quoted as part of the device data however
as an indication as to the true switching capability of the
device, these figures are largely irrelevant. The quoted
values are only a snapshot showing what will be achieved
under the stated conditions.
This report sets out to explain the switching characteristics
of Power MOSFETs. It will consider the main features of
the switching cycle distinguishing between what is device
determinant and what can be controlled by the drive circuit.
Therequirements for the drivecircuit are discussedinterms
of the energy that it must supply as well as the currents it
is required to deliver. Finally, how the drive circuit
influences switching performance, in terms of switching
times, dV/dt and dI/dt will be reviewed.
Voltage dependent capacitance
The switching characteristics of the Power MOSFET are
determined by its capacitances. These capacitances are
not fixed but are a function of the relative voltages between
each of the terminals. To fully appreciate Power MOSFET
switching, it is necessary to understand what gives rise to
this voltage dependency.
Parallel plate capacitance is expressed by the well known
equation
where ’a’ is the area of the plates, d is the separating
distance and Ε is the permittivity of the insulating material
between them. For a parallel plate capacitor, the plates are
surfaces on which charge accumulation / depletion occurs
in response to achange in the voltageapplied across them.
In a semiconductor, static charge accumulation / depletion
can occur either across a PN junction or at semiconductor
interfaces either side of a separating oxide layer.
i) P-N junction capacitance
The voltage supporting capability of most power
semiconductors is provided by a reverse biased P-N
junction. The voltageis supportedeither side of the junction
by a region of charge which is exposed by the applied
voltage. (Usually referred to as the depletion region
because it is depleted of majority carriers.) Fig.1 shows
how the electric field varies across a typical P-N
-
junction
for a fixed dc voltage. The shaded area beneath the curve
must be equal to the applied voltage. The electric field
gradient is fixed, independent of the applied voltage,
according to the concentration of exposed charge. (This is
equal to the background doping concentration used during
device manufacture.) A slight increase in voltage above
this dclevel will requirean extensionof thedepletion region,
and hence more charge to be exposed at its edges, this is
illustrated in Fig.1. Conversely a slight reduction in voltage
will cause the depletion region to contract with a removal
of exposed charge at its edge. Superimposing a small ac
signal on the dc voltage thus causes charge to be added
andsubtractedat either side of the depletion regionof width
d1. The effective capacitance per unit area is
Since the depletion regionwidth is voltage dependent it can
be seen from Fig.1 that if the dc bias is raised to say V2,
the junction capacitance becomes
Junction capacitance is thus dependent on applied voltage
with an inverse relationship.
Fig.1 Voltage dependence of a PN junction
capacitance
ii) Oxide capacitance
Fig.2 shows two semiconductor layers separated by an
insulating oxide. In this case the surface layer is polysilicon
(representative of the PowerMOS gate structure) and the
lower layer is a P-type substrate. Applying a negative
voltagetotheupper layer withrespect tothelower will cause
positive charge accumulation at the surface of the P-doped
C1 ·
Ε
d1
2
C2 ·
Ε
d2
3
E
x
d1
d2
V1
V2
N type silicon
P type silicon
C · Ε
a
d
1
29
Introduction Power Semiconductor Applications
Philips Semiconductors
material (positively charged holes of the P material are
attracted by the negative voltage). Any changes in this
applied voltage will cause a corresponding change in the
accumulation layer charge. The capacitance per unit area
is thus
where t = oxide thickness
Applyingapositivevoltagetothe gatewill causeadepletion
layer to form beneath the oxide, (ie the positively charged
holes of the P-material are repelled by the positive voltage).
The capacitance will nowdecrease with increasing positive
gate voltage as a result of widening of the depletion layer.
Increasing the voltage beyond a certain point results in a
process known as inversion; electrons pulled into the
conduction band by the electric field accumulate at the
surface of the P-type semiconductor. (The voltageat which
this occurs is the threshold voltage of the power MOSFET.)
Once the inversion layer forms, the depletion layer width
will not increase with additional dc bias andthe capacitance
is thus at its minimum value. (NB the electron charge
accumulation at the inversion layer cannot follow a high
frequency ac signal in the structure of Fig.2, so high
frequency capacitance is still determined by the depletion
layer width.) The solid line of Fig.3 represents the
capacitance-voltage characteristic of an MOS capacitor.
Fig.2 Oxide capacitance
In a power MOSFET the solid line is not actually observed;
the formation of the inversion layer in the P-type material
allows electrons to move fromthe neighbouring N
+
-source,
the inversion layer can therefore respond to a high
frequency gate signal and the capacitance returns to its
maximum value, dashed line of Fig.3.
Fig.3 C-V plot for MOS capacitance
Power MOSFET capacitances
Fig.4 Parasitic capacitance model
The circuit model of Fig.4 illustrates the parasitic
capacitances of the Power MOSFET. Most PowerMOS
data sheets do not refer to these components but to input
capacitance Ciss, output capacitance Coss and feedback
capacitance Crss. The data sheet capacitances relate to
the primary parasitic capacitances of Fig.4 as follows:
Ciss: Parallel combination of Cgs and Cgd
Coss: Parallel combination of Cds and Cgd
Crss: Equivalent to Cgd
Fig.5 shows the cross section of a power MOSFET cell
indicatingwheretheparasiticcapacitances occur internally.
Cox
C
Bias Voltage
(Polysilicon to P-type silicon)
Cox ·
Ε
t
4
Cgd
Cds
Cgs
G
S
D
t
oxide
P type silicon
Polysilicon
30
Introduction Power Semiconductor Applications
Philips Semiconductors
Fig.5 Cross section of a single PowerMOS cell showing
internal capacitance
ThecapacitancebetweendrainandsourceisaP-Njunction
capacitance, varying in accordance with the width of the
depletion layer, which in turn depends on the voltage being
supported by the device. The gate source capacitance
consists of the three components, CgsN
+
, CgsPand CgsM.
Of these CgsPis across the oxide which will vary according
to the applied gate source voltage as described above.
Of particular interest is the feedback capacitance Cgd. It
is this capacitance which plays a dominant role during
switching and which is also the most voltage dependent.
Cgd is essentially two capacitors in series such that
CgsN+
CgsM
Oxide
Polysilicon
N+
P-
P
N-
N+
Metalization
Source
Drain
Gate
Cgdbulk
Cgdox
CgsP
Cds Depletion Layer
1
Cgd
·
1
Cgdox
+
1
Cgdbulk
5
Fig.6 How Cgd is affected by voltage
Oxide
Polysilicon
N+
P-
P
N-
N+
Metalization
Source
Drain
Gate
Depletion Layer Widths
Area of Oxide
Capacitance Exposed
for Voltages V1 & V2
For Three Applied Voltages
Width for Cgdbulk
at Voltage V3
V3
V2
V1
31
Introduction Power Semiconductor Applications
Philips Semiconductors
Fig.6illustrateshowthis capacitanceisaffectedbythedrain
to gate voltage. With a large voltage drain to gate, Cgdbulk
is very small due to the wide depletion region and thus
maintains Cgd at a low value. As the voltage is reduced
the depletion region shrinks until eventually the oxide
semiconductor interface is exposed. This occurs as Vdg
approaches 0 V. Cgdox now dominates Cgd. As Vdg is
further reduced the drain will become negative with respect
to the gate (normal on-state condition) an increasing area
of the oxide-semiconductor interface is exposed and an
accumulation layer forms at the semiconductor surface.
Thenowlargearea of exposedoxideresults inalarge value
for Cgdox and hence Cgd. Fig.7 shows Cgd plotted as a
function of drain to gate voltage. This illustrates the almost
step increase in capacitance at the point where Vgs = Vgd.
Fig.7 How Cgd varies with drain to gate voltage
Charging cycle - The Gate Charge
Oscillogram
The switching cycle of a power MOSFET can be clearly
observed by applying a constant current to the gate and
using a constant current source as the load, Fig.8. In this
circuit the MOSFET is turned on by feeding a constant
current of 1 mA on to the gate, conversely the device is
turned off by extracting a constant current of 1 mAfromthe
gate. The gate and drain voltages with respect to source
can be monitored on an oscilloscope as a function of time.
Since Q = it, a 1 µsec period equates to 1 nc of charge
applied to the gate. The gate source voltage can thus be
plotted as a function of charge on the gate. Fig.9 shows
such a plot for the turn-on of a BUK555-100A, also shown
is the drain to source voltage. This gate voltage plot shows
the characteristic shape which results from charging of the
power MOSFETs input capacitance. This shape arises as
follows: (NB the following analysis uses the two circuit
models of Fig.10 to represent a MOSFET operating in the
active region (a) and the ohmic region (b). In the active
region the MOSFET is a constant current source where the
current isafunctionof thegate-sourcevoltage. Inthe ohmic
region the MOSFET is in effect just a resistance.)
Fig.8 Gate charge circuit
At time, t0 (Fig.9), the gate drive is activated. Current flows
into the gate as indicated in Fig.11(a), charging both Cgs
and Cgd. After a short period the threshold voltage is
reached and current begins to rise in the MOSFET. The
equivalent circuit is now as shown in Fig.11(b). The drain
sourcevoltage remains at the supply level as long as id < I0
and the free wheeling diode D is conducting.
Fig.9 Gate charge plot for a BUK555-100A (Logic Level
FET)
Vdd
Vdg 0
Cdg
0 10 20 30 40
26
24
22
20
18
16
14
12
10
8
6
4
2
0
(V)
(us)
(1us = 1 nc for Vgs plot)
Vds
Vgs
BUK555-100A
(@ Id = 25 A)
t0 t1 t2
32
Introduction Power Semiconductor Applications
Philips Semiconductors
The current in the MOSFET continues to rise until id = I0,
since the device is still in its active region, the gate voltage
becomes clampedat this point, (t1). The entire gate current
nowflows through Cgd causing the drain-source voltage to
drop as Cgd is discharged, Fig.11(c). The rate at which
Vds falls is given by:
As Vdg approaches zero, Cgd starts to increase
dramatically, reaching its maximum as Vdg becomes
negative. dVds/dt is now greatly reduced giving rise to the
voltage tail.
Once the drain-source voltage has completed its drop to
the on-state value of I0.R
DS(ON)
, (point t2), the gate source
voltage becomes unclamped and continues to rise,
Fig.11(d). (NB dVgs/dQ in regions 1 and 3 indicates the
input capacitance values.)
Fig.10 Equivalent circuits for a Power MOSFET during
switching
G
D
S
Cgd
Cgs
id = f(Vgs)
G
D
S
Cgd
Cgs
Rds(on)
(a)
(b)
dVds
dt
·
dVdg
dt
·
ig
Cgd
6
Fig.11 Charging the parasitic capacitance during turn-on
Vdd
Cgd
Cgs
Io
(a) Vdd
Cgd
Cgs
id = f(Vgs)
Io
(b)
Vdd
Cgd
Cgs
id = f(Vgs)
Io
(c)
Vdd
Cgd
Cgs
Rds(on)
Io
(d)
33
Introduction Power Semiconductor Applications
Philips Semiconductors
The gate charge oscillogram can be found in the data for
all Philips PowerMOS devices. This plot can be used to
determine the required average gate drive current for a
particular switching speed. The speed is set by how fast
the charge is supplied to the MOSFET.
Energy consumed by the switching event
In the majority of applications the power MOSFET will be
driven not from a constant current source but via a fixed
gate drive impedance froma voltage source. Fig.13 shows
thevoltageonavoltageindependent capacitor asafunction
of charge. The area beneath the charge vs voltage curve
equals the stored energy (E = Q.V/2). The area above the
charge vs voltage curve (bounded by the supply voltage)
istheamount of energy dissipatedduringthe chargingcycle
from a fixed voltage source. The total energy delivered by
the supply is therefore Q.V, where 1/2 Q.V is stored on the
capacitor to be dissipated during the discharge phase.
Fig.12 Gate charging cycle
t0 t1 t2 t3 t4 t5 t6
1a 2a 3a
1b 2b
3b
4a
4b
Vgg
Vdd
O
u
t
p
u
t

C
a
p
a
c
i
t
a
n
c
e
34
Introduction Power Semiconductor Applications
Philips Semiconductors
Although the voltage vs charge relationship for the
MOSFETs gate is not linear, energy loss is easily identified.
The following discussion assumes a simple drive circuit
consisting of a voltage source and drive resistance.
Fromt0 to t1 energy is stored in the gate capacitance which
is equal to the area of region 1a. Since this charge has
fallen through a voltage Vgg - Vgs(t), the area of region 1b
represents the energy dissipated in the drive resistance
during its delivery. Between t1 and t2 all charge enters
Cgd, the area of region 2a represents the energy stored in
Cgdwhile 2b againcorresponds with the energy dissipation
in the drive resistor. Finally, between t2 and t3 additional
energy is stored by the input capacitance equal to the area
of region 3a.
Fig.13 Energy stored on a capacitor
Thetotal energy dissipated inthedrive resistanceat turn-on
is therefore equal to the area 1b + 2b + 3b. The
corresponding energy stored on the input capacitance is
1a + 2a + 3a, this energy will be dissipated in the drive
resistance at turn-off. The total energy expended by the
gate drive for the switching cycle is Q.Vgg.
As well as energy expended by the drive circuit, aswitching
cycle will also require energy to be expended by the drain
circuit due to the charging and discharging of Cgd and Cds
between the supply rail and V
DS(ON)
. Moving from t5 to t6
the drain side of Cgd is charged fromIo.R
DS(ON)
to Vdd. The
drain circuit must therefore supply sufficient current for this
charging event. The total charge requirement is given by
the plateau region, Q6 - Q5. The area 4a (Fig.12) under
the drain-source voltage curve represents the energy
stored by the drain circuit on Cgd during turn-on. Region
4b represents the corresponding energy delivered to the
load during this period. The energy consumed from the
drain supply to charge and discharge Cgd over one
switching cycle is thus given by:
(The energy stored on Cgd during turn-off is dissipated
internallyintheMOSFETduringturn-on.) Additional energy
is also stored on Cds during turn-off which again is
dissipated in the MOSFET at turn-on.
The energy lost by both the gate and drain supplies in the
charging and discharging of the capacitances is very small
over 1 cycle; Fig.9 indicates 40 nc is required to raise the
gate voltage to 10 V, delivered from a 10 V supply this
equates to 400 nJ; to charge Cgd to 80 V from an 80 V
supply will consume 12 nc x 80 V = 1.4 µJ. Only as
switching frequencies approach 1 MHz will this energy loss
start to become significant. (NB these losses only apply to
square wave switching, the case for resonant switching is
some-what different.)
Switching performance
1) Turn-on
The parameters likely to be of most importance during the
turn-on phase are,
turn-on time
turn-on loss
peak dV/dt
peak dI/dt.
Turn-on time is simply a matter of howquickly the specified
charge can be applied to the gate. The average current
that must be supplied over the turn-on period is
For repetitive switching the average current requirement of
the drive is
where f = frequency of the input signal
Turn-on loss occurs during the initial phase when current
flows in the MOSFET while the drain source voltage is still
high. To minimise this loss, a necessary requirement of
high frequency circuits, requires the turn-on time to be as
small aspossible. Toachievefast switchingthe drivecircuit
must be able to supply the initial peak current, given by
equation 10.
Voltage
Charge
Stored Energy
Supply Voltage
I
on
·
Q
t
on
8
I · Q.f 9
W
DD
· (Q
6
− Q
5
).(V
DD
− V
DS(ON)
) 7
35
Introduction Power Semiconductor Applications
Philips Semiconductors
Fig.14 Bridge Circuit
One of the main problems associated with very fast
switching MOSFETs is the high rates of change in voltage
and current. High values of dV/dt can couple through
parasitic capacitances to give unwanted noise on signal
lines. Similarly ahigh dI/dt may react with circuit inductance
togive problematic transients andovershoot voltages inthe
power circuit. dI/dt is controlled by the time taken to charge
the input capacitance up to the plateau voltage, while dV/dt
isgoverned by therate at which the plateau regionismoved
through.
Particular care is required regarding dV/dt when switching
in bridge circuits, (Fig.14). The free wheeling diode will
have associated with it a reverse recovery current. When
the opposing MOSFET switches on, the drain current rises
beyond the load current value Io to a value Io + Irr.
Consequently Vgs increases beyond Vgt(Io) to Vgt(Io + Irr)
as shown in Fig.15. Once the diode has recovered there
is arapid decrease in Vgs to Vgt(Io) and this rapid decrease
provides additional current to Cgd on top of that being
supplied by the gate drive. This in turn causes Vdg and
Vds to decrease very rapidly during this recovery period.
The dV/dt in this period is determined by the recovery
properties of the diode in relation to the dI/dt imposed upon
it by the turn-on of the MOSFET, (reducing dI/dt will reduce
this dV/dt, however it is best to use soft recovery diodes).
Fig.15 Gate charging cycle for a bridge circuit
ii) Turn-off
The parameters of most importance during the turn-off
phase are,
turn-off time
turn-off loss
peak dVds/dt
peak dId/dt.
Turn-off of a power MOSFET is more or less the inverse of
the turn-on process. The main difference is that the
charging current for Cgd during turn-off must flow through
both the gate circuit impedance and the load impedance.
A high load impedance will thus slow down the turn-off
speed.
The speed at which the plateau region is moved through
determines the voltage rise time. In most applications the
charging current for Cgd will be limited by the gate drive
circuitry. The chargingcurrent, assumingnonegativedrive,
is simply
and the length of the plateau region will be
T1
T2
D1
D2
Load
Vdd
0
Vdd
0
0
Vgt(Io)
Vgt(Io + Irr) Gate Source Voltage
Drain Source Voltage
MOSFET Current
0
Io
Io + Irr
Diode Current
0
Io
Irr
t
I
pk
·
V
GG
R
g
10
dVds
dt
·
ig
Cgd
·
V
GG
− V
GT
R
G
.Cgd
11
i ·
Vgt
R
G
12
tp ·
Q.R
G
Vgt
13
36
Introduction Power Semiconductor Applications
Philips Semiconductors
The implications for low threshold (Logic Level) MOSFETs
are clear fromthe above equations. The lower value of Vgt
will mean aslower turn-off for agivengateimpedance when
compared to an equivalent standard threshold device.
Equivalent switching therefore requires a lower drive
impedance to be used.
Conclusions
In theory the speed of a power MOSFET is limited only by
the parasitic inductances of its internal bond wires. The
speed is essentially determined by how fast the internal
capacitances can be charged and discharged by the drive
circuit. Switching speeds quoted in data should be treated
with caution since they only reflect performance for one
particular drive condition. The gate charge plot is a more
useful way of looking at switching capability since it
indicates how much charge needs to be supplied by the
drive to turn the device on. How fast that charge should be
applieddepends on the application andcircuit performance
requirements.
37
Introduction Power Semiconductor Applications
Philips Semiconductors
1.2.3 Power MOSFET Drive Circuits
MOSFETs are being increasingly used in many switching
applications because of their fast switching times and low
drive power requirements. The fast switching times can
easily be realised by driving MOSFETs with relatively
simple drive circuits. The following paragraphs outline the
requirementsof MOSFETdrivecircuits andpresent various
circuit examples. Alook at the special requirements of very
fast switching circuits is also presented, this can be found
in the latter part of this article.
The requirements of the drive circuit
The switching of a MOSFET involves the charging and
discharging of the capacitance between the gate and
source terminals. This capacitance is related to the size of
the MOSFET chip used typically about 1-2 nF. A
gate-source voltage of 6V is usually sufficient to turn a
standard MOSFET fully on. However further increases in
gate-to-source voltage are usually employed to reduce the
MOSFETs on-resistance. Therefore for switching times of
about 50 ns, applying a 10 V gate drive voltage to a
MOSFET with a 2 nF gate-source capacitance would
require the drive circuit to sink and source peak currents of
about 0.5 A. However it is only necessary to carry this
current during the switching intervals.
The gate drive power requirements are given in equation
(1)
where Q
G
is the peak gate charge, V
GS
is the peak gate
source voltage and f is the switching frequency.
In circuits which use a bridge configuration, the gate
terminalsof the MOSFETsin thecircuit need tofloat relative
to each other. The gate drive circuitry then needs to
incorporatesomeisolation. Theimpedanceof thegatedrive
circuit should not be so large that there is a possibility of
dV/dt turn on. dV/dt turn on canbe causedby rapidchanges
of drain to source voltage. The charging current for the
gate-drain capacitance C
GD
flows through the gate drive
circuit. This charging current can cause a voltage drop
across the gate drive impedance large enough to turn the
MOSFET on.
Non-isolated drive circuits
MOSFETs can be driven directly from a CMOS logic IC as
shown in Fig.1.
Fig.1 A very simple drive circuit utilizing a standard
CMOS IC
Faster switching speeds can be achieved by parallelling
CMOS hex inverting (4049) or non-inverting (4050) buffers
as shown in Fig.2.
Fig.2 Driving Philips PowerMOS with 6 parallelled
buffered inverters.
A push pull circuit can also be used as shown in Fig.3.
Theconnections betweenthe drivecircuit andthe MOSFET
should be kept as short as possible and twisted together if
the shortest switching times are required. If both the drive
circuit and the terminals of the MOSFET are on the same
PCB, then the inductance of tracks, between the drive
transistors and the terminals of the MOSFETs, should be
kept as small as possible. This is necessary to reduce the
impedance of the drive circuit in order to reduce the
switching times and lessen the susceptibility of the circuit
4011
4049
0 V
15 V
P
G
· Q
G
.V
GS
.f 1
39
Introduction Power Semiconductor Applications
Philips Semiconductors
Fig.3 A drive circuit using a two transistor push pull
circuit.
to dV/dt turn-on of the MOSFET. Attention to layout also
improves the immunity to spurious switching by
interference.
One of the advantages of MOSFETs is that their switching
times can be easily controlled. For example it may be
required tolimit the rate of change of drain current to reduce
overshoot on the drain source voltage waveform. The
overshoot may be caused by switching current in parasitic
lead or transformer leakage inductance. The slower
switching can be achieved by increasing the value of the
gate drive resistor.
The supply rails should be decoupled near to fast switching
elements such as the push-pull transistors in Fig.3. An
electrolytic capacitor in parallel with aceramic capacitor are
recommended since the electrolytic capacitor will not be a
low enough impedance to the fast edges of the MOSFET
drive pulse.
Isolated drive circuits
Some circuits demand that the gate and source terminals
of MOSFETs are floating with respect to those of other
MOSFETs in the circuit. Isolated drive to these MOSFETs
can be provided in the following way:
(a) Opto-isolators.
A drive circuit using an opto-isolator is shown in Fig.4.
A diode in the primary side of the opto-isolator emits
photons when it is forward biased. These photons impinge
on the base region of a transistor in the secondary side.
This causes photogeneration of carriers sufficient to satisfy
the base requirement for turn-on. In this way the
opto-isolator provides isolation between the primary and
secondary of the opto-isolator. An isolated supply is
required for the circuitry on the secondary side of the
opto-isolator. This supply can be derived, in some cases,
fromthe drain-to-source voltageacrossthe MOSFETbeing
driven as shown in Fig.5. This is made possible by the low
drive power requirements of MOSFETs.
Fig.4. An isolated drive circuit using an opto-isolator.
4049
0 V
15 V
Opto-Isolator
5 V
40
Introduction Power Semiconductor Applications
Philips Semiconductors
Fig.5. An opto-isolated drive circuit with the isolated power supply for the secondary derived from the drain source
voltage of the MOSFET.
4049
0 V
15 V
Opto-Isolator
5 V
Some opto-isolators incorporate an internal screen to
improve the common mode transient immunity. Values as
high as 1000 V/µs are quoted for common mode rejection
which is equivalent to rejecting a 300V peak-to-peak
sinewave.
The faster opto-isolators work off a maximum collector
voltage on the secondary side of 5V so some form of level
shifting may be required.
(b) Pulse transformers.
A circuit using a pulse transformer for isolation is shown in
Fig.6(a).
When T2 switches on, voltageis applied across the primary
of the pulse transformer. The current through T2 consists
of the sum of the gate drive current for T1 and the
magnetising current of the pulse transformer. From the
waveforms of current and voltage around the circuit shown
in Fig.6(b), it can be seen that after the turn off of T2 the
voltage across it rises to V
D
+ V
Z
, where V
Z
is the voltage
across the zener diode Z
D
. The zener voltage V
Z
applied
across the pulse transformer causes the flux in the core to
be reset. Thus the net volt second area across the pulse
transformer is zero over a switching cycle. The minimum
number of turns on the primary is given by equation (2).
where B is the maximum flux density, A
e
is the effective
cross sectional area of the core and t is the time that T2 is
on for.
The circuit in Fig.6(a) is best suited for fixed duty cycle
operation. The zener diode has to be large enough so that
the flux in the core will be reset during operation with the
maximum duty cycle. For any duty cycle less than the
maximum there will be a period when the voltage across
the secondary is zero as shown in Fig.7.
In Fig.8 a capacitor is used to block the dc components of
the drive signal.
Drive circuits using pulse transformers have problems if a
widely varying duty cycle is required. This causes widely
varying gate drive voltages when the MOSFET is off. In
consequence there are variable switching times and
varying levels of immunity to dV/dt turn on andinterference.
There are several possible solutions to this problem, some
examples are given in Figs.9 - 12.
N ·
V.t
B.A
e
2
41
Introduction Power Semiconductor Applications
Philips Semiconductors
Fig.6(a) A circuit using a pulse transformer for isolation.
Fig.6(b) Waveforms associated with pulse transformer.
Fig.7. The voltage waveforms associated with the circuit
in Fig.6(a) with varying duty cycles.
In the circuit shown in Fig.9 when A is positive with respect
to B the input capacitance of T1 is charged through the
parasitic diode of T2. The voltage across the secondary of
the pulse transformer can then fall to zero and the input
capacitance of T1 will remain charged. (It is sometimes
necessary to raise the effective input capacitance with an
external capacitor as indicated by the dashed lines.) When
B becomes positive with respect to A T2 will turn on and
the input capacitance of T2 will be discharged. The noise
immunity of the circuit can be increased by using another
MOSFET as shown in Fig.10.
Fig.8. A drive circuit using a capacitor to block the dc
component of the drive waveforms.
Fig.9. A drive circuit that uses a pulse transformer for
isolation which copes well with widely varying duty
cycles.
Fig.10. An isolated drive circuit with good performance
with varying duty cycles and increased noise immunity.
In Fig.10 the potential at A relative to B has to be sufficient
to charge the input capacitance of T3 and so turn T3 on
before T1 can begin to turn on.
T1
T2
ZD
Vd
0 V
T1
Primary
Voltage
Voltage
Across T2
time
time
T1
A
B
T2
time
time
High
Duty
Cycle
Low
Duty
Cycle
Secondary
Voltage
T1
A
B
T2
T3
42
Introduction Power Semiconductor Applications
Philips Semiconductors
Fig.11. A drive circuit that reduces the size of the pulse transformer.
T1
Q1
h.f. clock
drive signal
In Fig.11 the drive signal is ANDed with a hf clock. If the
clock has a frequency much higher than the switching
frequency of T1 then the size of the pulse transformer is
reduced. The hf signal on the secondary of the pulse
transformer is rectified. Q1 provides a low impedance path
for discharging the input capacitance of T1 when the hf
signal on the secondary of the pulse transformer is absent.
Fig.12 Example of pulse transformer isolated drive with a latching buffer
15 V
Z
HEF40097
2k2
2k2
10T 20T
47 pF
18 k
1 k c18v
DC Link
O V
100R
FX3848
8 uF
2n2
43
Introduction Power Semiconductor Applications
Philips Semiconductors
Figure 12 shows a hex non-inverting buffer connected on
the secondary side, with one of the six buffers configured
as a latch. The circuit operates such that the positive going
edge of the drive pulse will cause the buffers to latch into
the high state. Conversely the negative going edge of the
drive pulse causes the buffers to latch into the low state.
With the component values indicated on the diagram this
circuit can operate with pulse on-times as lowas 1 µs. The
impedance Z represents either the low side switch in a
bridge circuit (which can be a MOSFET configured with
identical drive) or a low side load.
The impedance of the gate drive circuit may be used to
control theswitchingtimes of the MOSFET. Increasinggate
drive impedance however can increase the risk of dV/dt
turn-on. To try and overcome this problem it may be
necessary to configure the drive as outlined in Fig.13.
(a)
(b)
Fig.13. Two circuits that reduce the risk of dV/dt turn on.
The diode in Fig.13(a) reduces the gate drive impedance
whenthe MOSFETis turned off. In Fig.13(b) when the drive
pulse is taken away, the pnp transistor is turned on. When
thepnptransistor is onit short-circuits the gatetothesource
and so reduces the gate drive impedance.
High side drive circuits
The isolated drive circuits in the previous section can be
used for either high or low side applications. Not all high
side applications however require an isolated drive. Two
examples showing how a high side drive can be achieved
simply witha boot strap capacitor areshown in Fig.14. Both
these circuits depend upon the topping up of the charge on
the boot strap capacitor while the MOSFET is off. For this
reason these circuits cannot be used for dc switching. The
minimum operating frequency is determined by the size of
the boot strap capacitor (and R1 in circuit (a)), as the
operating frequency is increased so the value of the
capacitor can be reduced. The circuit example in Fig. 14(a)
has a minimum operating frequency of 500 Hz.
Fig.14(a) Drive circuit for a low voltage half bridge
circuit.
At high frequencies it may be necessary to replace R1 with
the transistor T3 as shown in Fig.14(b). This enables very
fast turn-off times which would be difficult to achieve with
circuit (a) since reducing R1 to a lowvalue would cause the
boot strap capacitor to discharge during the on-period. The
impedance Z represents either the low side switch part of
the bridge or the load.
Fig.14(b) Modification for fast turn-off.
Very fast drive circuits for frequencies up
to 1 MHz
The following drive circuits can charge the gate source
capacitance particularly fast and so realise extremely short
switching times. These fast transition times are necessary
toreduce theswitchinglosses. Switchinglosses aredirectly
proportional totheswitchingfrequency andaregreater than
conduction losses above a frequency of about 500 kHz,
Vin
T1
T2
C 6.8uF
R1 47R
10k
22k
1k0
Z
24V
0V
T1
D1
R1
R2
T1
24V
Vin
T1
T2
C
T3
Z
0V
44
Introduction Power Semiconductor Applications
Philips Semiconductors
although this crossover frequency is dependent on circuit
configuration. Thus for operation above 500 kHz it is
important to have fast transition times.
At frequencies below 500 kHz the circuit in Fig.15 is often
used. Above 500 kHz the use of the DS0026 instead of the
4049 is recommended. The DS0026 has a high current
sinking and sourcing capability of 2.5 A. It is a National
Semiconductor device and is capable of charging a
capacitance of 100 pF in as short a time as 25 ns.
Fig.15 A MOSFET drive circuit using a hex CMOS
buffered inverter IC
In Fig.16 the value of capacitor C1 is made approximately
equal to the input capacitance of the driven MOSFET. Thus
the RC time constant for the charging circuit is
approximately halved. The disadvantage of this
arrangement is that a drive voltage of 30V instead of 15V
is needed because of the potential divider action of C1 and
the input capacitance of the driven MOSFET. Asmall value
of C1would be ideal for a fast turn on time and a large value
of C1 would produce a fast turn off. The circuit in Fig.17
replaces C1 by two capacitors and enables fast turn on and
fast turn off.
Fig.16 A simple drive circuit with reduced effective
input capacitance
For the circuit in Fig.17 when MOSFET T1 is turned on the
driven MOSFET T3 is driven initially by a voltage V
DD
feeding three capacitors in series, namely C1, C2 and the
input capacitance of T3. Since the capacitors are in series
their equivalent capacitance will be lowand so the RC time
constant of the charging circuit will be low. C1 is made low
to make the turn on time very fast.
Fig.17 A drive circuit with reduced effective input
capacitance and prolonged reverse bias at turn off.
The voltage across C2 will then settle down to
(V
DD
- V
ZD1
) R2/(R1 + R2). Therefore the inclusion of
resistors R1 and R2 means that C2 can be made larger
than C1 and still have a large voltage across it before the
turn off of T3. Thus C2can sustain areverse voltageacross
the gate source of T3 for the whole of the turn off time. The
initial discharging current will be given by Equation 3,
Making V
DD
large will make turn on and turn off times very
small.
Fast switching speeds can be achieved with the push pull
circuit of Fig.19. A further improvement can be made by
replacing the bipolar devices by MOSFETs as shown in
Fig.20. The positions of the P and N channel MOSFETs
may be interchanged and connected in the alternative
arrangement of Fig.21. However it is likely that one
MOSFET will turn on faster than the other turns off and so
the circuit in Fig.21 may cause a current spike during the
switching interval. The peak to average current rating of
MOSFETs is excellent so this current spike is not usually
a problem. In the circuit of Fig.20 the input capacitance of
the driven MOSFET is charged up to V
DD
- V
T
, where V
T
is
the threshold voltage, at which point the MOSFET T1 turns
off. Therefore when T2 turns on there is no current spike.
Vdd
T1
T2
T3
ZD1
C2
R1 C1
ZD2
R2
4049
0 V
15 V
I ·
V
ZD1
+
R
2
.(V
DD
−V
ZD1
)
(R
1
+R
2
)
R
STRAY
+ R
DS(ON)T2
3
30 V
0 V
C1 = 2 nF
45
Introduction Power Semiconductor Applications
Philips Semiconductors
Fig.18 A comparison of the switching times for
MOSFETs driven from a constant current source and a
constant voltage source.
Fig.19 A push-pull drive circuit using bipolar transistors
There may well be some advantages in charging the input
capacitanceof the MOSFETfromaconstant current source
rather than a constant voltage source. For a given drain
source voltage a fixed amount of charge has to be
transferred to the input capacitance of a MOSFET to turn
it on. As illustrated in Fig.18 this charge can be transferred
more quickly with a constant current of magnitude equal to
the peak current from a constant voltage source.
A fewother points are worthy of note when discussing very
fast drive circuits.
(1) SMPS working in the 1 - 15 MHz range sometimes use
resonant drive circuits. These SMPS are typically QRC
(Quasi Resonant Circuits). The resonant drive circuits do
not achieve faster switching by the fact that they are
resonant. But by being resonant, they recoup some of the
drive energy and reduce the gate drive power. There are
two main types of QRC - zero voltage and zero current
switching circuits. In one of these types, fall times are not
critical and in the other, rise times are not critical. On the
critical switching edge, a normal, fast switching edge is
provided by using a circuit similar to those given above. For
the non-critical edge there is a resonant transfer of energy.
Thus drive losses of Q
G
.V
GS
.f become 0.5.Q
G
.V
GS
.f.
Fig.20 A push-pull drive circuit using MOSFETs in the
common drain connection.
Fig.21 A push-pull drive circuit using MOSFETs in the
common source connection
(2) It isusual toprovideoverdriveof thegatesourcevoltage.
This means charging the input capacitance to a voltage
which is more than sufficient to turn the MOSFET fully on.
This has advantages in achieving lower on-resistance and
increasing noise immunity. The gate power requirements
are however increased when overdrive is applied. It may
well be a good idea therefore to drive the gate with only
12 V say instead of 15 V.
(3) It is recommended that a zener diode be connected
across the gate source terminals of a MOSFET to protect
against over voltage. This zener can have a capacitance
which isnot insignificant compared tothe input capacitance
of small MOSFETs. The zener can thus affect switching
times.
Constant
Current
Constant
Voltage
A1
A2
A1 = A2
T1
T2
time
time
I
I
Vdd
T1
T2
Vdd
T1
T2
46
Introduction Power Semiconductor Applications
Philips Semiconductors
Parallel operation
Power MOSFETs lend themselves readily to operation in
parallel since their positive temperature coefficient of
resistance opposes thermal runaway. Since MOSFETs
have low gate drive power requirements it is not normally
necessary toincrease the rating of drive circuit components
if more MOSFETs are connected in parallel. It is however
recommended that differential resistors are used in the
drive circuits as shown in Fig.22.
Fig.22. A drive circuit suitable for successful parallelling
of Philips MOSFETs incorporating differential resistors.
These differential resistors (R
D
) damp down possible
oscillationsbetweenreactivecomponents in thedevice and
in connections around the MOSFETs, with the MOSFETs
themselves, which have a high gain even up to 200 MHz.
Protection against gate-source
overvoltages
It is recommended that zener diodes are connected across
thegate-sourceterminals of the MOSFETtoprotect against
voltage spikes. One zener diode or two back-to-back zener
diodes are necessary dependent on whether the
gate-source is unipolar or bipolar, as shown in Fig.23.
The zener diodes should be connected close to the
terminals of the MOSFET to reduce the inductance of the
connecting leads. If the inductance of the connecting leads
is too large it can support sufficient voltage to cause an
overvoltage across the gate-source oxide.
In conclusion the low drive power requirement of Philips
PowerMOS make provision of gate drive circuitry a
relatively straightforward process as long as the few
guide-lines outlined in this note are heeded.
Rd Rd
Fig.23. Zener diodes used to suppress voltage spikes across the gate-source terminals of the MOSFET.
T1
4011
47
Introduction Power Semiconductor Applications
Philips Semiconductors
1.2.4 Parallel Operation of Power MOSFETs
This section is intended as a guide to the successful
parallelling of Power MOSFETs in switching circuits.
Advantages of operating devices in
parallel
Increased power handling capability
If power requirements exceed those of available devices
thenincreasedpower levelscan beachieved by parallelling
devices. The alternative means of meeting the power
requirements would be to increase the area of die. The
processing of the larger die would have a lower yield and
sothe relative cost of thediewould beincreased. The larger
die may also require a more expensive package.
Standardisation
Parallelling devices can mean that only one package, say
the TO220 package, needs to be used. This can result in
reduced production costs.
Increased operating frequency
Packages are commercially available which contain upto
five die connected in parallel. The switching capabilities of
these packages are typically greater than 10 kVA. The
parasitic inductances of connections to the parallelled dies
are different for each die. This means that the current rating
of the package has to be derated at high frequencies to
allowfor unequal current sharing. The voltage rating of the
multiple die package has to be derated for higher switching
speeds. This is because the relatively large inductances of
connections within the package sustain appreciable
voltages during the switching intervals. This means that the
voltages at the drain connections to the dice will be
appreciably greater than voltages at the terminals of the
package. By parallelling discrete devices these problems
can be overcome.
Faster switching speeds are achieved using parallelled
devices than using a multiple die package. This is because
switching times are adversely affected by the impedance
of the gate drive circuit. When devices are parallelled these
impedances are parallelled and so their effect is reduced.
Hence faster switching times and so reduced switching
losses can be achieved.
Faster switching speeds improve parallelling. During
switching intervals one MOSFET may carry more current
than other MOSFETs in parallel with it. This is caused by
differencesin electrical parameters between the parallelled
MOSFETs themselves or between their drive circuits. The
increased power dissipation in the MOSFET which carries
more current will be minimised if switching speeds are
increased. The inevitable inductance in the source
connection, caused by leads within the package, causes a
negative feedback effect during switching. If the rate of rise
of current in one parallelled MOSFET is greater than in the
others then the voltage drop across inductances in its drain
and source terminals will be greater. This will oppose the
build up of current in this MOSFETand so have a balancing
effect. This balancing effect will be greater if switching
speeds are faster. This negative feedback effect reduces
thedeleterious effect of unequal impedances of drivecircuit
connections to parallelled MOSFETs. The faster the
switching speeds then the greater will be the balancing
effect of the negative feedback. Parallelling devices
enables higher operating frequencies to be achieved than
using multiple die packages. The faster switching speeds
possible by parallelling at the device level promote better
current sharing during switching intervals.
Increased power dissipation capability
If two devices, each rated for half the total required current,
are parallelled then the sum of their individual power
dissipationcapabilities will be morethanthe possible power
dissipation in a single device rated for the total required
current. This isespecially useful for circuits operatingabove
100 kHz where switching losses predominate.
Fig.1. A typical graph of on resistance versus
temperature for a Power MOSFET
-60 -20 20 60 100 140 180
2
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
N
o
r
m
a
l
i
s
e
d

R
e
s
i
s
t
a
n
c
e
Junction Temperature ( C)
49
Introduction Power Semiconductor Applications
Philips Semiconductors
Advantages of power MOSFETs for
parallel operation
Reduced likelihood of thermal runaway
If one of the parallelled devices carries more current then
the power dissipation in this device will be greater and its
junction temperature will increase. The temperature
coefficient of R
DS(ON)
for Power MOSFETs is positive as
shown in Fig.1. Therefore there will be a rise in R
DS(ON)
for
the device carrying more current. This mechanism will
oppose thermal runaway in parallelled devices and also in
parallelled cells in the device.
Low Drive Power Requirements
The low drive power requirements of power MOSFETs
mean that many devices can be driven fromthe same gate
drive that would be used for one MOSFET.
Very good tolerance of dynamic
unbalance
The peak to average current carrying capability of power
MOSFETs is very good. A device rated at 8A continuous
draincurrent can typically withstand apeak current of about
30A. Therefore, for the case of three 8A devices in parallel,
if one of the devices switches on slightly before the others
no damage will result since it will be able to carry the full
load current for a short time.
Design points
Derating
Since there is a spread in on-resistance between devices
from different batches it is necessary to derate the
continuous current rating of parallelled devices by about
20%.
Layout
There are two aspects to successful parallelling which are
static and dynamic balance. Static balance refers to equal
sharing of current between parallelled devices when they
have been turned on. Dynamic balance means equal
sharing of current between parallelled transistors during
switching intervals.
Unsymmetrical layout of thecircuit causes staticimbalance.
If the connections between individual MOSFETs and the
rest of the power circuit have different impedances then
there will be static imbalance. The connections need to be
kept as short as possible to keep their inductance as small
as possible. Symmetrical layout is particularly important in
resonant circuits where MOSFETs carry a sinusoidal
current e.g. in a voltage fed inverter feeding a series
resonant circuit. In a current fed inverter, where switching
in the inversion stage causes a rectangular wave of current
to be passed through a parallel resonant tank circuit, the
voltage sustained by MOSFETs when they are off will be
half sinusoid. A component of the current carried by
MOSFETs will be acharging current for snubber capacitors
which will be sinusoidal so again symmetrical layout will be
important.
Fig.2. The waveforms of current through two parallelled
BUK453-50A MOSFETs with symmetrical layout.
Fig.3. The waveforms of current through two parallelled
BUK453-50A MOSFETS with 50 nH connected in the
source connection on one MOSFET.
Unsymmetrical layout of the gate drive circuitry causes
dynamic imbalance. Connections between the gate drive
circuitry and the MOSFETs need to be kept short and
twisted together to reduce their inductance. Further to this
-500 -300 -100 100 300 500
50
40
30
20
10
0
-10
time (ns)
C
u
r
r
e
n
t

(
A
)
-500 -300 -100 100 300 500
50
40
30
20
10
0
-10
time (ns)
C
u
r
r
e
n
t

(
A
)
50
Introduction Power Semiconductor Applications
Philips Semiconductors
the connections between the gate drive circuit and
parallelled MOSFETs need to be approximately the same
length.
Figures 2 and 3 illustrate the effect of unsymmetrical layout
on the current sharing of two parallelled MOSFETs. The
presence of 50 nH in the source connection of one of the
two parallelled BUK453-50A MOSFETs causes noticeable
imbalance. A square shaped loop of 1 mm diameter wire
and side dimension only 25 mm is sufficient to produce an
inductance of 50 nH.
Symmetrical layout becomes more important if more
MOSFETs are parallelled, e.g. if a MOSFET with an R
DS(ON)
of 0.7 Ohm was connected in parallel with a MOSFET with
an R
DS(ON)
of 1 Ohmthen the MOSFETwith the lower R
DS(ON)
would carry 18% more current that if both MOSFETs had
an R
DS(ON)
of 1 ohm. If the MOSFET with an R
DS(ON)
of 0.7
ohm was connected in parallel with a hundred MOSFETs
with R
DS(ON)
of 1 ohm it would carry 42% more current than
if all the MOSFETs had an R
DS(ON)
1 Ohm.
Good Thermal Coupling
Thereshould be goodthermal coupling between parallelled
MOSFETs. This is achieved by mounting parallelled
MOSFETs on the same heatsink or on separate heatsinks
which are in good thermal contact with each other.
If poor thermal coupling existed between parallelled
MOSFETs and the positive temperature coefficient of
resistancewas reliedon to promote static balance, then the
total current carried by the MOSFETs would be less than
with good thermal coupling. Some MOSFETs would also
have relatively high junction temperatures and so their
reliability would be reduced. The temperature coefficient of
MOSFETs is not large enough to make poor thermal
coupling tolerable.
The Suppression of Parasitic Oscillations
Parasitic oscillations can occur. MOSFETs have transition
frequencies typically in excess of 200 MHz and parasitic
reactances are present both in the MOSFET package and
circuit connections, so the necessary feedback conditions
for parasitic oscillations exist. These oscillations typically
occur at frequencies above 100 MHz so a high bandwidth
oscilloscope is necessary to investigate them. The
likelihood of these parasitic oscillations occurring is very
much reduced if small differential resistors are connected
in the leads to each parallelled MOSFET. A common gate
drive resistor of between 10 and 100 Ohms with differential
resistors of about 10 Ohm are recommended as shown in
Fig.4.
Fig.4. Differential gate drive resistors
The suppression of parasitic oscillations between
parallelled MOSFETs can also be aided by passing the
connections from the gate drive circuit through ferrite
beads. The effect of these beads below1 MHz is negligible.
The ferrite beads however damp the parasitic oscillations
which occur at frequencies typically above 100 MHz. An
example of parasitic oscillations is shown in Fig.5.
Fig.5. Parasitic oscillations on the voltage waveforms of
a MOSFET
If separate drive circuits with closely decoupled power
supplies are used for each parallelled device then parasitic
oscillations will be prevented. This condition could be
satisfiedby drivingeach parallelledMOSFETfrom3buffers
in a CMOS Hex buffer ic.
To take this one stage further, separate push pull transistor
drivers could be used for each MOSFET. (Aseparate base
resistor is needed for each push-pull driver to avoid a
MOSFET with a low threshold voltage clamping the drive
voltage to all the push pull drivers). This arrangement also
has the advantage that the drive circuits can be positioned
very close to the terminals of each MOSFET. The
impedance of connections from the drive circuits to the
MOSFETs will be minimised and so there will be a reduced
10 Ohm 10 Ohm
50 Ohm
0
5
10
15
0
10
20
30
40
V
d
s

(
V
)
V
g
s

(
V
)
0 400 800 1200 1600 2000
time (ns)
51
Introduction Power Semiconductor Applications
Philips Semiconductors
likelihood of spurious turn on. Spurious turn on can occur
when there is a fast change in the drain to source voltage.
Thechargingcurrent for thegatedraincapacitanceinherent
in the MOSFET structure can cause a voltage drop across
thegatedrive impedancelargeenoughtoturn the MOSFET
on. The gate drive impedance needs to be kept as low as
possible to reduce the likelihood of spurious turn on.
Resonant power supplies
If a resonant circuit is used then there will be reduced
interference and switching losses. The reduced
interferenceisachieved becausesinusoidal waveformsare
present in resonant circuits rather than rectangular
waveforms. Rectangular waveforms have large high
frequency harmonic components.
MOSFETs are able to switch at a zero crossing of either
thevoltageor the current waveformandso switchinglosses
are ideally zero. For example, in the case of a current fed
inverter feeding a parallel resonant load switching can take
place at a zero crossing of voltage so switching losses are
negligible. In this case the sinusoidal drain source voltage
sustained by MOSFETs reduces the likelihood of spurious
dv/dt turn on. This is because the peak charging current for
the internal gate to drain capacitance of the MOSFET is
reduced.
The current fed approach
Switch mode power supplies using the current fed topology
have a d.c. link which contains a choke to smooth the
current in the link. Thus a high impedance supply is
presented to the inversion stage. Switching in the inversion
stage causes a rectangular wave of current to be passed
through the load. The current fed approach has many
advantages for switch mode power supplies. It causes
reduced stress on devices caused by the slow reverse
recovery time of the parasitic diodeinherent in the structure
of MOSFETs.
Thecurrent fedapproach canalso reduceproblemscaused
by dynamic imbalance. If more than three MOSFETs are
parallelled then it is advantageous to use more than one
choke in the d.c. link rather than wind a single choke out of
thicker gauge wire. One of the connections to each choke
is connected to the output of the rectification stage. The
other connection of each choke is connected to a group of
three MOSFETs. This means that if oneMOSFET switches
on before the others it will carry a current less than its peak
pulse value even when many MOSFETs are parallelled.
The parallel operation of MOSFETs in the
linear mode
The problems of parallelling MOSFETs which are being
used in the linear mode are listed below.
(a) The parallelled devices have different threshold
voltages and transconductances. This leads to poor
sharing.
(b) MOSFETs have a positive temperature coefficient of
gain at low values of gate to source voltage. This can lead
to thermal runaway.
The imbalance caused by differences in threshold voltage
and transconductance can be reduced by connecting
resistors (R
S
) in the source connections. These resistors
are in the gate drive circuit and so provide negative
feedback. The negative feedback reduces the effect of
different values of VT and g
m
. The effective
transconductance gm of the MOSFET is given in
Equation 1.
R
S
must be large compared to 1/g
m
to reduce the effects of
differences in g
m
. Values of 1/g
m
typically vary between 0.1
and 1.0 Ohm. Therefore values of R
S
between 1 ohm and
10 ohm are recommended.
Differential heating usually has a detrimental effect on
sharing and so good thermal coupling is advisable.
Conclusions
Power MOSFETs can successfully be parallelled to realise
higher power handling capability if a few guidelines are
followed.
g
m
·
1
R
s
+
1
g
m
1
52
Introduction Power Semiconductor Applications
Philips Semiconductors
1.2.5 Series Operation of Power MOSFETs
The need for high voltage switches can be well illustrated
by considering the following examples. In flyback
converters the leakage inductance of an isolating
transformer can cause a large voltage spike across the
switch when it switches off. If high voltage MOSFETs are
used the snubber components can be reduced in size and
in some cases dispensed with altogether.
For industrial equipment operation from a supply of 415 V,
550 V or 660 V is required. Rectification of these supply
voltages produces d.c. rails of approximately 550 V, 700 V
and 800 V. The need for high voltage switches in these
cases is clear.
Resonant topologies are being increasingly used in
switching circuits. These circuits have advantages of
reduced RFI and reduced switching losses. To reduce the
size of magnetic components and capacitors the switching
frequencyof power suppliesisincreased. RFI andswitching
losses become more important at high frequencies so
resonant topologies are more attractive. Resonant circuits
have the disadvantage that the ratio of peak to average
voltage can be large. For example a Parallel Resonant
Power Supply for a microwave oven operating off a 240 V
supply can be designed most easily using a switch with a
voltage rating of over 1000 V.
In high frequency induction heating power supplies
capacitors are used to resonate the heating coil. The use
of high voltage switches in the inversion bridge can result
inbetter utilisationof thekVAr capabilityof thesecapacitors.
This is advantageous since capacitors rated at tens of kVAr
above 100 kHz are very expensive.
In most TV deflection and monitor circuits peak voltages of
up to 1300 V have to be sustained by the switch during the
flyback period. This high voltage is necessary to reset the
current in the horizontal deflection coil. If the EHT flashes
over, the switch will have to sustain a higher voltage so
1500 V devices are typically required.
The Philips range of PowerMOS includes devices rated at
voltages up to 1000 V to cater for these requirements.
However in circuits, particularly in resonant applications
where voltages higher than this are required, it may be
necessary to operate devices in series.
Series operation canbe attractive for the following reasons:
Firstly, the voltage rating of a PowerMOS transistor
cannot be exceeded. A limited amount of energy can be
absorbed by a device specified with a ruggedness rating
(eg device can survive some overvoltage transients), but
a 1000 V device cannot block voltages in excess of
1000 V.
Secondly, series operation allows flexibility as regards
on-resistance and so conduction losses.
The following are problems that have to be overcome for
successful operation of MOSFETs in series. If one device
turns off before another it may be asked to block a voltage
greater than its breakdown voltage. This will cause a
reduction in the lifetime of the MOSFET. Also there is a
requirement for twice as many isolated gate drive circuits
in many circuits.
The low drive power requirements of Philips PowerMOS
mean that the provision of more isolated gate drive circuits
is made easier. Resonant circuits can have advantages in
reducing the problems encountered if one MOSFET turns
off beforeanother. The current fed full bridgeinverter is one
such circuit.
To illustrate how devices can be operated in series, a
current fed full bridge inverter is described where the peak
voltage requirement is greater than 1200 V.
The current fed inverter
A circuit diagram of the full bridge current fed inverter is
shown in Fig.1. A choke in the d.c. link smooths the link
current. Switching in the inversion bridge causes a
rectangular wave of current to be passed through the load.
The load is a parallel resonant tank circuit. Since the Q of
the tank circuit is relatively high the voltage across the load
is a sinewave. MOSFETs sustain a half sinusoid of voltage
when they are off. Thus series operation of MOSFETs is
made easier because if one MOSFET turns off before
another it only has to sustain a small voltage. To achieve
the best sharing, the gate drive to MOSFETs connected in
series should be as similar as possible. In particular the
zerocrossings shouldbesynchronised. The MOSFETdrive
circuit shown in Fig.2 has been found to be excellent in this
respect. For current fed resonant circuits in which the duty
cyclevaries over largeranges thecircuit inFig.3will perform
well. A short pulse applied to the primary of the pulse
transformer is sufficient to turn MOSFET M4 on. This short
pulse can be achieved by designing the pulse transformer
so that it saturates during the time that M1 is on. The gate
source capacitance of M4 will remain charged until M2 is
turned on. M3 will then be turned on and the gate source
capacitance of M4 will be discharged and so
53
Introduction Power Semiconductor Applications
Philips Semiconductors
Fig.1. Circuit diagram of the full bridge current-fed inverter feeding a parallel resonant load.
LEG 1
LEG 2
LEG 3 LEG 4
Drive
Circuit
Crowbar
Circuit
Hall Effect
Current Sense
Semiconductor
Fuse
120 uH
2.2 nF
M4 is turned off. Thus this circuit overcomes problems of
resetting the flux in the core of the pulse transformer for
large duty cycles.
Each leg of the inverter consists of two MOSFETs, type
BUK456-800B, connected in series. The ideal rating of the
two switches in each leg is therefore 1600 Vand 3.5 A. The
inverter is fed into a parallel resonant circuit with values of
L = 120 µH (Q = 24 at 150 kHz) and C = 2.2 nF.
Fig.2. The MOSFET drive circuit.
Capacitors are shown connected across the drain source
terminals of MOSFETs. The value of the capacitor across
the drain to source of each MOSFET is 6.6 nF. (Six 10 nF
polypropylene capacitors, type 2222 376 92103.) This
gives a peak voltage rating of about 850 V at 150 kHz for
the capacitor combination across each MOSFET. (This
voltagerating takes intoaccount that the capacitors will only
have to sustain voltage when the MOSFET is off). The
functionof thesecapacitors is twofold. Firstly theysuppress
spikes caused by switching off current in parasitic lead
inductance. Secondly they improve the sharing of voltage
between the MOSFETs connected in series. These
capacitors are effectively in parallel with the tank circuit
capacitor. However only half of the capacitors across
MOSFETs are in circuit at any one time. This is because
half of the capacitors are shorted out by MOSFETs which
have been turned on. The resonant frequency of the tank
circuit and drain source capacitors is given by Equation 1.
Where C
tot
is the equivalent capacitance of the tank circuit
capacitor and the drain source capacitors and is given by
Equation 2.
T1
T2
15 V
0 V
0.68 uF
FX3434
30 turns secondary
15 turns primary
33 Ohm
33 Ohm
33 Ohm
f ·
1


L.C
tot
1
54
Introduction Power Semiconductor Applications
Philips Semiconductors
Therefore the resonant frequency of the tank circuit is
155 kHz.
An expression for the impedance at resonance of the
parallel resonant circuit (Z
D
) is given in Equation 3.
The Q of the circuit is given by Equation 4.
Substituting Equation 3.
Thus Z
D
for the parallel resonant load was 2.7 kOhms.
In a conventional rectangular switching circuit the
connection of capacitors across MOSFETs will cause
additional losses. These losses are caused because when
a MOSFET turns on, the energy stored in the drain source
capacitance is dissipated in the MOSFET and in a series
resistor. This series resistor is necessary to limit the current
spike in the MOSFET at turn on. These losses are
appreciable at 150 kHz, e.g. the connection of 1 nF across
a MOSFET switching 600 V would cause losses of more
than 25 Wat 150 kHz. In the current fed inverter described
inthis articlethe MOSFETs turn on whenthevoltageacross
the capacitor is ideally zero. Thus there is no need for a
series resistor and the turn on losses are ideally zero.
In this case the supply to the inverter was 470 V rms. This
means that the peak voltage in the d.c. link was 650 V.
Equating the power flowing in the d.c. link to the power
dissipated in the tank circuit produces an expression for the
peak voltage across the tank circuit (V
T
) as given in
Equation 6.
Therefore the peak to peak voltage across the tank circuit
was ideally 2050 V
The voltage across each MOSFET should be 512 V.
Circuit performance
The switching frequency of this circuit is 120 kHz. Thus the
loadisfedslightly belowitsresonant frequency. This means
that theloadlooksinductiveandensuresthat theMOSFETs
do not switch on when the capacitors connected across
their drain source terminals are charged.
C
tot
· C
t
+ C
DS
2
Z
D
·
L
C
tot
.R
3
Q ·
1
R
.

L
C
tot
4
V
T
· 2 ×

2×1.11 × V
dclink
6
Z
D
· Q.

L
C
tot
5
Fig.3. Drive circuit with good performance over widely varying duty cycles.
15 V
0 V
0.68 uF
33 Ohm
33 Ohm
33 Ohm
M1
M2
M3 M4
55
Introduction Power Semiconductor Applications
Philips Semiconductors
The waveforms of the voltage across two MOSFETs in
series in a leg of the inversion bridge are shown in Fig.4. It
can be seen that the sharing is excellent. The peak voltage
across each MOSFET is 600 V. This is higher than 512 V
because of ringing between parasitic lead inductance and
the drain source capacitance of MOSFETs when they
switch off.
The MOSFETs carry two components of current. The first
component is the d.c. link current. The second component
is a fraction of the circulating current of the tank circuit. The
size of the second component is dependent on the relative
sizes of the drain source capacitance connected across
MOSFETs and the tank circuit capacitor.
In this circuit the peak value of charging current for drain
source capacitors, which is carried by the MOSFET, is 4 A.
The on-resistance of the BUK456-800B is about 5 Ohms
at 80 ˚C. This explains the rise in V
DS(ON)
of about 20 Vseen
in Fig.4 just above the turn off of the MOSFETs.
The sharing of Philips PowerMOS in this configuration is
so good that the value of drain source capacitance is not
determined by its beneficial effect on sharing. Therefore,
the value can be selected solely on the need to control
ringing which in turn is dependent on power output and
layout. (The increased current level associated with
increased power output makes the ringing worse).
Inany given configurationthere isamaximumoutput power
that single MOSFETs can handle and there will be a value
of drain source capacitance associated with it. This value
Fig.4. The drain-source voltage waveforms for two
MOSFETs connected in series in a leg of the inversion
bridge.
can be used as the ’capacitance per MOSFET’ in higher
power circuits where it becomes necessary to use
MOSFETs connected in parallel. A value of between 5 and
10 nF is probably sufficient given a sensible layout.
Conclusions
It has been shown that MOSFETs can be connected in
series to realise a switch that is as high as 90% of the sum
of the voltage sustaining capabilities of the individual
transistors.
0 13 26 39 52 65 78 91 104 117 130
0
80
160
240
320
400
480
560
640
D
r
a
i
n
-
S
o
u
r
c
e

V
o
l
t
a
g
e

(
V
)
time (us)
56
Introduction Power Semiconductor Applications
Philips Semiconductors
1.2.6 Logic Level FETS
Standard Power MOSFETs require a gate-source voltage
of 10 V to be fully ON. With Logic Level FETs (L
2
FETs)
however, the same level of conduction is possible with a
gate-source voltage of only 5 V. They can, therefore, be
driven directly from 5 V TTL/CMOS ICs without the need
for the level shifting stages required for standard
MOSFETs, see Fig.1. This makes them ideal for today’s
sophisticated electrical systems, where microprocessors
are used to drive switching circuits.
Fig.1 Drive circuit for a standard MOSFET and an
L
2
FET
This characteristic of L
2
FETs is achieved by reducing the
gate oxide thickness from - 800 Angstroms to - 500
Angstroms, which reduces the threshold voltage of the
device from the standard 2.1-4.0 V to 1.0-2.0 V. However
the result is a reduction in gate-source voltage ratings,
fromt30 V for a standard MOSFET to t15 V for the L
2
FET.
The t15 V rating is an improvement over the ’industry
standard’ of t10 V, and permits Philips L
2
FETs to be used
in demanding applications such as automotive.
Although a 5 V gate-drive is ideal for L
2
FETs, they can be
used in circuits with gate-drive voltages of up to10 V. Using
a 10 V gate-drive results in a reduced R
DS(ON)
(see Fig.2)
but the turn-off delay time is increased. This is due to
excessive charging of the L
2
FET’s input capacitance.
Fig.2 R
DS(ON)
as a function of V
GS
for a standard
BUK453-100B MOSFET and a BUK553-100B L
2
FET. T
j
= 25 ˚C; V
GS
= 10 V
Capacitances, Transconductance and
Gate Charge
Figure3shows theparasitic capacitances areasof atypical
Power MOSFET cell. Both the gate-source capacitance
C
gs
and the gate-drain capacitance C
gd
increase due to the
reduction in gate oxide thickness, although the increase
in C
gd
is only significant at low values of V
DS
, when the
depletion layer is narrow. Increases of the order of 25% in
input capacitance C
iss
, output capacitanceC
oss
andreverse
transfer capacitance C
rss
result for the L
2
FET, compared
with a similar standard type, at V
DS
= 0 V. However at the
standard measurement condition of V
DS
= 25 V the
differences are virtually negligible.
Forward transconductance g
fs
is a function of the oxide
thickness so the g
fs
of an L
2
FET is typically 40% - 50%
higher than a standard MOSFET. This increase in g
fs
more
than offsets the increase in capacitance of an L
2
FET, so
the turn on charge requirement of the L
2
FET is lower than
the standard type see Fig.4. For example, the standard
BUK453-100B MOSFET requires about 17 nC to be fully
switched on (at a gate voltage of 10 V) while the
BUK553-100B L
2
FET only needs about 12 nC (at a gate
source voltage of 5 V).
input
TTL / CMOS
+10 V
V
DD
Standard
MOSFET
Standard MOSFET drive
input
TTL / CMOS
V
DD
L FET drive
2
L FET
2
+5 V
57
Introduction Power Semiconductor Applications
Philips Semiconductors
Fig.3 Parasitic capacitances of a typical Power
MOSFET cell
Fig.4 Turn-on gate charge curves of a standard
BUK453-100B and a BUK553-100B L
2
FET. V
DD
= 20 V;
I
D
= 12 A
Switching speed.
Figure5comparesthe turn-on performanceof the standard
BUK453-100B MOSFET and the BUK553-100B L
2
FET,
under identical drive conditions of 5 V from a 50 Ω
generator using identical loads. Thanks to its lower gate
threshold voltage V
GST
, the L
2
FET can be seen to turn on
in a much shorter time from the low level drive.
Figure 6 shows the turn-off performance of the standard
BUK453-100B MOSFET and the BUK553-100B L
2
FET,
again with the same drive. This time the L
2
FET is slower
to switch. The turn-off times are determined mainly by the
time required for C
gd
to discharge. The C
gd
is higher for the
L
2
FET at low V
DS
, and the lower value of V
GST
leads to a
lower discharging current. The net result is an increase
in turn off time.
Fig.5 Comparison of (a) gate-source voltage and (b)
drain-source voltage waveforms during turn-on of a
standard BUK453-100B MOSFET and a BUK553-100B
L
2
FET. V
GS
is 5 V, I
D
is 3 A and V
DD
is 30 V.
Fast switching in many applications, for example
automotive circuits, is not important. In areas where it is
important however the drive conditions should be
examined. For example, for a given drive power, a 10 V
drive with a 50 Ω source impedance is equivalent to a 5 V
drive with a source impedance of only 12 Ω. This results in
faster switching for the L
2
FET compared with standard
MOSFETs.
Ruggedness and reliability
MOSFETs are frequently required to be able to withstand
the energy of an unclamped inductive load turn-off. Since
this energy is dissipated in the bulk of the silicon, stress
is avoided in the gate oxide. This means that the
ruggedness performance of L
2
FETs is comparable with
that of standard MOSFETs. The use of thinner gate oxide
in no way compromises reliability. Good control of key
process parameters such as pinhole density, mobile ion
content, interface state density ensures good oxide quality.
The projected MTBF is 2070 years at 90˚C, at a 60%
confidence level.
58
Introduction Power Semiconductor Applications
Philips Semiconductors
Fig.6 Comparison of (a) gate-source voltage and (b)
drain-source voltage waveforms during turn-off of a
standard BUK453-100B MOSFET and a BUK553-100B
L
2
FET. V
GS
is 5 V, I
D
is 3 A and V
DD
is 30 V.
The V
GS
rating of an L
2
FET is about half that of a standard
MOSFET, but thisdoesnot affect theV
DS
rating. In principle,
an L
2
FET version of any standard MOSFET is feasible.
Temperature stability
In general threshold voltage decreases with increasing
temperature. Although the threshold voltage of L
2
FETs is
lower than that of standard MOSFETs, so is their
temperature coefficient of threshold voltage (about half in
fact), so their temperature stability compares favourably
with standard MOSFETs. Philips low voltage L
2
FETs
(≤200v) in TO220 all feature T
jmax
of 175˚C, rather than
the industry standard of 150˚C.
Applications
The Philips Components range of rugged Logic Level
MOSFETs enable cost effective drive circuit design
without compromisingruggedness or reliability. Sincethey
enable power loads to be driven directly fromICs they may
be considered to be the first step towards intelligent power
switching. Thanks to their good reliability and 175˚C T
jmax
temperature rating, they aredisplacing mechanical relays
in automotive body electrical functions and are being
designed in to such safety critical areas as ABS.
59
Introduction Power Semiconductor Applications
Philips Semiconductors
1.2.7 Avalanche Ruggedness
Recent advances in power MOS processing technology
now enables power MOS transistors to dissipate energy
while operating in the avalanche mode. This feature results
in transistors able to survive in-circuit momentary
overvoltage conditions, presenting circuit designers with
increased flexibility when choosing device voltage grade
against required safety margins.
This paper considers the avalanche characteristics of
’rugged’ power MOSFETs and presents results from
investigations into the physical constraints which ultimately
limit avalanche energy dissipation in the VDMOS structure.
Results suggest that the maximum sustainable energy is a
function of the applied power density waveform,
independent of device voltage grade and chip size.
The ability of a rugged device to operate reliably in a circuit
subject to extreme interference is also demonstrated.
Introduction.
Susceptibility to secondary breakdown is a phenomenon
which limits the power handling capability of a bipolar
transistor to below its full potential. For a power MOSFET,
power handling capability is a simple function of thermal
resistance and operating temperature since the device is
not vulnerable to a second breakdown mechanism. The
previous statement holds true provided the device is
operated at or below its breakdown voltage rating (B
VDSS
)
and not subject to overvoltage. Should the transistor be
forced into avalanche by a voltage surge the structure of
the device permits possible activation of a parasitic bipolar
transistor which may then suffer the consequences of
second breakdown. In the past this mechanism was typical
of failure in circuits where the device became exposed to
overvoltage. To reduce the risk of device failure during
momentaryoverloads improvements havebeen introduced
to the Power MOS design which enable it to dissipate
energy whileoperatingintheavalanchecondition. The term
commonly used to describe this ability is ’Ruggedness’,
however before discussing in further detail the merits of a
rugged Power MOSFET it is worth considering the failure
mechanism of non-rugged devices.
Failure mechanism of a non-rugged Power
MOS.
A power MOS transistor is made up of many thousands of
cells, identical in structure. The cross section of a typical
cell is shown in Fig. 1. When in the off-state or operating in
saturation, voltage is supported across the p-n junction as
shown by the shaded region. If the device is subjected to
over-voltage (greater than the avalanche value of the
device), the peak electric field, located at the p-n junction,
rises to the critical value (approx. 200 kV / cm ) at which
avalanche multiplication commences.
Computer modelling has shown that the maximum electric
field occurs at the corners of the P diffusions. The
electron-hole plasma generated by the avalanche process
in these regions gives rise to a source of electrons, which
are swept across the drain, and a source of holes, which
flowthrough the P- and P regions towards the source metal
contact.
Fig. 1 Cross section of a typical Power MOS cell.
Clearly the P- regionconstitutes aresistance whichwill give
rise to a potential drop beneath the n+. If this resistance is
too large the p-n junction may become forward biased for
relatively low avalanche currents.
Also if the manufacturing process does not yield a uniform
cell structure across the device or if defects are present in
the silicon then multiplication may be a local event within
the crystal. This would give rise to a high avalanche current
density flowing beneath the source n+ and cause a
relatively large potential drop sufficient to forward bias the
p-n junction and hence activate the parasitic npn bipolar
transistor inherent in the MOSFET structure. Due to the
positive temperature coefficient associated with a forward
biased p-n junction, current crowding will rapidly ensuewith
the likely result of second breakdown and eventual device
destruction.
N+ Substrate
N- Layer
P
P- P-
N+
N+
Source Contact Metal
Polysilicon Gate
Drain
Source
Parasitic
Bipolar
Transistor
61
Introduction Power Semiconductor Applications
Philips Semiconductors
In order that a power MOS transistor may survive transitory
excursions into avalanche it is necessary to manufacture a
device with uniform cell structure, free from defects
throughout the crystal and that within the cell the resistance
beneath the n+ should be kept to a minimum. In this way a
forward biasingpotential across the p-n junction is avoided.
Definition of ruggedness.
The term ’Ruggedness’ when applied to a power MOS
transistor, describes the ability of that device to dissipate
energy while operating in the avalanche condition. To test
ruggedness of a device it is usual to use the method of
unclamped inductive load turn-off using the circuit drawn in
Fig. 2.
Fig. 2 Unclamped inductive load test circuit for
ruggedness evaluation.
Fig. 3 Typical waveforms taken from the unclamped
inductive load test circuit.
Circuit operation:-
A pulse is applied to the gate such that the transistor turns
on and load current ramps up according to the inductor
value, L and drain supply voltage, V
DD
. At the end of the
gate pulse, channel current in the power MOSbegins to fall
while voltage on the drain terminal rises rapidly in
accordance with equation 1.
The voltage on the drain terminal is clamped by the
avalanche voltage of the Power MOS for a duration equal
to that necessary for dissipation of all energy stored in the
inductor. Typical waveforms showing drain voltage and
source current for a device undergoing successful test are
shown in Fig. 3.
The energy stored in the inductor is given by equation 2
where I
D
is the peak load current at the point of turn-off of
the transistor.
All this energy is dissipated by the Power MOS while the
device is in avalanche.
Providedthe supply rail iskept below50 %of the avalanche
voltage, equation2approximates closely tothe total energy
dissipation by the device during turn-off. However a more
exact expression which takes account of additional energy
delivered from the power supply is given by equation 3.
Clearly the energy dissipated is a function of both the
inductor value and the load current I
D
, the latter being set
by the duration of the gate pulse. The 50 Ohm resistor
between gate and source is necessary to ensure a fast
turn-off such that the device is forced into avalanche.
The performance of anon-rugged device in response to the
avalanche test is shown in Fig. 4. The drain voltage rises
to the avalanche value followed by an immediate collapse
to approximately 30 V. This voltage is typical of the
sustaining voltage during Second Breakdown of a bipolar
transistor, [1]. The subsequent collapse to zero volts after
12 µS signifies failure of the device. The transistor shown
here was only able to dissipate a fewmicro joules at a very
low current if a failure of this type was to be avoided.
dv
dt
· L
d
2
I
dt
2
(1)
L
T.U.T.
VDD
RGS
R 01
VDS
-ID/100
+
-
shunt
VGS
0
W
DSS
· 0.5LI
D
2
(2)
W
DSS
·
BV
DSS
BV
DSS
− V
DD
0.5LI
D
2
(3)
62
Introduction Power Semiconductor Applications
Philips Semiconductors
Fig. 4 Failure waveforms of a non rugged Power MOS
transistor.
Fig. 5 Power and energy waveforms prior to failure for a
typical BUK627-500B
Characteristics of a rugged Power MOS.
i) The energy limitation of a rugged device
The power waveformfor a BUK627-500B(500 V, 0.8 Ohm)
tested at a peak current of 15 A is presented in Fig. 5.
The area within the triangle represents the maximum
energy that this particular device type may sustain without
failure at the above current. Figure 6 shows the junction
temperature variation in response to the power pulse,
calculated from the convolution integral as shown in
equation 4.
where transient thermal impedance.
Fig. 6 Junction temperature during the power pulse for
the avalanche ruggedness test on a Philips
BUK627-500B.
Equation 4 predicts that the junction temperature will pass
through a maximum of 325 ˚C during the test. The
calculation of Z
th
(t) assumes that the power dissipation is
uniform across the active area of the device. When the
device operates in the avalanche mode the power will be
dissipated more locally in the region of the p-n junction
where the multiplication takes place. Consequently a local
temperature above that predicted by equation 4 is likely to
be present within the device.
Work on bipolar transistors [2] has shown that at a
temperature of the order of 400 ˚C, the voltage supporting
p-n region becomes effectively intrinsic as a result of
thermal multiplication, resulting in a rapid collapse in the
terminal voltage. It is probable that a similar mechanism is
responsible for failure of the Power MOS with a local
temperature approaching 400 ˚Cresulting in a device short
circuit. A subsequent rapid rise in internal temperature will
result in eventual device destruction.
Clearly the rise in T
j
is a function of the applied power
waveform which is in turn related to circuit current,
avalanche voltage of the device and duration of the energy
pulse. Thustheenergy requiredtobringabout devicefailure
will vary as a function of each of these parameters. The
ruggednessof Power MOSFETSof varying crystal size and
voltage specification together with dependence on circuit
current is considered below.
ii) Sustainable avalanche energy as a
function of current.
The typical avalanche energy required to cause device
failure is plotted as a function of peak current in Fig. 7 for
a BUK553-60A(60 V, 0.085 OhmLogic Level device). This
result was obtained through destructive device testing
using the circuit of Fig. 2 and a variety of inductor values.
T
j
(t ) ·


τ · 0
τ · t
P(t − τ)Z
th
(τ)dτ (4)
Z
th
(τ) ·
63
Introduction Power Semiconductor Applications
Philips Semiconductors
Fig. 7 Avalanche energy against current for a typical
Philips BUK553-60A
Fig. 8(a) Temperature during avalanche test for a
BUK553-60A; ID = 10 A
Fig. 8(b) Temperature during avalanche test for a
BUK553-60A; ID = 22 A
Theplot showsthat the effect of reducingcurrent istopermit
greater energy dissipation during avalanche prior to failure.
This is an expected result since lower currents result in
reduced power dissipation enabling avalanche to be
sustained over a longer period. Temperature plots (Fig. 8)
calculated for the 10 A and 22 A failure points confirm that
the maximum junction temperature reached in each case
is the same despite the different energy values. (N.B. The
critical temperature is again underestimated as previously
stated.)
iii) Effect of crystal size.
To enable a fair comparison of ruggedness between
devices of various chip size it is necessary to normalise the
results. Therefore instead of plotting avalanche energy
against current, avalanche energy density and current
densitybecomemore appropriateaxes. Figure 9shows the
avalanche energy density against current density failure
locus for two 100 V Philips Power MOS types which are
different only in silicon area. Also shown on this plot are
two competitor devices of different chip areas (B
VDSS
= 100
V). This result demonstrates two points:
a) the rise in T
j
to the critical value for failure is dependent
on the power density dissipated within the device as a
function of time,
b) the sustainable avalanche energy scales proportional to
chip size.
KEY: x Philips BUK553-100A (6.25 mm
2
chip)
+ Philips BUK555-100A (13 mm
2
chip)
Competitor Devices (100 V)
Fig. 9 Avalanche energy density against current density
iv) Dependence on the drain source
breakdown voltage rating.
Energy density against current density failure loci are
shown for devices of several different breakdown voltages
in Fig. 10.
64
Introduction Power Semiconductor Applications
Philips Semiconductors
KEY: x Philips BUK553-60A
+ Philips BUK555-100A
Philips BUK627-500B
Fig. 10 Avalanche energy density against current
density
Presented in this form it is difficult to assess the relative
ruggedness of each device since the current density is
reduced for increasing voltage. If instead of peak current
density, peak power density is used for the x-axis then
comparison is made very simple. The data of Fig. 10 has
beenreplottedinFig. 11intheabovemanner. Represented
in this fashion the ruggedness of each chip appears very
similar highlighting that the maximum energy dissipation of
adevice while in avalanche is dependent only on the power
density function.
KEY: x Philips BUK553-60A
+ Philips BUK555-100A
Philips BUK627-500B
Fig. 11 Avalanche energy density against peak power
density
Ruggedness ratings.
It shouldbestressedthat the avalancheenergiespresented
in the previous section result in a rise of the junction
temperaturefar inexcessof thedevicerating andinpractice
energies should be kept within the specification.
Ruggedness is specified in data for each device in terms
of an unclamped inductive load test maximum condition;
recommended energy dissipation at a particular current
(usually the rated current of the device).
DEVICE R
DSON
V
DS
I
D
W
DSS
TYPE (Ω) (V) (A) (mJ)
BUK552-60A 0.15 60 14 30
BUK552-100A 0.28 100 10 30
BUK553-60A 0.085 60 20 45
BUK553-100A 0.18 100 13 70
Table 1 Ruggedness Ratings
The ruggedness rating is chosen to protect against a rise
in T
j
above the maximum rating. Examples of ruggedness
ratingsfor asmall selectionof devices are showninTable 1.
Fig. 12 Normalised temperature derating curve
This data is applicable for T
j
= 25 C. For higher operating
temperatures the permissible rise in junction temperature
during the energy test is reduced. Consequently
ruggedness needs to be derated with increasing operating
temperature. A normalised derating curve for devices with
Tj max 175 ˚C is presented in Fig. 12.
20 40 60 80 100 120 140 160 180
Tmb / C
120
110
100
90
80
70
60
50
40
30
20
10
0
WDSS%
65
Introduction Power Semiconductor Applications
Philips Semiconductors
Fig. 13(a) Test circuit
Fig. 13(b) Output from transient generator.
Performance of a rugged Power MOS
device.
The ability of a rugged Power MOS transistor to survive
momentary power surges results in excellent device
reliability. The response of a BUK553-60A to interference
spikes while switching a load is presented below. The test
circuit is shown in Fig. 13(a) together with the profile of the
interference spike in Fig. 13(b).
The interference generator produces pulses asynchronous
to the switching frequency of the Power MOS. Figure 14
shows the drain voltage and load current response at four
instances in the switching cycle. Devices were subjected
to 5000 interference spikes at a frequency of 5 Hz. No
degradation in device performance was recorded.
Conclusions.
The ability of power MOSdevices to dissipate energy in the
avalanche mode has been made possible by process
optimisation to remove the possibility of turn-on of the
parasitic bipolar structure. The failure mechanism of a
rugged device is one of excessive junction temperature
initiating a collapse in the terminal voltage as the junction
area becomes intrinsic. The rise in junction temperature is
dictatedby the power density dissipation which isa function
of crystal size, breakdown voltage and circuit current.
Ruggedness ratings for Philips PowerMOS are chosen to
ensure that the specified maximumjunction temperature of
the device is not exceeded.
References.
1. DUNN and NUTTALL, An investigation of the voltage
sustained by epitaxial bipolar transistors in current
mode second breakdown. Int.J.Electronics, 1978,
vol.45, no.4, 353-372
2. DOW and NUTTALL, A study of the current distribution
established in npn epitaxial transistors during current
mode second breakdown. Int.J.Electronics, 1981,
vol.50, no.2, 93-108
T.U.T.
50 R
VDS
7.5 V
0
14 V DC
SOURCE
TRANSIENT
GENERATOR
14 V
38 W
LAMP
20 R
100 Hz - 1 kHz
50 % DUTY CYCLE
SQUARE WAVE
t1 = point of turn-on of PowerMOS
t2 = point of turn-off of PowerMOS
Fig. 14 VDS and ID waveforms for the circuit in Fig. 13(a)
66
Introduction Power Semiconductor Applications
Philips Semiconductors
1.2.8 Electrostatic Discharge (ESD) Considerations
Charge accumulates on insulating bodies and voltages as
highas20,000 Vcanbedevelopedby, for example, walking
across a nylon carpet. Electrically the insulator can be
represented by many capacitors and resistors connected
as shown in Fig. 1. The value of the resistors is large and
asaconsequenceit isnot possibleto dischargean insulator
by connecting it straight to ground. An ion source is
necessary to discharge an insulator.
Fig. 1. An electrical representation of a charged
insulator.
Since MOSFETs have a very high input impedance,
typically > 10
9
Ohms at dc, there is a danger of static
electricity building up on the gate source capacitance of the
MOSFET. This can lead to damage of the thin gate oxide.
There are two ways in which the voltage across the gate
source terminals of a MOSFET can be increased to its
breakdown voltage by static electricity.
Firstly a charged object can be brought into contact with
the MOSFETterminals or with tracks electrically connected
to the terminals. This is represented electrically by Fig. 2.
Secondly charge can be induced onto the terminals of the
MOSFET. Electrically this canberepresentedby thecircuit
in Fig. 3.
Fig. 2. The gate source terminals of a MOSFET
connected to a charged insulator.
FromFigs. 2 and 3, it can be seen that, as the total area of
the gate source region increases then the sensitivity of the
devices to ESD will decrease. Hence power MOSFETs
are less prone to ESD than CMOS ICs. Also, for a given
voltage rating, MOSFETs with a larger die area (i.e. the
devices with lower on-resistance) are less probe to ESD
than smaller dice.
Toprevent the destruction of MOSFETs through ESDa two
pronged approach is necessary. Firstly it is important to
minimise the build up of static electricity. Secondly
measures need to be taken to prevent the charging up of
the input capacitance of MOSFETs by static electric
charges.
Fig. 3. A charged insulator inducing charge on the
terminals of a MOSFET.
In the Philips manufacturing facilities many precautions are
taken to prevent ESD damage and these are summarised
below.
Precautions taken to prevent the build up
of static electricity
1. It is important to ensure that personnel working with
MOSFETs are aware of the problems and procedures that
have to be followed. This involves the training of staff.
Areas in which MOSFETs are handled are designated
Special Handling Areas (SHA) and are clearly marked as
such. Checks are made every month that anti-static rules
are being rigourously implemented.
2. Some materials are more prone to the build up of static
electricity than others (e.g. polyester is worse than cotton).
Therefore it is important to minimise the use of materials
that enhance the likelihood of build up of static electricity.
Materials best avoided are acetate, rayon and polyester.
The wearing of overclothing made frompolycotton with 1%
stainless steel fibre is one solution. In clean rooms nylon
overalls which have been antistatically treated are worn.
The use of insulating materials is avoided.
3. Work benches and floors are covered in a static
dissipative material and connected to a common earth. A
high conductive material is not used since it would create
an electric shock hazard and cause too rapid a discharge
of charged material. From the point of view of ESD
materials can be classified according to their conductivity
as shown below.
Insulator
+
+
+
- - -
C11 C12 C13 C1n
R11 R12 R(1n-1)
C11 C12
R11 R12
C1n Cgs
Vgs
Ct
C11 C12
R11 R12
C1n Cgs
Vgs
67
Introduction Power Semiconductor Applications
Philips Semiconductors
insulator (>10
14
ohm/square)
antistatic (10
9
- 10
14
Ohm/square)
static dissipative (10
5
- 10
9
Ohm/square)
conductor (<10
5
Ohm/square).
4. Conducting straps are used to electrically connect
personnel to the point of common earthing. This prevents
the build up of static charge on staff. The connection is
static dissipative to prevent an electric shock hazard.
5. Air plays an important part in the build up of static
electricity.
This is particularly troublesome in a dry atmosphere.
Many of the techniques mentioned above are referred to in
BS5783.
Precautions taken to prevent damage to
MOSFETs by electrostatic build up of
charge
1. When MOSFETs are being transported or stored they
shouldbe inantistatic containers. Thesecontainers should
be totally enclosed to prevent charges being induced onto
the terminals of devices.
2. If MOSFETs have to be left out on the bench, e.g. during
a test sequence, they should be in sockets which have the
gate and source pins electrically connected together.
The precautions that should be taken at the customers’
premisesare the sameas above. It should be remembered
that whenever a MOSFET is touched by someone there is
a danger of damage. The precautions should be taken in
every area in which MOSFETs are tested or handled. In
addition where devices are soldered into circuits with a
soldering iron an earthed bit should always be used.
The probability of device destruction caused by ESD is low
even if only the most rudimentary precautions are taken.
However without such precautions and with large numbers
of PowerMOSdevices now being designed into equipment
a few failures would be inevitable. The adoption of the
precautions outlined will mean that ESD will no longer be
a problem.
68
Introduction Power Semiconductor Applications
Philips Semiconductors
1.2.9 Understanding the Data Sheet: PowerMOS
All manufacturers of power MOSFETs provide a data sheet
for every type produced. The purpose of the data sheet is
primarily to give an indication as to the capabilities of a
particular product. It is also useful for the purpose of
selecting device equivalents between different
manufacturers. In some cases however data on a number
of parameters may be quoted under subtly different
conditions by different manufacturers, particularly on
second order parameters such as switching times. In
addition the information contained within the data sheet
does not always appear relevant for the application. Using
data sheets and selecting device equivalents therefore
requires caution and an understanding of exactly what the
data means and how it can be interpreted. Throughout this
chapter the BUK553-100A is used as an example, this
device is a 100 V logic level MOSFET.
Information contained in the Philips data
sheet
The data sheet is divided into 8 sections as follows:
* Quick reference data
* Limiting values
* Thermal resistances
* Static characteristics
* Dynamic characteristics
* Reverse diode limiting values and characteristics
* Avalanche limiting value
* Graphical data
The information contained within each of these sections is
now described.
Quick reference data
This data is presented for the purpose of quick selection. It
lists what is considered to be the key parameters of the
device such that a designer can decide at a glance whether
the device is likely to be the correct one for the application
or not. Five parameters are listed, the two most important
are the drain-source voltage V
DS
and drain-source on-state
resistance, R
DS(ON)
. V
DS
is the maximum voltage the device
will support between drain and source terminals in the
off-state. R
DS(ON)
is the maximum on-state resistance at the
quoted gate voltage, V
GS
, and a junction temperature of
25 ˚C. (NB R
DS(ON)
is temperature dependent, see static
characteristics). It is these two parameters which provide
a first order indication of the devices capability.
A drain current value (I
D
) and a figure for total power
dissipation are also given in this section. These figures
should be treated with caution since they are quoted for
conditions that are rarely attainable in real applications.
(See limiting values.) For most applications the usable dc
current will be less than the quoted figure in the quick
reference data. Typical power dissipations that can be
tolerated by the majority of designers are less than 20 W
(for discrete devices), depending on the heatsinking
arrangement used. The junction temperature (T
J
) is usually
given as either 150 ˚C or 175 ˚C. It is not recommended
that the internal device temperature be allowed to exceed
this figure.
Limiting values
This table lists the absolute maximum values of six
parameters. The device may be operated right up to these
maximum levels however they must not be exceeded, to
do so may incur damage to the device.
Drain-sourcevoltageanddrain-gate voltagehavethe same
value. The figure given is the maximum voltage that may
be applied between the respective terminals. Gate-source
voltage, tV
GS
, gives the maximum value that may be
allowed between the gate and source terminals. To exceed
this voltage, even for the shortest period can cause
permanent damage to the gate oxide. Two values for the
dc drain current, I
D
, are quoted, one at a mounting base
temperature of 25 ˚C and one at a mounting base
temperature of 100 ˚C. Again these currents do not
represent attainable operating levels. These currents are
the values that will cause the junction temperature to reach
its maximum value when the mounting base is held at the
quoted value. The maximum current rating is therefore a
function of the mounting base temperature and the quoted
figures are just two points on the derating curve ,see Fig.1.
The third current level quoted is the pulse peak value, I
DM
.
PowerMOS devices generally speaking have a very high
peakcurrent handling capability. It is the internal bond wires
which connect to the chip that provide the final limitation.
The pulse width for which I
DM
can be applied depends upon
the thermal considerations (see section on calculating
currents.) The total power dissipation, P
tot
, and maximum
junction temperature are also stated as for the quick
reference data. The P
tot
figure is calculated fromthe simple
quotient given in equation 1 (see section on safe operating
area). It isquotedfor the conditionwherethe mountingbase
temperature is maintained at 25 ˚C. As an example, for the
BUK553-100A the P
tot
figure is 75 W, dissipating this
amount of power while maintaining the mounting base at
25 ˚C would be a challenge! For higher mounting base
temperatures the total power that can be dissipated is less.
69
Introduction Power Semiconductor Applications
Philips Semiconductors
Fig.1 Normalised continuous drain current.
ID% = 100 . I
D
/I
D25 ˚C
= f(T
mb
); conditions: V
GS
≥ 5 V
Obviously if the mounting base temperature was made
equal to the max permitted junction temperature, then no
power could be dissipated internally. A derating curve is
given as part of the graphical data, an example is shown in
Fig.2 for a device with a limiting T
j
of 175 ˚C.
Fig.2 Normalised power dissipation.
PD% = 100 P
D
/P
D 25 ˚C
= f(T
mb
)
Storage temperature limits are also quoted, usually
between -40 /-55 ˚C and +150 /+175 ˚C. Both the storage
temperature limits and the junction temperature limit are
figures at which extensive reliability work is performed by
our Quality department. To exceed these figures will cause
a reduction in long-term reliability.
Thermal resistance.
For non-isolated packages two thermal resistance values
are given. The value fromjunctionto mounting base (R
thj-mb
)
indicates howmuch the junction temperature will be raised
above the temperature of the mounting base when
dissipating a given power. Eg a BUK553-100A has a R
thj-mb
of 2 K/W, dissipating 10 W, the junction temperature will be
20 ˚C above the temperature of its mounting base. The
other figure quoted is from junction to ambient. This is a
much larger figure and indicates how the junction
temperature will rise if the device is NOT mounted on a
heatsink but operated in free air. Eg for a BUK553-100A,
R
thj-a
= 60 K/W, dissipating 1 W while mounted in free air
will produce a junction temperature 60 ˚C above the
ambient air temperature.
For isolated packages, (F-packs) the mounting base (the
metal plate upon which the silicon chip is mounted) is fully
encapsulated in plastic. Therefore it is not possible to give
a thermal resistance figure junction to mounting base.
Instead a figure is quoted from junction to heatsink, R
thj-hs
,
whichassumes the useof heatsinkcompound. Careshould
be taken when comparing thermal resistances of isolated
and non-isolated types. Consider the following example:
The non-isolated BUK553-100A has a R
thj-mb
of 2 K/W. The
isolatedBUK543-100Ahas aR
thj-hs
of 5 K/W. Thesedevices
have identical crystals but mounted in different packages.
At first glance the non-isolated type might be expected to
offer much higher power (and hence current) handling
capability. However for the BUK553-100A the thermal
resistance junction to heatsink has to be calculated, this
involves adding the extra thermal resistance between
mounting base and heatsink. For most applications some
isolation is used, such as a mica washer. The thermal
resistance mounting base to heatsink is then of the order
2 K/W. The total thermal resistance junction to heatsink is
therefore
R
thj-hs
(non isolated type) = R
thj-mb
+ R
thmb-hs
= 4 K/W
It canbe seen that the real performance difference between
the isolated and non isolated types will not be significant.
Static Characteristics
The parameters in this section characterise breakdown
voltage, threshold voltage, leakage currents and
on-resistance.
A drain-source breakdown voltage is specified as greater
than the limiting value of drain-source voltage. It can be
measured on a curve tracer, with gate terminal shorted to
the source terminal, it is the voltage at which a drain current
of 250 µA is observed. Gate threshold voltage, V
GS(TO)
,
indicates the voltage required on the gate (with respect to
the source) to bring the device into its conducting state. For
logic level devices this is usually between 1.0 and 2.0 V
and for standard devices between 2.1 and 4 V.
0 20 40 60 80 100 120 140 160 180
Tmb / C
ID%
Normalised Current Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140 160 180
Tmb / C
PD%
Normalised Power Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
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Introduction Power Semiconductor Applications
Philips Semiconductors
Fig.3 Typical transfer characteristics.
I
D
= f(V
GS
); conditions: V
DS
= 25 V; parameter T
j
Useful plots in the graphical data are the typical transfer
characteristics (Fig.3) showing drain current as a function
of V
GS
and the gate threshold voltage variation with junction
temperature (Fig.4). An additional plot also provided is the
sub-threshold conduction, showing how the drain current
varies with gate-source voltage below the threshold level
(Fig.5).
Off-state leakage currents are specified for both the
drain-source and gate-source under their respective
maximum voltage conditions. Note, although gate-source
leakage current is specified in nano-amps, values are
typically of the order of a few pico-amps.
Fig.4 Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
Fig.5 Sub-threshold drain current.
I
D
= f(V
GS
); conditions: T
j
= 25 ˚C; V
DS
= V
GS
Fig.6 Typical output characteristics, T
j
= 25 ˚C.
I
D
= f(V
DS
); parameter V
GS
The drain-source on-resistance is very important. It is
specifiedat agate-sourcevoltageof 5 Vfor logic level FETs
and 10 V for a standard device. The on-resistance for a
standard MOSFET cannot be reduced significantly by
increasing the gate source voltage above 10 V. Reducing
the gate voltage will however increase the on-resistance.
For the logic level FET, the on-resistance is given for a gate
voltage of 5 V, a further reduction is possible however at
gate voltages up to 10 V, this is demonstrated by the output
characteristics, Fig.6 and on-resistance characteristics,
Fig.7 for a BUK553-100A. .
0 2 4 6 8
BUK543-100A
VGS / V
15
10
5
0
ID / A
Tj / C = 25 150
0 0.4 0.8 1.2 1.6 2 2.4
VGS / V
ID / A
1E-01
1E-02
1E-03
1E-04
1E-05
1E-06
SUB-THRESHOLD CONDUCTION
2 % typ 98 %
0 2 4 6 8 10
BUK553-100A
VDS / V
24
20
16
12
8
4
0
2
3
4
5
7
10
ID / A
VGS / V =
-60 -20 20 60 100 140 180
Tj / C
VGS(TO) / V
2
1
0
max.
typ.
min.
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Introduction Power Semiconductor Applications
Philips Semiconductors
The on-resistance is a temperature sensitive parameter,
between 25 ˚C and 150 ˚C it approximately doubles in
value. A plot of normalised R
DS(ON)
versus temperature
(Fig.8) is included in each data sheet. Since the MOSFET
will normally operate at a T
j
higher than25 ˚C, whenmaking
estimates of power dissipation in the MOSFET, it is
important to take into account the higher R
DS(ON)
.
Fig.7 Typical on-state resistance, T
j
= 25 ˚C.
R
DS(ON)
= f(I
D
); parameter V
GS
Fig.8 Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 ˚C
= f(T
j
); I
D
= 6.5 A; V
GS
= 5 V
Dynamic Characteristics
These include transconductance, capacitance and
switching times. Forward transconductance, g
fs
, is
essentially the gain parameter which indicates the change
in drain current that will result from a fluctuation in gate
voltage when the device is saturated. (NB saturation of a
MOSFET refers to the flat portion of the output
characteristics.) Fig.9 shows howg
fs
varies as a function of
the drain current for a BUK553-100A.
Fig.9 Typical transconductance, T
j
= 25 ˚C.
g
fs
= f(I
D
); conditions: V
DS
= 25 V
Fig.10 Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
Capacitances are specifiedby most manufacturers, usually
in terms of input, output and feedback capacitance. The
values quoted are for a drain-source voltage of 25 V.
However this is only part of the story as the MOSFET
capacitances are strongly voltage dependent, increasing
asdrain-sourcevoltageisreduced. Fig.10showshowthese
capacitances vary with voltage. The usefulness of the
capacitance figures is limited. The input capacitance value
gives only a rough indication of the charging required by
the drive circuit. Perhaps more useful is the gate charge
information an example of which is shown in Fig.11. This
plot shows how much charge has to be input to the gate to
0 2 4 6 8 10 12 14 16 18 20
BUK543-100A
ID / A
gfs / S
10
9
8
7
6
5
4
3
2
1
0
0 4 8 12 16 20 24 28
BUK553-100A
ID / A
0.5
0.4
0.3
0.2
0.1
0
2.5 3 3.5 4
4.5
5
10
RDS(ON) / Ohm
VGS / V =
0 20 40
VDS / V
C / pF
Ciss
Coss
Crss
10
100
1000
10000
BUK5y3-100
-60 -20 20 60 100 140 180
Tj / C
Normalised RDS(ON) = f(Tj)
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
a
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Introduction Power Semiconductor Applications
Philips Semiconductors
reach a particular gate-source voltage. Eg. to charge a
BUK553-100A to V
GS
= 5 V, starting from a drain-source
voltage of 80 V, requires 12.4 nc. The speed at which this
charge is to be applied will give the gate circuit current
requirements. More information on MOSFET capacitance
is given in chapter 1.2.2.
Resistive load switching times are also quoted by most
manufacturers, however extreme care should be taken
when making comparisons between different
manufacturers data. The speed at which a power MOSFET
can be switched is essentially limited only by circuit and
package inductances. The actual speed in a circuit is
determined by how fast the internal capacitances of the
MOSFET are charged and discharged by the drive circuit.
The switching times are therefore extremely dependent on
the circuit conditions employed; a lowgate drive resistance
will provide for faster switching and vice-versa. The Philips
data sheet presents the switching times for all PowerMOS
witharesistor between gateandsourceof 50 Ω. The device
isswitchedfromapulsegenerator withasourceimpedance
also of 50 Ω. The overall impedance of the gate drive circuit
is therefore 25 Ω.
Fig.11 Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); conditions: I
D
= 13 A; parameter V
DS
Also presented under dynamic characteristics are the
typical inductances of the package. These inductances
become important when very high switching speeds are
employed such that large dI/dt values exist in the circuit.
Eg. turning-on 30 A within 60 ns gives a dI/dt of 0.5 A/ns.
The typical inductance of the source lead is 7.5 nH, from
V = -L*dI/dt the potential drop from the source bond pad
(point where the source bond wire connects to the chip
internally) to the bottomof the source lead would be 3.75 V.
Normallyastandarddevice will bedrivenwithagate-source
voltage of 10 V applied across the gate and source
terminals, the actual voltage gate to source on the
semiconductor however would only be 6.25 V during the
turn-on period! The switching speed is therefore ultimately
limited by package inductance.
Reverse diode limiting values and
characteristics
The reverse diode is inherent in the vertical structure of the
power MOSFET. In some circuits this diode is required to
performauseful function. For this reasonthecharacteristics
of the diode are specified. The forward currents permissible
in the diode are specified as ’continuous reverse drain
current’ and ’pulsed reverse drain current’. The forward
voltage drop of the diode is also provided together with a
plot of the diode characteristic, Fig.12. The switching
capability of the diode is given in terms of the reverse
recovery parameters, t
rr
and Q
rr
.
Fig.12 Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= ) V; parameter T
j
Because the diode operates as a bipolar device it is subject
to charge storage effects. This charge must be removed for
the diode to turn-off. The amount of charge stored is given
byQ
rr
, the reverserecovery charge, thetimetakentoextract
the charge is given by t
rr
, the reverse recovery time. NB. trr
depends very much on the -dI
f
/dt in the circuit, t
rr
is specified
in data at 100 A/µs.
Avalanche limiting value
This parameter is an indication as to the ruggedness of the
product in terms of its ability to handle a transient
overvoltage, ie the voltage exceeds the drain-source
voltage limiting value and causes the device to operate in
an avalanche condition. The ruggedness is specified in
terms of a drain-source non-repetitive unclamped inductive
turn-off energy at a mounting base temperature of 25 ˚C.
This energy level must be derated at higher mounting base
temperatures as shown in Fig.13. NB. this rating is
0 1 2
BUK553-100A
VSDS / V
30
20
10
0
IF / A
Tj / C = 150 25
0 2 4 6 8 10 12 14 16 18 20
QG / nC
VGS / V
12
10
8
6
4
2
0
VDS / V =20
80
BUK553-100
73
Introduction Power Semiconductor Applications
Philips Semiconductors
non-repetitive which means the circuit should not be
designed to force the PowerMOS repeatedly into
avalanche. This rating is only to permit the device to survive
if exceptional circuit conditions arise such that a transient
overvoltage occurs.
The new generation of Philips Medium Voltage MOSFETs
also feature a repetitive ruggedness rating. This rating is
specified in terms of a drain-source repetitive unclamped
inductive turn-off energy at a mounting base temperature
of 25 ˚C, andindicates that thedevicesareabletowithstand
repeated momentary excursions into avalanche
breakdown provided the maximum junction temperature is
not exceeded. (Amoredetailedexplanationof Ruggedness
is given in chapter 1.2.7.)
Fig.13. Normalised avalanche energy rating.
W
DSS
% = f(T
mb
); conditions: I
D
= 13 A
Safe Operating Area
A plot of the safe operating area is presented for every
PowerMOS type. Unlike bipolar transistors a PowerMOS
exhibits no second breakdown mechanism. The safe
operating area is therefore simply defined from the power
dissipationthat will cause the junction temperature to reach
the maximum permitted value.
Fig.14 shows the SOA for a BUK553-100. The area is
bounded by the limiting drain source voltage, limiting
current values and a set of constant power curves for
various pulse durations. The plots in data are all for a
mounting base temperature of 25 ˚C. The constant power
curves therefore represent the power that raises the
junction temperature by an amount T
jmax
- T
mb
, ie. 150 ˚C
for a device with a limiting T
j
of 175 ˚C and 125 ˚C for a
device with a limiting T
j
of 150 ˚C. . Clearly in most
applications the mounting base temperature will be higher
than 25 ˚C, the SOA would therefore need to be reduced.
The maximum power curves are calculated very simply.
Fig.14 Safe operating area. T
mb
= 25 ˚C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
The dc curve is based upon the thermal resistance junction
tomountingbase(junctiontoheatsinkinthe caseof isolated
packages), which issubstituted intoequation 1. The curves
for pulsed operationassumeasingleshot pulseandinstead
of thermal resistance, a value for transient thermal
impedance is used. Transient thermal impedance is
supplied as graphical data for each type, an example is
shown in Fig.15. For calculation of the single shot power
dissipation capability, a value at the required pulse width is
read from the D = 0 curve and substituted in to equation 2.
(A more detailed explanation of transient thermal
impedance and how to use the curves can be found in
chapter 7.)
Examples of how to calculate the maximum power
dissipation for a 1 ms pulse are shown below. Example 1
calculatesthe maximumpower assuming aT
j
of 175 ˚Cand
T
mb
of 25 ˚C. This power equates to the 1 ms curve on the
SOA plot of Fig.14. Example 2 illustrates how the power
capability is reduced if T
mb
is greater than 25 ˚C.
Example 1: 1 ms pulse at 25 ˚C for a BUK553-100A
Z
th
= 0.32 K/W, T
jmax
= 175 ˚C, T
mb
= 25 ˚C
1 100
VDS / V
ID / A
100
10
1
0.1
10 us
100 us
1 ms
10 ms
R
D
S
(
O
N
)

=

V
D
S
/
I
D
100 ms
DC
tp =
BUK553-100
10
B
A
20 40 60 80 100 120 140 160 180
Tmb / C
120
110
100
90
80
70
60
50
40
30
20
10
0
WDSS%
P
tot (dc)
·
T
jmax
− T
mb
R
thj − mb
1
P
tot (pulse)
·
T
jmax
− T
mb
Z
thj − mb
2
74
Introduction Power Semiconductor Applications
Philips Semiconductors
Fig.15 Transient thermal impedance.
Z
thj-mb
= f(t); parameter D = t
p
/T
The 469 Wline is observed on Fig.13, (4.69 A@100 Vand
15.6 A @ 30 V etc)
Example 2: 1 ms pulse at 75 ˚C for a BUK553-100A
Z
th
= 0.32 K/W, T
jmax
= 175 ˚C, T
mb
= 75 ˚C
Therefore with a mounting base temperature of 75 ˚C the
maximumpermissible power dissipation is reduced by one
third compared with the 25 ˚C value on the SOA plot.
Calculating Currents
The current ratings quoted in the data sheet are derived
directly from the maximum power dissipation.
substituting for P
tot
from equation 1
To calculate a more realistic current it is necessary to
replace T
jmax
in equation 4 with the desired operating
junction temperature and T
mb
with a realistic working value.
It is generally recommended that devices are not operated
continuously at T
jmax
. For reasons of long term reliability,
125 ˚C is a more suitable junction operating temperature.
A value of T
mb
between 75 ˚C and 110 ˚C is also a more
typical figure.
As an example a BUK553-100A is quoted as having a dc
current rating of 13 A. Assuming a T
mb
of 100 ˚C and
operating T
j
of 125 ˚C the device current is calculated as
follows:
From Fig.8
R
thj-mb
= 2 K/W, using equation 4
The device could therefore conduct 6.3 A under these
conditions which equates to a 12.5 W power dissipation.
Conclusions
The most important information presented in the data sheet
is the on-resistance and the maximum voltage
drain-source. Current values and maximum power
dissipation values should be viewed carefully since they
are only achievable if the mounting base temperature is
held to 25 ˚C. Switching times are applicable only for the
specific conditions described in the data sheet, when
making comparisons between devices from different
manufacturers, particular attention should be paid to these
conditions.
I
D
(@T
mb
) ·
¹
'
¹
T
jmax
− T
mb
R
thj − mb
⋅ R
DS(ON)
(@T
jmax
)
¹
;
¹
1
2
4
1E-07 1E-05 1E-03 1E-01 1E+01
t / s
Zth j-mb / (K/W)
1E+01
1E+00
1E-01
1E-02
1E-03
0
0.5
0.2
0.1
0.05
0.02
BUKx53-lv
D =
tp
tp
T
T
P
t
D
D =
R
DS(ON)
(@125
o
C) · 1.75 ⋅ R
DS(ON)
(@25
o
C) · 1.75 ⋅ 0.18 · 0.315Ω
P
max(1ms pulse)
·
175 − 25
0.32
· 469W
I
D
·
¹
'
¹
25
2 ⋅ 0.315
¹
;
¹
1
2
· 6.3A
P
max(1ms pulse)
·
175 − 75
0.32
· 312W
I
D
(@T
mb
)
2
⋅ R
DS(ON)
(@T
jmax
) · P
tot
3
75
Introduction Power Semiconductor Applications
Philips Semiconductors
High Voltage Bipolar Transistor
77
Introduction Power Semiconductor Applications
Philips Semiconductors
1.3.1 Introduction To High Voltage Bipolar Transistors
This section introduces the high voltage bipolar transistor
and discusses its construction and technology. Specific
transistor properties will be analysed in more detail in
subsequent sections and in Chapter 2, section 2.1.2.
Basic Characteristics
High voltage transistors are almost exclusively used as
electronic switches. Therefore, the characteristics of these
devices are given for the on state, the off state and the
transition between the two i.e. turn-on and turn-off.
The relative importance of the V
CES
and V
CEO
ratings usually
depends on the application. In a half bridge converter, for
instance, the rated V
CEO
is the dominant factor, whilst in a
forward converter V
CES
is important. Which rating is most
applicablemay also depend on whether a slowrise network
or snubber is applied (see section 1.3.3).
The saturation properties in the on state and the switching
times are given at a specific collector current called the
collector saturation current, I
Csat
. It is this current which is
normally considered to be the practical working current of
the device. If this device is used at higher currents the total
dissipation may be too high, while at low currents the
storage time is long. At I
Csat
the best compromise is present
for the total spread of products. The value of the base
current used to specify the saturation and switching
properties of the device is called I
Bsat
which is also an
important design parameter. As the device requirements
can differ per application a universal I
Bsat
cannot be quoted.
Device Construction
A drawing of a high voltage transistor, in this case a fully
isolated SOT186 F-pack, is shown in Fig. 1 with the plastic
encapsulation stripped away. This figure shows the three
leads, two of which are connected with wires to the
transistor chip. The third lead makes contact with the
mounting base on which the crystal is soldered, enabling
good thermal contact with a heatsink. It is the transistor
package which basically determines the thermal properties
of the device. The electrical properties are mainly
determined by the design of the chip inside.
A cross-section of a transistor chip is given in Fig. 2. Here
the transistor structure can be recognised with the emitter
and the base contacts at the top surface and the collector
connected to the mounting base. The thickest part in the
drawing is the collector n- region across which the high
voltage will be supported in the off state. This layer is of
Fig. 1 Cut-away View of a High Voltage Transistor
primeimportance in the determinationof thecharacteristics
of the device. Below the n- region is an extra n+ layer,
needed for a good electrical contact to the heatsink.
Fig. 2 Cross-section of a High Voltage Transistor
Above the collector is the base p layer, and the emitter n+
layer with their respective metallic contacts on top. It is
important to realise that the characteristics of the device
are determined by the active area, this is the area
underneath the emitter where the collector current flows
and the high voltage can be developed. The active area of
two devices with the same chip size may not be the same.
nickel-plated
copper lead
frame
passivated
chip
aluminium
wires
tinned copper
leads
ultrasonic
wire bonds
Base Collector Emitter
base emitter
250V
600V
850V
1150V
n-
n+
n+
p
n+
n-
special glass
79
Introduction Power Semiconductor Applications
Philips Semiconductors
Fig. 3 Maximum Voltages vs. n- Collector Thickness
N+
P
N-
N+
N+
P
N-
N+
N+
P
N-
N+
TIP49
450 V
BUT11
850 V
BU2508A
1500 V
In addition to the basic collector-base-emitter structure
manufacturers have to add electrical contacts, and special
measures are needed at the edges of the crystal to sustain
the design voltage. This introduces another very important
feature, the high voltage passivation. The function of the
passivation, (theexampleshownhereisreferredtoasglass
passivation), is to ensure that the breakdown voltage of the
device is determined by the collector-base structure and
not by the construction at the edges. If no special
passivation was used the breakdown voltage might be as
lowas 50%of the maximumvalue. Manufacturersoptimise
the high voltage passivation and much work has also been
done to ensure that its properties do not change in time.
Process Technology
There are several ways to make the above structure. The
starting material can be an n- wafer where first an n+
diffusion is made in the back, followed by the base (p) and
emitter (n+) diffusions. This is the well known triple diffused
process.
Another way is to start with an n+ wafer onto which an n-
layer is deposited using epitaxial growth techniques. A
further two diffusions (base and emitter) forms the basic
transistor structure. This is called a double diffused
epitaxial process.
Another little used technology is to grow, epitaxially, the
base p-type layer onto an n-/n+ wafer and then diffuse an
n+ emitter. This is referred to as a single diffused epi-base
transistor.
The question often asked is which is the best technology
for high voltage bipolar transistors ? The basic difference
in the technologies is the concentration profile at the n-/n+
junction. For epitaxial wafers the concentration gradient is
much more steeper fromn- to n+ than it is for back diffused
wafers. There are more applications where a smoother
concentration gradient gives the better performance.
Manufacturers utilising epitaxial techniques tend to use
buffer layers between the n- and n+ to give smoother
concentration gradients. Another disadvantage of epitaxial
processing is cost: back diffused wafers are much cheaper
than equivalent high voltage epitaxial wafers.
The process technology used to create the edge
passivationisalso diverse. The expression "planar" isused
to indicate the passivation technique which is most
commonly used in semiconductors. This involves the
diffusion of additional n-type rings around the active area
of the device which give an even electric field distribution
at the edge. However, for high voltage bipolar transistors
planar passivation is relatively new and the long term
reliability has yet to be completely optimised. For high
voltage bipolar transistors the most common passivation
systems employ a deep trough etched, or cut, into the
device with a special glass coating. Like the planar
passivation, the glass passivation ensures an even
distribution of the electric field around the active area.
Maximum Voltage and Characteristics
Fig. 4 Switching Times and h
FE
vs. V
CEO
200 400 800
15
25
50 10
5
2.5
30 60 120
hFEsat hFE0
Width of n- layer (um)
0.8
0.4
0.2 1.5
3
6
tf ts
Vceo (V)
(us)
hFE
ts, tf
80
Introduction Power Semiconductor Applications
Philips Semiconductors
High voltage and low voltage transistors differ primarily in
thethickness andresistivity of the n- layer. As the thickness
and resistivity of this layer is increased, the breakdown
voltage goes up. The difference over the range of Philips
high voltage transistors of different voltages is illustrated in
Fig. 3. The TIP49 has a V
CBO
= 450 V, the BUT11 has a
V
CES
= 850 V, while the BU2508A can be used up to
voltages of 1500 V.
The penalty for increasing the n- layer is a decrease in high
current h
FE
and an in switching times. The graph in Fig. 4
points this out by giving both switching times and h
FE
as a
functionof the breakdownvoltage. The valuesgivenshould
be used as a guide to illustrate the effect. The effect can
be compensated for by having a bigger chip.
Applications of High Voltage Transistors
High voltage transistors are mainly used as the power
switch in energy conversion systems. What is common to
all thesesystems, isthat acurrent flowsthroughaninductor,
thus storing energy in its core. When the current is
interrupted by turning off the power switch, the energy must
be transferred one way or another. Very often the energy
is converted into an electrical output e.g. in switched mode
power supplies and battery chargers.
Two special applications are electronic fluorescent lamp
ballasts and horizontal deflection of the electron beam in
TV’sandmonitors. Inthe ballast, anac voltageisgenerated
to deliver energy to a fluorescent lamp. In the TV and
monitor a sawtooth current in the deflection coil sweeps the
beamacross the screen fromleft to right and back again in
a much shorter blanking, or flyback, period
Other ways to transfer the energy are ac and dc motor
control where the output is delivered as movement, or
induction heating where the output is delivered in the form
of heat.
81
Introduction Power Semiconductor Applications
Philips Semiconductors
1.3.2 Effects of Base Drive on Switching Times
Introduction
The switching processes that take place within a high
voltage transistor are quite different from those in a small
signal transistor. This section describes, figuratively, what
happens within high voltage transistors under various base
drive conditions. After an analysis of the charges that are
present in a high voltage transistor, the switch-off process
is described. Then comparisons are made of switching for
various forward and reverse base drive conditions. A
fundamental knowledge of basic semiconductor physics is
assumed.
Charge distribution within a transistor
An off-state transistor has no excess charge, but to enable
transistor conduction in the on-state excess charge build
up within the device takes place. There are three distinct
charge distributions to consider that control the current
through the device, see Fig. 1. These charge distributions
are influenced by the level of collector-emitter bias, V
CE
,
and collector current, I
C
, as shown in Fig. 2.
Forward biasing the base-emitter (BE) junction causes a
depletion layer to form across the junction. As the bias
exceeds the potential energy barrier (work function) for that
junction, current will flow. Electrons will flow out of the
emitter into the base and out of the base contact. For high
voltage transistors the level of BE bias is much in excess
of the forward bias for a small signal transistor. The bias
generates free electron-hole pairs in the base-emitter
leadingtoa concentration of electrons in the base in excess
of the residual holeconcentration. This producesanexcess
charge in the base, Qb, concentrated underneath the
emitter.
Fig. 1. On-state Charge Flow
Not only is there an excess charge in the base near the
emitter junction but the injection and base width ensure that
this excess charge is also present at the collector junction.
Applying a load in series with the collector and a dc supply
between load and emitter will trigger some sort of collector
current, I
C
. The level of I
C
is dependent on the base current,
I
B
, the load and supply voltage. For a certain I
B
, lowvoltage
supply and high impedance load there will be a small I
C
. As
the supply voltage rises and/or the load impedance falls so
I
C
will rise. As I
C
rises so the collector-emitter voltage, V
CE
,
falls. The I
C
is composed mainly of the excess emitter
electrons that reach the base-collector junction (BC). This
electron concentration will continue into the collector
inducing an excess charge in the collector, Qc.
The concentration of electrons decreases only slightly from
the emitter-base junction to some way into the collector. In
effect, thebasewidthextendsintothecollector. Decreasing
V
CE
below V
BE
causes the BC junction to become forward
biased throughout. This creates a path for electrons from
the collector to be driven back into the base and out of the
base contact. This electron flow is in direct opposition to
the established I
C
. With no change in base drive, the
ultimate effect is a reduction in I
C
. This is the classical
‘saturation’ region of transistor operation. As V
CE
falls so
the BC forward bias increases leading to an excess of
electrons at the depletion layer edge in the collector
beneath the base contact. This concentration of electrons
leads to an excess charge, Qd.
The charge flows and excess charges Qb, Qc and Qd are
shown in Fig. 1. An example of the excess charge
distributions for fixed I
C
and I
B
are shown in Fig. 2.
Fig. 2. On-state Charge Distribution (example)
The switching process of a transistor
Removingthebias voltage, V
BE
, will causethe electron-hole
pairs to recombine and the excess charge regions to
disappear. Allowing this to happen just by removing V
BE
Q
Qd
Qc
Qb
Vce (V)
Ic = 5 A
Ib = 1 A
B E B
Qd Qc
Qb
P
N+
N-
N+
C
83
Introduction Power Semiconductor Applications
Philips Semiconductors
takes a long time so usually turn-off is assisted in some
way. It is common practice to apply a negative bias
(typically 5V) to the base, via a resistor and/or inductor,
inducing a negative current that draws the charge out of
the transistor. In the sequence that follows, four phases of
turn-off can be distinguished (see Fig. 3).
1. First the applied negative bias tries to force a negative
bias across the BC junction. The BC electron flow now
stops andthe charge Qd dissipates as the bias nowcauses
the base holes out through the base contact and the
collector electrons back into the bulk collector. When the
BC was forward biased this current had the effect of
reducing the total collector current, so nowthe negative V
BE
can cause the total collector current to increase (this also
dependsontheload). Althoughthebasehasbeenswitched
off the load current is maintained by the stored charge
effects; this is called the transistor storage time, t
s
.
During this stage the applied negative bias appears as a
positive V
BE
at the device terminals as the internal charge
distributions create an effective battery voltage. Depleting
the charge, of course, lowers this effective battery voltage.
2. The next phase produces a reduction in both Qb, Qc
and, consequently, I
C
. The BCjunction is no longer forward
biased and Qd has dissipated to provide the negative base
current. The inductance in series in the base path requires
acontinuationinthebase current. Theinjectionof electrons
into the base opposes the established electron flow from
emitter to collector via the base. At first the opposing
electron flows cancel at the edge of the emitter nearest the
base contacts. This reduces both Qb and Qc in this region.
QbandQc becomeconcentrated inthe centreof the emitter
area. The decrease in I
C
is called the fall time, t
f
.
3. Now there is an extra resistance to the negative base
current as the electrons flow through the base under the
emitter area. This increase in resistance limits the increase
in amplitude of the negative base current. As Qb and Qc
reducefurther so the resistanceincreases andthe negative
base current reaches its maximum value.
As Qb and Qc tend to zero the series inductance ensures
that negative base current must be continued by other
means. The actual mechanismis by avalanche breakdown
of the base-emitter junction. This now induces a negative
V
BE
which is larger than the bias resulting in a reverse in
polarity of the voltage across the inductance. This in turn
triggers a positive rate of change in base current. The
negative base current now quickly rises to zero while the
base-emitter junction is in avalanche breakdown.
Avalanchebreakdown ceases when the base current tends
to zero and the V
BE
becomes equal to the bias voltage.
Fig. 3. Phases during turn-off
B E B
Qd Qc
Qb
P
N+
N-
N+
C
B E B
Qc
Qb
P
N+
N-
N+
C
B E B
P
N+
N-
N+
C
0 Qb
Qc 0
B E B
P
N+
N-
N+
C
Qr
84
Introduction Power Semiconductor Applications
Philips Semiconductors
4. If a very small series base inductor is used with the 5V
reverse bias then the base current will have a very fast rate
of change. This will speed up the phases 1 to 3 and,
therefore, the switching times of the transistor. However,
there is a point when reducing the inductor further
introduces another phase to the turn-off process. High
reverse base currents will draw the charges out closest to
the base contact and leave a residual charge trapped deep
in the collector regions furthest away from the base. This
charge, Qr, must be removed before the transistor returns
fully to the off-state. This is detected as a tail to I
C
at the
end of turn-off with a corresponding tail to the base current
as it tends to zero.
The switching waveforms for a BUT11 in a forward
converter are given in Fig. 4 where the four phases can
easily be recognised. (Because of the small base coil used
both phases in the fall time appear clearly!).
1 - Removal of Qd until t ≈ 0.7 µs ts
2 - Qc and Qb decrease until t ≈ 1.7 µs ts
3 - Removal of Qb and Qc until t ≈ 1.75 µs tf
4 - Removal of Qr until t ≈ 1.85 µs tf
Note the course of V
BE
: first the decrease in voltage due to
the base resistance during current contraction and second
(because a base coil has been used) the value of V
BE
is
clamped by the emitter-base breakdown voltage of the
transistor. It should be remembered that because
breakdown takes place near the surface and not in the
active region no harm comes to the transistor.
Fig. 4. BUT11 waveforms at turn-off
The influence of forward drive on stored
charge
Fig. 5 shows how, for a transistor in the on-state, at a fixed
value of I
C
and I
B
the three charges Qb, Qc and Qd depend
upon V
CE
. The base charge, Qb, is independent of V
CE
, it
primarily depends upon V
BE
. For normal base drive
conditions, a satisfactory value for V
CEsat
is obtained,
indicated by N in Fig. 5, and moderate values for Qc and
Qd result.
Fig. 5. Charges as a function of V
CE
With the transistor operating in the active region, for
V
CE
≥ 1V, there will be a charge Qc but no charge Qd. This
is indicated by D in Fig. 5. At the other extreme, with the
transistor operatinginthesaturationregionQcwill behigher
and Qd will be higher than Qc. This is indicated by O in
Fig. 5. Inthis conditionthereare moreexcess electron-hole
pairs to recombine at switch off.
Increasing I
B
causes Qb to increase. Also, for a given I
C
,
Qc and Qd will be higher as V
CE
reduces. Therefore, for a
givenI
C
, the storedchargeinthe transistor canbecontrolled
by the level of I
B
. If the I
B
is too low the V
CE
will be high with
lowQc and zero Qd, as D in Fig. 5. This condition is called
underdrive. If the I
B
is too high the V
CE
will be lowwith high
Qc and Qd, as O in Fig. 5. This condition is called
overdrive. The overdrive condition (high forward drive)
gives high stored charge and the underdrive condition (low
forward drive) gives low stored charge.
Deep-hole storage
As the high free electron concentration extends into the
base and collector regions ther must be an equivalent hole
concentration. Fig. 6 shows results obtained from a
computer model which illustrates charge storage as a
function of V
CE
. Here the hole density, p(x), is given as a
function of depth inside the active area; the doping profile
is also indicated. It can be seen that overdrive, O, causes
holes to be stored deep in the collector at the collector -
substrate junction known as "deep-hole storage", this is the
main reason for the increase in residual charge, Qr.
Q
Qd
Qc
Qb
0.2 0.5 1.0 Vce (V)
O N D
Ic
Vce
Ib
Vbe
1 A/div
1 A/div
200 V/div
5 V/div
0.5 us/div
85
Introduction Power Semiconductor Applications
Philips Semiconductors
During overdrive not only Qd becomes very big but also
holes are stored far away fromthe junction: this thus leads
not only to a longer storage time, but also to a large Qr
resulting in tails in the turn-off current.
Fig. 6. Deep hole storage in the collector region
Desaturation networks
Adesaturation network, as shown in Fig. 7, limits the stored
charge in the transistor and, hence, aids switching. The
series base diode, D1 means that the applied drive voltage
nowhas to be V
BE
plus the V
F
of D1. The anti-parallel diode,
D2 is necessary for the negative I
B
at turn-off. As V
CE
reduces below V
BE
+ V
F
so the external BC diode, D3,
becomes forward biased. D3 now conducts any further
increase in drive current away from the base and into the
collector. Transistor saturation is avoided.
Withadesaturation network the charge Qdequals zero and
the charge Qc is minimised. When examining the
distribution of the charge in the collector region (see Fig. 6)
it can be seen that deep hole storage does not appear.
Desaturation networks are a common technique for
reducing switching times.
It should be realised that there is a drawback attached to
operatingout of saturation: increaseddissipationduringthe
on-state. Base drive design often requires a trade-off
between switching and on-state losses.
Fig. 7. Desaturation network
(Baker clamp)
Breakdown voltage vs. switching times
For a higher breakdown voltage transistor the n- layer (see
Fig. 1) will be thicker and of higher resistivity (ie a lower
donor atom concentration). This means that when
comparing identical devices the values for Qd and Qc will
be higher, for a given I
C
, in the device with the higher
breakdown voltage.
In general:
- the higher BV
CEO
the larger Qd and Qc will be;
- during overdrive Qd is very high and there is a charge
located deep in the collector region (deep hole storage);
- when desaturated Qd equals zero and there is no deep
hole storage: Qc is minimised for the I
C
.
Turn-off conditions
Various ways of turning off a high voltage transistor are
used but the base should always be switched to a negative
supply via an appropriate impedance. If this is not done,
(ie turn-off is attempted by simply interrupting the base
current), very long storage times result and the collector
voltage increases, while the collector current falls only
slowly. A very high dissipation and thus a short lifetime of
the transistor are the result. The charges must be removed
using a negative base current.
a) Hard turn-off
The technique widely used, especially for low voltage
transistors, is to switch directly to a negative voltage, (see
Fig. 8a). In the absence of a negative supply, this can be
achieved with an appropriate R-C network (Fig. 8b). Also
applying an "emitter-drive" (Fig. 8c) with a large base
capacitor in fact is identical to hard-turn-off.
The main drawback for high voltage transistors is that the
base charge Qb is removed too quickly, leaving a high
residual charge. This leads to current tails (long fall times)
and high dissipation. It depends upon what state the
transistor isin(overdrivenor desaturated), whether this way
of turn-off isbest. It also depends upon the kindof transistor
that must be switched off. If it is a lower voltage transistor
(BV
CEO
≤ 200V) then this will work very well because the
charges Qc and Qd will be rather low. For transistors with
a higher breakdown voltage, hard turn-off will yield the
shortest storagetime at the cost, however, of higher turn-off
dissipation (longer t
f
).
b) Smooth turn-off
To properly turn-off a high voltage transistor a storage time
tominimiseQdandQcisrequired, andthenalargenegative
base current to give a short fall time.
0 80 160 40 20 60 120 100 140
20
10
12
14
16
18
10
10
10
10
10
10
Vce = 1 V 0.5 V
0.2 V
p(x) at J = 140 A / cm2
p(x)
x (um)
E
B
C
D N
O
B
C
E
D3
D1
D2
86
Introduction Power Semiconductor Applications
Philips Semiconductors
Fig. 8. Hard turn-off
-V
+Ib
++
Lc
++
Lc
+V
C
R
++
Lc
+V
+I
R
C
(a)
(b)
(c)
The easiest way to obtain these turn-off requirements is to
switch the base to a negative supply via a base coil, see
Fig. 9.
The base coil gives a constant dI
B
/dt (approx.) during the
storage time. When the fall time begins the negative base
current reaches its maximum and the Lb induces the BE
junction into breakdown (see Fig. 4).
An optimumvalue exists for the base coil: if Lb = 0 we have
thehardturn-off condition whichisnot optimumfor standard
highvoltagetransistors. If the value of Lb istoo high it slows
the switching process so that the transistor desaturates.
The V
CE
increases too much during the storage time and
so higher losses result (see Fig. 10).
For high voltage transistors in typical applications (f = 15 to
40 kHz, standard base drive, not overdriven, not
desaturated) the following equations give a good indication
for the value of Lb.
Using - V
dr
= 5V, V
BEsat
= 1V and transistors having
BV
CEO
= 400V it follows that:
c) Other ways of turn-off
Of course, other ways of turn-off are applicable but in
general these can be reduced to one of the methods
described above, or something in between. The BV
CEO
has
a strong influence on the method used: the higher BV
CEO
the longer the storage time required to achieve proper
turn-off. For transistors having aBV
CEO
of 200Vor less hard
turn-off and the use of a base coil yield comparable losses,
so hard turn-off works well. For transistors having BV
CEO
more than 400V hard turn-off is unacceptable because of
the resulting tails.
Fig. 9. A base coil to aid turn-off.
+Ib
++
Lc
-Vdr
L
B
·
(−V
dr
+ V
BEsat
)
¸
¸
dI
B
dt
_
,
with
dI
B
dt
≈ 0.5 ⋅ I
C
(A/µs) for BV
CEO
· 400V, BV
CES
· 800V
and
dI
B
dt
≈ 0.15 ⋅ I
C
(A/µs) for BV
CEO
· 700V, BV
CES
· 1500V
L
B
·
12
I
C
H (I
C
i n Amps)
87
Introduction Power Semiconductor Applications
Philips Semiconductors
Fig. 10. Variations of Lb on I
C
and V
CE
waveforms at turn-off
Ic
Vce
Ic
Vce
Ic
Vce
Lb = 0
Lb = opt Lb > Lb opt
Turn-off for various forward drive
conditions
Using the BUT11 as an example, turn-off characteristics
are discussed for optimum drive, underdrive and overdrive
with hard and smooth turn-off.
a) Optimum drive
The optimum I
B
and Lb for a range of I
C
is given in Fig. 11
for the BUT11. The I
B
referred to is I
Bend
which is the value
of I
B
at the end of the on-state of the applied base drive
signal. In most applications during the on-state the I
B
will
not be constant, hence the term I
Bend
rather than I
Bon
. For
optimumdrive thelevel of I
Bend
increases withI
C
. For smooth
turn-off the level of Lb decreases with increasing I
C
.
Fig. 11. I
Bend
and Lb for the BUT11
Deviations from Fig. 11 will generally lead to higher power
dissipation. If a short storage time is a must in a certain
application then Lb can be reduced but this will lead to
longer fall times and current tails.
With hard turn-off I
B
reaches its peak negative value as all
the charge is removed from the base. For continuity this
current must besourcedfromelsewhere. It hasbeenshown
that the BE junction now avalanches, giving instantaneous
continuity followed by a positive dI
B
/dt. However, for hard
turn-off the current is sourced by the residual collector
charge without BE avalanche, see Fig. 12. The small
negative V
BE
ensures a long tail to I
C
and I
B
.
b) Underdrive (Desaturated drive)
As has been indicated previously, desaturating, or
underdriving, atransistor results in less internal charge. Qd
will be zero and Qc is low and located near the junction.
If the application requires such a drive then steps should
be taken to optimise the characteristics. One simple way
of obtaining underdrive is to increase the series base
resistance with smooth turn-off. The same effect can be
achieved with optimumI
Bend
and a base coil having half the
value used for optimum drive, ie hard turn-off. Both
methods give shorter t
s
and t
f
. For 400VBV
CEO
devices (like
the Philips BUT range) such a harder turn-off can lead to
reasonable results.
Fig. 13 compares the use of the optimum base coil with
hard turn-off for an undriven BUT11. For underdrive the
final I
C
is less and hence the collector charge is less.
Therefore, underdrive and hard turn-off gives less of a tail
thanfor ahigher I
Bend
. Underdrivewith smooth turn-off gives
longer ts but reduced losses.
c) Overdrive
When a transistor is severely overdriven the BC charge,
Qd, becomes so large that a considerable tail will result
even with smooth turn-off. In general, deliberately
designingadrivecircuit tooverdriveatransistor isnot done:
it has noreal value. However, most circuits dohavevariable
collector loads which can result in extreme conditions when
the circuit is required to operate with the transistor in
overdrive.
88
Introduction Power Semiconductor Applications
Philips Semiconductors
Fig. 12. Optimum drive with hard turn-off (top)
and smooth turn-off (bottom) for BUT11
Fig. 13. Underdrive with hard turn-off (top)
and smooth turn-off (bottom) for BUT11
Fig. 14. Overdrive with hard turn-off (top)
and smooth turn-off (bottom) for BUT11
Fig. 14 compares the use of the optimum base coil with
hard turn-off for an overdriven BUT11. For overdrive there
is more base charge, also the final collector current will be
higher and, hence, there will be more collector charge. The
overdriventransistor isthencertaintohavelonger switching
times as there are more electron-hole pairs in the device
that need to recombine before the off-state is reached.
Conclusions
Two ways of turning off a high voltage transistor, hard
turn-off and the use of a base coil, were examined in three
conditions of the on-state: optimum drive, overdrive and
underdrive.
For transistors having BV
CEO
~ 400 V the use of a base coil
yields low losses compared to hard turn-off. As a good
approximation the base coil should have the value:
for optimum drive.
When using a desaturation circuit the value for Lb can be
halved with acceptable results.
Overdrive should be prevented as much as possible
because considerable tails in the collector current cause
unacceptable losses.
Ic
Vce
Ib
Vbe
1 A/div
1 A/div
200 V/div
5 V/div
0.5 us/div
Ic
Vce
Ib
Vbe
1 A/div
1 A/div
200 V/div
5 V/div
0.5 us/div
Ic
Vce
Ib
Vbe
1 A/div
1 A/div
200 V/div
5 V/div
0.5 us/div
Ic
Vce
Ib
Vbe
1 A/div
1 A/div
200 V/div
5 V/div
0.5 us/div
Ic
Vce
Ib
Vbe
1 A/div
1 A/div
200 V/div
5 V/div
0.5 us/div
Ic
Vce
Ib
Vbe
1 A/div
1 A/div
200 V/div
5 V/div
0.5 us/div
L
B
·
12
I
C
µH
89
Introduction Power Semiconductor Applications
Philips Semiconductors
1.3.3 Using High Voltage Bipolar Transistors
This section looks at some aspects of using high voltage
bipolar transistors in switching circuits. It highlights points
suchasswitching, bothturn-onandturn-off, SafeOperating
Areas and the need for snubber circuits. Base drive design
curves for the BUT11, BUW12 and BUW13 are discussed
under ’Application Information’ at the end of this section.
Transistor switching: turn-on
To make optimum use of today’s high voltage transistors,
one should carefully choose the correct value for both the
positive base current when the transistor is on and the
negative base current when the device is switched off (see
Application Information section).
When a transistor is in the off-state, there are no carriers
in the thick n- collector, effectively there is a resistor with a
relatively high value in the collector. To obtain a low
on-state voltage, a base current is applied such that the
collector area is quickly filled with electron - hole pairs
causing the collector resistance to decrease. In the
transition time, the so called turn-on time, the voltage and
current may both be high, especially in forward converters,
and high turn-on losses may result. Initially, all the carriers
in the collector will be delivered via the base contact and,
therefore, the base current waveform should have a peak
at the beginning. In this way the carriers quickly fill the
collector area so the voltage is lower and the losses
decrease.
In flyback converters the current to be turned on is normally
low, but in forward converters this current is normally high.
Thecollector current, I
C
, reaches itson-state valueinashort
time which is normally determined by the leakage
inductance of the transformer.
Fig. 1 Turn-on of a high voltage bipolar transistor
In Fig. 1 the characteristic ‘hump’ which often occurs at
turn-on in forward converters due to the effect of the
collector series resistance is observed.
The turn-on losses are strongly dependent on the value of
the leakage inductance and the applied base drive. It is
generally advised to apply a high initial +I
B
for a short time
in order to minimise turn on losses.
Adeeper analysis can be found in sections 1.3.2, 2.1.2 and
2.1.3. Turn on losses are generally low for flyback
converters but are the most important factor in forward
converter types.
Turn-off of high voltage transistors
All charge stored in the collector when the transistor is on
should be removed again at turn-off. To ensure a quick
turn-off anegativebasecurrent isapplied. Thetimeneeded
to remove the base - collector charge is called the storage
time. A short storage time is needed to minimise problems
within the control loop in SMPSand deflection applications.
Fig. 2 Effects of -I
B
on turn-off
Care is needed to implement the optimum drive. First
overdriveshouldbepreventedby keeping+I
B
toaminimum.
Overdrive results in current tails and long storage times.
But, decreasing I
B
too much results in high on-state losses.
Second, the negative base current should be chosen
carefully. A small negative base current (-I
B
) will give a long
storage time and ahigh V
CEsat
at the end of the storage time,
whilethe current is still high. As aconsequence, the turn-off
losses will be high. If, however, a large negative base
current is used, the danger exists that tails will occur in the
collector current, again resulting in high losses. There is
an optimum as shown in Fig. 2.
A circuit which is worth considering, especially for higher
frequencies, is the Baker Clamp or desaturation circuit.
This circuit prevents saturation of the transistor and, hence,
faster switching times are achieved.
Ic
Vce
Ic
Vce
Ic
Vce
-Ib is too high
-Ib is optimum -Ib is too low
Ic
Vce
Ic = 1 A/div
Vce = 50 V/div
91
Introduction Power Semiconductor Applications
Philips Semiconductors
The total losses depend on the base drive and the collector
current. In Fig.3 the total losses are shown for a BUW133
as a function of the positive base current, for both the
saturated and the desaturated case. Note that when
different conditions are being used the picture will change.
The application defines the acceptable storage time which
then determines the base drive requirements.
Fig. 3 BUW133 losses versus base drive
The total number of variables is too large to give unique
base drive advice for each application. As a first hint the
device data sheets give I
C
and I
B
values for V
CEsat
, V
BEsat
and
switching. However, it is more important to appreciate the
ways to influence base drive and the consequences of a
non-optimised circuit.
For a flyback converter the best value of I
Bend
to start with
is about 2/3 of the I
B
value given in data for V
CEsat
and V
BEsat
.
In this application the forward base current is proportional
to the collector current (triangular shaped waveforms) and
this I
Bend
value will give low on-state losses and fast
switching.
The best turn-off base current depends on the breakdown
voltage of the transistor. As a guide, Table 1 gives
reasonable values for the target storage time and may be
used to begin optimising the base drive:
f (kHz) tp (µs) target ts (µs)
25 20 2.0
150 10 1.5
100 5 1.0
Table 1 Target ts for varying frequency and pulse width
The above table holds for transistors with a V
CEOmax
rating
of 400-450V and V
CESmax
between 850-1000V. Transistors
with higher voltages require longer storage times, eg.
transistors with V
CEOmax
= 700V and V
CESmax
= 1500V need
a storage time which is approximately double the value in
the table.
A recommended way to control the storage time is by
switching the base to a negative voltage rail via a base coil.
The leakage inductance of a driver transformer may serve
as an excellent base coil. As a guide, the base coil should
be chosen such that the peak value of the negative base
current equals half the value of the collector current.
Specific problems and solutions
Ahigh voltagetransistor needs protection circuits to ensure
that the device will survive all the currents and voltages it
will see during its life in an application.
a) Over Current
Exceeding current ratings normally does not lead to
immediate transistor failure. In the case of a short circuit,
the protection is normally fast enough for problems to be
avoided. Most devices are capable of carrying very high
currents for short periods of time. High currents will raise
the junction temperature and if T
jmax
is exceeded the
reliability of the device may be weakened.
b) Over Voltage
In contrast with over current, it is NOT allowed to exceed
the published voltage ratings for V
CEO
and V
CES
(or V
CBO
).
In switching applications it is common for the base - emitter
junction to be taken into avalanche, this does not harm the
device. For this reason V
EBO
limits are not given in data.
Exceeding V
CEO
and V
CES
causes high currents to flow in
very small areas of the device. These currents may cause
immediate damage to the device in very short times
(nanoseconds). So, even for very short times it is not
allowed to have voltages above data for the device.
In reality V
CEO
and V
CES
are unlikely to occur in a circuit. If
V
BE
= 0V the there will probably still be a path between the
base and the emitter. In fact the situation is V
CEX
where X
is the impedance of this path. To cover for all values of X,
the limit is X=∞, ie V
CEO
. For all V
BE
< 0V, ie V
CEV
, the limit
case is V
BE
= 0V, ie V
CES
.
If voltage transients that exceed the voltage limits are
detected then a snubber circuit may limit the voltage to a
safe value. If the over voltage states last greater than a
few µs a higher voltage device is required.
c) Forward Bias Safe Operating Areas (FBSOA)
The FBSOA is valid for positive values of V
BE
. There is a
time limit to V
CE
- I
C
operating points beyond which device
failure becomes a risk. At certain values of V
CE
and I
C
there
is a risk of secondary breakdown; this is likely to lead to the
immediate failure of the device. The FBSOA curve should
only be considered during drastic change sequences; for
example, start-up, s/c or o/c load.
With Baker Clamp
Saturated
100
200
300
400
500
600
700
Etot (uJ)
1 2 3 4
Ib (A)
Forward Converter
Ic = 10 A
92
Introduction Power Semiconductor Applications
Philips Semiconductors
d) Reverse Bias Safe Operating Area (RBSOA)
The RBSOA is valid for negative values of V
BE
. During
turn-off with an inductive load the V
CE
will rise as the I
C
falls.
For each device type there is a V
CE
- I
C
boundary which, if
exceeded, will lead to the immediate failure of the device.
Tolimit the V
CE
- I
C
pathat turn-off snubber circuits are used,
see Fig. 4.
Fig. 4 HVT with inductive load and typical snubber
At turn-off, as the V
CE
rises the diode starts conducting
chargingthe capacitor. The additional diodecurrent means
that the total load current does not decrease so fast at
turn-off. This slower current tail in turn ensures a slower
V
CE
rise. The slower V
CE
rise takes the transistor through
a safer V
CE
- I
C
path away from the limit, see Fig. 5.
As a handy guide, the snubber capacitor in a 20-40 kHz
converter is about 1nF for each 100W of throughput power
(this is the power which is being transferred via the
transformer). This value may be reduced empirically as
required.
Fig. 5 BUW13A RBSOA limit
V
CE
- I
C
path with and without snubber
The following table may serve as a guide to the value of
dV
CE
/dt for some switching frequencies
f (kHz) 25 50 100
dV
CE
/dt 1 2 4
(kV/µs)
Thesnubber resistor should bechosensothat thecapacitor
will be discharged in the shortest occurring on-time of the
switch.
In some cases the losses in the snubber may be
considerable. Clever designs exist to feed the energy
stored in the capacitor back into the supply capacitor, but
this is beyond the scope of this report.
5
10
15
20
200
400
600 800 1000
BUW13A
Ic
Vce
Without Snubber
With Snubber
Vs
Fig. 6 Transistor with maximum protection networks in SMPS circuit
R5
C5
C4
D4
D5
D6
R4
TR1
L6
R6
D3 D1
D2
Lo
Co
Vo
Vi
93
Introduction Power Semiconductor Applications
Philips Semiconductors
d) Other protection networks
In Fig. 6 a "maximum protection" diagram is shown with
various networks connected. R4, C4, and D4 form the
snubber to limit the rate of rise of V
CE
. The network with
D5, R5 and C5 forms a "peak detector" to limit the peak
V
CE
.
The inductor L6 serves to limit the rate of rise of I
C
which
may bevery highfor sometransformer designs. The slower
dI
C
/dt leads to considerably lower turn-on losses. Added
to L6 is a diode D6 and resistor R6, with values chosen so
that L6 loses its energy during the off-time of the power
switch.
While the snubber is present in almost all SMPS circuits
where transistors are used above V
CEOmax
, the dI
C
/dt limiter
is only needed when the transformer leakage inductance
is extremely low. The peak detector is applied in circuits
which have bad coupling between primary and secondary
windings.
Application Information
Important design factorsof SMPScircuits are the maximum
power losses, heatsink requirements and base drive
conditions of the switching transistor. The power losses
are very dependent on the operating frequency, the
maximum collector current amplitude and shape.
The operating frequency is usually between 15 and 50 kHz.
The collector current shape varies from rectangular in a
forward converter to sawtooth in a flyback converter.
Examples of base drive and losses are given in Appendix 1
for the BUT11, BUW12 and BUW13. In these figures I
CM
represents the maximum repetitive peak collector current,
which occurs during overload. The information is derived
fromlimit-case transistors at a mounting base temperature
of 100 ˚C under the following conditions (see also Fig. 7):
- collector current shape I
C1
/ I
CM
= 0.9
- duty factor (t
p
/ T) = 0.45
- rate of rise of I
C
during turn-on = 4 A/µs
- rate of rise V
CE
during turn-off = 1 kV/µs
- reverse drive voltage during turn-off = 5 V
- base current shape I
B1
/ I
Be
= 1.5
The required thermal resistance of the heatsink can be
calculated from
Toensure thermal stability amaximumvalue of the ambient
temperature, T
amb
, is assumed: T
amb
≤ 40˚C.
R
th(mb −amb)
<
100 − T
amb
P
tot
K/W
Fig. 7 Relevant waveforms of the switching transistor in a forward SMPS.
Ic
Ic1
Icm
Vce
Ib
Vbe
Ib1
Ib(end)
-Vdrive
T
tp
dIc/dt
0.9 Icm
0.1 Icm
t1 = 0.5 us
Vce(t1)
ts
tf
Turn-on
Turn-off
94
Introduction Power Semiconductor Applications
Philips Semiconductors
As a base coil is normally advised and a negative drive
voltageof -5Vis rather common, the value for the base coil,
L
B
, is given for these conditions. For other values of -V
drive
(-3 to -7 volt) the base coil follows from:
Where L
Bnom
is the value given in Appendix 1.
It should be noted, that this advice yields acceptable power
losses for the whole spread in the product. It is not just for
typical products as is sometimes thought ! This is
demonstrated in Fig. 8, where limit and typical devices are
compared (worst-case saturation and worst-case
switching).
It appears that the worst-case fall time devices have losses
P0 for I
Bend
= (Ib adv) + 20%, while the saturation
worst-casedevices havethe samelossesat (Ib adv) - 20%.
A typical device now has losses P1 at Ib adv, while the
optimum I
Bend
for the typical case might yield losses P2 at
an approximately 15% lower I
Bend
(NB: this is not a rule, it
is an example).
Fig. 8 Losses as a function of I
Bend
Conclusion
To avoid exceeding the RBSOA of an HVT, snubbers are
arequirement for most circuits. To minimiseboth switching
and on-state losses, particular attention should be given to
the design of the base drive circuit. It is generally advised
that a high initial base current is applied for a short time to
minimise turn-on loss. As a guide-line for turn-off, a base
coil should be chosen such that the peak value of the
negative base current equals half the value of the collector
current.
-20% Ib adv +20%
Ibe
w.c. (tf) typ. w.c. (sat)
P0
P1
P2
Ploss
L
B
· L
Bnom

(−V
drive
+ 1)
6
95
Introduction Power Semiconductor Applications
Philips Semiconductors
Appendix 1 Base Drive Design Graphs
BUT11 Base Drive Design Information
BUW12 Base Drive Design Information
BUW13 Base Drive Design Information
96
Introduction Power Semiconductor Applications
Philips Semiconductors
1.3.4 Understanding The Data Sheet: High Voltage Transistors
Introduction
Being one of the most important switching devices in
present day switched mode power supplies and other fast
switching applications, the high voltage transistor is a
component withmany aspects that designersdo not always
fully understand. In spite of its "age" and the variety of
papersandpublications bymanufacturersandusers of high
voltagetransistors, datasheets are somewhat limited in the
information they give. This section deals with the data
sheets of high voltage transistors and the background to
their properties. A more detailed look at the background to
transistor specifications can be found in chapter 2.1.2.
Fig. 1 shows the cross section of a high voltage transistor.
The active part of the transistor is highlighted (the area
underneath the emitter) and it is this part of the silicon that
determines the primary properties of the device:
breakdown voltages, h
FE
, switching times. All the added
parts can only make these properties worse: a bad
passivation scheme can yield a much lower collector-base
breakdown voltage, too thin wires may seriously decrease
the current capability, a bad die bond (solder layer) leads
to a high thermal resistance leading to poor thermal fatigue
behaviour.
Fig. 1 Simplified cross section of an HVT
The Data Sheet
The data sheet of a high voltage transistor can specify -
* Limiting Values / Ratings: the maximum allowable
currents through and voltages across terminals, as well as
temperatures that must not be exceeded.
* Characteristics: describing properties in the on and off
state (static) as well as dynamic, both in words and in
figures.
* SOA: Safe Operating Area both in forward and reverse
biased conditions.
Data sheets are intended to be a means of presenting the
essentials of a device and, at the same time, to give an
overview of the guaranteed specification points. This data
is checked as a final measurement of the device and
customers may wish to use it for their incoming inspection.
For this reason the data is such that it can be inspected
rather easily in relatively simple test circuits. This
somewhat application unfriendly way of presenting data is
unavoidable if cheap devices are a must, and they are !
Each of the above mentioned items will now be discussed
in more detail, in some instances parts of the data for a
BUT11 will be used as an example. The BUT11 is intended
for 3A applications and has a maximum V
CES
of 850V.
Limiting Values / Maximum Ratings
There is a significant difference between current and
voltage ratings. Exceeding voltage ratings can lead to
breakdown phenomena which are possibly destructive
within fractions of a second. The avalanche effects
normally take place within a very small volume and,
therefore, only a little energy can be absorbed. Surge
voltages, that are sometimes allowed for other
components, are out of the question for high voltage
transistors.
There is, however, no reason to have a derating on
voltages: using the device up to its full voltage ratings - in
worst case situations - is allowed. The life tests, carried out
in Philips quality laboratories, clearly show that no voltage
degradation takes place and excellent reliability is
maintained.
Fromthe above, it should be clear that the habit of derating
is not a good one. If, in a particular application, the
collector-emitter voltage never exceeds, say 800V, the
required device should be an 850V device not a 1500V
device. Higher voltage devices not only have lower h
FE
, but
also slower switching speeds and higher dissipation.
The rating for the emitter-base voltage is a special case:
to allowa base coil to be used, the base-emitter diode may
be brought into breakdown; in some cases a -I
Bav
is given
to prevent excessive base-emitter dissipation. The only
effect of long term repetitive base-emitter avalanche
breakdown that has been observed is a slight decrease in
h
FE
at very low values of collector current (approximately
10% at ≤ 5mA); at higher currents the effects can be
neglected completely.
N
P
N
mounting base = collector
bonding wire
glass passivation
active area
solder
97
Introduction Power Semiconductor Applications
Philips Semiconductors
The maximum value for V
CEO
is important if no snubber is
applied; it sets a firm boundary in applications with a very
fast rising collector voltage and a normal base drive (see
also section on SOA).
Currents above a certain value may be destructive if they
last long enough: bonding wires fuse due to excessive
heating. Therefore, short peak currents are allowed well
above the rated I
Csat
with values up to five times this value
beingpublished for I
CM
. Exceedingthe publishedmaximum
temperatures is not immediately destructive, but may
seriously affect the useful life of the device. It is well known,
that the useful life of a semiconductor device doubles for
each 10K decrease in working junction temperature.
Another factor that should be kept in mind is the thermal
fatigue behaviour, which strongly depends on the
die-bonding technology used. Philips high voltage devices
are capable of 10,000 cycles with a temperature rise of 90K
without any degradation in performance.
This kind of consideration leads to the following advice:
under worst case conditions the maximum
case-temperature should not exceed 115 ˚C for reliable
operation. This advice is valid regardless of the maximum
temperature being specified. Of course, for storage the
published values remain valid.
The maximum total power dissipation P
tot
is an industry
standard, but not very useful, parameter. It is the quotient
of T
jmax
- T
mb
and R
th(j-mb)
(R
th(j-mb)
is the thermal resistance
from junction to mounting base and T
mb
is assumed to be
25˚C). This implies a rather impractical infinite heatsink,
kept at 25˚C !
Electrical Characteristics
Static parameters characterise leakage currents, h
FE
,
saturation voltages; dynamic parameters and switching
times, but also include transition frequency and collector
capacitance.
To start: I
Csat
, the collector saturation current, is that value
of the collector current where both saturation and switching
properties of the devices are specified. I
Csat
is not a
characteristic that can be measured, but it is used as an
indicationof theof thepeak workingcurrent allowedthrough
a device.
In the off-state various leakage currents are specified,
however, theseare of little use as they indicate the lowlevel
of dissipation in the off state. Also a V
CEOsust
is specified,
usually being equal to the max. V
CEO
. For switching
purposes it is the RBSOA that is important (see next
section).
In the on state the saturation voltages V
CEsat
and, to a lesser
extent, V
BEsat
are important. V
CEsat
is an indication of the
saturation losses and V
BEsat
normally influences base drive.
Sometimes worst case V
CEsat
is given as a function of both
I
C
and I
B
. It is not possible to precisely relate these curves
to a real circuit; in practice, currents and voltages will vary
over the switching cycle. The dynamic performance is
different to the static performance. However, a reasonable
indication can be obtained from these curves.
Both the transition frequency (f
T
) and the collector
capacitance (C
c
or C
ob
) are minor parameters relating to the
design and processing technology used.
Switching times may be given in circuits with an inductive
or a resistive collector load. See Figs. 2a-b for simplified
test circuits and Figs. 3a-b for waveforms.
Fig. 2a Test circuit for resistive load
Fig. 2b Test circuit for inductive load
When comparing similar devices from different
manufacturersoneisconfrontedwith agreat varietyof base
drive conditions. The positive base current (+I
B
) may be
the same as the one used in the V
CEsat
spec. but also lower
values (up to 40% lower) or desaturation networks may be
used, yielding better ts and tf values. The negative base
drive, -I
B
, may equal +I
B
or it may betwicethis value, yielding
a shorter ts, and sometimes it is determined by switching
the base to a negative voltage, possibly via a base coil.
Altogether it is quite confusing and when comparing
switching times one should be well aware of all the
differences!
tp
T
VCC
RL
RB
T.U.T. 0
VIM
LB
IBon
-VBB
LC
T.U.T.
VCC
98
Introduction Power Semiconductor Applications
Philips Semiconductors
Fig. 3a Waveforms for Resistive Switching.
Fig. 3b Waveforms for Inductive Switching.
As an example a BUT11 has been measured at I
C
= 3A in
a resistive test circuit varying both +I
B
and -I
B
. The results
in Table 1 showthat it is possible to turn a normal transistor
into a super device by simple specmanship!
I
C
= 3 A ts (µs) tf (ns)
+I
B
= 0.6 A; -I
B
= 0.6 A 2.5 260
(normal case)
+I
B
= 0.36 A; -I
B
= 0.72 A 1.6 210
(underdriven)
+I
B
= 0.36 A; -V
BE
= -5 V 0.8 50
(underdriven, hard turn-off)
Table 1 Switching times and base drive for the BUT11
The effect of base drive variations on storage and fall times
is given in Table 2. The reference is the condition that both
+I
B
as well as -I
B
equals the value for I
B
given for the V
CEsat
specification in the data sheet.
ts tf comments
+I
B
= ref. normal normal reference
+I
B
= 40% less ↓ ↓
Desaturated ↓ ↓
-I
B
= ref. normal normal reference
-I
B
= 2 x +I
B
↓ ↓
Directly to -5 V ↓ ↑ with normal
base drive!
Directly to -5 V ↓ ↓ if underdriven
Via L to -5 V ↓ ↓
Table 2 Switching times and base drive variations.
The turn-on time is a parameter which only partially
correlates with dissipation as it is usually the behaviour
directly after the turn-on time which appears to be most
significant. Both inductive and resistive load test circuits
are only partially useful, as resistive loads are seldomused
and very often some form of slow-rise network is used with
inductive loads. Both circuits provide easy lab.
measurements and the results can be guaranteed. The
alternative of testing the devices in a real switched mode
power supply would be too costly!
Safe Operating Area
The difference between forward bias safe operating area
(FBSOA) and reverse bias safe operating area (RBSOA)
is in the device V
BE
: if V
BE
> 0V it is FBSOA and if V
BE
< 0V
it isRBSOA. Chapter 2.1.3 deals with bothsubjects in more
detail, a few of the main points are covered below.
FBSOA gives boundaries for dc or pulsed operation. In
switching applications, where the transistor is "on" or "off",
normally the excursion in the I
C
-V
CE
plane is fast enough to
allow the designer to use the whole plane, with the
boundaries I
Cmax
and V
CEO
, as given in the ratings. This is
useful for snubberless applications and for overload, fault
conditions or at switch-on of the power supply
Fig. 4 gives the FBSOA of the BUT11 with the boundaries
of I
Cmax
, I
CMmax
and V
CEO
, all as given in the ratings. There
is a P
totmax
(1) and I
SB
boundary (2), that both shift at higher
levels of I
C
when shorter pulses are used. Note that in the
upper right hand corner pulse times of 20µs are permitted
leading to a square switching SOA. For overload, fault
condition or power supply switch-on an extra area is added
(area III). All these conditions are for V
BE
≥ 0V.
IC
IB
10 %
10 %
90 % 90 %
ton
toff
ts
tf
IBon
-IBoff
ICon
IC
IB
ICon
IBon
-IBoff
t
t
ts
tf
toff
10 %
90 %
99
Introduction Power Semiconductor Applications
Philips Semiconductors
(1) P
totmax
and P
totpeak
max. lines
(2) Second breakdown limits (independent of
temperature).
I Region of permissible dc operation.
II Permissible extension for repetitive pulse
operation
III Area of permissible operation during turn-on
in single transistor converters, provided
R
BE
≤ 100 Ω and t
p
≤ 0.6 µs.
IV Repetitive pulse operation in this region is
permissible provided V
BE
≤ 0 V and t
p
≤ 5 ms.
Fig. 4 Safe Operating Area of BUT11.
Area IV is only valid for V
BE
≤ 0V, so this is an RBSOA
extension to the SOA curve. This is not the full picture for
RBSOA, area IV is only for continuous pulsed operation.
For single cycle and short burst fault conditions see the
separate RBSOA curve.
The RBSOA curve is valid when a negative voltage is
applied to the base-emiiter terminals during turn-off. This
curve should be used for fault condition analysis only;
continuous operation close to the limit will result in 100’s W
of dissipation ! Due to localised current contraction within
the chip at turn-off, damage will occur if the limit is
exceeded. In nearly all cases, the damage will result in the
immediate failure of the device to short circuit.
Emitter switching applications force different mechanisms
for carrier recombination in the device which allow a
‘square’ RBSOA. A typical example is shown in Fig. 5,
where for both base and emitter drive the RBSOA of the
BUT11 is given.
Fig. 5 RBSOA of BUT11 for Base and Emitter Drive.
It is striking that for emitter drive the whole I
C
-V
CES
plane
may be used so no snubber is necessary, however, a small
snubber may prevent overshoot. The base drive RBSOA
normally depends on base drive conditions, but
unfortunately there is no uniform trend in this behaviour.
Therefore, the RBSOA curve in the data gives the worst
case behaviour of the worst case devices. Other data
sheets may give RBSOAcurves that at first sight look better
than the Philips equivalent, but beware, these curves might
hold for only a limited base drive range.
Summary
Voltage limiting values / ratings as given in the data must
never be exceeded, as they may lead to immediate device
failure. Surge voltages, as sometimes given for other
components, are not allowed for high voltage transistors.
Current limiting values / ratings are less strict as they are
time-dependent and should be used in conjunction with the
FBSOA.
Static characteristics are useful for comparisons but offer
little in describing the performance in an application. The
dynamic characteristics may be defined for a simple test
circuit but the values give a good indication of the switching
performance in an application.
RBSOA is, for all switching applications, of prime
importance. Philips give in their data sheets a curve for
worst case devices under worst case conditions. For
snubber design a value of 1 nF per 100W of throughput
200
400
600 800 1000
Ic (A)
Vce (V)
0
1
2
3
4
5
6
7
8
base drive
emitter drive
Vcesm
100
Introduction Power Semiconductor Applications
Philips Semiconductors
power is advised as a starter value; afterwards, the I
C
-V
CE
locus must be checked to see if it stays within the published
RBSOA curve.
For characteristics bothsaturation and switchingproperties
are given at I
Csat
. Most figures are of limited use as they
give static conditions, where in a practical situation
properties are time-dependent. Switching times are given
in relatively simple circuits that may be replicated rather
easily e.g. for incoming inspection.
Switching times depend strongly on drive conditions. By
altering them a normal device can be turned into a super
device. Beware of specmanship, this may disguise poor
tolerance to variations in base drive.
101
Preface Power Semiconductor Applications
Philips Semiconductors
Acknowledgments
We are grateful for all the contributions fromour colleagues within Philips and to the Application Laboratories in Eindhoven
and Hamburg.
We would also like to thank Dr.P.H.Mellor of the University of Sheffield for contributing the application note of section 3.1.5.
The authors thank Mrs.R.Hayes for her considerable help in the preparation of this book.
The authors also thank Mr.D.F.Haslam for his assistance in the formatting and printing of the manuscripts.
Contributing Authors
N.Bennett
M.Bennion
D.Brown
C.Buethker
L.Burley
G.M.Fry
R.P.Gant
J.Gilliam
D.Grant
N.J.Ham
C.J.Hammerton
D.J.Harper
W.Hettersheid
J.v.d.Hooff
J.Houldsworth
M.J.Humphreys
P.H.Mellor
R.Miller
H.Misdom
P.Moody
S.A.Mulder
E.B.G. Nijhof
J.Oosterling
N.Pichowicz
W.B.Rosink
D.C. de Ruiter
D.Sharples
H.Simons
T.Stork
D.Tebb
H.Verhees
F.A.Woodworth
T.van de Wouw
This book was originally prepared by the Power Semiconductor Applications Laboratory, of the Philips Semiconductors
product division, Hazel Grove:
M.J.Humphreys
C.J.Hammerton
D.Brown
R.Miller
L.Burley
It was revised and updated, in 1994, by:
N.J.Ham C.J.Hammerton D.Sharples
Preface Power Semiconductor Applications
Philips Semiconductors
Preface
This book was prepared by the Power Semiconductor Applications Laboratory of the Philips Semiconductors product
division, Hazel Grove. The book is intended as a guide to using power semiconductors both efficiently and reliably in power
conversion applications. It is made up of eight main chapters each of which contains a number of application notes aimed
at making it easier to select and use power semiconductors.
CHAPTER 1 forms an introduction to power semiconductors concentrating particularly on the two major power transistor
technologies, Power MOSFETs and High Voltage Bipolar Transistors.
CHAPTER 2 is devoted to Switched Mode Power Supplies. It begins with a basic description of the most commonly used
topologies and discusses the major issues surrounding the use of power semiconductors including rectifiers. Specific
design examples are given as well as a look at designing the magnetic components. The end of this chapter describes
resonant power supply technology.
CHAPTER 3 describes motion control in terms of ac, dc and stepper motor operation and control. This chapter looks only
at transistor controls, phase control using thyristors and triacs is discussed separately in chapter 6.
CHAPTER 4 looks at television and monitor applications. A description of the operation of horizontal deflection circuits is
givenfollowed by transistor selection guides for both deflectionand power supply applications. Deflection and power supply
circuit examples arealsogivenbasedoncircuitsdesignedbytheProduct Concept andApplicationLaboratories(Eindhoven).
CHAPTER5 concentrates on automotive electronics looking in detail at the requirements for the electronic switches taking
into consideration the harsh environment in which they must operate.
CHAPTER6 reviews thyristor andtriac applications fromthe basics of device technology and operation to the simple design
rules which should be followed to achieve maximum reliability. Specific examples are given in this chapter for a number
of the common applications.
CHAPTER 7 looks at the thermal considerations for power semiconductors in terms of power dissipation and junction
temperaturelimits. Part of this chapter is devotedto worked examples showing howjunctiontemperatures can becalculated
to ensure the limits are not exceeded. Heatsink requirements and designs are also discussed in the second half of this
chapter.
CHAPTER 8 is an introduction to the use of high voltage bipolar transistors in electronic lighting ballasts. Many of the
possible topologies are described.
Contents Power Semiconductor Applications
Philips Semiconductors
Table of Contents
CHAPTER 1 Introduction to Power Semiconductors 1
General 3
1.1.1 An Introduction To Power Devices ............................................................ 5
Power MOSFET 17
1.2.1 PowerMOS Introduction ............................................................................. 19
1.2.2 Understanding Power MOSFET Switching Behaviour ............................... 29
1.2.3 Power MOSFET Drive Circuits .................................................................. 39
1.2.4 Parallel Operation of Power MOSFETs ..................................................... 49
1.2.5 Series Operation of Power MOSFETs ....................................................... 53
1.2.6 Logic Level FETS ...................................................................................... 57
1.2.7 Avalanche Ruggedness ............................................................................. 61
1.2.8 Electrostatic Discharge (ESD) Considerations .......................................... 67
1.2.9 Understanding the Data Sheet: PowerMOS .............................................. 69
High Voltage Bipolar Transistor 77
1.3.1 Introduction To High Voltage Bipolar Transistors ...................................... 79
1.3.2 Effects of Base Drive on Switching Times ................................................. 83
1.3.3 Using High Voltage Bipolar Transistors ..................................................... 91
1.3.4 Understanding The Data Sheet: High Voltage Transistors ....................... 97
CHAPTER 2 Switched Mode Power Supplies 103
Using Power Semiconductors in Switched Mode Topologies 105
2.1.1 An Introduction to Switched Mode Power Supply Topologies ................... 107
2.1.2 The Power Supply Designer’s Guide to High Voltage Transistors ............ 129
2.1.3 Base Circuit Design for High Voltage Bipolar Transistors in Power
Converters ........................................................................................................... 141
2.1.4 Isolated Power Semiconductors for High Frequency Power Supply
Applications ......................................................................................................... 153
Output Rectification 159
2.2.1 Fast Recovery Epitaxial Diodes for use in High Frequency Rectification 161
2.2.2 Schottky Diodes from Philips Semiconductors .......................................... 173
2.2.3 An Introduction to Synchronous Rectifier Circuits using PowerMOS
Transistors ........................................................................................................... 179
i
Contents Power Semiconductor Applications
Philips Semiconductors
Design Examples 185
2.3.1 Mains Input 100 W Forward Converter SMPS: MOSFET and Bipolar
Transistor Solutions featuring ETD Cores ........................................................... 187
2.3.2 Flexible, Low Cost, Self-Oscillating Power Supply using an ETD34
Two-Part Coil Former and 3C85 Ferrite .............................................................. 199
Magnetics Design 205
2.4.1 Improved Ferrite Materials and Core Outlines for High Frequency Power
Supplies ............................................................................................................... 207
Resonant Power Supplies 217
2.5.1. An Introduction To Resonant Power Supplies .......................................... 219
2.5.2. Resonant Power Supply Converters - The Solution For Mains Pollution
Problems .............................................................................................................. 225
CHAPTER 3 Motor Control 241
AC Motor Control 243
3.1.1 Noiseless A.C. Motor Control: Introduction to a 20 kHz System ............... 245
3.1.2 The Effect of a MOSFET’s Peak to Average Current Rating on Invertor
Efficiency ............................................................................................................. 251
3.1.3 MOSFETs and FREDFETs for Motor Drive Equipment ............................. 253
3.1.4 A Designers Guide to PowerMOS Devices for Motor Control ................... 259
3.1.5 A 300V, 40A High Frequency Inverter Pole Using Paralleled FREDFET
Modules ............................................................................................................... 273
DC Motor Control 283
3.2.1 Chopper circuits for DC motor control ....................................................... 285
3.2.2 A switched-mode controller for DC motors ................................................ 293
3.2.3 Brushless DC Motor Systems .................................................................... 301
Stepper Motor Control 307
3.3.1 Stepper Motor Control ............................................................................... 309
CHAPTER 4 Televisions and Monitors 317
Power Devices in TV & Monitor Applications (including selection
guides) 319
4.1.1 An Introduction to Horizontal Deflection .................................................... 321
4.1.2 The BU25XXA/D Range of Deflection Transistors .................................... 331
ii
Contents Power Semiconductor Applications
Philips Semiconductors
4.1.3 Philips HVT’s for TV & Monitor Applications .............................................. 339
4.1.4 TV and Monitor Damper Diodes ................................................................ 345
TV Deflection Circuit Examples 349
4.2.1 Application Information for the 16 kHz Black Line Picture Tubes .............. 351
4.2.2 32 kHz / 100 Hz Deflection Circuits for the 66FS Black Line Picture Tube 361
SMPS Circuit Examples 377
4.3.1 A 70W Full Performance TV SMPS Using The TDA8380 ......................... 379
4.3.2 A Synchronous 200W SMPS for 16 and 32 kHz TV .................................. 389
Monitor Deflection Circuit Example 397
4.4.1 A Versatile 30 - 64 kHz Autosync Monitor ................................................. 399
CHAPTER 5 Automotive Power Electronics 421
Automotive Motor Control (including selection guides) 423
5.1.1 Automotive Motor Control With Philips MOSFETS .................................... 425
Automotive Lamp Control (including selection guides) 433
5.2.1 Automotive Lamp Control With Philips MOSFETS .................................... 435
The TOPFET 443
5.3.1 An Introduction to the 3 pin TOPFET ......................................................... 445
5.3.2 An Introduction to the 5 pin TOPFET ......................................................... 447
5.3.3 BUK101-50DL - a Microcontroller compatible TOPFET ............................ 449
5.3.4 Protection with 5 pin TOPFETs ................................................................. 451
5.3.5 Driving TOPFETs ....................................................................................... 453
5.3.6 High Side PWM Lamp Dimmer using TOPFET ......................................... 455
5.3.7 Linear Control with TOPFET ...................................................................... 457
5.3.8 PWM Control with TOPFET ....................................................................... 459
5.3.9 Isolated Drive for TOPFET ........................................................................ 461
5.3.10 3 pin and 5 pin TOPFET Leadforms ........................................................ 463
5.3.11 TOPFET Input Voltage ............................................................................ 465
5.3.12 Negative Input and TOPFET ................................................................... 467
5.3.13 Switching Inductive Loads with TOPFET ................................................. 469
5.3.14 Driving DC Motors with TOPFET ............................................................. 471
5.3.15 An Introduction to the High Side TOPFET ............................................... 473
5.3.16 High Side Linear Drive with TOPFET ...................................................... 475
iii
Contents Power Semiconductor Applications
Philips Semiconductors
Automotive Ignition 477
5.4.1 An Introduction to Electronic Automotive Ignition ...................................... 479
5.4.2 IGBTs for Automotive Ignition .................................................................... 481
5.4.3 Electronic Switches for Automotive Ignition ............................................... 483
CHAPTER 6 Power Control with Thyristors and Triacs 485
Using Thyristors and Triacs 487
6.1.1 Introduction to Thyristors and Triacs ......................................................... 489
6.1.2 Using Thyristors and Triacs ....................................................................... 497
6.1.3 The Peak Current Handling Capability of Thyristors .................................. 505
6.1.4 Understanding Thyristor and Triac Data .................................................... 509
Thyristor and Triac Applications 521
6.2.1 Triac Control of DC Inductive Loads .......................................................... 523
6.2.2 Domestic Power Control with Triacs and Thyristors .................................. 527
6.2.3 Design of a Time Proportional Temperature Controller ............................. 537
Hi-Com Triacs 547
6.3.1 Understanding Hi-Com Triacs ................................................................... 549
6.3.2 Using Hi-Com Triacs .................................................................................. 551
CHAPTER 7 Thermal Management 553
Thermal Considerations 555
7.1.1 Thermal Considerations for Power Semiconductors ................................. 557
7.1.2 Heat Dissipation ......................................................................................... 567
CHAPTER 8 Lighting 575
Fluorescent Lamp Control 577
8.1.1 Efficient Fluorescent Lighting using Electronic Ballasts ............................. 579
8.1.2 Electronic Ballasts - Philips Transistor Selection Guide ............................ 587
8.1.3 An Electronic Ballast - Base Drive Optimisation ........................................ 589
iv
Index Power Semiconductor Applications
Philips Semiconductors
Index
Airgap, transformer core, 111, 113
Anti saturation diode, 590
Asynchronous, 497
Automotive
fans
see motor control
IGBT, 481, 483
ignition, 479, 481, 483
lamps, 435, 455
motor control, 425, 457, 459, 471, 475
resistive loads, 442
reverse battery, 452, 473, 479
screen heater, 442
seat heater, 442
solenoids, 469
TOPFET, 473
Avalanche, 61
Avalanche breakdown
thyristor, 490
Avalanche multiplication, 134
Baker clamp, 138, 187, 190
Ballast
electronic, 580
fluorescent lamp, 579
switchstart, 579
Base drive, 136
base inductor, 147
base inductor, diode assisted, 148
base resistor, 146
drive transformer, 145
drive transformer leakage inductance, 149
electronic ballast, 589
forward converter, 187
power converters, 141
speed-up capacitor, 143
Base inductor, 144, 147
Base inductor, diode assisted, 148
Boost converter, 109
continuous mode, 109
discontinuous mode, 109
output ripple, 109
Bootstrap, 303
Breakback voltage
diac, 492
Breakdown voltage, 70
Breakover current
diac, 492
Breakover voltage
diac, 492, 592
thyristor, 490
Bridge circuits
see Motor Control - AC
Brushless motor, 301, 303
Buck-boost converter, 110
Buck converter, 108 - 109
Burst firing, 537
Burst pulses, 564
Capacitance
junction, 29
Capacitor
mains dropper, 544
CENELEC, 537
Charge carriers, 133
triac commutation, 549
Choke
fluorescent lamp, 580
Choppers, 285
Clamp diode, 117
Clamp winding, 113
Commutation
diode, 164
Hi-Com triac, 551
thyristor, 492
triac, 494, 523, 529
Compact fluorescent lamp, 585
Continuous mode
see Switched Mode Power Supplies
Continuous operation, 557
Converter (dc-dc)
switched mode power supply, 107
Cookers, 537
Cooling
forced, 572
natural, 570
Crest factor, 529
Critical electric field, 134
Cross regulation, 114, 117
Current fed resonant inverter, 589
Current Mode Control, 120
Current tail, 138, 143
Damper Diodes, 345, 367
forward recovery, 328, 348
losses, 347
outlines, 345
picture distortion, 328, 348
selection guide, 345
Darlington, 13
Data Sheets
High Voltage Bipolar Transistor, 92,97,331
MOSFET, 69
i
Index Power Semiconductor Applications
Philips Semiconductors
dc-dc converter, 119
Depletion region, 133
Desaturation networks, 86
Baker clamp, 91, 138
dI/dt
triac, 531
Diac, 492, 500, 527, 530, 591
Diode, 6
double diffused, 162
epitaxial, 161
schottky, 173
structure, 161
Diode Modulator, 327, 367
Disc drives, 302
Discontinuous mode
see Switched Mode Power Supplies
Domestic Appliances, 527
Dropper
capacitive, 544
resistive, 544, 545
Duty cycle, 561
EFD core
see magnetics
Efficiency Diodes
see Damper Diodes
Electric drill, 531
Electronic ballast, 580
base drive optimisation, 589
current fed half bridge, 584, 587, 589
current fed push pull, 583, 587
flyback, 582
transistor selection guide, 587
voltage fed half bridge, 584, 588
voltage fed push pull, 583, 587
EMC, 260, 455
see RFI, ESD
TOPFET, 473
Emitter shorting
triac, 549
Epitaxial diode, 161
characteristics, 163
dI/dt, 164
forward recovery, 168
lifetime control, 162
operating frequency, 165
passivation, 162
reverse leakage, 169
reverse recovery, 162, 164
reverse recovery softness, 167
selection guide, 171
snap-off, 167
softness factor, 167
stored charge, 162
technology, 162
ESD, 67
see Protection, ESD
precautions, 67
ETD core
see magnetics
F-pack
see isolated package
Fall time, 143, 144
Fast Recovery Epitaxial Diode (FRED)
see epitaxial diode
FBSOA, 134
Ferrites
see magnetics
Flicker
fluorescent lamp, 580
Fluorescent lamp, 579
colour rendering, 579
colour temperature, 579
efficacy, 579, 580
triphosphor, 579
Flyback converter, 110, 111, 113
advantages, 114
clamp winding, 113
continuous mode, 114
coupled inductor, 113
cross regulation, 114
diodes, 115
disadvantages, 114
discontinuous mode, 114
electronic ballast, 582
leakage inductance, 113
magnetics, 213
operation, 113
rectifier circuit, 180
self oscillating power supply, 199
synchronous rectifier, 156, 181
transformer core airgap, 111, 113
transistors, 115
Flyback converter (two transistor), 111, 114
Food mixer, 531
Forward converter, 111, 116
advantages, 116
clamp diode, 117
conduction loss, 197
continuous mode, 116
core loss, 116
core saturation, 117
cross regulation, 117
diodes, 118
disadvantages, 117
duty ratio, 117
ferrite cores, 116
magnetics, 213
magnetisation energy, 116, 117
ii
Index Power Semiconductor Applications
Philips Semiconductors
operation, 116
output diodes, 117
output ripple, 116
rectifier circuit, 180
reset winding, 117
switched mode power supply, 187
switching frequency, 195
switching losses, 196
synchronous rectifier, 157, 181
transistors, 118
Forward converter (two transistor), 111, 117
Forward recovery, 168
FREDFET, 250, 253, 305
bridge circuit, 255
charge, 254
diode, 254
drive, 262
loss, 256
reverse recovery, 254
FREDFETs
motor control, 259
Full bridge converter, 111, 125
advantages, 125
diodes, 126
disadvantages, 125
operation, 125
transistors, 126
Gate
triac, 538
Gate drive
forward converter, 195
Gold doping, 162, 169
GTO, 11
Guard ring
schottky diode, 174
Half bridge, 253
Half bridge circuits
see also Motor Control - AC
Half bridge converter, 111, 122
advantages, 122
clamp diodes, 122
cross conduction, 122
diodes, 124
disadvantages, 122
electronic ballast, 584, 587, 589
flux symmetry, 122
magnetics, 214
operation, 122
synchronous rectifier, 157
transistor voltage, 122
transistors, 124
voltage doubling, 122
Heat dissipation, 567
Heat sink compound, 567
Heater controller, 544
Heaters, 537
Heatsink, 569
Heatsink compound, 514
Hi-Com triac, 519, 549, 551
commutation, 551
dIcom/dt, 552
gate trigger current, 552
inductive load control, 551
High side switch
MOSFET, 44, 436
TOPFET, 430, 473
High Voltage Bipolar Transistor, 8, 79, 91,
141, 341
‘bathtub’ curves, 333
avalanche breakdown, 131
avalanche multiplication, 134
Baker clamp, 91, 138
base-emitter breakdown, 144
base drive, 83, 92, 96, 136, 336, 385
base drive circuit, 145
base inductor, 138, 144, 147
base inductor, diode assisted, 148
base resistor, 146
breakdown voltage, 79, 86, 92
carrier concentration, 151
carrier injection, 150
conductivity modulation, 135, 150
critical electric field, 134
current crowding, 135, 136
current limiting values, 132
current tail, 138, 143
current tails, 86, 91
d-type, 346
data sheet, 92, 97, 331
depletion region, 133
desaturation, 86, 88, 91
device construction, 79
dI/dt, 139
drive transformer, 145
drive transformer leakage inductance, 149
dV/dt, 139
electric field, 133
electronic ballast, 581, 585, 587, 589
Fact Sheets, 334
fall time, 86, 99, 143, 144
FBSOA, 92, 99, 134
hard turn-off, 86
horizontal deflection, 321, 331, 341
leakage current, 98
limiting values, 97
losses, 92, 333, 342
Miller capacitance, 139
operation, 150
iii
Index Power Semiconductor Applications
Philips Semiconductors
optimum drive, 88
outlines, 332, 346
over current, 92, 98
over voltage, 92, 97
overdrive, 85, 88, 137, 138
passivation, 131
power limiting value, 132
process technology, 80
ratings, 97
RBSOA, 93, 99, 135, 138, 139
RC network, 148
reverse recovery, 143, 151
safe operating area, 99, 134
saturation, 150
saturation current, 79, 98, 341
secondary breakdown, 92, 133
smooth turn-off, 86
SMPS, 94, 339, 383
snubber, 139
space charge, 133
speed-up capacitor, 143
storage time, 86, 91, 92, 99, 138, 144, 342
sub emitter resistance, 135
switching, 80, 83, 86, 91, 98, 342
technology, 129, 149
thermal breakdown, 134
thermal runaway, 152
turn-off, 91, 92, 138, 142, 146, 151
turn-on, 91, 136, 141, 149, 150
underdrive, 85, 88
voltage limiting values, 130
Horizontal Deflection, 321, 367
base drive, 336
control ic, 401
d-type transistors, 346
damper diodes, 345, 367
diode modulator, 327, 347, 352, 367
drive circuit, 352, 365, 406
east-west correction, 325, 352, 367
line output transformer, 354
linearity correction, 323
operating cycle, 321, 332, 347
s-correction, 323, 352, 404
TDA2595, 364, 368
TDA4851, 400
TDA8433, 363, 369
test circuit, 321
transistors, 331, 341, 408
waveforms, 322
IGBT, 11, 305
automotive, 481, 483
clamped, 482, 484
ignition, 481, 483
Ignition
automotive, 479, 481, 483
darlington, 483
Induction heating, 53
Induction motor
see Motor Control - AC
Inductive load
see Solenoid
Inrush current, 528, 530
Intrinsic silicon, 133
Inverter, 260, 273
see motor control ac
current fed, 52, 53
switched mode power supply, 107
Irons, electric, 537
Isolated package, 154
stray capacitance, 154, 155
thermal resistance, 154
Isolation, 153
J-FET, 9
Junction temperature, 470, 557, 561
burst pulses, 564
non-rectangular pulse, 565
rectangular pulse, composite, 562
rectangular pulse, periodic, 561
rectangular pulse, single shot, 561
Lamp dimmer, 530
Lamps, 435
dI/dt, 438
inrush current, 438
MOSFET, 435
PWM control, 455
switch rate, 438
TOPFET, 455
Latching current
thyristor, 490
Leakage inductance, 113, 200, 523
Lifetime control, 162
Lighting
fluorescent, 579
phase control, 530
Logic Level FET
motor control, 432
Logic level MOSFET, 436
Magnetics, 207
100W 100kHz forward converter, 197
100W 50kHz forward converter, 191
50W flyback converter, 199
core losses, 208
core materials, 207
EFD core, 210
ETD core, 199, 207
iv
Index Power Semiconductor Applications
Philips Semiconductors
flyback converter, 213
forward converter, 213
half bridge converter, 214
power density, 211
push-pull converter, 213
switched mode power supply, 187
switching frequency, 215
transformer construction, 215
Mains Flicker, 537
Mains pollution, 225
pre-converter, 225
Mains transient, 544
Mesa glass, 162
Metal Oxide Varistor (MOV), 503
Miller capacitance, 139
Modelling, 236, 265
MOS Controlled Thyristor, 13
MOSFET, 9, 19, 153, 253
bootstrap, 303
breakdown voltage, 22, 70
capacitance, 30, 57, 72, 155, 156
capacitances, 24
characteristics, 23, 70 - 72
charge, 32, 57
data sheet, 69
dI/dt, 36
diode, 253
drive, 262, 264
drive circuit loss, 156
driving, 39, 250
dV/dt, 36, 39, 264
ESD, 67
gate-source protection, 264
gate charge, 195
gate drive, 195
gate resistor, 156
high side, 436
high side drive, 44
inductive load, 62
lamps, 435
leakage current, 71
linear mode, parallelling, 52
logic level, 37, 57, 305
loss, 26, 34
maximum current, 69
motor control, 259, 429
modelling, 265
on-resistance, 21, 71
package inductance, 49, 73
parallel operation, 26, 47, 49, 265
parasitic oscillations, 51
peak current rating, 251
Resonant supply, 53
reverse diode, 73
ruggedness, 61, 73
safe operating area, 25, 74
series operation, 53
SMPS, 339, 384
solenoid, 62
structure, 19
switching, 24, 29, 58, 73, 194, 262
switching loss, 196
synchronous rectifier, 179
thermal impedance, 74
thermal resistance, 70
threshold voltage, 21, 70
transconductance, 57, 72
turn-off, 34, 36
turn-on, 32, 34, 35, 155, 256
Motor, universal
back EMF, 531
starting, 528
Motor Control - AC, 245, 273
anti-parallel diode, 253
antiparallel diode, 250
carrier frequency, 245
control, 248
current rating, 262
dc link, 249
diode, 261
diode recovery, 250
duty ratio, 246
efficiency, 262
EMC, 260
filter, 250
FREDFET, 250, 259, 276
gate drives, 249
half bridge, 245
inverter, 250, 260, 273
line voltage, 262
loss, 267
MOSFET, 259
Parallel MOSFETs, 276
peak current, 251
phase voltage, 262
power factor, 262
pulse width modulation, 245, 260
ripple, 246
short circuit, 251
signal isolation, 250
snubber, 276
speed control, 248
switching frequency, 246
three phase bridge, 246
underlap, 248
Motor Control - DC, 285, 293, 425
braking, 285, 299
brushless, 301
control, 290, 295, 303
current rating, 288
v
Index Power Semiconductor Applications
Philips Semiconductors
drive, 303
duty cycle, 286
efficiency, 293
FREDFET, 287
freewheel diode, 286
full bridge, 287
half bridge, 287
high side switch, 429
IGBT, 305
inrush, 430
inverter, 302
linear, 457, 475
logic level FET, 432
loss, 288
MOSFET, 287, 429
motor current, 295
overload, 430
permanent magnet, 293, 301
permanent magnet motor, 285
PWM, 286, 293, 459, 471
servo, 298
short circuit, 431
stall, 431
TOPFET, 430, 457, 459, 475
topologies, 286
torque, 285, 294
triac, 525
voltage rating, 288
Motor Control - Stepper, 309
bipolar, 310
chopper, 314
drive, 313
hybrid, 312
permanent magnet, 309
reluctance, 311
step angle, 309
unipolar, 310
Mounting, transistor, 154
Mounting base temperature, 557
Mounting torque, 514
Parasitic oscillation, 149
Passivation, 131, 162
PCB Design, 368, 419
Phase angle, 500
Phase control, 546
thyristors and triacs, 498
triac, 523
Phase voltage
see motor control - ac
Power dissipation, 557
see High Voltage Bipolar Transistor loss,
MOSFET loss
Power factor correction, 580
active, boost converted, 581
Power MOSFET
see MOSFET
Proportional control, 537
Protection
ESD, 446, 448, 482
overvoltage, 446, 448, 469
reverse battery, 452, 473, 479
short circuit, 251, 446, 448
temperature, 446, 447, 471
TOPFET, 445, 447, 451
Pulse operation, 558
Pulse Width Modulation (PWM), 108
Push-pull converter, 111, 119
advantages, 119
clamp diodes, 119
cross conduction, 119
current mode control, 120
diodes, 121
disadvantages, 119
duty ratio, 119
electronic ballast, 582, 587
flux symmetry, 119, 120
magnetics, 213
multiple outputs, 119
operation, 119
output filter, 119
output ripple, 119
rectifier circuit, 180
switching frequency, 119
transformer, 119
transistor voltage, 119
transistors, 121
Qs (stored charge), 162
RBSOA, 93, 99, 135, 138, 139
Rectification, synchronous, 179
Reset winding, 117
Resistor
mains dropper, 544, 545
Resonant power supply, 219, 225
modelling, 236
MOSFET, 52, 53
pre-converter, 225
Reverse leakage, 169
Reverse recovery, 143, 162
RFI, 154, 158, 167, 393, 396, 497, 529, 530,
537
Ruggedness
MOSFET, 62, 73
schottky diode, 173
Safe Operating Area (SOA), 25, 74, 134, 557
forward biased, 92, 99, 134
reverse biased, 93, 99, 135, 138, 139
vi
Index Power Semiconductor Applications
Philips Semiconductors
Saturable choke
triac, 523
Schottky diode, 173
bulk leakage, 174
edge leakage, 174
guard ring, 174
reverse leakage, 174
ruggedness, 173
selection guide, 176
technology, 173
SCR
see Thyristor
Secondary breakdown, 133
Selection Guides
BU25XXA, 331
BU25XXD, 331
damper diodes, 345
EPI diodes, 171
horizontal deflection, 343
MOSFETs driving heaters, 442
MOSFETs driving lamps, 441
MOSFETs driving motors, 426
Schottky diodes, 176
SMPS, 339
Self Oscillating Power Supply (SOPS)
50W microcomputer flyback converter, 199
ETD transformer, 199
Servo, 298
Single ended push-pull
see half bridge converter
Snap-off, 167
Snubber, 93, 139, 495, 502, 523, 529, 549
active, 279
Softness factor, 167
Solenoid
TOPFET, 469, 473
turn off, 469, 473
Solid state relay, 501
SOT186, 154
SOT186A, 154
SOT199, 154
Space charge, 133
Speed-up capacitor, 143
Speed control
thyristor, 531
triac, 527
Starter
fluorescent lamp, 580
Startup circuit
electronic ballast, 591
self oscillating power supply, 201
Static Induction Thyristor, 11
Stepdown converter, 109
Stepper motor, 309
Stepup converter, 109
Storage time, 144
Stored charge, 162
Suppression
mains transient, 544
Switched Mode Power Supply (SMPS)
see also self oscillating power supply
100W 100kHz MOSFET forward converter,
192
100W 500kHz half bridge converter, 153
100W 50kHz bipolar forward converter, 187
16 & 32 kHz TV, 389
asymmetrical, 111, 113
base circuit design, 149
boost converter, 109
buck-boost converter, 110
buck converter, 108
ceramic output filter, 153
continuous mode, 109, 379
control ic, 391
control loop, 108
core excitation, 113
core loss, 167
current mode control, 120
dc-dc converter, 119
diode loss, 166
diode reverse recovery effects, 166
diode reverse recovery softness, 167
diodes, 115, 118, 121, 124, 126
discontinuous mode, 109, 379
epitaxial diodes, 112, 161
flux swing, 111
flyback converter, 92, 111, 113, 123
forward converter, 111, 116, 379
full bridge converter, 111, 125
half bridge converter, 111, 122
high voltage bipolar transistor, 94, 112, 115,
118, 121, 124, 126, 129, 339, 383, 392
isolated, 113
isolated packages, 153
isolation, 108, 111
magnetics design, 191, 197
magnetisation energy, 113
mains filter, 380
mains input, 390
MOSFET, 112, 153, 33, 384
multiple output, 111, 156
non-isolated, 108
opto-coupler, 392
output rectifiers, 163
parasitic oscillation, 149
power-down, 136
power-up, 136, 137, 139
power MOSFET, 153, 339, 384
pulse width modulation, 108
push-pull converter, 111, 119
vii
Index Power Semiconductor Applications
Philips Semiconductors
RBSOA failure, 139
rectification, 381, 392
rectification efficiency, 163
rectifier selection, 112
regulation, 108
reliability, 139
resonant
see resonant power supply
RFI, 154, 158, 167
schottky diode, 112, 154, 173
snubber, 93, 139, 383
soft start, 138
standby, 382
standby supply, 392
start-up, 391
stepdown, 109
stepup, 109
symmetrical, 111, 119, 122
synchronisation, 382
synchronous rectification, 156, 179
TDA8380, 381, 391
topologies, 107
topology output powers, 111
transformer, 111
transformer saturation, 138
transformers, 391
transistor current limiting value, 112
transistor mounting, 154
transistor selection, 112
transistor turn-off, 138
transistor turn-on, 136
transistor voltage limiting value, 112
transistors, 115, 118, 121, 124, 126
turns ratio, 111
TV & Monitors, 339, 379, 399
two transistor flyback, 111, 114
two transistor forward, 111, 117
Switching loss, 230
Synchronous, 497
Synchronous rectification, 156, 179
self driven, 181
transformer driven, 180
Temperature control, 537
Thermal
continuous operation, 557, 568
intermittent operation, 568
non-rectangular pulse, 565
pulse operation, 558
rectangular pulse, composite, 562
rectangular pulse, periodic, 561
rectangular pulse, single shot, 561
single shot operation, 561
Thermal capacity, 558, 568
Thermal characteristics
power semiconductors, 557
Thermal impedance, 74, 568
Thermal resistance, 70, 154, 557
Thermal time constant, 568
Thyristor, 10, 497, 509
’two transistor’ model, 490
applications, 527
asynchronous control, 497
avalanche breakdown, 490
breakover voltage, 490, 509
cascading, 501
commutation, 492
control, 497
current rating, 511
dI/dt, 490
dIf/dt, 491
dV/dt, 490
energy handling, 505
external commutation, 493
full wave control, 499
fusing I
2
t, 503, 512
gate cathode resistor, 500
gate circuits, 500
gate current, 490
gate power, 492
gate requirements, 492
gate specifications, 512
gate triggering, 490
half wave control, 499
holding current, 490, 509
inductive loads, 500
inrush current, 503
latching current, 490, 509
leakage current, 490
load line, 492
mounting, 514
operation, 490
overcurrent, 503
peak current, 505
phase angle, 500
phase control, 498, 527
pulsed gate, 500
resistive loads, 498
resonant circuit, 493
reverse characteristic, 489
reverse recovery, 493
RFI, 497
self commutation, 493
series choke, 502
snubber, 502
speed controller, 531
static switching, 497
structure, 489
switching, 489
viii
Index Power Semiconductor Applications
Philips Semiconductors
switching characteristics, 517
synchronous control, 497
temperature rating, 512
thermal specifications, 512
time proportional control, 497
transient protection, 502
trigger angle, 500
turn-off time, 494
turn-on, 490, 509
turn-on dI/dt, 502
varistor, 503
voltage rating, 510
Thyristor data, 509
Time proportional control, 537
TOPFET
3 pin, 445, 449, 461
5 pin, 447, 451, 457, 459, 463
driving, 449, 453, 461, 465, 467, 475
high side, 473, 475
lamps, 455
leadforms, 463
linear control, 451, 457
motor control, 430, 457, 459
negative input, 456, 465, 467
protection, 445, 447, 451, 469, 473
PWM control, 451, 455, 459
solenoids, 469
Transformer
triac controlled, 523
Transformer core airgap, 111, 113
Transformers
see magnetics
Transient thermal impedance, 559
Transient thermal response, 154
Triac, 497, 510, 518
400Hz operation, 489, 518
applications, 527, 537
asynchronous control, 497
breakover voltage, 510
charge carriers, 549
commutating dI/dt, 494
commutating dV/dt, 494
commutation, 494, 518, 523, 529, 549
control, 497
dc inductive load, 523
dc motor control, 525
dI/dt, 531, 549
dIcom/dt, 523
dV/dt, 523, 549
emitter shorting, 549
full wave control, 499
fusing I
2
t, 503, 512
gate cathode resistor, 500
gate circuits, 500
gate current, 491
gate requirements, 492
gate resistor, 540, 545
gate sensitivity, 491
gate triggering, 538
holding current, 491, 510
Hi-Com, 549, 551
inductive loads, 500
inrush current, 503
isolated trigger, 501
latching current, 491, 510
operation, 491
overcurrent, 503
phase angle, 500
phase control, 498, 527, 546
protection, 544
pulse triggering, 492
pulsed gate, 500
quadrants, 491, 510
resistive loads, 498
RFI, 497
saturable choke, 523
series choke, 502
snubber, 495, 502, 523, 529, 549
speed controller, 527
static switching, 497
structure, 489
switching, 489
synchronous control, 497
transformer load, 523
transient protection, 502
trigger angle, 492, 500
triggering, 550
turn-on dI/dt, 502
varistor, 503
zero crossing, 537
Trigger angle, 500
TV & Monitors
16 kHz black line, 351
30-64 kHz autosync, 399
32 kHz black line, 361
damper diodes, 345, 367
diode modulator, 327, 367
EHT, 352 - 354, 368, 409, 410
high voltage bipolar transistor, 339, 341
horizontal deflection, 341
picture distortion, 348
power MOSFET, 339
SMPS, 339, 354, 379, 389, 399
vertical deflection, 358, 364, 402
Two transistor flyback converter, 111, 114
Two transistor forward converter, 111, 117
Universal motor
back EMF, 531
ix
Index Power Semiconductor Applications
Philips Semiconductors
starting, 528
Vacuum cleaner, 527
Varistor, 503
Vertical Deflection, 358, 364, 402
Voltage doubling, 122
Water heaters, 537
Zero crossing, 537
Zero voltage switching, 537
x
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
CHAPTER 2
Switched Mode Power Supplies
2.1 Using Power Semiconductors in Switched Mode Topologies
(including transistor selection guides)
2.2 Output Rectification
2.3 Design Examples
2.4 Magnetics Design
2.5 Resonant Power Supplies
103
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Using Power Semiconductors in Switched Mode Topologies
105
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
2.1.1 An Introduction to Switched Mode Power Supply
Topologies
For many years the world of power supply design has seen
a gradual movement away from the use of linear power
supplies to the more practical switched mode power supply
(S.M.P.S.). The linear power supply contains a mains
transformer and a dissipative series regulator. This means
the supply has extremely large and heavy 50/60 Hz
transformers, and also very poor power conversion
efficiencies, bothserious drawbacks. Typical efficiencies of
30% are standard for a linear. This compares with
efficiencies of between 70 and 80%, currently available
using S.M.P.S. designs.
Furthermore, by employing high switching frequencies, the
sizes of the power transformer and associated filtering
components in the S.M.P.S. are dramatically reduced in
comparison to the linear. For example, an S.M.P.S.
operating at 20kHz produces a 4 times reduction in
component size, and this increases to about 8 times at
100kHz and above. This means an S.M.P.S. design can
produce very compact and lightweight supplies. This is now
an essential requirement for the majority of electronic
systems. The supply must slot into an ever shrinking space
left for it by electronic system designers.
Outline
At the heart of the converter is the high frequency inverter
section, where the input supply is chopped at very high
frequencies(20to200kHzusingpresent technologies) then
filtered and smoothed to produce dc outputs. The circuit
configuration which determines how the power is
transferred is called the TOPOLOGY of the S.M.P.S., and
is an extremely important part of the design process. The
topology consists of an arrangement of transformer,
inductors, capacitors and power semiconductors (bipolar
or MOSFET power transistors and power rectifiers).
Presently, there is a very wide choice of topologies
available, each one having its own particular advantages
and disadvantages, making it suitable for specific power
supply applications. Basic operation, advantages,
drawbacks and most common areas of use for the most
commontopologies arediscussed in the followingsections.
A selection guide to the Philips range of power
semiconductors (including bipolars, MOSFETs and
rectifiers) suitable for use in S.M.P.S. applications is given
at the end of each section.
(1) Basic switched mode supply circuit.
An S.M.P.S. can be a fairly complicated circuit, as can be
seen from the block diagram shown in Fig. 1. (This
configuration assumes a 50/60Hz mains input supply is
used.) The ac supply is first rectified, and then filtered by
the input reservoir capacitor to produce a rough dc input
supply. This level can fluctuate widely due to variations in
the mains. In addition the capacitance on the input has to
be fairly large to hold up the supply in case of a severe
droop in the mains. (The S.M.P.S. can also be configured
tooperate fromany suitable dc input, in this case the supply
is called a dc to dc converter.)
Fig. 1. Basic switched mode power supply block diagram.
Power
Transformer
High
Frequency
switch
Output rectification
and filtering and filtering
dc output
voltage
Vref
PWM
OSC
control
circuitry
T
ac input
supply
duty cycle
control
mosfet or
bipolar
Input rectification
107
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
The unregulated dc is fed directly to the central block of the
supply, the high frequency power switching section. Fast
switchingpower semiconductor devices such asMOSFETs
and Bipolars are driven on and off, and switch the input
voltage across the primary of the power transformer. The
drive pulses are normally fixed frequency (20 to 200kHz)
and variable duty cycle. Hence, a voltage pulse train of
suitable magnitude and duty ratio appears on the
transformer secondaries. This voltage pulse train is
appropriately rectified, and then smoothed by the output
filter, which is either a capacitor or capacitor / inductor
arrangement, depending upon the topology used. This
transfer of power has tobecarriedout withthelowest losses
possible, to maintain efficiency. Thus, optimum design of
the passive andmagnetic components, andselection of the
correct power semiconductors is critical.
Regulation of the output to provide a stabilised dc supply
is carried out by the control / feedback block. Generally,
most S.M.P.S. systems operate on a fixed frequency pulse
width modulation basis, where the duration of the on time
of the drive to the power switch is varied on a cycle by cycle
basis. This compensates for changes in the input supply
and output load. The output voltage is compared to an
accurate reference supply, and the error voltage produced
by the comparator is used by dedicated control logic to
terminatethe drive pulseto the mainpower switch/switches
at the correct instance. Correctly designed, this will provide
a very stable dc output supply.
It is essential that delays in the control loop are kept to a
minimum, otherwisestabilityproblemswouldoccur. Hence,
very high speed components must be selected for the loop.
In transformer-coupled supplies, in order to keep the
isolation barrier intact, some type of electronic isolation is
required in the feedback. This is usually achieved by using
a small pulse transformer or an opto-isolator, hence adding
to the component count.
In most applications, the S.M.P.S. topology contains a
power transformer. This provides isolation, voltage scaling
through the turns ratio, and the ability to provide multiple
outputs. However, there are non-isolated topologies
(without transformers) such as the buck and the boost
converters, where the power processing is achieved by
inductive energy transfer alone. All of the more complex
arrangements are based on these non-isolated types.
(2) Non-Isolated converters.
The majority of the topologies used in today’s converters
are all derived from the following three non-isolated
versions called the buck, the boost and the buck-boost.
These are the simplest configurations possible, and have
the lowest component count, requiring only one inductor,
capacitor, transistor and diode to generate their single
output. If isolation between the input and output is required,
a transformer must be included before the converter.
(a) The Buck converter.
The forward converter family which includes the push-pull
and bridge types, are all based on the buck converter,
shown in Fig. 2. Its operation is straightforward. When
switch TR1 is turned on, the input voltage is applied to
inductor L1 and power is delivered to the output. Inductor
current also builds up according to Faraday’s law shown
below:-
When the switch is turned off, the voltage across the
inductor reverses and freewheel diode D1 becomes
forwardbiased. Thisallows theenergy storedintheinductor
tobe deliveredto the output. This continuous current is then
smoothed by output capacitor Co. Typical buck waveforms
are also shown in Fig. 2.
Fig. 2 Buck Regulator (step-down).
The LC filter has an averaging effect on the applied
pulsating input, producing a smooth dc output voltage and
current, with very small ripple components superimposed.
The average voltage/sec across the inductor over a
complete switching cycle must equal zero in the steady
state. (The same applies to all of the regulators that will be
discussed.)
V · L
dI
dt
Vin Vo
CONTROL
CIRCUIT
Vo
L1
D1
Co
TR1
T = ton + toff
ton
toff
Applied
voltage
v
A
Vin
Vin - Vo
Io
Vo
Vo
Inductor
current
I
L
Inductor
voltage
V
L
TR1
current
Iin
I
D
ton toff
T
0
0
0
0
t
t
t
t
Continuous mode
108
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Neglecting circuit losses, the average voltage at the input
side of the inductor is V
in
D, while V
o
is the output side
voltage. Thus, in the steady state, for the average voltage
across the inductor to be zero, the basic dc equation of the
buck is simply:-
D is the transistor switch duty cycle, defined as the
conduction time divided by one switching period, usually
expressed in the form shown below:-
Thus, the buck isastepdowntype, wherethe output voltage
isalways lower than theinput. (SinceDnever reaches one.)
Output voltage regulation is provided by varying the duty
cycle of the switch. The LC arrangement provides very
effective filtering of the inductor current. Hence, the buck
and its derivatives all have very low output ripple
characteristics. The buck is normally always operated in
continuous mode ( inductor current never falls to zero)
where peak currents are lower, and the smoothing
capacitor requirements are smaller. There are no major
control problems with the continuous mode buck.
(b) The Boost Converter.
Operation of another fundamental regulator, the boost,
shown in Fig. 3 is more complex than the buck. When the
switch is on, diode D1 is reverse biased, and V
in
is applied
across inductor, L1. Current builds up in the inductor to a
peak value, either from zero current in a discontinuous
mode, or an initial value in the continuous mode. When the
switch turns off, the voltage across L1 reverses, causing
the voltage at the diode to rise above the input voltage. The
diode then conducts the energy stored in the inductor, plus
energy direct from the supply to the smoothing capacitor
and load. Hence, V
o
is always greater than V
in
, making this
a stepup converter. For continuous mode operation, the
boost dc equation is obtained by a similar process as for
the buck, and is given below:-
Again, the output only depends upon the input and duty
cycle. Thus, by controlling the duty cycle, output regulation
is achieved.
From the boost waveforms shown in Fig. 3, it is clear that
the current supplied to the output smoothing capacitor from
the converter is the diode current, which will always be
discontinuous. This means that the output capacitor must
be large, with a low equivalent series resistance (e.s.r) to
produce a relatively acceptable output ripple. This is in
contrast to the buck output capacitor requirements
describedearlier. Ontheother hand, the boost input current
is the continuous inductor current, and this provides low
input ripple characteristics. The boost is very popular for
capacitive load applications such as photo-flashers and
battery chargers. Furthermore, the continuousinput current
makestheboost apopular choice asapre-regulator, placed
before the main converter. The main functions being to
regulate the input supply, and to greatly improve the line
power factor. This requirement has become very important
in recent years, in a concerted effort to improve the power
factor of the mains supplies.
Fig. 3 Boost Regulator (step-up).
If the boost is used in discontinuous mode, the peak
transistor and diode currents will be higher, and the output
capacitor will need to be doubled in size to achieve the
same output ripple as in continuous mode. Furthermore, in
discontinuous operation, the output voltage also becomes
dependent on the load, resulting in poorer load regulation.
Unfortunately, there are major control and regulation
problems with the boost when operated in continuous
mode. The pseudo LC filter effectively causes a complex
second order characteristic in the small signal (control)
response. In the discontinuous mode, the energy in the
inductor at the start of each cycle is zero. This removes the
inductance fromthe small signal response, leaving only the
output capacitance effect. This produces a much simpler
response, which is far easier to compensate and control.
V
o
V
i
· D
D ·
t
on
T
; where T · t
on
+ t
off
Vin Vo
CONTROL
CIRCUIT
Vo
L1
Co
TR1
D1
Inductor
current
I
L
TR1
current
ton toff
T
0
0
0
0
t
t
t
t
Vo
I
in
TR1
voltage
V
ce
Diode
current
I
D
Io
CONTINUOUS MODE
V
o
V
i
·
1
1 − D
109
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
(c) The Buck-Boost Regulator
(Non-isolated Flyback).
The very popular flyback converter (see section 5(a)) is not
actually derived solely from the boost. The flyback only
delivers stored inductor energy during the switch off-time.
The boost, however, also delivers energy from the input.
The flyback is actually based on a combined topology of
the previous two, called the buck-boost or non isolated
flyback regulator. This topology is shown in Fig. 4.
Fig. 4 Buck-Boost (Flyback) Regulator.
When the switch is on, the diode is reverse biased and the
input is connected across the inductor, which stores energy
as previously explained. At turn-off, the inductor voltage
reverses and the stored energy is then passed to the
capacitor and load through the forward biased rectifier
diode.
The waveforms are similar to the boost except that the
transistor switch now has to support the sumof Vin and Vo
across it. Clearly, both the input and output currents must
be discontinuous. There is also a polarity inversion, the
output voltage generated is negative with respect to the
input. Close inspection reveals that the continuous mode
dc transfer function is as shown below:-
Observation shows that the value of the switch duty ratio,
D can be selected such that the output voltage can either
be higher or lower than the input voltage. This gives the
converter the flexibility to either step up or step down the
supply.
This regulator also suffers fromthe same continuous mode
control problems as the boost, and discontinuous mode is
usually favoured.
Since both input and output currents are pulsating, low
ripple levels are very difficult to achieve using the
buck-boost. Very large output filter capacitors are needed,
typically up to 8 times that of a buck regulator.
The transistor switch also needs to be able to conduct the
highpeakcurrent, aswell as supportingthehigher summed
voltage. Theflyback regulator (buck-boost) topologyplaces
the most stress on the transistor. The rectifier diode also
has to carry high peak currents and so the r.m.s conduction
losses will be higher than those of the buck.
V
o
V
i
·
D
1 − D
Vin
CONTROL
CIRCUIT
Vo
L1
D1
Co
TR1
-Vo
Step up / down Polarity inversion
110
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
(3) Transformers in S.M.P.S. converters.
The non-isolated versions have very limited use, such as
dc-dc regulators only capable of producing a single output.
The output range is also limited by the input and duty cycle.
The addition of a transformer removes most of these
constraints and provides a converter with the following
advantages:-
1) Input to output isolation is provided. This is normally
always necessary for 220/ 110Vmains applications, where
a degree of safety is provided for the outputs.
2) The transformer turns ratio can be selected to provide
outputs widely different from the input; non-isolated
versions are limited to a range of approximately 5 times.
By selecting the correct turns ratio, the duty cycle of the
converter can also be optimised and the peak currents
flowing minimised. The polarity of each output is also
selectable, dependent upon the polarity of the secondary
w.r.t the primary.
3) Multiple outputs are very easily obtained, simply by
adding more secondary windings to the transformer.
There are some disadvantages with transformers, such as
their additional size, weight and power loss. The generation
of voltage spikes due to leakage inductance may also be a
problem.
Theisolatedconverters tobecoveredare split intotwomain
categories, called asymmetrical and symmetrical
converters, depending upon how the transformer is
operated.
Fig. 5 Comparative core usage of asymmetrical and
symmetrical converters.
In asymmetrical converters the magnetic operating point of
the transformer is always in one quadrant i.e the flux and
the magnetic field never changes sign. The core has to be
reset each cycle to avoid saturation, meaning that only half
of the usable flux is ever exploited. This can be seen in
Fig. 5, which shows the operating mode of each converter.
The flyback and forward converter are both asymmetrical
types. The diagramalso indicates that the flyback converter
is operated at a lower permeability (B/H) and lower
inductance than the others. This is because the flyback
transformer actually stores all of theenergy beforedumping
into the load, hence an air gap is required to store this
energy and avoid coresaturation. The air gap has the effect
of reducing the overall permeability of the core. All of the
other converters have true transformer action and ideally
store no energy, hence, no air gap is needed.
Inthe symmetrical converters whichalways requireaneven
number of transistor switches, the full available flux swing
in both quadrants of the B / H loop is used, thus utilising
the core much more effectively. Symmetrical converters
can therefore produce more power than their asymmetrical
cousins. The 3 major symmetrical topologies used in
practiceare the push-pull, the half-bridgeandthe full bridge
types.
Table 1 outlines the typical maximum output power
available from each topology using present day
technologies:-
Converter Topology Typical max output power
Flyback 200W
Forward 300W
Two transistor forward / 400W
flyback
Push-pull 500W
Half-Bridge 1000W
Full-Bridge >1000W
Table 1. Converter output power range.
Many other topologies exist, but the types outlined in Table
1 are by far the most commonly used in present S.M.P.S.
designs. Each is now looked at in more detail, with a
selection guide for the most suitable Philips power
semiconductors included.
B
H
Bs
2Bs
flyback
converter
forward
converter
symmetrical
converters
asymmetrical
converters
symmetrical
converters
available
flux swing
111
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
(4) Selection of the power
semiconductors.
The Power Transistor.
The two most common power semiconductors used in the
S.M.P.S. are theBipolar transistor andthepower MOSFET.
The Bipolar transistor is normally limited to use at
frequencies up to 30kHz, due to switching loss. However,
it has very low on-state losses and is a relatively cheap
device, making it the most suitable for lower frequency
applications. The MOSFETis selected for higher frequency
operation because of its very fast switching speeds,
resulting in low (frequency dependent) switching losses.
The driving of the MOSFET is also far simpler and less
expensive than that required for the Bipolar. However, the
on-state losses of the MOSFET are far higher than the
Bipolar, and they are also usually more expensive. The
selection of which particular device to use is normally a
compromise between the cost, and the performance
required.
(i) Voltage limiting value:-
After deciding upon whether to use a Bipolar or MOSFET,
the next step in deciding upon a suitable type is by the
correct selection of the transistor voltage. For transformer
coupled topologies, the maximum voltage developed
across the device is normally at turn-off. This will be either
half, full or double themagnitudeof the input supply voltage,
dependent upon the topology used. There may also be a
significant voltage spike due to transformer leakage
inductance that must be included. The transistor must
safely withstand these worst case values without breaking
down. Hence, for a bipolar device, a suitably high V
ces(max)
must be selected, and for a MOSFET, a suitably high
V
BR(DSS)
. At present 1750Vis the maximumblocking voltage
available for power Bipolars, and a maximum of 1000V for
power MOSFETs.
The selection guides assume that a rectified 220V or 110V
mains input is used. The maximum dc link voltages that will
be produced for these conditions are 385V and 190V
respectively. Thesevalues arethe input voltagelevelsused
to select the correct device voltage rating.
(ii) Current limiting value:-
The Bipolar device has a very low voltage drop across it
during conduction, which is relatively constant within the
rated current range. Hence, for maximum utilisation of a
bipolar transistor, it should be run close to its I
Csat
value.
This gives a good compromise between cost, drive
requirements and switching. The maximum current for a
particular throughput power is calculated for each topology
using simple equations. These equations are listed in the
appropriatesections, and the levels obtained used toselect
a suitable Bipolar device.
The MOSFET device operates differently from the bipolar
in that the voltage developed across it (hence, transistor
dissipation) is dependent upon the current flowing and the
device "on-resistance" which is variable with temperature.
Hence, the optimum MOSFET for a given converter can
onlybechosenonthe basis that thedevice must not exceed
a certain percentage of throughput (output) power. (In this
selection a 5% loss in the MOSFET was assumed). A set
of equations used to estimate the correct MOSFET R
DS(on)
value for a particular power level has been derived for each
topology. These equations are included in Appendix A at
the end of the paper. The value of RDS(on) obtained was
then used to select a suitable MOSFET device for each
requirement.
NOTE! This method assumes negligible switching losses
in the MOSFET. However for frequencies above 50kHz,
switching losses become increasingly significant.
Rectifiers
Two types of output rectifier are specified from the Philips
range. For very low output voltages below 10V it is
necessarytohaveanextremely lowrectifier forwardvoltage
drop, V
F
, in order tokeep converter efficiency high. Schottky
types are specified here, sincethey have very lowV
F
values
(typically 0.5V). The Schottky also has negligible switching
losses and can be used at very high frequencies.
Unfortunately, theverylowV
F
of theSchottkyislost at higher
reverse blocking voltages (typically above 100V) and other
diode types become more suitable. This means that the
Schottky is normally reserved for use on outputs up to 20V
or so.
Note. A suitable guideline in selecting the correct rectifier
reversevoltageis toensurethe device will block 4to6times
theoutput voltageit isusedtoprovide(depends on topology
and whether rugged devices are being used).
For higher voltage outputs the most suitable rectifier is the
fast recovery epitaxial diode (FRED). This device has been
optimised for use in high frequency rectification. Its
characteristics include low V
F
(approx. 1V) with very fast
and efficient switching characteristics. The FRED has
reverse voltage blocking capabilities up to 800V. They are
therefore suitable for use in outputs from 10 to 200V.
The rectifier devices specified in each selection guide were
chosenashaving the correct voltagelimitingvalueand high
enough current handling capability for the particular output
power specified. (A single output is assumed).
112
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
(5) Standard isolated topologies.
(a) The Flyback converter.
Operation
Of all the isolated converters, by far the simplest is the
single-ended flyback converter shown in Fig. 6. The use of
a single transistor switch means that the transformer can
only be driven unipolar (asymmetrical). This results in a
large core size. The flyback, which is an isolated version of
the buck-boost, does not in truth contain a transformer but
a coupled inductor arrangement. When the transistor is
turned on, current builds up in the primary and energy is
stored in the core, this energy is then released to the output
circuit through the secondary when the switch is turned off.
(A normal transformer such as the types used in the buck
derived topologies couples the energy directly during
transistor on-time, ideally storing no energy).
Fig. 6 Flyback converter circuit and waveforms.
The polarity of the windings is such that the output diode
blocks during the transistor on time. When the transistor
turns off, the secondary voltage reverses, maintaining a
constant flux in the core and forcing secondary current to
flow through the diode to the output load. The magnitude
of the peak secondary current is the peak primary current
reached at transistor turn-off reflected through the turns
ratio, thus maintaining a constant Ampere-turn balance.
The fact that all of the output power of the flyback has to
be stored in the core as 1/2LI
2
energy means that the core
size and cost will be much greater than in the other
topologies, where only the core excitation (magnetisation)
energy, which is normally small, is stored. This, in addition
to the initial poor unipolar core utilisation, means that the
transformer bulk is one of the major drawbacks of the
flyback converter.
Inorder toobtain sufficiently high stored energy, the flyback
primary inductance has to be significantly lower than
required for a true transformer, since high peak currents
are needed. This is normally achieved by gapping the core.
The gap reduces the inductance, and most of the high peak
energy is then stored in the gap, thus avoiding transformer
saturation.
When the transistor turns off, the output voltage is back
reflectedthroughthetransformer totheprimaryandinmany
cases this can be nearly as high as the supply voltage.
There is also a voltage spike at turn-off due to the stored
energy in the transformer leakage inductance. This means
that the transistor must be capable of blocking
approximately twice the supply voltage plus the leakage
spike. Hence, for a 220V ac application where the dc link
canbe up to 385V, the transistor voltagelimiting valuemust
lie between 800 and 1000V.
Using a 1000V Bipolar transistor such as the BUT11A or
BUW13Aallows a switching frequency of 30kHz to be used
at output powers up to 200Watts.
MOSFETs with 800V and 1000V limiting values can also
beused, suchastheBUK456-800Awhichcansupply100W
at switching frequencies anywhere up to 300kHz. Although
the MOSFET can be switched much faster and has lower
switching losses , it does suffer from significant on-state
losses, especially in the higher voltage devices when
compared to the bipolars. An outline of suitable transistors
and output rectifiers for different input and power levels
using the flyback is given in Table 2.
Oneway of removingthe transformer leakagevoltagespike
is to add a clamp winding as shown in Fig. 8. This allows
the leakage energy to be returned to the input instead of
stressing the transistor. The diode is always placed at the
high voltage end so that the clamp winding capacitance
does not interfere with the transistor turn-on current spike,
which would happen if the diode was connected to ground.
This clamp is optional and depends on the designer’s
particular requirements.
T1
n:1
Vo
Co
D1
Vin
TR1
I
P
I
sw
Primary
current
sec
current
I
I
D
S
Ip = Vin.ton/Lp
Isec = Idiode
Switch
voltage
Vce
or
Vds
ton toff
Vin
leakage
inductance
spike
T
t
t
t
0
0
0
(discontinuous)
Discontinuous
Vin + Vo n1
n2
113
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Advantages.
The action of the flyback means that the secondary
inductance is in series with the output diode when current
is delivered to the load; i.e driven from a current source.
This means that no filter inductor is needed in the output
circuit. Hence, each output requires only one diode and
output filter capacitor. This means the flyback is the ideal
choicefor generatinglowcost, multipleoutput supplies. The
cross regulationobtained usingmultipleoutputs isalso very
good (load changes on one output have little effect on the
others) because of the absence of the output choke, which
degrades this dynamic performance.
The flyback is also ideally suited for generatinghigh voltage
outputs. If a buck type LCfilter was used to generate a high
voltage, a very large inductance value would be needed to
reduce the ripple current levels sufficiently to achieve the
continuous mode operation required. This restriction does
not apply to the flyback, since it does not require an output
inductance for successful operation.
Disadvantages.
From the flyback waveforms in Fig. 6 it is clear that the
output capacitor is only supplied during the transistor off
time. This means that the capacitor has to smooth a
pulsating output current which has higher peak values than
the continuous output current that would be produced in a
forward converter, for example. In order to achieve low
output ripple, very large output capacitors are needed, with
very low equivalent series resistance (e.s.r). It can be
shown that at the same frequency, an LC filter is
approximately 8 times more effective at ripple reduction
than a capacitor alone. Hence, flybacks have inherently
much higher output ripples than other topologies. This,
together with the higher peak currents, largecapacitors and
transformers, limits the flyback to lower output power
applications in the 20 to 200W range. (It should be noted
that at higher voltages, the required output voltage ripple
magnitudes are not normally as stringent, and this means
that the e.s.r requirement and hence capacitor size will not
be as large as expected.)
Two transistor flyback.
One possible solution to the 1000V transistor requirement
is the two transistor flyback version shown in Fig. 7. Both
transistors are switched simultaneously, and all waveforms
are exactly the same, except that the voltage across each
transistor never exceeds the input voltage. The clamp
winding is now redundant, since the two clamp diodes act
to return leakage energy to the input. Two 400 or 500V
devices can now be selected, which will have faster
switching and lower conduction losses. The output power
and switching frequencies can thus be significantly
increased. The drawbacks of the two transistor version are
the extra cost and more complex isolated base drive
needed for the top floating transistor.
Fig. 7 Two transistor Flyback.
Continuous Vs Discontinuous operation.
As with the buck-boost, the flyback can operate in both
continuous and discontinuous modes. The waveforms in
Fig. 6 show discontinuous mode operation. In
discontinuous mode, the secondary current falls to zero in
each switching period, and all of the energy is removed
from the transformer. In continuous mode there is current
flowing in the coupled inductor at all times, resulting in
trapezoidal current waveforms.
The main plus of continuous mode is that the peak currents
flowing are only half that of the discontinuous for the same
output power, hence, lower output ripple is possible.
However, the core size is about 2 to 4 times larger in
continuous mode to achieve the increased inductance
needed to reduce the peak currents to achieve continuity.
A further disadvantage of continuous mode is that the
closed loop is far more difficult to control than the
discontinuous mode flyback. (Continuous mode contains a
right hand plane zero in its open loop frequency response,
the discontinuous flyback does not. See Ref[2] for further
explanation.) This means that much more time and effort
is required for continuous mode to design the much more
complicatedcompensationcomponents needed to achieve
stability.
There is negligible turn-on dissipation in the transistor in
discontinuous mode, whereas this dissipation can be fairly
high in continuous mode, especially when the additional
effects of the output diode reverse recovery current, which
only occurs in the continuous case, is included. This
normally means that a snubber must be added to protect
the transistor against switch-on stresses.
One advantageof the continuous mode is that its open loop
gain is independent of the output load i.e V
o
only depends
upon D and V
in
as shown in the dc gain equation at the end
of the section. Continuous mode has excellent open loop
load regulation, i.e varying the output load will not affect V
o
.
Discontinuous mode, on the other-hand, does have a
dependency on the output, expressed as R
L
in the dc gain
equation. Hence, discontinuous mode has a much poorer
Vo
Vin
T1
Co
n : 1
TR1
D1
TR2
isolated
base
drive
114
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
open loop load regulation, i.e changing the output will affect
V
o
. This problem disappears, however, when the control
loop is closed, and the load regulation problem is usually
completely overcome.
The use of current mode control with discontinuous flyback
(where both the primary current and output voltage are
sensed and combined to control the duty cycle) produces
a much improved overall loop regulation, requiring less
closed loop gain.
Although the discontinuous mode has the major
disadvantage of very high peak currents and a large output
capacitor requirement, it is much easier to implement, and
is by far the more common of the two methods used in
present day designs.
Output power 50W 100W 200W
Line voltage, Vin 110V ac 220V ac 110V ac 220V ac 110V ac 220V ac
Transistor requirements
Max current 2.25A 1.2A 4A 2.5A 8A 4.4A
Max voltage 400V 800V 400V 800V 400V 800V
Bipolar transistors.
TO-220 BUT11 BUX85 BUT12 BUT11A --- BUT12A
Isolated SOT-186 BUT11F BUX85F BUT12F BUT11AF --- BUT12AF
SOT-93 --- --- --- --- BUW13 ---
Isolated SOT-199 --- --- --- --- BUW13F ---
Power MOSFET
TO-220 BUK454-400B BUK454-800A BUK455-400B BUK456-800A --- ---
Isolated SOT-186 BUK444-400B BUK444-800A BUK445-400B BUK446-800A --- ---
SOT-93 --- --- --- --- BUK437-400B BUK438-800A
Output Rectifiers
O/P voltage
5V PBYR1635 PBYR2535CT ---
10V PBYR10100 PBYR20100CT PBYR30100PT
BYW29E-100/150/200 BYV79E-100/150/200 BYV42E-100/150/200
BYV72E-100/150/200
20V PBYR10100 PBYR10100 PBYR20100CT
BYW29E-100/150/200 BYW29E-100/150/200 BYV32E-100/150/200
50V BYV29-300 BYV29-300 BYV29-300
100V BYV29-500 BYV29-500 BYV29-500
Table 2. Recommended Power Semiconductors for single-ended flyback.
Note! The above values are for discontinuous mode. In continuous mode the peak transistor currents are approximately
halved and the output power available is thus increased.
Flyback
Converter efficiency, η = 80%; Max duty cycle, D
max
= 0.45
Max transistor voltage, V
ce
or V
ds
= 2V
in(max)
+ leakage spike
dc voltage gain:- (a) continuous (b) Discontinuous
Applications:- Lowest cost, multiple output supplies in the 20 to 200W range. E.g. mains input T.V. supplies, small
computer supplies, E.H.T. supplies.
Maxtransistorcurrent , I
C
; I
D
· 2
P
out
η D
max
V
min
Vo
Vin
· n
D
1 − D
Vo
Vin
· D

R
L
T
2 L
P
115
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
(b) The Forward converter.
Operation.
The forward converter is also a single switch isolated
topology, and is shown in Fig. 8. This is based on the buck
converter described earlier, with the addition of a
transformer and another diode in the output circuit. The
characteristic LC output filter is clearly present.
In contrast to the flyback, the forward converter has a true
transformer action, where energy is transferred directly to
the output through the inductor during the transistor
on-time. It can be seen that the polarity of the secondary
winding is opposite to that of the flyback, hence allowing
direct current flow through blocking diode D1. During the
on-time, the current flowing causes energy to be built up in
the output inductor L1. When the transistor turns off, the
secondary voltage reverses, D1 goes from conducting to
blocking mode and the freewheel diode D2 then becomes
forward biased and provides a path for the inductor current
to continue to flow. This allows the energy stored in L1 to
be released into the load during the transistor off time.
The forward converter is always operated in continuous
mode (in this case the output inductor current), since this
producesvery lowpeak input and output currents and small
ripple components. Going into discontinuous mode would
greatly increase these values, as well as increasing the
amount of switching noise generated. No destabilising right
hand plane zero occurs in the frequency response of the
forward in continuous mode (as with the buck). See Ref[2].
This means that the control problems that existed with the
continuous flyback are not present here. So there are no
real advantages to be gained by using discontinuous mode
operation for the forward converter.
Advantages.
As can be seen from the waveforms in Fig. 8, the inductor
current I
L
, which is also the output current, is always
continuous. The magnitude of the ripple component, and
hence the peak secondary current, depends upon the size
of the output inductor. Therefore, the ripple can be made
relatively small compared to the output current, with the
peak current minimised. This low ripple, continuous output
current is very easy to smooth, and so the requirements for
the output capacitor size, e.s.r and peak current handling
are far smaller than they are for the flyback.
Since the transformer in this topology transfers energy
directly there is negligible stored energy in the core
compared to the flyback. However, there is a small
magnetisation energy required to excite the core, allowing
it to become an energy transfer medium. This energy is
very small and only a very small primary magnetisation
current is needed. This means that a high primary
inductance is usually suitable, with no need for the core air
gap required in the flyback. Standard un-gapped ferrite
cores with high permeabilities (2000-3000) are ideal for
providing the high inductance required. Negligible energy
storage means that the forward converter transformer is
considerably smaller than the flyback, and core loss is also
muchsmaller for the samethroughput power. However, the
transformer is still operated asymmetrically, which means
that power is only transferred during the switch on-time,
and this poor utilisation means the transformer is still far
bigger than in the symmetrical types.
The transistors have the same voltage rating as the
discontinuous flyback (see disadvantages), but the peak
current required for the same output power is halved, and
this can be seen in the equations given for the forward
converter. This, coupled with the smaller transformer and
output filter capacitor requirements means that the forward
converter is suitable for use at higher output powers than
the flyback can attain, and is normally designed to operate
in the 100 to 400Wrange. Suitable bipolars and MOSFETs
for the forward converter are listed in Table 3.
Fig. 8 The Forward converter and waveforms.
CONTROL
CIRCUIT
Vo
Vo
Vin
T1 D1
Co
n : 1
TR1
D2
L1
D3
Clamp
winding
necessary
Io
Inductor
current
I
L
TR1
current
ton toff
T
0
0
0
t
t
t
t
Diode
currents
Id1
Id2
Ip
output
TR1
voltage
Vce
Vin
2Vin
t
Imag
0
0
Id3
Is
116
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Disadvantages.
Because of the unipolar switching action of the forward
converter, there is a major problem in how to remove the
core magnetisation energy by the end of each switching
cycle. If this did not happen, there would be a net dc flux
build-up, leading to core saturation, and possible transistor
destruction. This magnetisation energy is removed
automatically by the push-pull action of the symmetrical
types. In the flyback this energy is dumped into the load at
transistor turn-off. However, there is no such path in the
forward circuit.
This path is provided by adding an additional reset winding
of opposite polarity to the primary. A clamp diode is added,
such that the magnetisation energy is returned to the input
supply during the transistor off time. The reset winding is
wound bifilar with the primary to ensure good coupling, and
is normally made to have the same number of turns as the
primary. (The reset winding wire gauge can be very small,
since it only has to conduct the small magnetisation
current.) The time for the magnetisation energy to fall to
zero is thus the same duration as the transistor on-time.
This means that the maximum theoretical duty ratio of the
forward converter is 0.5 and after taking into account
switchingdelays, this falls to0.45. This limited control range
is one of the drawbacks of using the forward converter. The
waveform of the magnetisation current is also shown in
Fig. 8. The clamp winding in the flyback is optional, but is
always needed in the forward for correct operation.
Due to the presence of the reset winding, in order to
maintain volt-sec balance within the transformer, the input
voltage is back reflected to the primary from the clamp
winding at transistor turn-off for the duration of the flow of
the magnetisation reset current through D3. (There is also
a voltage reversal across the secondary winding, and this
is why diode D1 is added to block this voltage from the
output circuit.) This means that the transistor must block
two times Vin during switch-off. The voltage returns to Vin
after reset has finished, which means transistor turn-on
losses will be smaller. The transistors must have the same
added burden of the voltage rating of the flyback, i.e 400V
for 110V mains and 800V for 220V mains applications.
Output diode selection.
The diodes in the output circuit both have to conduct the
full magnitude of the output current. They are also subject
to abrupt changes in current, causing a reverse recovery
spike, particularly in the freewheel diode, D2. This spike
cancauseadditional turn-onswitchingloss inthe transistor,
possibly causing device failure in the absence of snubbing.
Thus, very high efficiency, fast trr diodes are required to
minimise conduction losses and to reduce the reverse
recovery spike. These requirements are met with Schottky
diodes for outputs up to 20V, and fast recovery epitaxial
diodesfor higher voltageoutputs. It is not normal for forward
converter outputs to exceed 100V because of the need for
a very large output choke, and flybacks are normally used.
Usually, both rectifiers are included in a single package i.e
a dual centre-tap arrangement. The Philips range of
Schottkies and FREDs which meet these requirements are
also included in Table 3.
Two transistor forward.
In order to avoid the use of higher voltage transistors, the
two transistor version of the forward can be used. This
circuit, shown in Fig. 9, is very similar to the two transistor
flyback and has the same advantages. The voltage across
the transistor is again clamped to V
in
, allowing the use of
faster more efficient 400 or 500V devices for 220V mains
applications. The magnetisation reset is achieved through
the two clamp diodes, permitting the removal of the clamp
winding.
Fig. 9 Two transistor Forward.
The two transistor version is popular for off-line
applications. It provides higher output powers and faster
switching frequencies. The disadvantages are again the
extra cost of the higher component count, and the need for
an isolated drive for the top transistor.
Although this converter has some drawbacks, and utilises
the transformer poorly, it is a very popular selection for the
power range mentioned above, and offers simple drive for
the single switch and cheap component costs. Multiple
output types are very common. The output inductors are
normally wound on a single core, which has the effect of
improving dynamic cross regulation, and if designed
correctly also reduces the output ripple magnitudes even
further. The major advantage of the forward converter is
the very lowoutput ripple that can be achieved for relatively
small sized LC components. This means that forward
converters are normally used to generate lower voltage,
high current multiple outputs such as 5, 12, 15, 28V from
mains off-line applications, where lower ripple
specifications are normally specified for the outputs. The
high peak currents that would occur if a flyback was used
would place an impossible burden on the smoothing
capacitor.
Vo
Vin
T1
Co
n : 1
TR1
D1
TR2
isolated
base
drive
D2
L1
117
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Output power 100W 200W 300W
Line voltage, Vin 110V ac 220V ac 110V ac 220V ac 110V ac 220V ac
Transistor requirements
Max current 2.25A 1.2A 4A 2.5A 6A 3.3A
Max voltage 400V 800V 400V 800V 400V 800V
Bipolar transistors.
TO-220 BUT11 BUX85 BUT12 BUT11A --- BUT12A
Isolated SOT-186 BUT11F BUX85F BUT12F BUT11AF --- BUT12AF
SOT-93 --- --- --- --- BUW13 ---
Isolated SOT-199 --- --- --- --- BUW13F ---
Power MOSFET
TO-220 BUK454-400B BUK454-800A BUK455-400B BUK456-800A --- ---
Isolated SOT-186 BUK444-400B BUK444-800A BUK445-400B BUK446-800A --- ---
SOT-93 --- --- --- --- BUK437-400B BUK438-800A
Output Rectifiers (dual)
O/P voltage
5V PBYR2535CT --- ---
10V PBYR20100CT PBYR30100PT PBYR30100PT
BYV32E-100/150/200 BYV42E-100/150/200 BYV72E-100/150/200
BYV72E100/150/200
20V PBYR20100CT PBYR20100CT PBYR20100CT
BYQ28E-100/150/200 BYV32E-100/150/200 BYV32E-100/150/200
50V BYT28-300 BYT28-300 BYT28-300
Table 3. Recommended Power Semiconductors for single-ended forward.
Forward
Converter efficiency, η = 80%; Max duty cycle, D
max
= 0.45
Max transistor voltage, V
ce
or V
ds
= 2V
in(max)
dc voltage gain:-
Applications:- Low cost, low output ripple, multiple output supplies in the 50 to 400W range. E.g. small computer
supplies, DC/DC converters.
Maxtransistorcurrent , I
C
; I
D
·
P
out
η D
max
V
min
Vo
Vin
· n D
118
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
(c) The Push-pull converter.
Operation.
To utilise the transformer flux swing fully, it is necessary to
operate the core symmetrically as described earlier. This
permits much smaller transformer sizes and provides
higher output powers than possible with the single ended
types. The symmetrical types always require an even
number of transistor switches. One of the best known of the
symmetrical types is the push-pull converter shown in
Fig. 10.
The primary is a centre-tapped arrangement and each
transistor switch is driven alternately, driving the
transformer in both directions. The push-pull transformer is
typically half the size of that for the single ended types,
resulting in a more compact design. This push-pull action
produces natural core resetting during each half cycle,
hence no clamp winding is required. Power is transferred
to the buck type output circuit during each transistor
conduction period. The duty ratio of each switch is usually
less than 0.45. This provides enough dead time to avoid
transistor cross conduction. The power can now be
transferred to the output for up to 90% of the switching
period, hence allowing greater throughput power than with
the single-ended types. The push-pull configuration is
normally used for output powers in the 100 to 500Wrange.
Fig. 10 Push-pull converter.
The bipolar switching action also means that the output
circuit is actually operated at twice the switching frequency
of thepower transistors, ascanbeseenfromthewaveforms
in Fig. 11. Therefore, the output inductor and capacitor can
be even smaller for similar output ripple levels. Push-pull
converters are thus excellent for high power density, low
ripple outputs.
Advantages.
As stated, the push-pull offers very compact design of the
transformer and output filter, while producing very low
output ripple. So if space is a premiumissue, the push-pull
could be suitable. The control of the push-pull is similar to
theforward, inthat it isagainbasedon the continuousmode
buck. When closing the feedback control loop,
compensation is relatively easy. For multiple outputs, the
same recommendations given for the forward converter
apply.
Clamp diodes are fitted across the transistors, as shown.
This allows leakage and magnetisation energy to be simply
channelled back to the supply, reducing stress on the
switches and slightly improving efficiency.
The emitter or source of the power transistors are both at
the same potential in the push-pull configuration, and are
normally referenced to ground. This means that simple
base drive can be used for both, and no costly isolating
drive transformer is required. (This is not so for the bridge
types which are discussed latter.)
Disadvantages.
One of the main drawbacks of the push-pull converter is
the fact that each transistor must block twice the input
voltage due to the doubling effect of the centre-tapped
primary, even though two transistors are used. This occurs
whenonetransistor isoff andthe other isconducting. When
both are off, each then blocks the supply voltage, this is
shown in the waveforms in Fig. 11. This means that TWO
expensive, less efficient 800 to 1000Vtransistors would be
required for a 220V off-line application. A selection of
transistors and rectifiers suitable for the push-pull used in
off-line applications is given in Table 4.
A further major problem with the push-pull is that it is prone
to flux symmetry imbalance. If the flux swing in each half
cycle is not exactly symmetrical, the volt-sec will not
balance and this will result in transformer saturation,
particularly for high input voltages. Symmetry imbalance
can be caused by different characteristics in the two
transistors such as storage time in a bipolar and different
on-state losses.
The centre-tap arrangement also means that extra copper
is needed for the primary, and very good coupling between
the two halves is necessary to minimise possible leakage
spikes. It should also be noted that if snubbers are used to
protect the transistors, the design must be very precise
since each tends to interact with the other. This is true for
all symmetrically driven converters.
These disadvantages usually dictate that the push-pull is
normally operated at lower voltage inputs such as 12, 28
or 48V. DC-DC converters found in the automotive and
telecommunication industries are often push-pull designs.
At these voltage levels, transformer saturation is easier to
avoid.
Since the push-pull is commonly operated with low dc
voltages, a selection guide for suitable power MOSFETs is
also included for 48 and 96V applications, seen in Table 5.
Vo T1 D1
Co
n : 1
TR1
D2
L1
TR2
Vin
119
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Current mode control.
The introduction of current mode control circuits has also
benefited the push-pull type. In this type of control, the
primary current is monitored, and any imbalance which
occurs is corrected on a cycle by cycle basis by varying the
duty cycle immediately. Current mode control completely
removes the symmetry imbalance problem, and the
possibilities of saturation are minimised. This has meant
that push-pull designs have becomemore popular in recent
years, with some designers even using them in off-line
applications.
Fig. 11 Push Pull waveforms.
Transistor
I
TR1
I
TR2
TR1
voltage
TR2
voltage
D1
current
D2
current
output
inductor
current
I
L
0
0
0
0
0
0
t
t
t
t
t
t
ton
ton
1 2
T
Vin
2Vin
2Vin
Vin
currents
120
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Output power 100W 300W 500W
Line voltage, Vin 110V ac 220V ac 110V ac 220V ac 110V ac 220V ac
Transistor requirements
Max current 1.2A 0.6A 4.8A 3.0A 5.8A 3.1A
Max voltage 400V 800V 400V 800V 400V 800V
Bipolar transistors.
TO-220 BUT11 BUX85 BUT12 BUT11A --- BUT12A
Isolated SOT-186 BUT11F BUX85F BUT12F BUT11AF --- BUT12AF
SOT-93 --- --- --- --- BUW13 ---
Isolated SOT-199 --- --- --- --- BUW13F ---
Power MOSFET
TO-220 BUK454-400B BUK454-800A BUK455-400B BUK456-800A --- ---
Isolated SOT-186 BUK444-400B BUK444-800A BUK445-400B BUK446-800A --- ---
SOT-93 --- --- --- --- BUK437-400B BUK438-800A
Output Rectifiers (dual)
O/P voltage
5V PBYR2535CT --- ---
10V PBYR20100CT PBYR30100PT ---
BYV32E-100/150/200 BYV72E-100/150/200 BYT230PI-200
20V PBYR20100CT PBYR20100CT PBYR30100PT
BYQ28E-100/150/200 BYV32E-100/150/200 BYV42E-100/150/200
BYV72E-100/150/200
50V BYT28-300 BYT28-300 BYV34-300
Table 4. Recommended Power Semiconductors for off-line Push-pull converter.
Output power 100W 200W 300W
Line voltage, Vin 96V dc 48V dc 96V dc 48V dc 96V dc 48V dc
Power MOSFET
TO-220 BUK455-400B BUK454-200A BUK457-400B BUK456-200B --- ---
Isolated SOT-186 BUK445-400B BUK444-200A BUK437-400B BUK436-200B --- ---
SOT-93 --- --- --- --- BUK437-400B ---
Table 5. Recommended power MOSFETs for lower input voltage push-pull.
Push-Pull converter.
Converter efficiency, η = 80%; Max duty cycle, D
max
= 0.9
Max transistor voltage, V
ce
or V
ds
= 2V
in(max)
+ leakage spike.
dc voltage gain:-
Applications:- Compact design, very low output ripple supplies in the 100 to 500W range. More suited to low input
applications. E.g. battery, 28, 40V inputs, high current outputs. Telecommunication supplies.
Maxtransistorcurrent , I
C
; I
D
·
P
out
η D
max
V
min
Vo
Vin
· 2 n D
121
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
(d) The Half-Bridge.
Of all the symmetrical high power converters, the
half-bridge converter shown in Fig. 12 is the most popular.
It is also referred to as the single ended push-pull, and in
principle is a balanced version of the forward converter.
Again it is a derivative of the buck. The Half-Bridge has
some key advantages over the push-pull, which usually
makes it first choice for higher power applications in the
500 to 1000W range.
Operation.
The two mains bulk capacitors C1 and C2 are connected
in series, and an artificial input voltage mid-point is
provided, shown as point A in the diagram. The two
transistor switches are driven alternately, andthis connects
each capacitor across the single primary winding each half
cycle. V
in
/2 is superimposed symmetrically across the
primary in a push-pull manner. Power is transferred directly
to the output on each transistor conduction time and a
maximum duty cycle of 90% is available (Some dead time
is required to prevent transistor cross-conduction.) Since
the primary is driven in both directions, (natural reset) a full
wave buck output filter (operating at twice the switching
frequency) rather than a half wave filter is implemented.
This again results in very efficient core utilisation. As can
be seen in Fig. 13, the waveforms are identical to the
push-pull, except that the voltage across the transistors is
halved. (The device current would be higher for the same
output power.)
Fig. 12 Half-Bridge converter.
Advantages.
Since both transistors are effectively in series, they never
see greater than the supply voltage, V
in
. When both are off,
their voltages reach an equilibriumpoint of V
in
/2. This is half
the voltage rating of the push-pull (although double the
current). This means that the half-bridge is particularly
suited to high voltage inputs, such as off-line applications.
For example, a 220V mains application can use two higher
speed, higher efficiency 450V transistors instead of the
800V types needed for a push-pull. This allows higher
frequency operation.
Another major advantage over the push-pull is that the
transformer saturation problems due to flux symmetry
imbalance are not a problem. By using a small capacitor
(less than 10µF) any dc build-up of flux in the transformer
is blocked, and only symmetrical ac is drawn fromthe input.
The configuration of the half-bridge allows clamp diodes to
be added across the transistors, shown as D3 and D4 in
Fig. 12. The leakage inductance and magnetisation
energies are dumped straight back into the two input
capacitors, protecting the transistors from dangerous
transients and improving overall efficiency.
A less obvious exclusive advantage of the half-bridge is
that the two series reservoir capacitors already exist, and
this makes it ideal for implementing a voltage doubling
circuit. This permits the use of either 110V /220V mains as
selectable inputs to the supply.
The bridge circuits also have the same advantages over
the single-ended types that the push-pull possesses,
including excellent transformer utilisation, very low output
ripple, andhighoutput power capabilities. Thelimitingfactor
inthe maximumoutput power availablefromthe half-bridge
is the peak current handling capabilities of present day
transistors. 1000W is typically the upper power limit. For
higher output powers the four switch full bridge is normally
used.
Disadvantages.
The need for two 50/60 Hz input capacitors is a drawback
because of their large size. The top transistor must also
have isolated drive, since the gate / base is at a floating
potential. Furthermore, if snubbers are used across the
power transistors, great care must be taken in their design,
since the symmetrical action means that they will interact
with one another. The circuit cost and complexity have
clearly increased, and this must be weighed up against the
advantages gained. In many cases, this normally excludes
the use of the half-bridge at output power levels below
500W.
Suitable transistors and rectifiers for the half-bridge are
given in Table 6.
Vo
T1
D1
Co
n : 1
TR1
D2
L1
TR2
Vin
isolated
drive
needed
D3
D4
C1
C2
C3
A
122
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Fig. 13 Half-Bridge waveforms.
Transistor
I
TR1
I
TR2
TR1
voltage
TR2
voltage
D1
current
D2
current
output
inductor
current
I
L
0
0
0
0
0
0
t
t
t
t
t
t
ton
ton
1 2
T
currents
Vin
2
Vin
2
Vin
Vin
123
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Output power 300W 500W 750W
Line voltage, Vin 110V ac 220V ac 110V ac 220V ac 110V ac 220V ac
Transistor requirements
Max current 4.9A 2.66A 11.7A 6.25A 17.5A 9.4A
Max voltage 250V 450V 250V 450V 250V 450V
Bipolar transistors.
TO-220 BUT12 BUT11 --- --- --- ---
Isolated SOT-186 BUT12F BUT11F --- --- --- ---
SOT-93 --- --- BUW13 BUW13 --- BUW13
Isolated SOT-199 --- --- BUW13F BUW13F --- BUW13F
Power MOSFET
SOT-93 --- BUK437-500B --- --- --- ---
Output Rectifiers (dual)
O/P voltage
5V --- --- ---
10V PBYR30100PT --- ---
BYV72E-100/150/200
20V PBYR20100CT PBYR30100PT ---
BYV32E-100/150/200 BYV42E-100/150/200
BYV72E-100/150/200
50V BYT28-300 BYV34-300 BYV34-300
Table 6. Recommended Power Semiconductors for off-line Half-Bridge converter.
Half-Bridge converter.
Converter efficiency, η = 80%; Max duty cycle, D
max
= 0.9
Max transistor voltage, V
ce
or V
ds
= V
in(max)
+ leakage spike.
dc voltage gain:-
Applications:- High power, up to 1000W. High current, very low output ripple outputs. Well suited for high input
voltage applications. E.g. 110, 220, 440V mains. E.g. Large computer supplies, Lab equipment supplies.
Maxtransistorcurrent , I
C
; I
D
· 2
P
out
η D
max
V
min
Vo
Vin
· n D
124
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
(e) The Full-Bridge.
Outline.
The Full-Bridge converter shown in Fig. 14 is a higher
power version of the Half-Bridge, and provides the highest
output power level of any of the converters discussed. The
maximum current ratings of the power transistors will
eventually determine the upper limit of the output power of
the half-bridge. These levels can be doubled by using the
Full-Bridge, which is obtained by adding another two
transistors and clamp diodes to the Half-Bridge
arrangement. The transistors are drivenalternately in pairs,
T1 and T3, then T2 and T4. The transformer primary is now
subjectedtothe full input voltage. The current levels flowing
are halved compared to the half-bridge for a given power
level. Hence, the Full-Bridge will double the output power
of the Half-Bridge using the same transistor types.
The secondary circuit operates in exactly the samemanner
as the push-pull and half-bridge, also producing very low
ripple outputs at very high current levels. Therefore, the
waveforms for the Full-Bridge are identical to the
Half-Bridge waveforms shown in Fig. 13, except for the
voltage across the primary, which is effectively doubled
(and switch currents halved). This is expressed in the dc
gain and peak current equations, where the factor of two
comes in, compared with the Half-Bridge.
Advantages.
As stated, the Full-Bridge is ideal for the generation of very
high output power levels. The increased circuit complexity
normally means that the Full-Bridge is reserved for
applications with power output levels of 1kW and above.
For such high power requirements, designers often select
power Darlingtons, since their superior current ratings and
switching characteristics provide additional performance
and in many cases a more cost effective design.
The Full-Bridge also has the advantage of only requiring
one mains smoothing capacitor compared to two for the
Half-Bridge, hence, saving space. Its other major
advantages are the same as for the Half-Bridge.
Disadvantages.
Four transistors and clamp diodes are needed instead of
two for the other symmetrical types. Isolated drive for two
floating potential transistors is now required. The
Full-Bridge has the most complex and costly design of any
of theconverters discussed, andshould onlybeused where
other types do not meet the requirements. Again, the four
transistor snubbers (if required) must be implemented
carefully to prevent interactions occurring between them.
Table 7 gives an outline of the Philips power
semiconductors suitable for use with the Full-Bridge.
Fig. 14 The Full-Bridge converter.
Vo
T1
D1
Co
TR1
D2
L1
TR2
Vin
D3
D4
C1
*
*
* Isolated drive required.
C2
TR3
TR4
D5
D6
125
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Output power 500W 1000W 2000W
Line voltage, Vin 110V ac 220V ac 110V ac 220V ac 110V ac 220V ac
Transistor requirements
Max current 5.7A 3.1A 11.5A 6.25A 23.0A 12.5A
Max voltage 250V 450V 250V 450V 250V 450V
Bipolar transistors.
TO-220 BUT12 BUT18 --- --- --- ---
Isolated SOT-186 BUT12F BUT18F --- --- --- ---
SOT-93 --- --- BUW13 BUW13 --- BUW13
Isolated SOT-199 --- --- BUW13F BUW13F --- BUW13F
Power MOSFET
SOT-93 --- BUK438-500B --- --- --- ---
Output Rectifiers (dual)
O/P voltage
5V --- --- ---
10V --- --- ---
20V PBYR30100PT --- ---
BYV42E-100/150/200
BYV72E-100/150/200
50V BYV34-300 BYV44-300 ---
Table 7. Recommended Power Semiconductors for the Full-Bridge converter.
Full-Bridge converter.
Converter efficiency, η = 80%; Max duty cycle, D
max
= 0.9
Max transistor voltage, V
ce
or V
ds
= V
in(max)
+ leakage spike.
dc voltage gain:-
Applications:- Very high power, normally above 1000W. Very high current, very low ripple outputs. Well suited for
high input voltage applications. E.g. 110, 220, 440V mains. E.g. Computer Mainframe supplies, Large lab equipment
supplies, Telecomm systems.
Maxtransistorcurrent , I
C
; I
D
·
P
out
η D
max
V
min
Vo
Vin
· 2 n D
126
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Conclusion.
The 5 most common S.M.P.S. converter topologies, the
flyback, forward, push-pull, half-bridgeandfull-bridge types
have been outlined. Each has its own particular operating
characteristics and advantages, which makes it suited to
particular applications.
The converter topology alsodefines thevoltage andcurrent
requirements of the power transistors (either MOSFET or
Bipolar). Simple equations and calculations used to outline
the requirements of the transistors for each topology have
been presented.
The selection guide for transistors and rectifiers at the end
of each topology section shows some of the Philips devices
which are ideal for use in S.M.P.S. applications.
References.
(1) Philips MOSFET Selection Guide For S.M.P.S. by
M.J.Humphreys. Philips Power Semiconductor
Applications group, Hazel Grove.
(2) Switch Mode Power Conversion - Basic theory and
design by K.Kit.Sum. (Published by Marcel Dekker
inc.1984)
127
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Appendix A.
MOSFET throughput power calculations.
Assumptions made:-
The power loss (Watts) in the transistor due to on-state
losses is 5% of the total throughput (output) power.
Switching losses in the transistor are negligible. N.B. At
frequencies significantly higher than 50kHz the switching
losses may become important.
The device junction temperature, T
j
is taken to be 125˚C.
The ratio R
ds(125C˚)
/R
ds(25˚C)
is dependent on the voltage of the
MOSFET device. Table A1 gives the ratio for the relevant
voltage limiting values.
The value of V
s(min)
for each input value is given in Table
A2.
Device voltage limiting R
ds(125C)
value. --------
R
ds(25C)
100 1.74
200 1.91
400 1.98
500 2.01
800 2.11
1000 2.15
Table A1. On resistance ratio.
Main input Maximum dc link Minimum dc
voltage voltage link
voltage
220 / 240V ac 385V 200V
110 / 120V ac 190V 110V
Table A2. Max and Min dc link voltages for mains inputs.
Using the following equations, for a given device with a
known R
ds(125˚C)
, the maximum throughput power in each
topology can be calculated.
Where:-
P
th(max)
= Maximum throughput power.
D
max
= maximum duty cycle.
τ = required transistor efficiency (0.05 t 0.005)
Rds
(125˚C)
= R
ds(25˚C)
x ratio.
V
s(min)
= minimum dc link voltage.
Forward converter.
D
max
= 0.45
Flyback Converter.
D
max
= 0.45
Push Pull Converter.
D
max
= 0.9
Half Bridge Converter.
D
max
= 0.9
Full Bridge Converter.
D
max
= 0.9
P
th(max)
·
τ × V
s(min)
2
× D
max
R
ds(125c)
P
th(max)
·
3 × τ × V
s(min)
2
× D
max
4 × R
ds(125c)
P
th(max)
·
τ × V
s(min)
2
× D
max
R
ds(125c)
P
th(max)
·
τ × V
s(min)
2
× D
max
4 × R
ds(125c)
P
th(max)
·
τ × V
s(min)
2
× D
max
2 × R
ds(125c)
128
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
2.1.2 The Power Supply Designer’s Guide to High Voltage
Transistors
One of the most critical components in power switching
converters is the high voltage transistor. Despite its wide
usage, feedback from power supply designers suggests
that there are several features of high voltage transistors
which are generally not well understood.
This section begins with a straightforward explanation of
the key properties of high voltage transistors. This is done
by showing howthe basic technology of the transistor leads
to its voltage, current, power and second breakdown limits.
It is also made clear how deviations from conditions
specified in the data book will affect the performance of the
transistor. The final section of the paper gives practical
advicefor designers on howcircuits might be optimisedand
transistor failures avoided.
Introduction
A large amount of useful information about the
characteristics of a given component is provided in the
relevant data book. By using this information, a designer
can usually be sure of choosing the optimum component
for a particular application.
However, if aproblemarises with the completed circuit, and
a more detailed analysis of the most critical components
becomes necessary, the data book can become a source
of frustration rather than practical assistance. In the data
book, a component is often measured under a very specific
set of conditions. Verylittleissaidabout howthe component
performance is affected if these conditions are not
reproducedexactly whenthecomponent isused inacircuit.
There are as many different sets of requirements for high
voltage transistors as there are circuits which make use of
them. Covering every possible drive and load condition in
the device specification is an impossible task. There is
therefore a real need for any designer using high voltage
transistorstohave anunderstandingof howdeviationsfrom
theconditionsspecifiedinthe transistor databookwill affect
the electrical performance of the device, in particular its
limiting values.
Feedbackfromdesigners implies that this informationis not
readily available. The intention of this report is therefore to
provide designers with the information they need in order
tooptimise the reliability of their circuits. The characteristics
of high voltage transistors stemfromtheir basic technology
and so it is important to begin with an overview of this.
HVT technology
Stripping away the encapsulation of the transistor reveals
how the electrical connections are made (see Fig. 1). The
collector is contacted through the back surface of the
transistor chip, which issolderedtothenickel-plated copper
lead frame. For Philips power transistors the lead frame
andthe centreleg are formed fromasingle pieceof copper,
and so the collector can be accessed through either the
centre leg or any exposed part of the lead frame (eg the
mounting base for TO-220 and SOT-93).
Fig. 1 High voltage transistor without the plastic case.
The emitter area of the transistor is contacted from the top
surface of the chip. A thin layer of aluminium joins all of the
emitter areatoalargebondpad. This bondpadisaluminium
wire bonded to the emitter leg of the transistor when the
transistor is assembled. The same method is used to
contact the base area of the chip. Fig. 2 shows the top view
of a high voltage transistor chip in more detail.
Viewing the top surface of the transistor chip, the base and
emitter fingers are clearly visible. Around the periphery of
the chip is the high voltage glass passivation. The purpose
of this is explained later.
Taking a cross section through the transistor chip reveals
its npn structure. A cross section which cuts one of the
emitter fingersandtwoof the basefingersisshowninFig. 3.
nickel-plated
copper lead
frame
passivated
chip
aluminium
wires
tinned copper
leads
ultrasonic
wire bonds
Base Collector Emitter
129
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Fig. 2 High voltage transistor chip.
Onthe topsurface of the transistor are the aluminiumtracks
whichcontact thebase andemitter areas. Theemitter finger
isshown connectedtoann+ region. This is theemitter area.
The n+ denotes that this is very highly doped n type silicon.
Surrounding the n+ emitter is the base, and as shown in
Fig. 3 this is contacted by the base fingers, one on either
side of the emitter. The p denotes that this is highly doped
p type silicon.
On the other side of the base is the thick collector n- region.
The n- denotes that this is lightly doped n type silicon. The
collector region supports the transistor blocking voltage,
and its thickness and resistivity must increase with the
voltage rating of the device.
Fig. 3 Cross section of HVT.
Following the collector region is the n+ back diffusion. The
n+ back diffusion ensures a good electrical contact is made
between the collector region and the lead frame/collector
leg, whilst also allowing the crystal to be thick enough to
prevent it from cracking during processing and assembly.
The bottomsurface of the chip is solderedtothe lead frame.
Voltage limiting values
Part 1: Base shorted to emitter.
When the transistor is in its off state with a high voltage
applied to the collector, the base collector junction is
reverse biased by a very high voltage. The voltage
supportingdepletion region extends deep into the collector,
right up to the back diffusion, as shown in Fig. 4.
Fig. 4 Depletion region extends deep into the collector
during the off state.
With the base of the transistor short circuited to the emitter,
or at a lower potential than the emitter, the voltage rating
is governed by the voltage supporting capability of the
reverse biased base collector junction. This is the transistor
V
CESMmax
. The breakdownvoltageof thereversebiasedbase
collector junctionisdeterminedmainlybythe collector width
and resistivity as follows:
Figure 5 shows the doping profile of the transistor. Note the
very high doping of the emitter and the back diffusion, the
high doping of the base and the lowdoping of the collector.
Also shown in Fig. 5 is the electric field concentration
throughout the depletion region for the case where the
transistor is supporting its off state voltage. The electric
field, E, is given by the equation, E = -dV/dx, where -dV is
the voltage drop in a distance dx. Rewriting this equation
gives the voltage supported by the depletion region:
emitter fingers base fingers
emitter
bond pad
base
bond pad
high
voltage
passivation
n+
p
n-
n+
base finger emitter finger base finger
emitter
base
collector
back diffusion
Depletion Region
n+
p
n-
n+
base finger emitter finger base finger
emitter
base
collector
back diffusion
solder
lead frame
V · −


Edx
130
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Fig. 5 Doping profile and E field distribution.
This is the area under the dotted line in Fig.5.
During the off state, the peak electric field occurs at the
basecollector junction asshown in Fig. 5. If the electric field
anywhere in the transistor exceeds 200 kVolts per cm then
avalanche breakdown occurs and the current which flows
in the transistor is limited only by the surrounding circuitry.
If the avalanche current is not limited to a very low value
then the power rating of the transistor can easily be
exceededandthetransistor destroyedas aresult of thermal
breakdown. Thus the maximum allowable value of electric
field is 200 kV/cm.
The gradient of the electric field, dE/dx, is proportional to
charge density which is in turn proportional to the level of
doping. In the base, the gradient of the electric field is high
because of the high level of doping, and positive because
the base is p type silicon. In the collector, the gradient of
the electric field is low because of the low level of doping,
and negative because the collector is n type silicon. In the
back diffused region, the gradient of the electric field is very
highly negative because this is very highly doped n type
silicon.
Increasing the voltage capability of the transistor can
therefore be done by either increasing the resistivity
(lowering the level of doping) of the collector region in order
to maintain a high electric field for the entire collector width,
or increasing the collector width itself. Both of these
measures can be seen to work in principle because they
increase the area under the dotted line in Fig. 5.
The breakdown voltage of the transistor, V
CESMmax
, is limited
by the need to keep the peak electric field, E, below 200
kV/cm. Without special measures, the electric field would
crowd at the edges of the transistor chip because of the
surface irregularities. This would limit breakdown voltages
to considerably less than the full capability of the silicon.
Crowding of the equipotential lines at the chip edges is
avoided by the use of a glass passivation (see Fig. 6). The
glass passivation therefore allows the full voltage capability
of the transistor to be realised.
Fig. 6 High voltage passivation.
The glass used isnegatively charged to inducea p- channel
underneath it. This ensures that the applied voltage is
supported evenly over the width of the glass and does not
crowd at any one point. High voltage breakdown therefore
occurs in the bulk of the transistor, at the base collector
junction, and not at the edges of the crystal.
Exceeding the voltage rating of the transistor, even for a
fraction of a second, must be avoided. High voltage
breakdowneffects can be concentratedin avery small area
of the transistor, and only a small amount of energy may
damage the device. However, there is no danger in using
the full voltage capability of the transistor as the limit under
worst case conditionsbecause the high voltagepassivation
is extremely stable.
Part 2: Open circuit base.
With the base of the transistor open circuit the voltage
capability is much lower. This is the V
CEOmax
of the device
and it is typically just less than half of the V
CESMmax
rating.
The reason for the lower voltage capability under open
circuit base conditions is as follows:
As the collector emitter voltage of the transistor rises, the
peakelectric fieldlocatedat thebase collector junctionrises
too. Above a peak E field value of 100 kV/cm there is an
appreciable leakage current being generated.
In the previous case, with the base contact short circuited
to the emitter, or held at a lower potential than the emitter,
any holes which are generated drift from the edge of the
depletion region towards the base contact where they are
extracted. However, with the base contact open circuit, the
holes generated diffuse from the edge of the depletion
region towards the emitter where they effectively act as
base current. This causes the emitter to inject electrons into
the base, which diffuse towards the collector. Thus there is
a flow of electrons from the emitter to the collector.
Doping
Distance
n+ p
n-
n+
E B C
E field
base emitter
250V
600V
850V
1150V
n-
n+
n+
p
n+
n-
special glass
131
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
The high electric field in the collector accelerates the
electrons to the level where some have sufficient energy to
produce more hole electron pairs through their collisions
with the lattice. The current generated in this way adds to
the leakagecurrent. Thus with the base contact open circuit
the emitter becomes active and provides the system with
gain, multiplying the leakage current and consequently
reducing the breakdown voltage.
For a given transistor the gain of the system is dependant
on two things. Firstly it is dependant on the probability that
a hole leaving the depletion region will reach the emitter. If
the base is open circuit and no recombination occurs then
this probability is 1. If the base is not open circuit, and
instead a potential below V
BEon
is applied, then there is a
chance that a hole leaving the depletion region will be
extracted at the base contact. As the voltage on the base
contact is made less positive the probability of holes
reaching the emitter is reduced.
Secondly, the gain is dependant on the probability of
electrons leaving the emitter, diffusing across the base and
being accelerated by the high field in the collector to the
level where they are able to produce a hole electron pair in
one of their collisions with the lattice. This depends on the
electric field strength which is in turn dependant on the
collector voltage.
Thusfor agivenvoltageat the basethereisacorresponding
maximum collector voltage before breakdown will occur.
With the base contact shorted to the emitter, or at a lower
potential than the emitter, the full breakdown voltage of the
transistor isachieved(V
CESMmax
). Withthebasecontact open
circuit, or at a higher potential than the emitter, the
breakdown voltage is lower (V
CEOmax
) because in this case
the emitter is active and it provides the breakdown
mechanism with gain.
With the base connected to the emitter by a non zero
impedance, the breakdown voltage will be somewhere
between the V
CESMmax
and the V
CEOmax
. A low impedance
approximates to the shorted base, ’zero gain’, case and a
highimpedanceapproximates tothe openbase, ’high gain’,
case. With a base emitter impedance of 47 Ω and no
externally applied base voltage, the breakdown voltage is
typically 10% higher than the V
CEOmax
.
Current limiting values
The maximum allowed DC current is limited by the size of
the bond wires to the base and emitter. Exceeding the DC
limiting values I
Cmax
and I
Bmax
, for any significant length of
time, may blow these bond wires. If the current pulses are
short and of a low duty cycle then values greatly in excess
of the DC values are allowed. The I
CMmax
and I
BMmax
ratings
are recommendations for peak current values. For a duty
cycle of 0.01 and a pulse width of 10ms these values will
typically be double the DC values.
If the pulses are shorter than 10ms then even the
recommended peak values can be exceeded under worst
case conditions. However, it should be noted that
combinations of high collector current and high collector
voltagecanleadtofailurebysecondbreakdown(discussed
later). As the collector current is increased, the collector
voltage required to trigger second breakdown drops, and
so allowing large collector current spikes increases the risk
of failure by second breakdown. It is therefore advised that
the peak values given in the data book are used as design
limits in order to maximise the component reliability.
In emitter drive circuits, the peak reverse base current is
equal to the peak collector current. The pulse widths and
duty cycles involved are small, and this mode of operation
is within the capability of all Philips high voltage transistors.
Power limiting value
The P
totmax
given in device data is not generally an
achievable parameter because in practice it is obtainable
only if the mounting base temperature can be held to 25 ˚C.
In practice, the maximum power dissipation capability of a
given device is limited by the heatsink size and the ambient
temperature. The maximumpower dissipationcapability for
a particular circuit can be calculated as follows;
T
jmax
is the maximumjunction temperature given in the data
sheet. The value normally quoted is 150 ˚C. T
amb
is the
ambient temperature around the device heatsink. A typical
value in practice could be 65 ˚C. R
thj-mb
is the device thermal
resistance given in the data sheet, but to obtain a value of
junction to ambient thermal resistance, R
thj-a
, the thermal
resistance of the mica spacer (if used), heatsink and
heatsink compound should be added to this.
Themaximumpower whichcanbedissipated under agiven
set of circuit conditions is calculated using;
P
max
= (T
jmax
-T
amb
)/R
thj-a
For a BUT11AF, in an ambient temperature of 65 ˚C,
mounted on a 10 K/W heatsink with heatsink compound,
this gives;
R
thj-a
= 3.95 K/W + 10 K/W = 13.95 K/W
andhencethe maximumpower capableof beingdissipated
under these conditions is;
P
max
= (150-65)/13.95 = 6 W
Exceeding the maximum junction temperature, T
jmax
, is not
recommended. All of the quality and reliability work carried
out on the device is based on the maximum junction
temperaturequoted in data. If T
jmax
is exceeded inthe circuit
then the reliability of the device is no longer guaranteed.
132
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Secondary breakdown
Pure silicon, also known as ’intrinsic’ silicon, contains few
mobile charge carriers at room temperature and so its
conductivity is low. By doping the silicon (ie introducing
atoms of elements other than silicon) the number of mobile
charge carriers, and hence the conductivity, can be
increased. Silicon doped in such a way as to increase the
number of mobile electrons (negative charge) is called n
type silicon. Silicon doped in such a way as to increase the
number of mobile holes (positive charge) is called p type
silicon. Thus the base region of an npn transistor contains
an excess of mobile holes and the collector and emitter
regions contain an excess of mobile electrons.
When a high voltage is applied to the transistor, and the
collector base junction is reverse biased, adepletion region
is developed. This was shown in Fig. 4. The depletion
region supports the applied voltage. The electric field
distribution within the depletion region was shown in Fig. 5.
The term depletion region refers to a region depleted of
mobile charge carriers. Therefore, within the depletion
region, the base will have lost some holes and hence it is
left with a net negative charge. Similarly the collector will
have lost some electrons and hence it is left with a net
positive charge. The collector is said to have a ’positive
space charge’ (and the base a ’negative space charge’.)
Consider the case where a transistor is in its off state
supporting a high voltage which is within its voltage
capability. The resulting electric field distribution is shown
in Fig. 7.
Fig. 7 V
CE
high, I
C
= 0.
If the collector voltage is held constant, and the collector
current increased so that there is now some collector
current flowing, this current will modify the charge
distribution within the depletion region. The effect this has
on the base is negligible because the base is very highly
doped. The effect this has on the collector is significant
because the collector is only lightly doped.
The collector current is due to the flowof electrons fromthe
emitter to the collector. As the collector current increases,
the collector current density increases. This increase in
collector current density is reflected in Fig. 8 by an increase
in the electron concentration in the collector.
At a certain collector current density, the negative charge
of the electrons neutralises the positive space charge of the
collector. The gradient of the electric field, dE/dx, is
proportional to charge density. If the space charge is
neutralised then the gradient of the electric field becomes
zero. This is the situation illustrated in Fig. 8. Note that the
shaded arearemains constant becausethe appliedvoltage
remains constant. Therefore the peak value of electric field
drops slightly.
Fig. 8 V
CE
high, I
C
>0.
Keepingthecollector-emitter voltageconstant, andpushing
up the collector current density another step, increases the
concentration of electrons in the collector still further. Thus
the collector charge density is now negative, the gradient
of electric field in the collector is nowpositive, and the peak
electric field has shifted from the collector-base junction to
the collector-back diffusion interface. This is shown in
Fig. 9.
Increasing the collector current density another step will
further increase the positive gradient of electric field. The
collector voltageisunchangedandsotheshadedareamust
remain unchanged. Therefore the peak electric field is
forced upwards. This is shown in Fig. 10.
Efield
Electron Concentration
Collector Base
Efield
Collector Base
133
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Fig. 9 V
CE
high, I
C
increased further.
Fig. 10 V
CE
high, I
C
increased further.
At a certain critical value of peak electric field, E
crit
, a
regenerative breakdown mechanism takes place which
causes the electron concentration in the collector to
increase uncontrollably by a process known as avalanche
multiplication. As the electron concentration increases, the
gradient of electric field increases (because the gradient of
electric field is proportional to charge density). The peak
electric field is clamped by the breakdown and so the
collector voltage drops. In most circuits the collapsing
collector voltage will result in a further rise in collector
current density, causing a further rise in electron
concentration (ie positive feedback). This is shown in
Fig. 11.
At approximately 30 V, the holes produced by the
avalanche multiplication build up sufficiently to temporarily
stabilize the system. However, with 30 V across the device
and a high collector current flowing through it, a
considerable amount of heat will be generated. Within less
than one microsecond thermal breakdown will take place,
followed by device destruction.
Fig.11 V
CE
falling, I
C
increasing
Safe Operating Area
It has been shown that the electric field profile, and hence
the peak electric field, is dependent on the combination of
collector current density and applied collector voltage. The
peak electric field increases with increasing collector
voltage (increase in shaded area in Figs. 7 to 11). It also
increases with increasing collector current density
(increase in gradient of electric field). At all times the peak
electric field must remain below the critical value. If the
collector voltage is lowered then a higher collector current
density is permitted. If the collector current density is
lowered then a higher collector voltage is permitted.
Potentially destructive combinations of collector current
density and collector voltage are most likely to occur during
switchingandduringfault conditionsinthecircuit (egashort
circuited load). The safe operating areas give information
about the capability of a given device under these
conditions.
The collector current density is dependent on the collector
current and the degree of current crowding in certain areas
of the collector. The degree of current crowding is different
for turn-on (positive base voltage) and turn-off (negative
base voltage). Therefore the allowed combinations of
collector current and collector voltage, collectively known
as the safe operating area (SOA) of the transistor, will be
different for turn-on of the transistor and turn-off.
Forward SOA
With a positive voltage applied to the base, the shape of
the safe operating area for DC operation is that shown in
Fig. 12. Operation outside the safe operating area is not
allowed.
For pulsed operation the forward SOA increases, and for
small, lowdutycyclepulses it becomes square. Theforward
SOA provides useful information about the capabilities of
the transistor under fault conditions in the circuit (eg. ashort
circuited load).
Efield
Electron Concentration
Collector Base
Efield
Electron Concentration
Ecrit
Electron Density Increasing
Voltage Collapsing
Base Collector
Efield
Electron Concentration
Collector Base
134
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Fig. 12 Forward SOA.
The safe operating area is designed to protect the current,
power, voltage and second breakdown limits of the
transistor. The current, power and voltage limits of the
transistor have already been discussed. Note that the peak
voltage rating is the V
CEOmax
rating and not the V
CESMmax
rating. The V
CESMmax
rating only applies if the base emitter
voltage is not greater than zero volts.
Sometimes shown on forward SOA curves is an extension
allowing higher voltages than V
CEOmax
to be tolerated for
short periods (of the order of 0.5 µs). This allows turn-on of
the transistor from a higher voltage than V
CEOmax
. However,
the pulses allowed are very short, and unless it can be
guaranteed that the rated maximum pulse time will never
be exceeded, transistor failures will occur. If the circuit
conditions can be guaranteed then there is no danger in
making use of this capability.
As mentioned in the previous section, second breakdown
is triggered by combinations of high collector voltage and
high collector current density. With a positive voltage
applied to the base, the region of highest current density is
at the edges of the emitter as shown in Fig. 13.
Fig. 13 Forward biased second breakdown.
The base region under the emitter constitutes a resistance
(known as the sub emitter resistance). With a positive
voltage applied to the base, the sub emitter resistance will
mean that the areas of the emitter which are nearest to the
base have a higher forward bias voltage than the areas
furthest from the base. Therefore the edges of the emitter
have a higher forward bias voltage than the centre and so
they receive a higher base current.
As a result of this the edges of the emitter conduct a
substantial proportionof the collector current whenthebase
is forward biased. If the collector current is high then the
current density at the edgesof theemitter isalsohigh. There
will be some spreading out of this current as it traverses
the base. When the edge of the depletion regionis reached,
the current is sucked across by the electric field.
If the transistor is conducting a high current and also
supporting a high voltage, then the current density will be
high when the current reaches the edge of the depletion
region. If the current density is beyond that allowed at the
applied voltage, then the second breakdown mechanismis
triggered (as explained in the previous section) and the
device will be destroyed.
With a positive base current flowing, the region of highest
current density is at the edges of the emitter. Aforward SOA
failurewill therefore produce burns which originate fromthe
edge of one of the emitter fingers.
Forward SOA failure becomes more likely as pulse width
and/or duty cycle is increased. Because the edges of the
emitter are conducting more current than the centre, they
will get hotter. The temperature of the emitter edges at the
end of each current pulse is a function of the pulse width
and the emitter current. Longer pulse widths will increase
the temperature of the emitter edges at the end of each
current pulse. Higher duty cycles will leave insufficient time
for this heat to spread. In this manner, combinations of long
pulse width and high duty cycle can give rise to cumulative
heating effects. Current will crowd towards the hottest part
of the emitter. There is therefore a tendency for current to
become concentrated in very narrow regions at the edges
of the emitter fingers, and as pulse width and/or duty cycle
is increased the degree of current crowding increases. This
is the reason why the forward SOA for DC operation is as
shown in Fig. 12, but for pulsed operation it is enlarged and
for small, low duty cycle pulses it becomes square.
Reverse SOA
During turn-on of the transistor, the high resistance of the
collector regionis reducedby the introductionof holes (from
the base) and electrons (from the emitter). This process,
knownasconductivitymodulation, isthereasonwhybipolar
transistors are able to achieve such a low collector voltage
duringthe on state, typically 0.2 V. However, during turn-off
Maximum Collector
Current rating
Maximum Power
rating (Ptotmax)
Second breakdown
limit
Maximum Collector
Voltage rating
(VCEOmax)
VCE
IC
ICmax
n+
p
n-
n+
emitter
base
collector
back diffusion
Depletion Region
e- e-
IB IB
1V 1V
0.8V 0.8V
135
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
of the transistor, these extra holes and electrons constitute
a stored charge which must be removed from the collector
beforethe voltagesupportingdepletionregioncandevelop.
To turn off the transistor, a negative voltage is applied to
the base and a reverse base current flows. During turn-off
of the transistor, it is essential that the device stays within
its reverse bias safe operating area (RBSOA). The shape
of a typical RBSOA curve is as shown in Fig. 14.
With no negative voltage applied to the base, the RBSOA
is very much reduced, as shown in Fig. 14. This is
particularly important to note at power up and power down
of power supplies, when rail voltages are not well defined
(see section on improving reliability).
Fig. 14 Reverse SOA.
On applying a negative voltage to the base, the charge
stored in the collector areas nearest to the base contacts
will be extracted, followed by the charge stored in the
remaining collector area. Holes not extracted through the
base contact are free to diffuse into the emitter where they
constitute a base current which keeps the emitter active.
During the transistor storage time, the collector charge is
being extracted through the base, but the emitter is still
active and so the collector current continues to flow.
During the transistor fall time, the voltage supporting
depletion region is being developed and therefore the
collector voltage is rising. In addition to this, the negative
voltage on the base is causing holes to drift towards the
base contact where they are neutralised, thus preventing
holes from diffusing towards the emitter.
This has two effects on the collector current. Firstly, the
rising collector voltage results in a reduction in the voltage
across the collector load, and so the collector current starts
to drop. Secondly, the extraction of holes through the base
will be most efficient nearest to the base contacts (due to
the sub emitter resistance), and so the collector current
becomes concentrated into narrow regions under the
centre of the emitter fingers (furthest from the base). This
is shown in Fig. 15. This current crowding effect leads to
an increase in the collector current density during turn off,
even though the collector current itself is falling.
Thus for a portion of the fall time, the collector voltage is
rising and the collector current density is also rising. This
is a critical period in the turn-off phase. If the turn-off is not
carefully controlled, the transistor may be destroyed during
this period due to the onset of the second breakdown
mechanism described earlier.
During this critical period, the collector current is
concentrated into a narrow region under the centre of the
emitter. RBSOA failure will therefore produce burns which
originate from the centre of one of the emitter fingers.
Fig. 15 Reverse biased second breakdown.
Useful tips as an aid to circuit design
In recent years, the Philips Components Power
Semiconductor Applications Laboratory (P.S.A.L.) has
worked closely with a number of HVT users. It has become
apparent that there are some important circuit design
features which, if overlooked, invariably give rise to circuit
reliability problems. This section addresses each of these
areas and offers guidelines which, if followed, will enhance
the overall performance and reliability of any power supply.
Improving turn-on
There is more to turning on a high voltage transistor than
simply applying a positive base drive. The positive base
drive must be at least sufficient to keep the transistor
saturated at the current it is required to conduct. However,
transistor gain as specified in data sheets tends to be
assessed under static conditions and therefore assumes
the device is already on.
Maximum Collector
Current rating
Second breakdown
limit
Maximum Collector
Voltage rating
(VCESMmax)
VCE
IC
VCEOmax
VBEoff = 5V
VBEoff = 0V
ICmax
n+
p
n-
n+
emitter
base
collector
back diffusion
Depletion Region
e-
IB IB
0V 0V
1V
136
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Fig. 16 Transistor switching waveforms in a typical
power supply.
Note 1. The base current requirements at turn-on of the
transistor are higher than the static gain would suggest.
The conductivity modulation process, described at the
beginning of the previous section, occurs every time the
transistor is turned on. The faster the charges are
introduced into the collector, the faster the collector
resistance will drop, allowing the collector voltage to drop
to its saturation level. The rate at which the collector charge
is built up is dependent on the applied base current and the
applied collector current. In order to turn the transistor on
quickly, and hence minimise the turn-on dissipation, the
transistor needs to be overdriven until the collector voltage
has dropped to its saturation level. This is achieved by
having a period of overshoot at the start of the base current
pulse. The turn-on waveforms are shown in Fig. 17.
Fig. 17 Turn on waveforms.
Note 2. A fast rising base current pulse with an initial period
of overshoot is a desirable design feature in order to keep
the turn-on dissipation low.
The base current overshoot is achieved by having a
capacitor inparallel withthe forwardbasedriveresistor (see
Fig. 18). The RC time constant determines the overshoot
period and as a first approximation it should be comparable
to the transistor storage time. The capacitor value is then
adjusted until the overshoot period is almost over by the
time the transistor is saturated. This is the optimum drive
condition. A resistor in series with the capacitor (typically
R/2) can be used to limit the peak base current overshoot
and remove any undesirable oscillations.
The initial period of overshoot is especially necessary in
circuits where the collector current rises quickly (ie square
wave switching circuits and circuits with a high snubber
discharge current). In these circuits the transistor would
otherwise be conducting a high collector current during the
early stages of the turn-on period where the collector
voltagecan still be high. This wouldlead toanunacceptable
level of turn-on dissipation.
Fig. 18 Forward base drive circuit.
Note 3. Square wave switching circuits, and circuits with a
highsnubber dischargecurrent, arevery susceptibletohigh
turn-on dissipation. Using an RC network in series with the
forward base current path increases the turn-on speed and
therefore overcomes this problem.
It should also benoted that duringpower up of power supply
units, when all the output capacitors of the supply are
discharged, the collector current waveform is often very
different to that seen under normal running conditions. The
rising edge of the collector current waveformis often faster,
the collector current pulse width is often wider and the peak
collector current value is often higher.
VCE
IC
TURN ON TURN OFF
+VBB
R
C
TR
R/2
IC
IB
VCE
5 V
137
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
In order to prevent excessive collector current levels (and
transformer saturation) a ’soft start’ could be used to limit
the collector current pulse width during power up.
Alternatively, since many power supply designs are now
using current mode control, excessive collector current can
be avoided simply by setting the overcurrent threshold at
an acceptable level.
Note 4. Using the ’soft start’ and/or the overcurrent
protection capability of the SMPS control IC prevents
excessive collector current levels at power up.
Improving turn-off
As far as the collector current is concerned, optimum
turn-off for a particular device is determined by how quickly
the structure of the device will allow the stored charge to
be extracted. If the device is turned off too quickly, charge
gets trapped in the collector when the collector base
junction recovers. Trapped charge takes time to recombine
leading to a long collector current tail at turn-off and hence
high turn-off losses. On the other hand, if the device is
turned off too slowly, the collector voltage starts to rise
prematurely (ie while the collector current is at its peak).
This would also lead to high turn-off losses.
Note 1. Turning the transistor off either too quickly or too
slowly leads to high turn-off losses.
Optimum turn-off is achieved by using the correct
combinationof reverse base drive andstorage time control.
Reverse base drive is necessary to prevent storage times
frombeingtoolong(andalsotogivethemaximumRBSOA).
Storage time control is necessary to prevent storage times
from being too short.
Storage time control is achieved by the use of a small
inductor in series with the reverse base current path (see
Fig. 19). This controls the slope of the reverse base current
(as shown in Fig. 20) and hence the rate at which charge
is extracted from the collector. The inductor, or ’base coil’,
is typically between 1 and 6 µH, depending on the reverse
base voltage and the required storage time.
Fig. 19 Reverse base drive circuit.
Note 2. Applying a base coil in series with the reverse base
current path increases the transistor storage time but
reduces both the fall time and the turn-off losses.
Applying this small base inductor will usually mean that the
base emitter junction of the transistor is brought into
breakdown during part of the turn-off cycle. This is not a
problemfor the device because the current is controlled by
the coil and the duty cycle is low.
If the transistor being used is replaced by a transistor of the
same technology but having either a higher current rating
or a higher voltage rating, then the volume of the collector
increases. If thecollector volumeincreases thenthevolume
of charge in the collector, measured at the same saturation
voltage, also increases. Therefore the required storage
time for optimum turn-off increases and also the required
negative drive energy increases.
Overdriving the transistor (ie. driving it well into saturation)
also increases the volume of stored charge and hence the
required storage time for optimumturn-off. Conversely, the
requiredstorage time for aparticular device canbe reduced
by using a desaturation network such as a Baker clamp.
The Baker clamp reduces the volume of stored charge by
holding the transistor out of heavy saturation.
Note 3. The required storage time for optimum turn-off and
the required negative drive energy will both increase as the
volume of stored charge in the collector is increased.
The reverse base current reaches its peak value at about
the same time as the collector current reaches its peak
value. The turn-off waveforms are shown in Fig. 20.
Fig. 20 Turn off waveforms.
Note 4. For optimum turn-off of any transistor, the peak
reverse base current should be half of the peak collector
current and the negative drive voltage should be between
2 and 5 volts.
IC
IB
ts tf
VCE
ICpeak
-IBpeak
(= -ICpeak/2)
TR
-VBB
OV
LB
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S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
As far as the collector voltage is concerned, the slower the
dV/dt the lower the turn-off dissipation. Control of the
collector dV/dt is achieved by the use of a snubber network
(see Fig. 21). The snubber capacitor also controls the
collector voltage overshoot and thus prevents overvoltage
of the transistor.
Fig. 21 RCD snubber.
High collector dV/dt at turn-off can bring an additional
problemfor the transistor. A charging current flows through
the collector-base (Miller) capacitance of the device, and
according to the law, I = C x dV/dt, this charging current
increases in magnitude with increasing dV/dt. If this current
enters the base then the transistor can begin to turn back
on. Control of the collector dV/dt is usually enough to
prevent this from happening. If this is insufficient then the
base-emitter impedance must be reduced by applying a
resistor and/or capacitor between base andemitter toshunt
some of this current.
Note 5. High collector dV/dt at turn-off leads to parasitic
turn-on if the charging current of the transistor Miller
capacitance is not shunted away from the base.
High collector dI/dt at turn-off can also bring problems if the
inductance between the emitter and the base ground
referenceistoo high. Thefalling collector current will induce
a voltage across this inductance which takes the emitter
more negative. If the voltage on the emitter falls below the
voltage on the base then the transistor can begin to turn
back on. This problem is more rare but if it does arise then
adding a resistor and/or capacitor between base and
emitter helps to keep the base and emitter more closely
coupled. At all times it is important to keep the length of the
snubber wiring to an absolute minimum.
Note 6. High collector dI/dt at turn-off leads to parasitic
turn-on if the inductance between the emitter and the base
ground reference is too high.
Fig. 22 HVT environment.
Improving reliability
Inthe majority of cases, the most stressful circuit conditions
occur during power up of the SMPS, when the base drive
is least well defined and the collector current is often at its
highest value. However, the electrical environment at
power up is very often hardly considered, and potentially
destructive operating conditions go unnoticed.
A very common circuit reliability problem is RBSOA failure
occurring on the very first switching cycle, because the
reverse drive to the base needs several cycles to become
established. With no negative drive voltage on the base of
thetransistor, theRBSOAisreduced (asdiscussed earlier).
To avoid RBSOA failure, the collector voltage must be kept
below V
CEOmax
until there is sufficient reverse drive energy
available to hold the base voltage negative during the
turn-off phase.
Even with the full RBSOA available, control of the rate of
risingcollector voltage through the use of a snubber is often
essential in order to keep the device within the specified
operating limits.
Note 1. The conditions at power up often come close to the
safeoperating limits. Until the negative drive voltagesupply
is fully established, the transistor must be kept below its
V
CEOmax
.
Another factor which increases the stress on many
components is increased ambient temperature. It is
essential that the transistor performance is assessed at the
full operating temperature of the circuit. As the temperature
of the transistor chip is increased, both turn-on and turn-off
losses may also increase. In addition to this, the quantity
of stored charge in the device rises with temperature,
leading to higher reverse base drive energy requirements.
TR
-VBB
LB
+VBB
R
C
D
R
C
0V
R/2
TR
D
R
C
0V
139
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Note 2. Transistor performance should be assessed under
all operating conditions of the circuit, in particular the
maximum ambient temperature.
Asignificant proportion of power supply reliability problems
could be avoided by applying these two guidelines alone.
By making use of the informationon howtoimprove turn-on
and turn-off, small design changes can be made to the
circuit which will enhance the electrical performance and
reliability of the transistor, leading to a considerable
improvement in the performance andreliability of the power
supply as a whole.
140
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
2.1.3 Base Circuit Design for High Voltage Bipolar Transistors
in Power Converters
Fast, high voltage switching transistors such as the
BUT211, BUT11, BUT12, BUT18, BUW13, BU1508,
BU2508, BU1706 and BU1708 have all helped to simplify
the design of converter circuits for power supply
applications. Because the breakdown voltage of these
transistors is high (from 850 to 1750V), they are suitable
for operation direct from the rectified 110V or 230V mains
supply. Furthermore, their fast switching properties allow
the use of converter operating frequencies up to 30kHz
(with emitter switching techniques pushing this figure past
100kHz).
The design of converter circuits using high-voltage
switching transistors requires a careful approach. This is
because the construction of these transistors and their
behaviour in practical circuits is different fromthose of their
low-voltage counterparts. In this article, solutions to base
circuit design for transistor converters and comparable
circuits are developed from a consideration of the
construction and the inherent circuit behaviour of high
voltage switching transistors.
Switching behaviour
Figure 1 shows a complete period of typical collector
voltage and current waveforms for a power transistor in a
switching converter. The turn-on and turn-off intervals are
indicated. The switching behaviour of the transistor during
these two intervals, and the way it is influenced by the
transistor base drive, will now be examined.
Fig. 1 V
CE
and I
C
waveforms during the conduction
period for a power transistor in an S.M.P.S.
Turn-on behaviour
A particular set of voltage and current waveforms at the
collector and base of a converter transistor during the
turn-on interval is shown in Fig. 2(a). Such waveforms are
found in a power converter circuit in which a (parasitic)
capacitance is discharged by a collector current pulse at
transistor turn-on. The current pulse due to this discharge
can be considered to be superimposed on the trapezoidal
current waveform found in basic converter operation.
Fig. 2(a) Turn-on waveforms of a practical converter
circuit.
A positive base current pulse I
B
turns on the transistor. The
collector-emitter voltage V
CE
starts to decrease rapidly and
the collector current I
C
starts to increase. After some time,
the rate of decrease of V
CE
reduces considerably and V
CE
remains relatively high because of the large collector
current due to the discharge of the capacitance. Thus, the
turn-on transient dissipation (shown by a broken line)
reaches a high value.
141
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Fig. 2(b) Turn-on waveforms: fast-rising base current
pulse.
The collector current then decreases to a trough before
assuming the normal trapezoidal waveform. This is again
followed by a rapid decrease in V
CE
, which reaches the
saturation value defined by the collector current and base
current of the particular transistor.
Figure 2(b) depicts a similar situation but for a greater rate
of rise of the base current. The initial rapid decrease in V
CE
is maintained until a lower value is reached, and it can be
seen that the peak and average values of turn-on
dissipation are smaller than they are in Fig. 2(a).
Figure 2(c) shows the effect on the transistor turn-on
behaviour of a very fast rising base current pulse which
initially overshoots the final value. The collector-emitter
voltage decreases rapidly to very nearly the transistor
saturation voltage. The turn-on dissipation pulse is now
lower and much narrower than those of Figs. 2(a) and 2(b).
From the situations depicted in Figs. 2(a), 2(b) and 2(c), it
follows that for the power transistor of a converter circuit
the turn-onconditions are most favourable whenthe driving
base current pulse has a fast leading edge and overshoots
the final value of I
B
.
Fig. 2(c) Turn-on waveforms: very fast-rising base
current pulse with overshoot.
Turn-off behaviour
The waveforms which occur during the turn-off interval
indicated in Fig. 1 are shown on an expanded timescale
andwithfour different basedrivearrangements inFigs. 3(a)
to 3(d). These waveforms can be provided by base drive
circuits as shown inFigs. 4(a) to4(c). The circuit of Fig. 4(a)
provides the waveforms of Fig. 3(a); the circuit of Fig. 4(b)
those of Fig. 3(b) and, with an increased reverse drive
voltage, Fig. 3(c). The circuit of Fig. 4(c) provides the
waveforms of Fig. 3(d). The waveforms shown are typical
of those found in the power switching stages of S.M.P.S.
and television horizontal deflection circuits, using
high-voltage transistors.
In practical circuits, the waveform of the collector-emitter
voltage is mainly determined by the arrangement of the
collector circuit. The damping effect of the transistor on the
base circuit is negligible except during the initial part of the
turn-off period, when it only causes some delay in the rise
of the V
CE
pulse.
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S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Fig. 3(a) Turn-off waveforms; circuit with speed-up
capacitor.
The I
C
× V
CE
(turn-off dissipation) pulse is dependent on
both the transistor turn-off time and the collector current
waveshape during turn-off. Turn-off dissipation pulses are
indicated in Figs. 3(a) to 3(d) by the dashed lines.
The circuit of Fig. 4(a) incorporates a speed-up capacitor,
an arrangement often used with low-voltage transistors.
The effect of this is as shown in Fig. 3(a), a very rapid
decrease in the base current I
B
, which passes through a
negative peak value, and becomes zero at t
3
. The collector
current I
C
remains virtually constant until the end of the
storage time, at t
1
, and then decreases, reaching zero at t
3
.
The waveform of the emitter current, I
E
, is determined by I
C
and I
B
, until it reaches zero at t
2
, when the polarity of the
base-emitter voltage V
BE
is reversed.
After timet
2
, whenV
BE
isnegativeandI
E
iszero, thecollector
base currents are equal and opposite, and the emitter is no
longer effective. Thus, the further decrease of collector
current is governed by the reverse recovery process of the
transistor collector-base diode. The reverse recovery ’tail’
of I
C
(fromt
2
to t
3
) is relatively long, and it is clear the turn-off
dissipation is high.
In the circuit of Fig. 4(b) the capacitor is omitted. Fig. 3(b)
shows that the negative base current is limited to a
considerably lower value than in the previous case. All the
currents I
B
, I
C
and I
E
reach zero at time t
3
. The transistor
emitter base junction becomes reverse biased at t
2
, so that
duringthe short interval fromt
2
to t
3
a small negative emitter
current flows.
Fig. 4 Base circuits for turn-off base drive. The driver
transistor is assumed to be bottomed to turn off the
power transistor.
(a) With speed-up capacitor.
(b) Without speed up capacitor.
(c) With series inductor.
The emitter current, determinedby the collector current and
by the (driven) base current, therefore maintains control
over the collector until it reaches zero. Furthermore, the
collector current has a less pronounced tail and so the fall
time is considerably shorter than that of Fig. 3(a). The
turn-off dissipation is also lower than in the previous case.
Increasing the reverse base drive voltage in the circuit of
Fig. 4(b), with the base series resistance adjusted so that
the same maximum reverse base current flows, gives rise
to the waveforms shown in Fig. 3(c). The collector current
tail is even less pronounced, and the fall time shorter than
in Fig. 3(b).
143
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Fig. 3(b) Turn-off waveforms: circuit without speed-up
capacitor.
A further improvement in turn-off behaviour can be seen in
the waveforms of Fig. 3(d), which are obtained by including
an inductor in the base circuit as in Fig. 4(c). The rate of
change of the negative base current is smaller than in the
preceding cases, and the negative peak value of the base
current is smaller than in Fig. 3(a). The collector current I
C
reaches zero at t
3
, and from t
3
to t
4
the emitter and base
currents are equal. At time t
2
the polarity of V
BE
is reversed
and the base-emitter junction breaks down. At time t
4
the
negative base-emitter voltage decreases from the
breakdown value V
(BR)EBO
to the voltage V
R
produced by the
drive circuit.
The collector current fall time in Fig. 3(d) is shorter than in
any of the previous cases. The emitter current maintains
control of the collector current throughout its decay. The
large negative value of V
BE
during the final part of the
collector current decay drives the base-emitter junction into
breakdown, and the junction breakdown voltage
determines the largest possible reverse voltage. The
turn-off of the transistor is considerably accelerated by the
application (correctly timed) of this large base
emitter-voltage, and the circuit gives the lowest turn-off
dissipation of those considered.
Fig. 3(c) Turn-off waveforms: circuit without speed-up
capacitor, with increased reverse drive voltage.
The operation of the base-emitter junction in breakdown
during transistor turn-off, as shown in Fig. 3(d), has no
detrimental effect on the behaviour of transistors such as
the BUT11 or BU2508 types. Published data on these
transistors allow operation in breakdown as a method of
achieving reliable turn-off, provided that the -I
B(AV)
and -I
BM
ratings are not exceeded.
It is evident from Figs. 3(a) to 3(d) that the respective
turn-off dissipation values are related by:-
P
off(a)
> P
off(b)
> P
off(c)
>P
off(d)
The fall times (related in each case to the interval from t
1
to t
3
) are given by:-
t
f(a)
> t
f(b)
> t
f(c)
> t
f(d)
The storage times (equal to the interval from t
0
to t
1
) are:-
t
s(a)
< t
s(b)
< t
s(d)
144
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
where the subscripts (a), (b), (c) and (d) refer to the
waveforms of Figs. 3(a), 3(b), 3(c) and 3(d) respectively. It
follows that the circuit of Fig. 4(c), which provides the
waveforms of Fig. 3(d), gives the most favourable turn-off
power dissipation. It has, however, thelongest storagetime.
Fig. 3(d) Turn-off waveforms: circuit with series
inductor.
From consideration of the waveforms in Figs. 3(a) to 3(d),
it can be concluded that optimum turn-off of a high voltage
transistor requires a sufficiently long storage time
determined by the turn-off base current and a sufficiently
large negative base-emitter voltage correctly timed with
respect to the collector current waveform.
The phenomena which have been described in this section
become more pronounced when the temperature of the
operating junction of the transistor is increased: in
particular, the fall times and storage times are increased.
The design of a base drive circuit should therefore be
checked by observing the waveforms obtained at elevated
temperatures.
Optimum base drive circuitry
From the foregoing study of the required base current and
base-emitter voltage waveforms, a fundamental base
circuit arrangement to give optimum turn-on and turn-off of
high voltage switching transistors will now be determined.
It will be assumed that the driver stage is
transformer-coupled to the base, as in Fig. 5(a), and that
the driver transformer primary circuit is such that a low
impedance is seen, looking into the secondary, during both
the forward and reverse drive pulses. The complete driver
circuit can then be represented as an equivalent voltage
source of +V
1
volts during the forward drive period and -V
2
volts during the reverse drive/bias period. This is shown in
Fig. 5(b).
Fig. 5 (a) Schematic drive circuit arrangement.
(b) Equivalent drive circuit arrangement.
(c) Equivalent circuit for current source forward drive.
Forward base drive can also be obtained from a circuit
whichacts as a current source rather than avoltagesource.
This situation, where the reverse drive is still obtained from
a voltage source, is represented in Fig. 5(c). The basic
circuit arrangements of Figs. 5(b) and 5(c) differ only with
respect to forward drive, and will where necessary be
considered separately.
Comparable base drive waveforms can, of course, be
obtained from circuits differing from those shown in
Figs. 5(b) and 5(c). For such alternative circuit
configurations the following discussion is equally valid.
145
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Base series resistor
Most drive circuits incorporate a resistor R
B
in series with
the base. The influence of the value of this resistor on the
drive characteristic will be briefly discussed.
Voltage source forward drive.
In circuits with a voltage source for forward drive, shown in
a simplified form in Fig. 6(a), the following parameters
determine the base current:-
The transistor base characteristic ;
The value of the base resistor R
B
;
The forward drive voltage V
1
.
Fig. 6(a) Drive circuit with base resistor R
B
and voltage
source forward drive.
Figure 6(b) shows how the tolerances in these parameters
affect the base current. It is clear that to avoid large
variations in I
B
, the tolerances in R
B
and V
1
should be
minimised. The voltage drop across R
B
reduces the
dependence of I
B
on the spreads and variations of the
transistor V
BE(on)
. For good results the voltage drop across
R
B
must not be less than V
BE(on)
.
Current source forward drive
In circuits where a current source is used for forward drive,
the forward base current is independent of spreads and
variations of V
BE(on)
. The base current level and tolerances
are governed entirely by the level and tolerances of the
drive. A separate base series resistor is therefore
unnecessary, but isnevertheless includedinmanypractical
current-source-driven circuits, to simplify the drive circuit
design. The following discussions will assume that a series
base resistor R
B
always forms part of the base drive
network.
Fig. 6(b) Effects on the value of I
B
on circuit tolerances.
(i) Variation of transistor base characteristic.
(ii) Variation of value of resistor R
B
.
(iii) Variation of drive voltage V
1
.
Turn-off arrangement
To initiate collector current turn-off, the drive voltage is
switchedat time t
0
fromthe forward value+V
1
to the reverse
value -V
2
.
146
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Fig. 7(a) Turn-off waveforms of the circuit of Fig. 7(b).
The desired turn-off voltage and current waveforms are
obtained by adding various circuit elements to the basic
resistive circuit of Fig. 6(a). A convenient method of
achieving the desired slowly-decreasing base current is to
use a series inductor L
B
as shown in Fig. 7(b). The turn-off
waveforms obtained by this method are shown in Fig. 7(a).
Fig. 7(b) Base drive circuit with series inductor.
Base series inductor
At time t
0
the base current starts to decrease from the
forward drive value I
B1
with a slope equal to:-
For a considerable time after t
0
, the (decreasing) input
capacitance of the transistor maintains a charge such that
there is no perceptible change in V
BE
. At time t
2
the amount
of charge removed by the negative base current (-I
B
) is
insufficient tomaintainthis current, andits slopedecreases.
At time t
3
, when:-
−V
2
− (+V
BE(on)
)
L
B
d I
B
dt
· 0 where I
B
· I
B2
V
BE
· −V
2
−R
B
I
B2
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S.M.P.S. Power Semiconductor Applications
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Immediately after t
3
, the stored energy in L
B
gives rise to a
voltage peak tending to increase the reverse bias of the
transistor. The voltage is clamped by the base-emitter
breakdown voltage, so that:-
At time t
4
the negative base current starts to decrease with
an initial slope equal to:-
At t
5
the base current reaches zero. The base-emitter
voltage then changes from -V
(BR)EBO
to the value -V
2
, the
level of the drive voltage. As has been demonstrated, the
collector storage time, t
s
, is an important parameter of the
drive circuit turn-off behaviour. Fig. 7(a) shows that the
value of t
s
can be calculated approximately from:-
and this expression is sufficiently accurate in practice. In
most cases the base current values are related by:-
In the case where (-I
B2
/ I
B1
) = 2, the collector storage time
is given by:-
In practical circuits, design considerations frequently
indicate a relatively small value for V
2
. The required value
of t
s
is then obtained with a small value of L
B
, and
consequently the energy stored in the inductor (1/2 L
B
I
B2
2
)
is insufficient to maintain the base-emitter junction in the
breakdown condition. Figure 7(a) shows that breakdown
should continue at least until the collector current is
completely turned off. The higher the transistor junction
temperature, the more stored energy is necessary to
maintainbreakdownthroughout the increasedturn-off time.
These phenomena are more serious in applications where
the storage time must be short, as is the case for the BUT12
or BUW13 transistors, for example. For horizontal
deflection output transistors such as the BU508 and
BU2508, which require a much longer storage time, the
base inductance usually stores sufficient energy for correct
turn-off behaviour.
Diode assisted base inductor
It is possible to ensure the storage of sufficient turn-off
energy by choosing a relatively large value for V
2
. Where
a driver transformer is employed, there is then a
corresponding increase in V
1
. To obtain the desired value
of forward base current, the base resistance R
B
must also
belarge. Alarge value of R
B
, however, diminishes the effect
of L
B
on the transistor turn-off behaviour, unless R
B
is
bypassed by a diode as in Fig. 8.
Fig. 8 Base drive circuit with diode-assisted series
inductor.
Fig. 9 Base drive circuit extended for improved turn-off
behaviour.
Turn-off RC network
Improved turn-off behaviour can be obtained without
increasing V
2
, if additional circuit elements are used. An
arrangement used in practice is shown in Fig. 9, and
consists of network R
3
C
3
which is connected in series with
R
B
and L
B
.
Avoltage V
3
is developed across C
3
because of the forward
base current. (This voltage drop must be compensated by
ahigher valueof V
1
). When reversecurrent flows at turn-off,
the polarity of V
3
is such that it assists the turn-off drive
voltage V
2
. Using the same approximation as before, the
storage time is given by:-
The same value of t
s
nowrequires a larger value of L
B
. The
energy stored in L
B
is therefore greater and the transistor
can more reliably be driven into breakdown for the time
required.
The waveforms of Fig. 7(a) are equally applicable to the
circuit of Fig. 9, if V
2
is replaced by (V
2
+ V
3
). In practice V
3
will not remain constant throughout the storage time, and
replacing V
3
by its instantaneous value will make a slight
difference to the waveforms.
V
BE
· −V
(BR)EBO
− V
2
+ V
(BR)EBO
L
B
− V
2
+ V
(BR)EBO
L
B
. t
s
· I
B1
− I
B2
¸

¸
I
B2
I
B1
_

,
≈ 1 to 3
t
s
·
3 I
B1
L
B
−V
2
− (+V
BE(on)
)
t
s
·
3 I
B1
L
B
− (V
2
+ V
3
) − (+V
BE(on)
)
148
S.M.P.S. Power Semiconductor Applications
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Turn-on arrangements
It has been shown that for optimumturn-onof ahigh voltage
switching transistor, the turn-on base current pulse must
have a large amplitude and a fast leading edge with
overshoot. However, the inductance L
B
included in the
circuits derived for optimum turn-off (Figs. 7 to 9) makes it
difficult to produce such a turn-on pulse. The additional
components (R
1
, C
1
, D
1
) in the circuit of Fig. 10(a) help to
solvethis problemasshownbythe waveformsof Fig. 10(b).
Fig. 10(a) Base drive circuit extended for improved
turn-on behaviour with voltage source drive.
At the instant of turn-on, network R
1
C
1
in series with D
1
provides a steep forward base current pulse. The turn-off
network is effectively by-passed during the turn-on period
byC
1
andD
1
. The time-constant R
1
C
1
of the turn-onnetwork
should be chosen so that the forward current pulse
amplitude is reduced virtually to zero by the time the
transistor is turned on.
The turn-on network of Fig. 10(a) can also be added to the
diode-assisted turn-off circuit of Fig. 8. In circuits which are
forward driven by a current source, the overshoot required
on the turn-on base current pulse must be achieved by
appropriate current source design.
Fig. 10(b) Turn-on waveforms of the circuit of Fig.10(a).
Practical circuit design
The base drive circuit of Fig. 10(a) combines the drive
voltage sources +V
1
and -V
2
with circuit elements R
B
, L
B
,
R
3
C
3
and R
1
C
1
D
1
which, if correctly dimensioned, allow
optimumtransient behaviour of the switchingtransistor. Not
all these elements, however, will be necessary in every
case for good results.
In circuits where the collector current rate of rise is limited
by collector circuit inductance, the turn-on network R
1
C
1
D
1
can be omitted without danger of excessive collector
dissipation at turn-on. In circuits where the base series
inductance L
B
is sufficiently large to give complete turn-off,
network R
3
C
3
can be omitted. Networks R
1
C
1
D
1
and R
3
C
3
are superfluous in horizontal deflection circuits which use
BU508, BU2508 transistors or similar types.
A discrete component for inductance L
B
need not always
be included, because the leakage inductance of the driver
transformer is sometimes sufficient.
The omission of R
B
from circuits which are forward driven
by a voltage source should generally be considered bad
design practice. It is, however, possible to select
component values such that the functions of R
1
C
1
and R
3
C
3
are combined in a single network.
In some cases, the circuits of Figs. 7 to 10 may generate
parasitic oscillations (ringing). These can usually be
eliminated by connecting a damping resistor R
4
between
the transistor base and emitter, as shown in broken lines
in Fig. 10(a).
Physical behaviour of high-voltage
switching transistors
Base circuit design for high-voltage switching transistors
will now be considered with respect to the physical
construction of the devices. To achieve a high breakdown
voltage, the collector includes a thick region of high
resistivity material. This is the major difference in the
construction of high and low voltage transistors.
The construction of a triple-diffused high voltage transistor
is represented schematically in Fig. 11(a). The collector
region of an n-p-n transistor comprises a high resistivity n-
region and a low resistivity n+ region. Most of the collector
voltage is dropped across the n- region. For semiconductor
material of achosenresistivity, thethickness of then- region
is determined by the desired collector breakdown voltage.
The thickness of the n+ region is determined by
technological considerations, in particular the mechanical
construction of the device. Fig. 11(b) shows the impurity
concentration profile of the transistor of Fig. 11(a).
149
S.M.P.S. Power Semiconductor Applications
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Fig. 11 High voltage switching transistor.
For good switching performance, the high voltage blocking
characteristic of the transistor structure must be modified
at transistor turn-on, so that a lowforward voltage condition
is exhibited. One method of achieving this is to inject alarge
number of carriers through the base to the collector region.
The high resistivity of the n- region is then "swamped" by
excess carriers. This effect is often referred to as a
collector-width modulation.
The following discussion of the physical changes which
occur at transistor turn-on and turn-off is based on a much
simplified transistor model; that is, the one dimensional
charge control model. Fig. 12 shows such a model of a
low-voltage transistor, and assumes a large free
carrier-to-doping concentration ratio in the base due to the
carriers injected fromthe emitter. Line a represents the free
carrier concentration in the base for transistor operation in
the active region (V
CB
>0), and line c that for the saturated
condition (V
CB
<0). Line b represents the concentration at
the onset of saturation, where V
CB
=0. The slope of the free
carrier concentration line at the collector junction is
proportional to the collector current density, and therefore,
to the collector current.
Turn-on behaviour
The carrier concentration profile of ahigh-voltagetransistor
during turn-on is shown in Fig. 13(a). Line 1 represents a
condition where relatively few carriers are injected into the
base fromthe emitter. Let line 1 be defined as representing
the onset of saturation for the metallurgic collector junction;
that is, point 1(C’). In this case, V
CB
=0, whereas the
externally measured collector voltage is very high because
of the voltage drop across the high-resistivity collector
region.
Fig. 12 Charge-control representation of a low-voltage
transistor:
Line a in the active region
Line b nearing the onset of saturation
Line c heavily saturated condition
Line2inFig. 13(a) represents ahighlevel of carrier injection
into the base from the emitter. Carriers have also
penetrated the high-resistivity collector region as far as
point 2(C’), and so the base region is now, in effect,
extendedto this point andthe effective width of the collector
region is reduced. The voltage drop across the collector
region, causedby the collector current which is proportional
to the concentration gradient at point 2(C’), is therefore less
thanthevoltagedropwhichoccurredwith thelevel of carrier
injection on line 1.
Lines 3, 4and 5represent still higher carrier injection levels,
and hence decreasing effective collector widths. The
voltage drop across the effective collector also decreases.
In the situation represented by line 6, the entire high
resistivity collector region has been flooded with excess
carriers. The collector-base voltage is therefore so lowthat
the transistor is effectively saturated. The low saturation
voltage has been obtained at the expense of a large base
current, and this explains why a high-voltage transistor has
a low current gain, especially at large collector currents.
Figure 13(b) shows simplified collector current/voltage
characteristicsfor atypical highvoltagetransistor. Between
lines OQ and OP, voltage V
CE
progressively decreases as
excess carriers swamp the high-resistivity collector region.
Line OP can be regarded as the ’saturation’ line.
When the transistor is turned on, the carrier injection level
increases from the very small cut-off level (not shown in
Fig. 13(a)) to the level represented by line 6 in Fig. 13(a).
The transistor operating point therefore moves from the
cut-off position along the locus shown in Fig. 13(b) to
position 6, which corresponds to line 6 in Fig. 13(a). The
effect of this process on I
C
and V
CE
is shown in Fig. 13(c),
where the time axis is labelled 0 to 6 to correspond to the
150
S.M.P.S. Power Semiconductor Applications
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Fig. 13 Turn-on behaviour of high voltage switching
transistor.
numbered positions on the operating point locus of
Fig. 13(b) and the numbered lines on the carrier
concentration diagram of Fig. 13(a).
The time taken to reach the emitter injection level 6 is
directly proportional to the turn-on time of the transistor.
Therate of build-upof emitter injectiondepends on thepeak
amplitude and rise time of the turn-on base current pulse.
Theshortest turn-ontime isobtainedfromalarge amplitude
base current pulse with a fast leading edge. Thus, physical
considerations support the conclusion already drawn from
a study of the circuit behaviour of the transistor.
Turn-off behaviour
The carrier concentration in the saturated transistor at the
beginning of the turn-off period is represented by line 0 in
Fig. 14(a), corresponding to line 6 in Fig. 13(a). As shown
in Fig. 14(b), the base current I
B
gradually decreases, but
I
C
remains almost constant for some time, and -I
E
therefore
decreases to match I
B
. The resulting carrier concentration
patterns are shown as lines 1 and 2 in Fig. 14(a). This
process is plotted against time in Fig. 14(b) where, again,
the graduation of the horizontal axis corresponds to that of
the lines in Fig. 14(a).
At time point 3 the emitter current has reduced to zero, and
is slightly negative until point 6. Thus the carrier
concentration lines 4 and 5 have negative slope. Complete
collector current cut-off is reached before point 6. (This
situation is not represented in Fig. 14).
Excess carriers present in the collector regionare gradually
removed from point 0 onwards. This results in increasing
collector voltage because of the increasing effective width
of the high-resistivity collector region.
Figures 14(a) and 14(b) depict a typical turn-off process
giving good results with high voltage transistors; the
waveforms of Fig. 14(b) should be compared with those of
Figs. 3(d) and 7(a). A different process is shown in
Figs. 15(a) and 15(b). The initial situation is similar (line 0,
Fig. 15(a)) but the base current has a steep negative slope.
At time point 1 of Fig. 15(b), the emitter current -I
E
has
reached zero, and so the carrier concentration line 1 has
zeroslope at the emitter junction. The emitter-base junction
is effectively cut off and only the relatively small leakage
current (not shown in Fig. 15(b)) is flowing. From point 1
onwards, therefore, the emitter has no influence on the
behaviour of the transistor. The switching process is no
longer ’transistor action’, but the reverse recovery process
of a diode. The carrier concentration pattern during this
process is shown in Fig. 15(a) in broken lines, with zero
slope at the emitter junction because the emitter is
inoperative.
The reverse recovery process is slow because of the high
resistivity of the collector region and the consequent slow
decrease of collector current. (Collector and base currents
are, of course, equal and opposite when the emitter is cut
off). The turn-off dissipation increases progressively as the
transition time fromcollector saturation to cut-off increases.
Furthermore, at higher junction temperatures the reverse
recovery charge, and hence the duration of the recovery
process, is greater.
151
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Fig. 14 Turn-off behaviour.
The longer the turn-off time, the greater the turn-off
dissipation and, hence, the higher the device temperature
which itself causes a further increase in turn-off time and
dissipation. To avoid the risk of thermal runaway and
subsequent transistor destruction which arises under these
conditions, the turn-off drive must be such that no part of
the turn-off is governed by the reverse recovery process of
the collector base diode. Actual transistor action should be
maintained throughout the time when an appreciable
amount of charge is present in the transistor collector and
base regions, and therefore the emitter should continue to
operate to remove the excess charge.
There are many conditions of transistor turn-off which lie
between the extreme cases of Figs. 14(a) and 15(a).
Circuits in which the operating conditions tend towards
those shown in Fig. 15(a) must be regarded as a potential
source of unreliability, and so the performance of such
circuits at elevated temperatures should be carefully
assessed.
Fig. 15 Further turn-off waveforms.
152
S.M.P.S. Power Semiconductor Applications
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2.1.4 Isolated Power Semiconductors for High Frequency
Power Supply Applications
This section describes a 100 W off-line switcher using the
latest component and application technology for
cost-effectiveminiaturisation(seeRef.1). Thepower supply
has a switching frequency of 500kHz with 1MHz output
ripple. The section focuses on new power semiconductor
components and, in particular, the need for good thermal
management and electrical isolation. The isolated F-pack
- SOT-186, SOT-199 and the new SOT-186A - are
introduced. Philips has developed these packages for
applications in S.M.P.S. The importance of screening to
minimise conducted R.F.I. is covered and supported with
experimental results.
Introduction
There is an ever-growing interest in high frequency power
supplies and examples are now appearing in the market
place. The strong motivation for miniaturisation is well
founded and a comprehensive range of high frequency
components is evolving to meet this important new
application area, including:-
The output filter capacitor, which was traditionally an
electrolytic type, can be replaced by the lower impedance
multi-layer ceramic type.
The output filter choke may be reduced in size and
complexity to a simple U-core with only a few turns.
The benefits of reduced transformer size can be realised
at high frequency by using core materials such as 3F3.
However, transformer size is ultimately limited by creepage
and clearance distances defined by international safety
standards.
Power MOSFETs provide the almost ideal switch, since
they are majority carrier devices with very low switching
losses. Similarly, Schottky diodes are the best choice for
the output rectifiers.
This paper concentrates on the semiconductors and
introduces three isolated encapsulations:- the ’F-packs’ -
SOT-186, SOT-186A and SOT-199 - and applies them to
high frequency S.M.P.S.
Power MOSFETs in isolated packages
Making power supplies smaller requires devices such as
MOSFETs to be used as the power switch at high
frequency. At this high frequency the size and efficiency of
the output filter can be dramatically improved. Present
abstract perception of acceptable inefficiency in power
semiconductors remains constant i.e. 5 to 10% overall
semiconductor loss at 500kHz is just as acceptable as at
50kHz. So throughout the trend to higher frequencies, the
heatsink size has remained constant.
Fig. 1 Mounting of SOT-186 and TO-220 compared.
153
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
At 50kHz it is possible to use the earthed open frame of the
power supply as the heatsink. Then all semiconductors are
laid out around the periphery of the p.c.b. andmounted with
isolation onto the heatsink. To gain the minimum overall
size from high frequency operation, this technique must
become standard practice to avoid having to leave
clearance distances between primary and secondary side
heatsinks. The component manufacturers are responding
to the need for transistors with isolation by making them
with a fully isolated package - the F-pack.
F-pack, SOT-186, is an encapsulation with a functionally
isolating epoxy layer moulded onto its header; see Fig. 1.
This allows a common heatsink to be used with no further
isolation components. With just a spring clip, an insulated
mounting (up to 1000V) of virtually all existing TO-220
components is possible without degrading performance.
Screw mounted, the SOT-186 is still simplicity itself; there
is no need for metal spacers, insulation bushes and mica
insulators. Mounted either way, the F-pack reduces
mounting hardware compared with that required for a
standard TO-220.
The insulating layer of a SOT-186 can withstand more than
1000V, but the maximum voltage between adjacent leads
is limited to 1000V. This is slightly less than the breakdown
voltage between TO-220 legs due to the distance between
the legs being reduced from 1.6mm to 1.05mm. However,
the375 µmthick epoxy gives morecreepage andclearance
betweentransistor legs and heatsink thana traditional mica
washer of 50 µm. The capacitive coupling to an earthed
heatsink is therefore reduced from 40pF to 13pF. This can
be of significant help with the control of R.F.I.
Fig. 2 Typical transient thermal response of SOT-186
and TO-220 packages (experimental).
The latest isolated package introduced by Philips is the
SOT-186A. This is a fully encapsulated TO-220
replacement which provides true isolation fromtheheatsink
of 2500V RMS. It is fully pin-compatible with the TO-220
packagesince it possesses the samedistance between the
leads andtheback of the tab wherethermal contact ismade
with the heatsink.
Thetransient thermal responseof theSOT-186andTO-220
encapsulations is shown in Fig. 2. A BUX84F (SOT-186)
and a BUX84 (TO-220) were used for the test. Each
transistor was mounted on a heatsink at 25˚C. The BUX84
was mounted on a mica washer. The test conditions were
given by: Mounting force = 30N; I
E
= 1A; V
CB
= 10V.
The thermal resistance of the F-pack is better than the
standard package in free air because it is all black and
slightly larger. The difference is quite small, 55K/W for the
SOT-186 and 70K/W for the TO-220. Mounted on a
heatsink, the typical thermal resistance of the SOT-186 is
slightly better than the standard TO-220, see Fig. 2.
However, the exact value of R
th(mb-hs)
depends on the
following:
- Whether heatsink compound is used.
- The screw’s torque or pressure on the encapsulation.
- The flatness of the heatsink.
The flatness of the TO-220 metal heatsink is more
controllable than the moulded epoxy on the back of the
SOT-186. Therefore, the use of a heatsink compound with
SOT-186 is of great importance. Once this is done the
thermal characteristics of the two approaches are similar.
Schottky diodes in isolated packages
To be consistent with the small, single heatsink approach,
the output rectifying diodes must be isolated from the
heatsink too. Schottky diodes in SOT-186 are available,
andencapsulations accommodatinglarger crystal sizes are
availablefor higher powers. The F-packversion of thelarger
SOT-93package is the SOT-199. Two Schottky diodes can
bemountedinSOT-199 for power outputsup toamaximum
of I
F(AV)
equal to 30 A. The SOT-199 package is similar to,
but larger than, the SOT-186 shown in Fig. 1, and can be
mounted similarly.
The epoxy isolation is thicker at 475µm. This further
reduces the capacitive coupling to heatsink when
compared to a Schottky diode isolated with either 50µm
mica or 250µm alumina. Equally important is the increase
in the breakdown voltage, from a guaranteed 1000V to
1500V. As with SOT-186, the use of heatsink compound is
advised to give good thermal contact.
In conclusion, the combination of isolated packages allows
an S.M.P.S. to be designed with many devices thermally
connected to, but electrically isolated from, a single
common heatsink.
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S.M.P.S. Power Semiconductor Applications
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Transistor characteristics affecting choice
of high frequency converter
In this exercise only MOSFETs were considered practical
for the target operating frequency of 500kHz. The range of
converters to choose from is enormous if all the resonant
circuits are included. The choice in this case is reduced by
considering only the square wave types because:-
• The p.w.m technique is well understood.
• The main output is easily controlled over a wide range of
input voltages and output loads.
• A resonant tank circuit, which may increase size, is not
needed.
It is recognised that there are many situations and
components which equally affect the choice of converter.
The transformer component has been studied in Ref. 1. For
maximum power through the transformer in a mains input,
500kHz, 100W power supply, a half-bridge converter
configuration was chosen. The influence of the transistor
is now examined.
The relationship of on-resistance R
DS(on)
, with drain-source
breakdown voltage, V
(BR)DSS
, has been examined in Ref. 2.
It was shown that R
DS(on)
is proportional to V
(BR)DSS
raised to
the power 2. This implies equal losses for equal total silicon
area. The advantage is therefore with the forward / flyback
circuits because they have easier drive arrangements and
often only require one encapsulation. Particular attention
is paid to the frequency dependent losses, which are now
considered.
C
OSS
and the loss during turn-on
No matter how fast the transistor is switched in an attempt
to avoid switching losses, there are always capacitances
associated with the structure of the transistor which will
dissipate energy each time the transistor is turned on and
off. For a BUK456-800A, 800V MOSFET of 20mm
2
chip
area, the turn-off waveform is shown in Fig. 3.
All loads have been reduced to nearly zero to highlight the
turn-on current spike due to the capacitance of the circuit.
The discharge of the output capacitance of the device will
be similar but is unseen by the oscilloscope because it is
completely internal to the device. The discharge of the
energy is done in two different stages:-
Stage 1 - From the flyback voltage to the D.C link voltage.
This energy is mainly either returned to the supply or
clamped in the inductance of the transformer by the
secondary diodes, which release it to supply the load when
the primary switch turns on. This energy is not dissipated
in the power supply.
Stage 2 - From the link voltage to the on-state voltage.
This energy is dissipated in the transistor when it turns on.
The calculation of the effective output capacitance at this
voltageinvolves integration to take into account the varying
nature of the capacitance with the applied drain voltage.
The general expression for energy stored in the output
capacitance of a MOSFET is:-
For a BUK456-800A switching on with V
DS
= 325V, the
energy is 1.6 µJ. Gate to drain capacitance is not taken into
account but would probably add about 20% extra
dissipation to take it to 1.9µJ. This is for a transistor
operating in a fixed frequency flyback, forward, or push-pull
converter. A transistor in the half bridge circuit switches on
fromhalf the linevoltageandsothelosses ineachtransistor
would be approximately a quarter of those in the previous
converters. In self-oscillating power supplies the transistor
switchesonfrom750 V. This woulddissipateall of thestage
(1) energy as well and so that could make approximately
four times the loss inthe transistor inthis configuration. This
example of a BUK456-800Aoperating at 500kHz, in a fixed
frequency forward, flyback, or push pull system would
dissipate 0.95 W internal to the device.
Stray capacitance around the circuit includes mounting
base to heatsink capacitance, which for a ceramic isolator
is 18pF. The energy for this is simply calculated by using
0.5 CV
2
, andis 1µJ when charged to325 V. F-pack reduces
this by about a factor of two.
Fig. 3 MOSFET voltage and current waveforms in a
forward converter.
In conclusion, the fixed frequency half-bridge system
benefits fromdischarging fromonly half the d.c. link voltage
and is the best choice to minimise these effects. There are
two switches, so the overall benefit is only half, but the
thermal resistance is also half, so the temperature rise of
E · 3.3 C
oss(25V)
V
d
1.5
155
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
each transistor is actually four times less than in a forward
converter. This makes this internal loss at 500kHz, 0.25 W
in each transistor.
C
ISS
and drive circuit losses
It is common to drive MOSFETs from a voltage source,
through a series gate resistor. This gate resistor is seen
usually to dampen stray inductance ringing with the gate
capacitance during turn-on and turn-off of the transistor.
This effectively prevents spurious turn-on. The resistor has
another function when operating at a frequency of 500kHz,
and that is to remove the dissipation of the energy of the
gate capacitance frominside to outside the transistor. This
is important because at frequencies in the MHz region the
dissipation becomes the order of 1 W. A graph of charging
the gate with a constant 1mA current source is shown in
Fig. 4. The area under the curvewas measured as 220µVs.
Therefore, at 10kHz, the power dissipation is 2mW and at
10MHz, 2W.
BUK455-500A
Fig. 4 Change of gate voltage with time for a power
MOSFET with a 1mA constant charge current.
If the system chosen has two transistors, as in the
half-bridge, then the dissipation will be doubled. Therefore,
a single transistor solution is the most efficient to minimise
these losses.
Concluding this section on the significant transistor
characteristics, the power loss due to discharging internal
MOSFET capacitances is seen to become significant
around 500kHz to 1MHz, affecting the efficiency of a 100W
converter. The predominant loss is output capacitance,
whichisdischargedby, anddissipated inR
DS(on)
. Converters
which reduce this loss are those which switch froma lower
V
DS
, i.e.:-
• Resonant converters which switch at zero voltage.
• Converters designed for rectified 110V a.c. mains rather
than 230V a.c. mains.
• Square-wave converters which use a half-bridge
configuration rather than forward, flyback, or push-pull
circuits.
Self oscillating power supplies give higher losses because
they discharge from the flyback voltage of 750V at turn-on.
SMPS design considerations
There are two major areas which influence the choice of
converter to be considered here:-
- multiple outputs
- R.F.I.
The influence of multiple outputs on the
choice of converter.
If only one output is required then the half-bridge would be
selected to minimise the loss due to output capacitance, as
described above.
If multiple outputs are specified, and some of these require
rectifying diodes other than Schottky diodes, then the
switching loss of power epitaxial diodes has to be
considered. Before the arrival of 100V Schottky diodes,
epitaxial diodes would have been a natural first choice for
outputs higher than 5V. However, a 12V auxiliary output
often has less current than a 5V output, so MOSFETs can
competebetter onforward volt drop. Thenthereisswitching
loss: a MOSFET can have less loss than an epitaxial diode,
but the actual frequency at which it becomes effective is
debatable.
Synchronous MOSFETrectifiers were first seen as a threat
toSchottkydiodesfor useinlowvoltageoutputs. Theycould
rectify with less forward volt drop, albeit sometimes at a
cost. MOSFETrectifiers arenowmoreof athreat toepitaxial
diodes in higher voltage outputs above 15 to 20V. Applying
these transistors is not as straightforward as it may first
appear. Looking at flyback, forward and bridge outputs in
turn:-
Flyback converter
A diode rectified output is replaced by a MOSFET, with no
extra components added, (Fig. 5). Putting the transistor in
the negative line and orientating it with the cathode of the
parasitic diode connected to the transformer allows it to be
driven well and does not threaten the gate oxide isolation.
If the drive is slowed down by the addition of a gate resistor,
the voltage across R
DS
during transient switching can be
large enough such that, when added to the output voltage,
gives V
GS
greater than that recommended in data. Fast
turn-on is therefore essential for the good health of the
transistor.
156
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Fig. 5 Flyback and Forward converters with Synchronous Rectification.
Forward converter
Normal diode rectifiers are replaced by MOSFETs in a
forward output, as shown in Fig. 5, with no extra
components added. However, there is a problem at
maximum input voltage. At minimum volts, the transformer
winding supplies V
out
+ V
choke
, where:-
V
out
= V
choke
= 12V (for a 12V output)
at 50% mark/space ratio.
V
trans
= 24V
At maximum input volts, the choke may have 2 or 3 times
the voltage across it, which makes the total 36V or 48V.
With the gate rated at 20V, the choke is necessary for the
forward transistor, as shown in Fig. 5, to supply the correct
voltage. It may also be necessary for the freewheel diode,
but this may be marginal depending on the input voltage
range specified. This costs even more money, but may be
considered good value if the loss in an epitaxial diode costs
too much in efficiency.
Bridge converters
The circuit shown in Fig. 6 at first glance looks attractive.
Parasitic diodes are arranged never to come on, and thus
do not cause switching losses themselves. Also, the choke
voltage drop is less than in the forward case, which may
indicate that the MOSFETs can be used without extra
overwinds to protect the gate voltage.
However, the simple drive waveforms used here, which are
naturally synchronised to the primary switches, do not bias
the rectifying transistors on when both the switches are off.
During this time the transformer magnetising currents need
a path to freewheel around. Normally this path is provided
by the diodes. When the drive has been removed in the
circuit example of Fig. 6, this path no longer exists. To turn
the transistor around so that their body diode can conduct
during this freewheel time would only give diode turn-off
loss, which is what the technique is intended to avoid. Any
bypass diode has the same drawback. The correct drive
waveformsare not even availablefromthe choke. They can
be generated most easily in conjunction with the primary
switch waveforms, but involves expensive isolating drive
toroids.
The conclusions on which converters are most suitable,
andhowtoconnect theMOSFETs inthemost cost-effective
manner for a 12V output are:-
• A flyback MOSFET rectifier can be connected with no
extra components.
• A forward MOSFET needs one overwind, maybe two.
• Abridge output requires drive toroids whose signal is not
easily derivable from the secondary side waveforms.
Fig. 6 Half-Bridge converter with Synchronous
Rectification.
157
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Even though MOSFETs may have less switching loss than
epitaxial diodes, they dohavecapacitancedischargedeach
cycle. The only consolation is that it has a built-in
’anti-snap-off’ feature. If the rectifiers are switching at low
V
DS
then this loss is indeed very low.
Influence of R.F.I. on the choice of
converter
This section deals with R.F.I. considerations of primary
switches and secondary rectifying diodes only. The
techniques will be applied to a power supply operating at
500kHz that has been developed to deliver a single 5V
output at 15A, from 250V a.c. mains input. The converter
choice is a half bridge circuit to minimise the loss in the
circuit due to C
OSS
.
Asingle heatsink arrangement is required to minimise size,
so primary and secondary semiconductors need to be
thermallycooledonthe sameheatsink. R.F.I. currentsneed
tobepreventedfromcouplingprimarytosecondarythrough
the heatsink. Connection of R.F.I. screens underneath all
components attached to the metal is not necessary when
the structure of the semiconductors is understood.
Taking the rectifiers first:-
The arrangement of the output bridge is shown in Fig. 7.
The cathodes of the diodes are connected to the substrate
within their encapsulation. Thus, as long as the cathodes
are connected as close as possible to the ceramic
capacitor, C3, of the output filter, the common
cathode/capacitor junction is a solid a.c. earth point.
Therefore, no R.F.I. currents are connected into the
common heatsink. An isolated encapsulation for an
electrical arrangement such as this is all that is needed to
minimise R.F.I. from diodes to heatsink.
Considering next the primary power transistors:-
The arrangement of power transistors is also shown in
Fig. 7. The drains of the transistors are connected to the
substrates of their encapsulations. Thus, as long as TR1 is
connected as close as possible to the film-foil bridge
capacitors, C1 and C2, the common drain/capacitor
junction is a solid a.c. earth point. A SOT-186, SOT-186A,
SOT-199 or TO-220 with mica washers may be suitable for
TR1, the final selection being dependent on the isolation
requirements. For TR2, the drain and therefore the
substrate is modulated by the action of the circuit. Thus,
without preventive action, R.F.I. currents will be coupled to
the heatsink.
Fig. 7 Half-Bridge converter power stage.
The transistor TR2 is in asimilar situation to onein a flyback
or forward configuration. A simple solution is to use a
SOT-186 (F-pack), plus copper screen connected to the
transistor source lead and the film-foil capacitor, C2, plus
whatever degree of isolation is required to the heatsink.
This assembly was tested, and the result was that the
screen reduced the line R.F.I. peaks by an average of 10dB
over the range 500kHz to 10MHz. A small percentage of
this can be attributed to the distance that the copper screen
movesthe substrate away fromthe heatsink. Nevertheless,
themajority isduetothe inclusionof the0.1mmthick copper
screen.
The conclusion is that a variety of encapsulations is
necessary to allow R.F.I. to be minimised when the power
supply is constructed.
Conclusions
This paper shows how to calculate some of the limiting
parameters in the application of semiconductors to high
frequency SMPS. It also highlights new encapsulations
developed for high frequency power conversion
applications. Some of the range of encapsulations were
demonstrated in a 500kHz half-bridge off-line switcher.
References
1. Improved ferrite materials and core outlines for high
frequency power supplies. Chapter 2.4.1
2. PowerMOS introduction. Chapter 1.2.1
158
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Output Rectification
159
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
2.2.1 Fast Recovery Epitaxial Diodes for use in High Frequency
Rectification
In the world of switched-mode power supply (S.M.P.S.)
design, one of the most pronounced advances in recent
years has been the implementation of ever increasing
switching frequencies. The advantages include improved
efficiency and an overall reduction in size, obtained by the
shrinkingvolume of the magnetics andfiltering components
when operated at higher frequencies.
Developments in switching speeds and efficiency of the
active switching power devices such as bipolars,
Darlingtons and especially power MOSFETs, have meant
that switching frequencies of 100kHzare nowtypical. Some
manufacturers are presently designing p.w.m. versions at
up to 500kHz, with resonant mode topologies (currently an
area of intensive academic research) allowing frequencies
of 1MHz and above to be achievable.
These changes have further increased demands on the
other fundamental power semiconductor device within the
S.M.P.S. - the power rectification diode.
Key Rectifier Characteristics.
In the requirements for efficient high frequency S.M.P.S.
rectification, the diode has to meet the following critical
requirements:-
- Short reverse recovery time, t
rr
,for compatibility with high
frequency use.
- Low forward voltage drop, V
F
, to maximise overall
converter efficiency.
- Low loss switching characteristics, which reduce the
major frequency dependent loss in the diode.
- A soft reverse recovery waveform, with a low dI
R
/dt rate,
reduces the generation of unwanted R.F.I. within the
supply.
The Philips range of fast recovery epitaxial diodes (FREDs)
has been developed to meet the requirements of high
frequency, high power rectification. With many years’
experience in the development of epitaxial device
technology, Philips offers a comprehensive range of
FREDs. Some of their standard characteristics include:-
- Areverse blocking voltage range from100Vto 800V, and
forward current handling capability from1Ato 30A. Thus,
they are compatible for use in a wide range of S.M.P.S.
applications, from low voltage dc/dc converters right
through to off-line ac/dc supplies. Philips epitaxial diodes
are compatible with a range of output voltages from 10V
to 200V, with the capability of supplying a large range of
output powers. Several different package outlines are
also available, offering the engineer flexibility in design.
- Very fast reverse recovery time, t
rr
, as low as 20ns,
coupled with inherent low switching losses permits the
diode to be switched at frequencies up to 1MHz.
- Low V
F
values, typically 0.8V, produce smaller on-state
diode loss and increased S.M.P.S. efficiency. This is
particularly important for low output voltage
requirements.
- Soft recovery is assured with the whole range of FREDs,
resulting in minimal R.F.I. generation.
Structure of the power diode
All silicon power diodes consist of some type of P-I-N
structure, made up of a highly doped P type region on one
side, and a highly doped N+ type on the other, both
separated by a near intrinsic middle region called the base.
The properties of this base region such as width, doping
levels and recombination lifetime determine the most
important diode characteristics, such as reverse blocking
voltage capability, on-state voltage drop V
F
, and switching
speed, all critical for efficient high frequency rectification.

(a) (b) (c) (d)
Fig. 1 Main steps in epitaxial diode process.
n
Epitaxial layer
Wafer
n+
n
n+
p
p-diffusion
n
n+
p
Full mesa passivation
n
n+
p metal glass
metal
161
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
A high blocking voltage requires a wide lightly doped base,
whereas a lowV
F
needs a narrowbase. Using a short base
recombination lifetime produces faster recovery times, but
this also increases V
F
. Furthermore, in any P-N junction
rectifier operating at high currents, carrier injection into the
base takes place from both the P and N+ regions, helping
to maintain a low V
F
.
Technology
High voltage power diodes are usually manufactured using
either double-diffused or an epitaxial technology. High
injectionefficiency intothe basecoupledwithanarrowbase
width are essential for achieving a low V
F
. High injection
efficiency requires the slope of the diffusion profile at the
P
+
N and N
+
N junctions to be very steep. Achieving a
minimumbase width requires very tight control of the lightly
doped base layer. Both these criteria can be met using
epitaxial technology.
Epitaxial process
The epitaxial method involves growing a very lightly doped
layer of silicon onto a highly doped N+ type wafer; see
Fig. 1(a). A very shallow P type diffusion into the epi layer
is then made to produce the required P-I-N structure
(Fig. 1(b)). This gives accuratecontrol of thebase thickness
such that very narrow widths may be produced. Abrupt
junction transitions are also obtained, thus providing for the
required high carrier injection efficiency. The tighter control
of width and junction profile also provides a tighter control
of Q
s
, hence, the switching recovery times are typically ten
times faster than double diffused types.
Fig. 2 Comparison of diffusion profiles.
(a) fast recovery epitaxial diode
(b) standard double diffused type
Double-diffused process
Double diffusion requires deep diffusions of the P+ and N+
regions into a slice of lightly doped silicon, to produce the
required base width. This method is fraught with tolerance
problems, resulting in poor control of the base region. The
junction transitions are also very gentle, producing a poor
carrier injection efficiency. The combination of the two
producesahigher V
F
value, andalsoapoor control of stored
charge Q
s
in the base, leading to a relatively slowswitching
speed.
Figure 2 gives a comparison of the diffusion profiles for the
two methods.
Lifetime control
To achieve the very fast recovery time and low stored
charge, Q
s
, required for high frequency rectification, it is
necessary to introduce lifetime killing (gold doping) into the
base of the diode. This produces a lower Q
s
and faster
reverse recovery time, t
rr
. Unfortunately, doping also has
the effect of increasing V
F
. Fig. 3 shows a graph of
normalised V
F
versus the minority carrier lifetime for a 200V
and 500V device. It can be seen that there is an optimum
lifetime for each voltage grade, below which the V
F
increases dramatically.
Philips has been using gold-killing techniques for well over
twenty years, and combining this with epitaxial technology
results inthe excellent lowV
F
, t
rr
and Q
s
combinations found
in the FRED range.
Fig. 3 Normalised V
F
versus minority carrier lifetime.
Passivation
To ensure that the maximum reverse blocking potential of
the diode is achieved, it is necessary to ensure that high
fields do not occur around the edges of the chip. This is
achieved by etching a trough in the epitaxial layer and
depositing a special glass into it (Fig. 1(c)). Known as full
mesaglass passivation, it achieves stable reverse blocking
characteristics at high voltages by reducing charge
build-up, and produces a strong chip edge, reducing the
risk of assembly damage. This means that the diodes are
rugged and reliable, and also allows all devices to be fully
tested on-slice.
200V
500V
*
*
100 10
minority carrier lifetime (nsec)
1.0
n
o
r
m
a
l
i
s
e
d

V
f
i
n
c
r
e
a
s
i
n
g
Depth
Doping
density
p
n
n+
Epitaxial
device
(a)
Depth
Doping
density
p
n
n+
Double
diffused
type
(b)
162
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Finally, Fig. 1(d) shows the chip after it has been diced and
metallised. The rectifier is then assembled into a wide
selectionof different power packages, thestandardTO-220
outline being one example.
Characteristics
Forward conduction loss
Forward conduction loss is normally the major component
of power loss in the output rectification diodes of an
S.M.P.S. For all buck derived output stages, for example
the forward converter shown in Fig. 4, the choke current
always flows in one or other of the output diodes (D1 and
D2).
Fig. 4 Forward converter schematic.
The output voltage is always lowered by the diode forward
voltage drop V
F
such that:-
Where D is the transistor duty cycle. Thus, the resulting
power loss due to V
F
of the output rectifiers is:-
where I
o
is the output load current of the converter. The loss
as a percentage of the output power is thus:-
This loss in efficiency for a range of standard S.M.P.S.
outputs is shown in Fig. 5. It is clear that V
f
needs to be kept
to an absolute minimum particularly for lowoutput voltages
if reasonable efficiency is to be achieved.
To accommodate variations in the input voltage, the output
rectifiers areusually chosensuch that their blocking voltage
capability is between 4 and 8 times the output voltage. For
the lowest output voltages, Schottky diodes should be the
first choice. Unfortunately, the characteristically low V
f
of
the Schottky cannot be maintained at voltages much higher
than 100V. For outputs above 24V, fast recovery epitaxial
diodes are the most suitable rectifiers.
Fig. 5 Percentage S.M.P.S. loss versus V
F
for some
standard output voltages.
Figure 6 shows an example of V
F
versus forward current I
F
for the Philips BYV32 series, rated from 50V to 200V and
with a maximumoutput current of 20A. This reveals the low
V
F
values typical of the epitaxial technique.
From Fig. 6 and equation 2, it is possible to estimate the
loss due to the output rectifiers in an S.M.P.S. For example,
for a 12V, 20A output, a conduction loss of 17Wtypical and
20W maximum is obtained. This corresponds to a worst
case loss of 8% of total output power, normally an
acceptable figure.
Philips devices offer some of the lowest V
F
values on the
market. Maximum as well as typical values are always
quotedat full rated currents in the datasheets. However this
is not the case with all manufacturers, and care should be
taken when comparing Philips devices with those of other
manufacturers.
V
f
I
o
V
o
I
o
·
V
f
V
o
(3)
C1
TR1
D1
D2
D3
L1
C2
prim
sec
Vi
Vo
Vp
Vs
Ip
Is
drive
Simple forward converter circuit
0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
100
10
1
Diode forward voltage Vf (volts)
P
e
r
c
e
n
t
a
g
e
(
%
)

l
o
s
s
5 V
O/P
10 V
12 V
20 V
24 V
48 V
Vs
time
I
I
D1
D2
time
time
Secondary voltage and diode current waveforms
reverse recovery
spike
at Vin max
at Vin min
Typ
5 x Vo
T
V
o
+ V
f
· V
s
D (1)
P
on
loss · V
f
I
o
(2)
163
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
- - - - 150˚C, 25˚C
Fig. 6 V
F
vs I
F
for the Philips BYV32 series.
Reverse recovery
a) Q
S
, t
rr
and I
rrm
FollowingV
F
, themost important featureof ahighfrequency
rectifier is the reverse recovery characteristic. This affects
S.M.P.S. performance in several ways. These include
increaseddiode switching loss, higher peak turn-on current
and dissipation in the power transistors, and increased
generation of electro-magnetic interference (e.m.i.) and
voltage transient oscillations in the outputs. Clearly, the
rectifier must have optimum reverse recovery
characteristics to keep this catalogue of effects to a
minimum.
WhentheP-Ndiodeisconductingforward current, acharge
is built up in the base region, consisting of both electrons
and holes. It is the presence of this charge which is the key
to achieving low V
f
. The higher the forward current, the
greater is this stored charge. In order to commutate the
diode (i.e switch the device from forward conduction into
reverseblocking mode) this chargehas tobe removed from
the diode before the base can sustain any reverse blocking
voltage. The removal of this charge manifests itself as a
substantial transient reverse current spike, which can also
generatea reverse voltage overshoot oscillation across the
diode.
The waveforms of the reverse recovery for a fast rectifier
areshown inFig. 7. The rectifier isswitched fromitsforward
conduction at a particular rate, called dI
F
/dt. Stored charge
begins to be extracted after the current passes through
zero, and an excess reverse current flows. At this point the
charge is being removed by both the forcing action of the
circuit, and recombination within the device (dependent
upon the base characteristics and doping levels).
At some point the charge has fallen to a low enough level
for adepletion regionto be supported across the base, thus
allowing the diode to support reverse voltage. The peak of
reverse current, I
rrm
occurs just after this point. The time for
the current to pass through zero to its peak reverse value
is called t
a
. From then on, the rectifier is in blocking mode,
and the reverse current then falls back to zero, as the
remainder of the stored charge is removed mostly by
recombination. The time for the peak reverse current to fall
from its maximum to 10% of this value is called t
b
.
Fig. 7 Rectifier diode reverse recovery waveforms.
The stored charge, Q
s
, is the area under the current-time
curve and is normally quoted in nano-Coulombs. The sum
of t
a
and t
b
is called the rectifier reverse recovery time, t
rr
and gives a measure of the switching speed of the rectifier.
Factors influencing reverse recovery
In practice, the three major parameters t
rr
, Q
s
and I
rrm
are
all dependent upon the operating condition of the rectifier.
This is summarised as follows:-
• Increasing the forward current, I
F
, increases t
rr
, Q
s
and
I
rrm
.
• Increasing the dI
F
/dt rate by using a faster transistor and
reducing stray inductance, significantly decreases t
rr
, but
increases Q
s
and I
rrm
. High dI
F
/dt rates occur in the high
frequency square wave switching found in S.M.P.S.
applications. (MOSFETs can produce very small fall
times, resulting in very fast dI
F
/dt).
• Increasing diode junction temperature, T
j
increases all
three.
• Reducing the reverse voltage across the diode, V
r
, also
slightly increases all three.
If
If
dIf
dt
Qs
t
trr
10%
dIr
dt
Vf
V
RM
I
RRM
current
voltage
V
R
0
I
R
ta tb
164
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Specifying reverse recovery
Presently, all manufacturers universally quote the t
rr
figure
as a guide. This figure is obtained using fixed test
procedures. There are two standard test methods normally
used:-
Method 1
Referring to the waveform of Fig. 7:
I
F
= 1A; dI
F
/dt =50A/µsec; V
r
> 30V; T
j
= 25˚C.
t
rr
is measured to 10% of I
rrm
.
Fig. 8 E.I.A. t
rr
test procedure.
Method 2
I
F
= 0.5A, the reverse current is clamped to 1A and t
rr
is
measured to 0.25A.
This is the Electronics Industries Association (E.I.A.) test
procedure, and is outlined in Fig. 8.
The first and more stringent test is the one used by Philips.
The second method, used by the majority of competitors
will give a t
rr
figure typically 30%lower than the first, i.e. will
make the devices look faster. Even so, Philips have the
best t
rr
/ Q
s
devices available on the market. For example,
the Philips BYW29 200V, 8A device has a t
rr
of 25ns, the
competitor devicesquote 35nsusingtheeasier secondtest.
This figure would be even higher using test method 1.
Reverse recovery is specified in data by Philips in terms of
all three parameters t
rr
, Q
s
and I
rrm
. Each of these
parameters however is dependent on exact circuit
conditions. A set of characteristics is therefore provided
showing how each varies as a function of dI
f
/dt, forward
current and temperature, Fig. 9. These curves enable
engineers to realise what the precise reverse recovery
performance will be under circuit operating conditions. This
performance will normally be worse than indicated by the
quoted figures, which generally speaking do not reflect
circuit conditions. For example, a BYW29 is quoted as
having a t
rr
of 25 ns but from the curves it may be as high
as 90 ns when operated at full current and high dI
F
/dt.
Similarly aquotedQ
s
of 11 nCcompareswith thefull current
worst case of 170 nC.
In the higher voltage devices (500V and 800Vtypes) t
rr
and
Q
s
are much higher, and will probably be the most critical
parameters in the rectification process. Care must be taken
to ensure that actual operating conditions are used when
estimating more realistic values.
Frequency range
Figure 10 compares the recovery of a Philips 200V FRED
with a double diffused type. The FRED may be switched
approximately10times faster thanthedoublediffusedtype.
This allows frequencies of up to 1MHz to be achieved with
the 200V range.
If
0.5A
1.0A
I
R
0
0.25A
t
RR
clamped I
R
time
Fig. 9 Reverse recovery curves for BYW29.
1 10 10
2
1
10
10
2
10
3
Tj = 25 C Tj = 100 C
trr
(ns)
(a) Maximum trr
If=10A
5A 1A
1A
5A 10A
dIf/dt (A/us)
1 10 10
2
1
10
10
2
10
3
Qs
(nC)
If=10A
5A
2A
10A
5A
2A
1A
Tj = 25 C Tj = 100 C
dIf/dt (A/us)
(b) Maximum Qs
1 10 10
2
Tj = 25 C Tj = 100 C
10
1
0.1
0.01
I
RRM
(A)
(c) Maximumm I
RRM
If=10A
5A
2A 1A
1A
2A
5A
10A
dIf/dt (A/us)
165
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
In the higher voltage devices where the base width is
increased to sustain the reverse voltage, the amount of
stored charge increases, as does the t
rr
. For a 500Vdevice,
500kHzoperationispossible, andfor 800Vtypically 200kHz
is realistic.
Fig. 10 Comparison of reverse recovery of FRED vs
double diffused.
(a) Philips 200V FRED.
(b) Double-diffused diode.
Effects on S.M.P.S operation
In order to analyse the effects of reverse recovery on the
power supply, a simple non-isolated buck converter shown
in Fig. 11 is considered. The rectifier D1 in this application
is used in freewheel mode, and conducts forward current
during the transistor off-time.
Fig. 11 Buck converter.
The waveforms for the diode and transistor switch during
the reverse recovery of the diode when the transistor turns
on again are given in Fig. 12.
As the transistor turns on, the current ramps up in the
transistor as it decays and reverses in the diode. The dI
F
/dt
is mainly dependent on the transistor fall time and, to some
extent, the circuit parasitic inductances. During the period
t
a
the diode has no blocking capability and therefore the
transistor must support the supply voltage. The transistor
thus simultaneously supports a high voltage and conducts
both the load current and the reverse recovery current,
implying a high internal power dissipation. After time t
a
the
diode blocking capability is restored and the voltage across
the transistor begins to fall. It is clear that a diode with an
I
rrm
half the value of I
F
will effectively double the peak power
dissipation in the transistor at turn-on. In severe cases
where a high I
rrm
/ t
rr
rectifier is used, transistor failure could
occur by exceeding the peak current or power dissipation
rating of the device.
Fig. 12 Reverse recovery diode and transistor
waveforms.
There is also an additional loss in the diode to be
considered. This is a product of the peak I
rrm
and the diode
reverse voltage, V
r
. The duration of current recovery to zero
will affect themagnitude of the diodeloss. However, inmost
cases the additional transistor loss is much greater than the
diode loss.
Diode loss calculation
As an example of the typical loss in the diode, consider the
BYW29, 8A, 200V device as the buck freewheel diode, for
the following conditions:-
I
F
= 8A; V
r
=100V; dI
F
/dt = 50A/µs;
T
j
= 25˚C; duty ratio D = 0.5; f = 100KHz.
The diode reverse recovery loss is given by:-
Fromthe curves of Fig. 7, t
rr
=35ns, I
rrm
= 1.5A. Assuming t
b
= t
rr
/2 gives:
(A)
(B)
1A/div
50ns/div
0A
0A
Irrm
t
t
t
t
Transistor
switch
waveforms
Transistor
loss
Diode
waveforms
Diode
loss
Vsw
Isw
Psw
Id
Vd
Pd
0
0
0
0
additional
turn-on
loss
diode
reverse recovery
loss
ta tb
trr
Vin Vo
L1
D1
Co
TR1
P
rr
·
1
2
⋅ V
r
⋅ I
rrm
⋅ t
b
⋅ f
P
rr
·
1
2
⋅ 100 ⋅ 1.5 ⋅ 17.5 ⋅ 100k · 132mW
166
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
This is still small compared to the diode V
F
conduction loss
of approximately 3.6 W. However, at T
j
=100˚C,
dI
F
/dt=100A/µs and f=200kHz, the loss becomes 1.05W,
which is fairly significant. In the higher voltage devices
where t
rr
and I
rrm
are significantly worse, then the frequency
dependent switching loss will tend to dominate, and can be
higher than the conduction loss. This will limit the upper
frequency of operation of the diode.
The turn-on current spike generated in the primary circuits
due to diode reverse recovery can also seriously affect the
control of the S.M.P.S. when current mode control is used
(where the peak current is sensed). An RC snubber is
usually required to remove the spike fromthe sense inputs.
Good reverse recovery removes the need for these
additional components.
b) Softness and dI
R
/dt
When considering the reverse recovery characteristics, it
is not just the magnitude (t
rr
and I
rrm
) which is important, but
also the shape of the recovery waveform. The rate at which
the peak reverse current I
rrm
falls to zero during time t
b
is
also important. The maximum rate of this slope is called
dI
R
/dt and is especially significant. If this slope is very fast,
it will generate significant radiated and conducted electrical
noise in the supply, causing R.F.I. problems. It will also
generate high transient voltages across circuit inductances
in series with the diode, which in severe cases may cause
damage to the diode or the transistor switch by exceeding
breakdown limits.
Fig. 13 "Soft" and "snappy" reverse recovery.
A diode which exhibits an extremely fast dI
R
/dt is said to
have a "snap-off" or "abrupt" recovery, and one which
returns at a relatively smooth, gentle rate to zero is said to
have a soft recovery. These two cases are shown in the
waveforms in Fig. 13. The softness is dependent upon
whether there is enough charge left in the base, after the
full spread of the depletion region in blocking mode, to allow
the current to return to zero smoothly. It is mainly by the
recombination mechanism that this remaining charge is
removed during t
b
.
Maintaining t
b
at a minimum would obviously give some
reduction to the diode internal loss. However, a snappy
rectifier will produce far more R.F.I. and transient voltages.
The power saving must therefore be weighed against the
additional cost of the snubbers and filtering which would
otherwise be required if the rectifier had a snappy
characteristic.
The frequency range of R.F.I. generated by dI
R
/dt typically
lies in the range of 1MHz to 30MHz, the magnitude being
dependent upon how abrupt the device is. One secondary
effect that is rarely mentioned is the additional transformer
losses that will occur due to the extremely high frequencies
generated inside it by the diode recovery waveform. For
example, core loss at 10MHz for a material designed to
operate at 100kHz can be significant. There will also be
additional high frequency loss in the windings due to the
skin effect. In this case the use of a soft device which
generates a lower frequency noise range will reduce these
losses.
Characterising softness
A method currently used by some manufacturers to
characterise the softness of a device is called the softness
factor, S. This is defined as the ratio of t
b
over t
a
.
An abrupt device would have S much less than 1, and a
soft device would have S greater than 1. A compromise
between R.F.I. and diode loss is usually required, and a
softness factor equal to 1 would be the most suitable value
for a fast epitaxial diode.
Fig. 14 Different diode dI
R
/dt rates for same softness
factor.
Although the softness factor does give a rough guide to the
type of recovery and helps in the calculation of the diode
switching loss, it does not give the designer any real idea
of the dI
R
/dt that the rectifier will produce. Hence, levels of
R.F.I. and overvoltages could be different for devices with
the same softness factor. This is shown in Fig. 14, where
the three characteristics have the same softness factor but
completely different dI
R
/dt rates.
In practice, a suitable level for dI
R
/dt would be to have it
very similar in magnitude to dI
F
/dt. This would keep the
noise generated to a minimum.
softness factor, S ·
t
b
t
a
t t
Irrm
Irrm
Snap-off
recovery
soft
recovery
(a) (b)
I I
ta tb ta tb ta tb
(a) (b)
(c)
167
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
At present there is no universal procedure used by
manufacturers to characterise softness, and so any figures
quoted must be viewed closely to check the conditions of
the test.
Comparison with competitor devices
Figure15compares aBYV32 with anequivalent competitor
device. This test was carried out using an L.E.M. Q
s
test
unit.
The conditions for each diode were identical. The results
were as follows:-
Fig. 15 Comparison of softness of reverse recovery.
(a) Philips BYV32 200V 8A device
(b) Equivalent competitor device
BYV32:- S = 1.2, dI
R
/dt = 40A/µs,
Voltage overshoot = 5V
Competitor:- S = 0.34, dI
R
/dt = 200A/µs,
Voltage overshoot = 22V
For the Philips device, apart from the very low Q
s
and I
rrm
values obtained, the S factor was near 1 and the dI
R
/dt rate
was less than the original dI
F
/dt of 50A/µs. These excellent
parameters produce minimal noise and the very small
overshoot voltageshown. The competitor device was much
snappier, the dI
R
/dt was 4 times the original dI
F
/dt, and
caused a much more severe overshoot voltage with the
associated greater R.F.I. The diode loss is also higher in
the competitor device even though it is more abrupt, since
Q
s
and I
rrm
are larger.
The lowQ
s
of the Philips FRED range thus maintains diode
loss to a minimum while providing very soft recovery. This
means using a Philips type will significantly reduce R.F.I.
and dangerous voltage transients, and in many cases
reducethe power supply component count by removing the
need for diode snubbers.
Forward recovery
A further diode characteristic which can affect S.M.P.S.
operation is the forward recovery voltage V
fr
. Although this
is not normally as important as the reverse recovery effects
in rectification, it can be particularly critical in some special
applications.
Fig. 16 Forward recovery characteristics.
I
V
20ns/div
(a)
If =8A
Tj = 25 C
Vr = 30V
1A/div
10V/div
dIf/dt = 50A/usec
V
I
1A/div
10V/div
20ns/div
(b)
If = 8A
Tj = 25 C
Vr = 30V
dIf/dt = 50A/usec
10%
90%
If
tr
100% 110%
t
fr
Vf
t
t
0
0
Vfrm
168
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Forward recovery is caused by the lack of minority carriers
in the rectifier p-n junction during diode turn-on. At the
instant a forward bias is applied, there are no carriers
present at the junction. This means that at the start of
conduction, the diode impedance is high, and an initial
forward voltage overshoot will occur. As the current flows
and charge builds up, conductivity modulation (minority
carrier injection) takes place. The impedance of the rectifier
falls and hence, the forward voltage drop falls rapidly back
to the steady state value.
The peak value of the forward voltage is known as the
forward recovery voltage, V
frm.
The time from the forward
current reaching 10% of the steady state value to the time
the forward voltage falls to within 10% of the final steady
state value is known as the forward recovery time (Fig. 16).
The magnitude and duration of the forward recovery is
normally dependent upon the device and the way it is
commutatedinthe circuit. Highvoltagedevices will produce
larger V
frm
values, since the base width and resistivity
(impedance) is greater.
The main operating conditions which affect V
fr
are:-
• I
f
; high forward current, which produces higher V
fr
.
• Current rise time, t
r
; a fast rise time produces higher V
fr
.
Effects on s.m.p.s.
The rate of rise in forward current in the diode is normally
controlled by the switching speed of the power transistor.
When the transistor is turned off, the voltage across it rises,
and the reverse voltage bias across the associated rectifier
falls. Once the diode becomes forward biased there is a
delay before conduction is observed. During this time, the
transistor voltage overshoots the d.c supply voltage while
it is still conducting a high current. This can result in the
failure of the transistor in extreme cases if the voltage
limiting value is exceeded. If not, it will simply add to the
transistor and diode dissipation. Waveforms showing this
effect are given in Fig. 17.
Fig. 17 Forward recovery effect on transistor voltage.
Table 1 outlines typical V
frm
values specified for rectifiers of
different voltagerating. This shows the relatively lowvalues
obtained. No comparable data for any of the competitor
devices could be found in their datasheets. It should be
noted that in most S.M.P.S. rectifier applications, forward
recovery canbe considered the least important factor in the
selection of the rectifier.
Device V
BR
I
f
dI
f
/dt typ V
frm
type (Volts) (Amps) (A/µs) (Volts)
BYW29 200 1.0 10 0.9
BYV29 500 10 10 2.5
BYR29 800 10 10 5.0
Table 1. V
frm
values for different Philips devices.
Reverse leakage current
When a P-N junction is reverse biased, there is always an
inherent reverse leakage current that flows. In any piece of
undoped semiconductor material there is a thermally
generated background level of electron and hole pairs.
These pairs also naturally recombine, such that an
equilibrium is established. In a p-n junction under reverse
voltage conditions, the electric field generated will sweep
someof the free carriers generated out of the device before
they can recombine, hence causing a leakage current. This
phenomenon is shown in Fig. 18.
Fig. 18 Clarification of reverse leakage current.
When the rectifier base is gold doped to decrease Q
s
and
t
rr
, a new energy level is introduced very close to the centre
of the semiconductor energy band gap. This provides lower
energy transition paths as shown, and thermal generation
P N
Vr
e
_
h
+
Ir
distance
E
applied
electric field
intensity
Econduction
Evalence
Ei
transition
transition
recombination centre added
1.1eV
lower energy
lower energy
p-n junction
due to doping
Vswitch
Vswitch
Iswitch
0 time
Idiode
switch off
diode
conducts
diode
forward biased
169
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
(andrecombination) of hole-electronpairsis morefrequent.
Thus, the reverseleakagecurrent isgreater still inthekilled,
fast rectifier.
Since the pairs are generated thermally, it is obvious that
raising the junction temperature will increase the leakage
significantly. For example, the leakage current of a FRED
can increase by up to 20 times by raising the junction
temperature, T
j
from 25˚C to 100˚C. This increase can be
far greater in other diode technologies.
Many S.M.P.S. designers have a misconception about
leakagecurrent, and believethat it renders the rectifier poor
quality, giving high losses, and is unreliable. This is not so.
Leakage is a naturally occurring effect, and is present in all
rectifiers. The leakage in an S.M.P.S. diode is normally
extremely small and stable, with very little effect on the
rectification process. Some manufacturers have
over-emphasised the benefits of very lowleakage devices,
claiming that they have great advantages. However, this
will be shown to be groundless, since any reduction in the
overall diode power loss will be minimal.
In practice, the reverse leakage current only becomes
significant at highoperatingtemperatures(above75˚C) and
for high reverse blocking voltages (above 500V), where the
product of reverse voltage and leakage current (hence,
power loss) is higher. Even then, the leakage current is still
usually lower than 1mA.
Table 2 lists the maximumleakage currents for some of the
devices from the Philips range (gold killed), revealing low
levels, even inthehigher voltagedevices, achievedthrough
optimised doping.
Device V
BR(max)
max I
r
(mA) max I
r
(µA)
type (Volts) T
j
=100˚C T
j
=25˚C
full V
rrm
full V
rrm
BYW29 200 0.6 10
BYV29 500 0.35 10
BYR29 800 0.2 10
Table 2. Maximum reverse leakage currents for Philips
devices.
The power dissipation due to leakage is a static loss and
depends on the product of the reverse voltage and the
leakage current over a switching cycle. A worst case
example is given below where the data sheet leakage
current maximum is used at maximum reverse blocking
voltage of the diode.
S.M.P.S example:-Flyback converter
Consider first the BYV29-500 as the output rectifier in the
discontinuous flyback converter (Note: the reverseblocking
occurs during the transistor on time, and a minimum duty
of 0.25 has been assumed.) The BYV29-500 could
generate a possible maximum output voltage of 125V. The
maximum leakage power loss is:-
Alternatively, for the BYR29-800, maximumrectified output
is approximately 200V, and by similar calculations, its
maximumloss is 40mW. Lower output voltages would give
leakage losses lower than this figure.
These types of calculation can be carried out for other
topologies, when similar low values are obtained.
Conclusion
Philips produces a comprehensive range of Fast Recovery
Epitaxial Diodes. The devices have been designed to
exhibit the lowest possible V
f
while minimising the major
reverse recovery parameters, Q
s
, t
rr
and I
rrm
. Because of the
low Q
s
, switching losses within the circuit are minimised,
allowing use up to very high frequencies. The soft recovery
characteristic engineered into all devices makes them
suitable for use in today’s applications where low R.F.I. is
an important consideration. Soft recovery also provides
additional benefits such as reduced high frequency losses
in the transformer core and, in some cases, the removal of
snubbing components.
P
L
· 500V⋅ 0.35mA⋅ 0.25 · 43.75mW
170
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
FRED Selection Guide
Single Diodes
Type Number Outline I
F(AV)
max Voltage Grades
Amps 100 150 200 300 400 500 600 700 800
BYW29E TO-220AC 8 * * *
BYV29 TO-220AC 9 * * *
BYR29 TO-220AC 8 * * * *
BYV79E TO-220AC 14 * * *
BYT79 TO-220AC 14 * * *
Dual Diodes (Common cathode)
Type Number Outline I
O
max Voltage Grades
Amps 100 150 200 300 400 500 600 700 800
BYV40 SOT-223 1.5 * * *
BYQ27 SOT-82 10 * * *
BYQ28E TO-220AB 10 * * *
BYT28 TO-220AB 10 * * *
BYV32E TO-220AB 20 * * *
BYV34 TO-220AB 20 * * *
BYV42E TO-220AB 30 * * *
BYV72E SOT-93 30 * * *
BYV44 TO-220AB 30 * * *
BYV74 SOT-93 30 * * *
’E’ denotes rugged device.
171
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Single Diodes (Electrically isolated Package)
Type Number Outline I
F(AV)
max Voltage Grades
Amps 100 150 200 300 400 500 600 700 800
BYW29F SOT-186 8 * * *
BYV29F SOT-186 9 * * *
BYR29F SOT-186 8 * * *
Dual Diodes (Electrically Isolated Package)
Type Number Outline I
O
max Voltage Grades
100 150 200 300 400 500 600 700 800
BYQ28F SOT-186 10 * * *
BYV32F SOT-186 12 * * *
BYV72F SOT-199 20 * * *
BYV74F SOT-199 20 * * *
172
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
2.2.2 Schottky Diodes from Philips Semiconductors
The Schottky diodes from Philips have always had good
forward characteristics and excellent switching
performance. With this new, more extensive range of
Schottky diodes come the additional benefits of stable, low
leakage reverse characteristics and unsurpassed levels of
guaranteed ruggedness.
The performance improvements have been achieved by
changing both the design and the processing of Schottky
diode wafers. The changes are the products of the
continuing programme of research in the field of Schottky
barrier technology being carried out at Stockport.
This report will look at the new range, the improvements
that have been made and the changes that have produced
them.
New process
The manufacturing process for all the devices in the new
range includes several changes which have significantly
improved the quality and performance of the product.
Perhaps the most significant change is moving the
production of the Schottky wafers from the bipolar
processing facility into the PowerMOS clean room. The
Schottky diodeis a ’surface’ device - its activeregion is right
at the conductor / semiconductor interface, not deep within
the silicon crystal lattice. This means that it can usefully
exploit the high precision equipments and extremely clean
conditions needed to produce MOS transistors. In some
respects Schottkies have more in common with MOS
transistors than they do with traditional bipolar products. In
one respect they are identical - their quality can be
dramatically improved by:-
- growing purer oxide layers,
- depositing metal onto cleaner silicon,
- more precise control of ion implantation.
Another change has been in the method of producing the
Schottky barrier. The original method was to ’evaporate’
molybdenum onto the surface of the silicon. In the new
process a Pt/Ni layer is ’sputtered’ onto the surface and
then a heat treatment is used to produce a Pt/Ni silicide.
This has the effect of moving the actual conductor /
semiconductor interface a small distance away from the
surface and into the silicon.
The advantage of this change is that it puts the barrier in
an environment where the conditions are more
homogeneous, resulting in a more consistent barrier. This
consistency produces devices in which every part of the
active area has the same reverse characteristic.
Ruggedness
The RUGGEDNESS of a Schottky diode is a measure of
its ability to withstand the surge of power generated by the
reverse current which flows through it when the applied
reverse voltage exceeds its breakdown voltage. Operation
in this mode is, of course, outside the boundaries of normal
operation - it always exceeds the V
RRM
rating of the device.
However, situations can arise where the voltages present
in the circuit far exceed the expectations of the designer. If
devices are damaged by these conditions then the
equipment they are in may fail. Such failures often result in
equipments being condemned as unreliable. In recognition
of this, Philips will now supply devices which operate
reliably during both normal and abnormal operation.
All the Schottky diodes supplied by Philips now have two
guaranteed reverse surge current ratings:-
I
RRM
- guarantees that devices can withstand repetitive
reversecurrent pulses (t
p
=2µs; ∆=0.001) of greater
than the quoted value,
I
RSM
- guarantees that single, 100µs pulses of the rated
value can be applied without damage.
At the moment these ratings are quoted as either 1A or 2A,
depending on device size. It should be understood that
these figures do not represent the limit of device capability.
They do, however, represent the limit of what, experience
suggests, might be needed in most abnormal operational
situations.
In an attempt to determine the actual ruggedness of the
new devices, a series of destructive tests was carried out.
The results shown in Fig. 1 give the measured reverse
ruggednessof different sizes of device. It clearly shows that
even small devices easily survive the 1AI
RRM
/ I
RSM
limit and
that the larger devices can withstand reverse currents
greater than the 85A that the test gear was designed to
deliver.
173
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Fig. 1 Typical reverse ruggedness
Reverse leakage
The reverse characteristic of any diode depends upon two
factors - ’bulk’ and ’edge’ leakage. The first is the current
which leaks through the reverse biased junction in the main
activeareaof the device. The secondisthe leakagethrough
the junction around its periphery - where the junction meets
the outside world. Attention must be paid to both of these
factorsif ahighperformancediodeistobeproduced. During
the development of the new range of Philips Schottky
diodes both of these factors received particular attention.
Bulk leakage
To achieve low forward voltage drop and very fast
switching, Schottky diodes use the rectifying properties of
a conductor / semiconductor interface. The ’height’ of the
potential barrier has a significant effect upon both the
forwardvoltagedropandthe reverseleakage. Highbarriers
raise the V
F
and lower the general reverse leakage level.
Conversely low barrier devices have a lower V
F
but higher
leakage. So the choice of barrier height must result in the
best compromise between leakage and V
F
to produce
devices with the best allround performance.
The height of a Schottky barrier depends, to a large extent,
upon the composition of the materials at the interface. So
the selection of the barrier metal and the process used for
itsdepositionisvery important. Thefinal decisionwasmade
with the help of the extensive research and device
modellingfacilities availablewithin the Philips organisation.
The materials and processes that were selected have
significantly reduced the bulk leakage of the new range of
Schottky diodes. It is believed that this present design gives
the optimum balance between leakage and V
f
that is
currently achievable.
Edge leakage
The other component influencing the reverse characteristic
is edge leakage. In a diffused diode the mechanisms which
operate at the edge of the active area - where the junction
meets the outside world - are different from those which
operate in the centre. The Schottky barrier is the same as
a diffused junction in this respect. The field at the edge of
asimple (untreated inany way) Schottky barrier is very high
and as a consequence the leakage through the junction at
the periphery can also be very high.
In diffused diodes the edge of the junction is treated by
’passivating’ it. In a Schottky diode the edge of the barrier
is treated by implanting a shallow, very low dose, p region
around the periphery of the active area. This region, called
a ’guard ring’, effectively replaces the high field periphery
of the barrier. It is now the characteristics of the guard ring
which determine the edge leakage and not those of the
Schottky barrier.
In this way the mechanisms controlling the two elements
of leakage are now independent and can be adjusted
separately, eliminating the need for compromises. This
freedom, and a combination of good design and the close
tolerance control - achievable with ion implantation -
ensures that the characteristics are excellent, having both
good stability and very low leakage.
Fig. 2 Cross Section of Schottky Diode
Overall leakage
As mentioned earlier, good reverse characteristics rely
upon both the edge and bulk leakages being good. By
eliminating the interactions between the mechanisms and
by concentrating on optimising each, it has been possible
toimproveboth edgeand bulkleakage characteristics. This
has allowed Philips to produce Schottky diodes with typical
room temperature reverse currents as low as 20µA, or
100µA max (PBYR645CT) - considerably lower than was
ever achieved with molybdenum barrier devices.
M
a
x
i
m
u
m

R
e
v
e
r
s
e

R
e
c
o
v
e
r
y

C
u
r
r
e
n
t

(
a
m
p
s
)
100
90
80
70
60
50
40
30
20
10
0
2 3 4 5 6 7 8 9 10 20 30
Data Limit
Test Gear Limit
Active Area of Crystal (mm
2
)
PtNi
Silicide
Guard Ring Oxide
TiAl
174
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Range
The Schottky diode was originally designed to be used as
the rectifier and freewheel diode in the 5V output of high
frequency SMPS. The arrival of the new 100V Schottkies
has now extended this up to 24V outputs. These supplies
are fitted into equipments whose power requirements vary
widely. Satisfying these needs efficiently means that an
equally wide range of supplies has to be produced. In
recognition of this, Philips has produced a range of diode
packages with current ratings from 6A to 30A. With this
range it is possible to produce power supplies of 20W to
500W output - higher powers are achievable with
parallelling.
The full range of Philips Schottky diodes is shown in
Table 1. At the heart of the range are the ’PBYR’ devices.
The numbers and letters following the PBYR prefix are
compatible with industry standards. These figures give an
indication of a device’s structure (single or dual) and its
current and voltage rating. An explanation of the numbers
is given in Table 2. Care has been taken to ensure
compatibility between Philips devices and those fromother
suppliers, which share number/letter suffices. It is hoped
that this will ease the process of equivalent type selection.
Included in the range is a group of devices with ’BYV1xx’
numbers. Thesedevices are aselectionof the most popular
types from the previous Philips Schottky range. They have
proved to be conveniently sized devices which have a mix
of ratings and characteristics not matched by other
manufacturers. Althoughtheseare’old’ numbers, delivered
devices will have been manufactured by the new process
and will therefore be better. However, changing the
production process of established types can often cause
concern amongst customers. Philips has recognised this
and, during the development, took particular care to ensure
that all the new devices would be as closely comparable
as possible with previously delivered product. Clarification
is given in the cross reference guide given in Table 3.
Summary
Thisrange of Schottky diodes enhancestheability of Philips
Components to meet all the requirements and needs of the
SMPS designer. The well established range of epitaxial
diodes, bipolar andPowerMOStransistors, ICs andpassive
components is now complemented by a range of Schottky
diodes with:-
- very low forward voltage drop,
- extremely fast reverse recovery,
- lowleakage reverse characteristics, achieved WITHOUT
compromising overall system efficiency
- stable characteristics at both high and low temperatures
- guaranteed ruggedness, giving reliability under both
normal and abnormal operating conditions.
175
S.M.P.S. Power Semiconductor Applications
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Table 1 Range of Schottky Diodes
Single Diode
Type Number Outline I
F(AV)
(A) I
O
(A) Voltage Grades (V)
per diode per device 35 40 45 60 80 100
PBYR7** TO-220AC 7.5 7.5 * * *
PBYR10** TO-220AC 10 10 * * * * * *
PBYR16** TO-220AC 16 16 * * *
Dual Diodes - Common Cathode
Type Number Outline I
F(AV)
(A) I
O
(A) Voltage Grades (V)
per diode per device 35 40 45 60 80 100
PBYR2**CT SOT-223 1 2 * * *
PBYR6**CT SOT-82 3 6 * * *
BYV118** TO-220AB 5 10 * * *
PBYR15**CT TO-220AB 7.5 15 * * *
BYV133** TO-220AB 10 20 * * *
PBYR20**CT TO-220AB 10 20 * * * * * *
BYV143** TO-220AB 15 30 * * *
PBYR25**CT TO-220AB 15 30 * * *
PBYR30**PT SOT-93 15 30 * * * * * *
Dual Diodes - Common Cathode (Electrically Isolated Package)
Type Number Outline I
F(AV)
(A) I
O
(A) Voltage Grades (V)
per diode per device 35 40 45 60 80 100
BYV118F** SOT-186 (3 leg) 5 10 * * *
PBYR15**CTF SOT-186 (3 leg) 7.5 15 * * *
BYV133F** SOT-186 (3 leg) 10 20 * * *
PBYR20**CTF SOT-186 (3 leg) 10 20 * * *
BYV143F** SOT-186 (3 leg) 15 30 * * *
PBYR25**CTF SOT-186 (3 leg) 15 30 * * *
PBYR30**PTF SOT-199 15 30 * * *
Single Diodes (Electrically Isolated Package)
Type Number Outline I
F(AV)
(A) I
O
(A) Voltage Grades (V)
per diode per device 35 40 45 60 80 100
PBYR7**F SOT-186 (2 leg) 7.5 7.5 * * *
PBYR10**F SOT-186 (2 leg) 10 10 * * *
PBYR16**F SOT-186 (2 leg) 16 16 * * *
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Table 2 ’PBYR’ Types - explanation of the numbering system.
The numerical part of the type number gives information about the current and voltage rating of the devices. The final
two digits are the voltage grade. The number(s) preceding these give an indication of the current rating. This figure must
be used with care. Single and dual devices derive this number in different ways so the data sheet should be consulted
before final selection is made.
Letters after the type number indicate that the device is NOT a single diode package. The codes used by Philips can
be interpreted as follows:-
CT - means that the device is dual and the cathodes of the two diodes are connected together.
PT - means the device is a dual with common cathode but for compatibility reasons ’CT’ cannot be used.
For example
PBYR1645 a device consisting of a single diode with an average current rating (I
F(AV)
) of 16 A and a reverse voltage
capability of 45 V.
Table 3 Cross Reference Guide
Single Diodes
Old Type Intermediate Type New Type
BYV19-** none PBYR7**
none none PBYR10**
BYV39-** none PBYR16**
BYV20-** BYV120-** none
BYV21-** BYV121-** none
BYV22-** withdrawn none
BYV23-** withdrawn none
Dual Diodes - Common Cathode
Old Type Intermediate Type New Type
none none PBYR6**CT
BYV18-** BYV118-** none
BYV33-** BYV133-** PBYR15**CT
none none PBYR20**CT
BYV43-** BYV143-** PBYR25**CT
BYV73-** none PBYR30**PT
FULL PACK Dual Diodes - Common Cathode
Old Type Intermediate Type New Type
none BYV118F-** none
BYV33F-** BYV133F-** PBYR15**CTF
none none PBYR20**CTF
BYV43F-** BYV143F-** PBYR25**CTF
177
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2.2.3 An Introduction to Synchronous Rectifier Circuits using
PowerMOS Transistors
Replacing diodes with very low R
DS(on)
POWERMOS
transistors as the output rectifiers in Switch Mode Power
Supplies operating at high operating frequencies can lead
to significant increases in overall efficiency. However, this
is at the expense of the extra circuitry required for transistor
drive and protection. In applications where efficiency is of
overriding importance (such as high current outputs below
5V) then synchronous rectification becomes viable.
This paper investigates two methods of driving
synchronous rectifiers:-
(i) Using extra transformer windings.
(ii) Self-driven without extra windings.
Multi-output power supplies do not easily lend themselves
toextratransformer windings (althoughthere isusually only
one very low output voltage required in each supply).
Therefore, the self-driven approach is of more interest. If
the additional circuitry and power devices were integrated,
an easy to use, highly efficient rectifier could result.
Introduction.
The voltage drop across the output diode rectifiers during
forward conduction in an SMPSabsorbs a high percentage
of the watts lost inthe power supply. This is amajor problem
for low output voltage applications below 5V (See section
2.2.1). The conduction loss of this component can be
reduced and hence, overall supply efficiency increased by
using very low R
DS(on)
POWERMOS transistors as
synchronous rectifiers (for example, the BUK456-60A).
The cost penalties involved with the additional circuitry
required are usually only justified in the area of high
frequency, low volume supplies with very low output
voltages. The methods used to provide these drive
waveforms have been investigated for various circuit
configurations, in order to assess the suitability of the
POWERMOS as a rectifier.
The main part of the paper describes these circuit
configurations which include flyback, forward andpush-pull
topologies. Tocontrol the synchronous rectifiers they either
use extra windings taken from the power transformer or
self-driven techniques.
The PowerMOS as a synchronous rectifier.
POWERMOS transistors have become more suitable for
low voltage synchronisation for the following reasons:-
(1) The cost of the POWERMOS transistor has fallen
sharply in recent years.
(2) Very lowR
DS(on)
versionswhich yieldvery lowconduction
losses have been developed.
(3) The excellent POWERMOS switching characteristics
and low gate drive requirements make them ideal for high
frequency applications.
(4) Parallellingthe POWERMOSdevices(which is normally
straightforward) will significantly reduce the R
DS(on)
, thus
providing further increases in efficiency. This process is not
possible with rectifier diodes since they have inherent
forward voltage offset levels.
Fig. 1 POWERMOS transistor showing body diode.
Design constraints.
When the POWERMOS transistor shown in Fig. 1 is used
as a synchronous rectifier, the device is configured such
that the current flow is opposite to that for normal operation
i.e. from source to drain. This is to ensure reverse voltage
blocking capability when the transistor is turned off, since
there will be no current path through the parasitic body
diode. This orientation also gives a degree of safety. If the
gate drive is lost, the body diode will then perform the
rectification, albeit at a much reduced efficiency.
Unfortunately, this configuration has limitations in the way
in which it can be driven. The device gate voltage must
always be kept below t 30V. The on-resistance (R
DS(on)
) of
the device must be low enough to ensure that the on-state
voltagedrop isalways lower than theV
f
of the POWERMOS
intrinsic body diode. The gate drive waveforms have to be
derived from the circuit in such a way as to ensure that the
body diode remains off over the full switching period. For
some configurations this will be costly since it can involve
discrete driver I.C.s and isolation techniques.
G
S
D
Intrinsic
body
diode
179
S.M.P.S. Power Semiconductor Applications
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If the body diode were to turn on at any point, it would result
in a significant increase in the POWERMOS conduction
loss. It would also introduce the reverse recovery
characteristic of the body diode, which could seriously
degrade switching performance and limit the maximum
allowable frequency of operation.
It is well known that the R
DS(on)
of the POWERMOS is
temperature dependent and will rise as the device junction
temperature increases during operation. This means that
the transistor conduction loss will also increase, hence,
lowering the rectification efficiency. Therefore, to achieve
optimum efficiency with the synchronous rectifier it is
important that careful design considerations are taken (for
example good heat-sinking) to ensure that the devices will
operate at as low a junction temperature as possible.
Fig. 2 Conventional output rectifier circuits.
Transformer Driven Synchronous
Rectifiers.
The conventional output rectifier circuits for the flyback,
forward and push-pull converters are shown in Fig. 2.
These diodes can be replaced by POWERMOS transistors
which are driven off the transformer as shown in Fig. 3.
These configurations can be summarised as follows:-
(a) Flyback converter - this is very straightforward; the gate
voltagecanbe maintained at below30Vand the body diode
will not come on.
(b) Forward converter - the gate drives for the two
transistors can be maintained below 30V. However, due to
the shape of the transformer waveforms, the freewheel
rectifier will not have a square wave signal and the body
diode could come on.
(c) Push-pull converter - deriving the gate drives for the two
synchronous rectifiers from the transformer means that
during the dead time which occurs in each switching cycle,
both transistors are off. There is nowhere for the circulating
current to go and body diodes will come on to conduct this
current. This is not permissible because of the slow
characteristics of the less than ideal body diode. Therefore,
thepush-pull configuration cannot be used for synchronous
rectification without the costly derivation of complex drive
waveforms.
Fig. 3 Synchronous rectifier circuits with windings.
One significant advantage of using this topology is that the
r.m.s. current of therectifiers and, hence, overall conduction
loss is significantly lower in the push-pull than it is in the
forward or flyback versions.
180
S.M.P.S. Power Semiconductor Applications
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Self-Driven Synchronous Rectifiers.
The disadvantage of the transformer driven POWERMOS
is the requirement for extra windings and extra pins on the
power transformer. This may cause problems, especially
for multi-output supplies. Amethod of driving the transistors
without the extra transformer windings would probably be
more practical. For this reason basic self-driven
synchronous rectifier circuits were investigated.
It should be noted that the following circuits were based
upon an output of 5V at 10A. In practice, applications
requiring lower voltages such as 3 or 3.3 volts at output
currents above 20A will benefit to a far greater extent by
using synchronous rectification. For these conditions the
efficiency gains will be far more significant. However, the
5V output was considered useful as a starting point for an
introductory investigation.
(a) The Flyback converter.
An experimental circuit featuring the flyback converter
self-oscillating power supply was developed. This was
designed to operate at a switching frequency of 40kHz and
delivered 50W (5V at 10A).
Directly substituting the single rectifier diode with the
POWERMOS transistor as is shown in Fig. 4(a) does not
work because the gate will always be held on. The gate is
Vo above the source so the device will not switch.
Therefore, some additional circuitry is required to perform
the switching, and the circuitry used is shown in Fig. 4(b).
The BUK456-60A POWERMOS transistor which features
a typical R
DS(on)
of 24mΩ (at 25˚C) was used as the
synchronous rectifier for these basic configurations.
The drive circuit operates as follows: the pnp transistor
switches on the POWERMOS and the npn switches it off.
Good control of the POWERMOS transistor is possible and
the body diodedoes not come on. The waveforms obtained
are also shown in Fig. 4.
If the small bipolar transistors were replaced by small
POWERMOS devices, then this drive circuit would be a
good candidate for miniaturisation in a Power Integrated
Circuit. This couldprovide goodcontrol withlowdrive power
requirements.
Unfortunately, thesinglerectifier inaflybackconverter must
conduct a much higher r.m.s. current than the two output
diodes of the buck derived versions (for the same output
power levels). Since the conduction loss in a POWERMOS
isgivenby I
D(RMS)
2
.R
DS(on)
, it is clear that the flyback, although
simple, does not lend itself as well to achieving large
increases in efficiency when compared to other topologies
that utilise POWERMOS synchronous rectifiers.
Fig. 4 Flyback self-driven synchronous rectifier circuits.
(b) The Forward converter.
An experimental self-driven circuit based on the forward
converter was then investigated. In this version the
frequencyof operationwasraisedto300kHzwiththesupply
again delivering 5V at 10A.
The direct replacement of the output diodes with
POWERMOS transistors is shown in Fig. 5. In this
arrangement, the gate sees the full voltage across the
transformer winding. Therefore, the supply input voltage
range must be restricted to ensure the gate of the
POWERMOS is not driven by excessively high voltages.
This would occur during low primary transistor duty cycle
181
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
conditions. The waveforms obtained for the forward
synchronous rectifier in this configuration are also shown
in Fig. 5.
(Forward rectifier) Timebase: 1µs/div
Top trace: V
GS
- 20V/div
Middle: V
DS
- 20V/div
Bottom: I
D
- 10A/div
Fig. 5 Forward converter with synchronous rectification
- direct replacement with POWERMOS.
In this case the method of control is such that the gate is
referenced to the source via the drain-source body diode.
This clamps the gate, enabling it to rise to a voltage which
will turn the POWERMOS on. If the body diode was not
present, the gate would always remain negative with
respect to the source and an additional diode would have
to be added to provide the same function.
Additional circuitry is required to turn off the freewheel
synchronous rectifier. This is due to the fact that when the
freewheel POWERMOS conducts, the body diode will take
the current first before the gate drive turns the device on.
An additional transistor can be used to turn off the
POWERMOS in order to keep conduction out of the body
diode. This additional transistor will short the gate to ground
and ensures the proper turn-off of the POWERMOS. The
circuit with this additional circuitry and the resulting
freewheel rectifier waveforms are given in Fig. 6.
(Freewheel rectifier) Timebase: 1µs/div
Top waveform: V
GS
- 20V/div
Middle: V
DS
- 20V/div
Bottom: I
D
- 10A/div
Fig. 6 Forward converter with synchronous rectification
- additional circuitry to turn-off body diode.
A very simple circuit configuration can be used in which
body diode conduction in the freewheel synchronous
rectifier does not occur. By driving the freewheel rectifier
fromthe output chokeviaaclosely coupledwinding, amuch
faster turn-on can be achieved because the body diode
does not comeon. This circuit configuration andassociated
waveforms are shown in Fig. 7.
To avoid gate over-voltage problems a toroid can been
added which will provide the safe drive levels. This toroid
effectively simulates extra transformer windings without
complicating the main power transformer design. The
limitations of this approach are that there will be extra
leakage inductance and that an additional wound
component is required. The applicable circuit and
waveforms for this arrangement are given in Fig. 8.
Conclusions
The main advantage of POWERMOS synchronous
rectifiers over existing epitaxial and Schottky diode
rectifiers is the increase in efficiency. This is especially true
for applications below 5V, since the development of very
low R
DS(on)
POWERMOS transistors allows very significant
182
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
efficiency increases. It is also very easy to parallel the
POWERMOS transistors in order to achieve even greater
efficiency levels.
The difficulties involved with generating suitable drives for
the POWERMOSsynchronous rectifiers tend to restrict the
number of circuits for which they are suitable. It will also
significantly increase the cost of the supply compared with
standard rectifier technology.
The circuit examples outlined in this paper were very basic.
However, they did showwhat can be achieved. The flyback
configuration was the simplest, and there were various
possibilities for the forward converters.
(Freewheel rectifier) Timebase: 1µs/div
Top waveform: V
GS
- 20V/div
Middle: V
DS
- 20V/div
Bottom: I
D
- 10A/div
Fig. 7 Forward converter with synchronous rectification
- avoiding body diode conduction.
Recent work has shown that there are topologies more
suited to using MOSFET synchronous rectifiers (featuring
low rectifier r.m.s. current levels) such as the push-pull.
These can achieve overall power supply efficiency levels
of up to 90% for outputs of 5V and below. However, the
discrete control circuitry required is quite complex and
requires optical/magnetic isolation, since the waveforms
must be derived from the primary-side control.
The true advantage of synchronous rectifiers may only be
reached when the drive circuit and POWERMOS devices
are hybridised into Power Integrated Circuits. However, in
applications where the efficiency performance is of more
importance than the additional costs incurred, then
POWERMOS synchronous rectification is presently the
most suitable technique to use.
(Freewheel rectifier) Timebase: 1µs/div
Top waveform: V
GS
- 20V/div
Middle: V
DS
- 20V/div
Bottom: I
D
- 10A/div
Fig. 8 Forward converter with synchronous rectifiers -
method of protecting the gate inputs.
183
S.M.P.S. Power Semiconductor Applications
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Design Examples
185
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
2.3.1 Mains Input 100 W Forward Converter SMPS: MOSFET
and Bipolar Transistor Solutions featuring ETD Cores
Thefollowingtwoswitched-modepower suppliesdescribed
are low cost easy to assemble units, intended primarily for
the large number of equipment manufacturers who wish to
build power supplies in-house.
The designs are based upon recent technologies and both
feature ETD (Economic Transformer Design) ferrite cores.
The first design features a high voltage Bipolar transistor,
the BUT11 at a switching frequency of 50kHz. The second
design is based around a power MOSFET transistor, the
BUK456-800A whose superior switching characteristics
allow higher switching frequencies to be implemented. In
this case 100kHz was selected for the MOSFET version
allowing the use of smaller and cheaper magnetic
components compared with the lower frequency version.
Both supplies operate from either 110/120 or 220/240 V
mains input, and supply 100W of regulated output power
up to 20A at 5V, with low power auxiliary outputs at t12V.
The PowerMOS solution provides an increase in efficiency
of 5% compared with the Bipolar version, and both have
been designed to meet stringent R.F.I. specifications.
ETD ferrite cores have round centre poles and constant
cross-sectional area, making them ideally suited for the
windings required in high-frequency S.M.P.S. converters.
The cores are available with clips for rapid assembly, and
the coil formers are suitable for direct mounting onto printed
circuit boards.
The ETD cores, power transistors and power rectifiers
featured are part of a comprehensive range of up-to-date
componentsavailablefromPhilipsfromwhichcost effective
and efficient S.M.P.S. designs can be produced.
50kHz Bipolar version
Circuit description
The circuit design which utilises the Bipolar transistor is
shown in Fig. 1. This is based upon the forward converter
topology, which has the advantage that only one power
switching transistor is required.
An operating frequency of 50kHz was implemented using
aBUT11transistor (availableinTO-220packageor isolated
SOT-186 version). This was achieved by optimising the
switching performance of the BUT11 Bipolar power
transistor TR5, by careful design of the base drive circuitry
and by the use of a Baker clamp. The 50kHz operating
frequency allows the size and the cost of the transformer
andchoketobereducedcomparedwitholder Bipolar based
systems which worked around 20kHz.
The base drive waveform generated by IC1 is buffered
through TR3 and TR4 to the switching transistor TR5.
Although operating from a single auxiliary supply line, the
drive circuit provides optimum waveforms. At turn-off,
inductor L3 controls the rate of change of reverse bias
current (-dI
B
/dt). The reverse base-emitter voltage is
provided by capacitor C16 (charged during the on-time).
The resulting collector current and voltage waveforms are
profiled by a snubber network to ensure that the transistor
SOA limits are not exceeded.
Voltage regulation of the 5V output is effected by means of
an error signal which is fed back, via the CNX82A
opto-coulper, to IC1 which adjusts the transistor duty cycle.
Over-current protection of this output is provided by
monitoring the voltage developed across the 1Ω resistor,
R28 and comparing this with an internal reference in IC1.
Voltage regulation and overcurrent protection for the 12V
outputs are provided by the linear regulating integrated
circuits IC4 and IC5.
Specification and performance
(Bipolar version)
Input
220/240 V a.c. nominal (range 187 to 264 V a.c.)
110/120 V a.c. nominal (range 94 to 132 V a.c.)
Output
Total output power = 100 W.
Fig. 2 Output voltage versus input voltage - (I
out
= 20A).
187
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Fig. 1 100W SMPS circuit diagram (50kHz Bipolar transistor version).
188
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Main output
5V at 20A max output power - Adjustment range t5%.
Line regulation
The change in output voltage over the full input voltage
range of 187 to 264 V is typically 0.2%; see Fig. 2.
Load regulation
The change in output voltage over the full load range of
zero to 100 W is typically 0.4%; see Fig. 3.
Fig. 3 Output voltage as a function of output current
(input voltage = 220Vac).
Auxiliary outputs
t12V at 0.1A.
Regulation (worst-case condition of max change in input
voltage and output load) < 0.4%.
Ripple and Noise
0.2% r.m.s. 1.0% pk-pk (d.c. to 100MHz).
Fig. 4 Output hold-up during mains drop-out at input.
Output hold-up
Both the main and auxiliary outputs will remain within
specification for a missing half-cycle (18ms) at full load and
minimum input voltage; see Fig. 4.
Isolation
Input to output ground 2kV r.m.s.
Output to ground 500V r.m.s.
Efficiency
The ratio of the d.c output power to the a.c input power is
typically 71% at full load; See Fig. 5.
Fig. 5 Efficiency as a function of output current.
Radio frequency interference
R.F.I. fed back to the mains meets VDE0875N and BS800.
Transient response
The response to a 50% change in load is less than 200mV
and the output returns to the regulation band within 400µs:
See Fig. 6.
Fig. 6 Response to 50% change in load with nominal
220Vmains input.
Vertical scale: 200nV/div
Horizontal scale: 1ms/div
189
S.M.P.S. Power Semiconductor Applications
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Optimum drive of high voltage Bipolar
transistor (H.V.T.)
A feature of the high voltage Bipolar transistor is the very
low conduction loss that can be obtained. This is made
possible by the "conductivity modulation" process that
takes place due to the influence of minority carriers in the
collector region of the device. However, the presence of
these carriers means that a stored charge will exist within
the collector region (especially in high voltage types) which
hasthe effect of producingrelatively slowswitchingspeeds.
This leads to significant switching losses, limiting the
maximum frequency of operation to around 50kHz.
To effectively utilise the power switching H.V.T. the base
drive must be optimised to produce the lowest switching
losses possible. This is achieved by accurate control of the
injection and more importantly the removal of the stored
charge during the switching periods. This is fulfilled by
controlling the transistor base drive current. (The Bipolar
transistor is a current-controlled device). The simple steps
taken to achieve this are summarised as follows:-
(1) A fast turn-on "kick-up" pulse in the base current should
be provided to minimise the turn-on time and associated
switching loss.
(2) Provide the correct level of forward base current during
conduction, based upon the high current gain of the
transistor. This ensures the device is neither over-driven
(which will cause a long turn-off current tail ) nor
under-driven (coming out of saturation causing higher
conduction loss). The Baker clamp arrangement used (see
Fig. 1) prevents transistor over-drive (hard saturation).
(3) The correct level of negative base drive current must be
produced to remove the stored charge from the transistor
at turn-off. The majority of this charge is removed during
the transistor storage time t
s
. This cannot be swept out too
quickly, otherwise a "crowding effect" will taken place
causing a turn-off current tail with very high switching loss.
This accurate control of the charge is provided by a series
inductor placed inthe path of thenegative base drivecircuit.
(For further information see sections 1.3.2. and 2.1.3).
BUT11 waveforms
These techniques have been applied in the BUT11 drive
circuit shown in Fig. 1, and the resulting base drive
waveforms are given in Fig. 7.
Optimised base drive minimises both turn-on and turn-off
switching loss, limiting the power dissipation in both the
transistor and snubber resistor allowing acceptable
operation at 50kHz. This is outlined in Fig. 8 which gives
the BUT11 collector current (I
C
) and collector-emitter
voltage (V
CE
) waveforms.
The transistor V
CE(sat)
would normally be as low as 0.3V.
However, the use of the Baker clamp limits it to about 1V.
Even so this still yields a transistor conduction loss of only
0.76W for the full output load condition.
Fig. 7 Base voltage V
B
and base current I
B
of BUT11
with nominal 220V input and full 5V, 20A output.
Upper trace V
B
: 5V/div
Lower trace I
B
: 0.2A/div
Horizontal scale: 5µs/div
Fig. 8 Collector-emitter voltage V
CE
and collector current I
C
for the BUT11
with nominal 220V mains input and full 5V, 20A output.
Upper trace V
CE
: 200V/div
Lower trace I
C
: 1A/div
Horizontal scale: 5µs/div
190
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
50kHz Magnetics design
Output Transformer
For 50kHz operation the transformer was designed using
an ETD39 core. The winding details are given in Fig. 9 and
listed as follows:-
Winding
1. 1/2 demag 42 turns 0.315mm dia. enamelled
copper wire (e.c.w.) (single layer).
2, 3 1/2 primary 42 turns 0.315mm e.c.w.(2 layers in
parallel).
4, 5 r.f.i. screens each 1 turn 0.05 x 16.5mm copper
strip.
6. 5V sec 6 turns 0.2 x 16.5mm copper strip.
7. t12V sec 18 turns 0.355mm e.c.w. bifilar
wound (1 wire each output).
8, 9 r.f.i. screens each 1 turn 0.05 x 16.55mm copper
strip.
10, 1/2 prim 42 turns 0.315mm e.c.w. (2 layers in
11 parallel).
12. 1/2 demag 42 turns 0.315 e.c.w (single layer).
13. primary drive 7 turns 0.2mm e.c.w.
- interleaving 0.04mm film insulation.
Airgap 0.1mm total in centre pole.
Fig. 9 50kHz Output transformer winding details. The 5V secondary and r.f.i. screens are connected together by
flying leads. Pin numbering is consistent with the ETD39 coil former.
(The insulation has been added to meet isolation and safety requirements for a mains input SMPS.)
191
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Fig. 10 50kHz output choke L1, winding details.
Inductance of 5V winding = 43µH.
Coupled Inductor technique.
50kHz output chokes
All of the output chokes have been wound on a single core;
i.e. using the coupled inductor approach. This reduces
overall volume of the supply and provides better dynamic
cross-regulation between the outputs. The design of this
choke, L1, is based upon 43µH for the main 5V output,
using an ETD44 core which was suitable for 100W, 50kHz
operation.
The winding details are shown in Fig. 10 and are specified
as follows :-
Windings
1. 19 turns 0.25 x 25mm copper strip.
2. 57 turns 0.4mm e.c.w. bifilar wound.
Airgap 2.5mm total in centre pole.
Note. Choke L3 was wound with 1 turn 0.4mm e.c.w.
100kHz MOSFET version
The circuit version of the 100W forward converter based
around the high voltage power MOSFET is shown in
Fig. 11. The operating frequency in this case has been
doubled to 100kHz.
Feedback is againviaopto-coupler IC1, the CNX83Awhich
controls the output by changing the duty cycle of the drive
waveform to the power MOSFET transistor, TR3 which is
the BUK456-800A(availablein TO-220 package or the fully
isolated SOT-186 version). The transistor is driven by IC4
viaR16 and operates within its SOAwithout a snubber: see
the waveforms of Fig. 15. There is low auxiliary supply
voltage protection and primary cycle by cycle current
limiting which inhibit output drive pulses and protect the
supply.
The power supply control and transistor drive circuitry
(enclosed within the broken lines in Fig. 11) have low
current requirements (5mA). This allows dropper resistors
R2 and R3 to provide the supply for these circuits directly
from the d.c. link thereby removing the supply winding
requirement from the transformer.
Specification and performance
(MOSFET version)
The specification andperformance of the 100kHz MOSFET
version is the same as the earlier 50kHz Bipolar version
with the exception of the following parameters:-
Output ripple and noise
< 10 mV r.m.s.
< 40mV pk-pk (100MHz bandwidth) See Fig. 12.
Fig. 12 Output voltage and noise at full load for 100kHz
version.
Vertical scale: 50mV/div.
Horizontal scale: 2µs/div.
Transient response
The transient response has been improved to a 100mVline
deviation returning to normal regulation limits within 100µs
for a 10A change in load current.
192
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
193
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Radio frequency interference
The 100kHz version meets BS800 and CISPRA
recommendations; see Fig. 13.
Fig. 13 Measured r.f.i. at supply terminals.
Efficiency
The overall efficiency has been improved by up to 5%
compared to the Bipolar version, achieving 76% at full
output load. This is mainly due to the more efficient
switching characteristics of the MOSFET allowing the
removal of the lossy snubber, reduced transistor drive
power requirements and lower control circuit power
requirements. Fig. 14 shows the overall efficiency of the
power supply against load current.
Fig. 14 Efficiency vs load current (V
IN
= 220V a.c.).
It should be noted that for the high current and low voltage
(5V) main output, a large portion of the efficiency loss will
be due solely to the output rectifiers’ forward voltage drop
V
F
. Therefore, these two output rectifiers are required to be
lowloss, very lowV
F
power Schottky diodes inorder tokeep
overall converter efficiency as high as possible. In this case
the Dual PBYR2535CT device was selected for the 5V
output. This is available in the TO-220 package and will
comfortably rectify an average output current well above
the 20A required, providing a suitably sized heat-sink is
added.
Mains isolation
The mains isolation conforms to IEC435.
The power MOSFET as a high frequency
switch
Power MOSFET transistors are well known for their ease
of drive and very fast switching characteristics. Since these
are majority carrier devices, they are free from the charge
storage effects which lessen the switching performance of
the Bipolar products. Driving the MOSFET is far simpler
and requires much less drive power than the equivalent
Bipolar version.
The speed at which a MOSFET can be switched is
determined by the rate at which its internal capacitances
can be charged and discharged by the drive circuit. In
practice these capacitances are very small (e.g the input
capacitanceC
iss
for the BUK456-800Aisquotedas1000pF)
allowing MOSFET rise and fall times in the tens of
nano-seconds region. The MOSFET can conduct full
current when the gate-source voltage V
GS
, is typically 4V to
6V. However, further increases in V
GS
are usually employed
to reduce the device on-resistance and 8V to 10V is
normally the final level appliedtoensure alower conduction
loss.
With such fast switching times, the associated switching
losses will be very low, giving the MOSFET the ability to
operate as an extremely high frequency switch. Power
switching in the MHz region can be obtained by using a
MOSFET.
One major disadvantage of the MOSFET is that it has a
relatively high conduction loss in comparison with bipolar
types. This is due to the absence of the minority carriers
meaning no "conductivity modulation" takes place.
MOSFET on-resistance
The conduction loss is normally calculated by using the
MOSFET "on-resistance", R
DS(on)
, expressed in Ohms. The
voltage developed across the device during conduction is
an Ohmic drop and will rise as the drain current increases.
Therefore, the conduction loss is strongly dependent upon
the operating current. Furthermore, the value of the
MOSFET R
DS(on)
is strongly dependent upon temperature,
and increases as the junction temperature of the device
rises during operation. Clearly, the MOSFET does not
compare well to the Bipolar which has a stable low
saturationvoltagedropV
CE(sat)
, andisrelativelyindependent
of operating current or temperature.
It should be noted that the R
DS(on)
of the MOSFET also
increases as the breakdownvoltagecapability of the device
is increased.
194
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
How fast should the MOSFET be switched?
Although very fast switching times are achievable with the
power MOSFET, it is not always suitable or necessary to
use the highest frequency possible. A major limiting factor
inS.M.P.S. designisthemagnetics. Present highfrequency
core loss for high grade ferrite core materials such as 3C85
limits the maximum operating frequency to about 200kHz,
although new types such as 3F3 are now suitable for use
at 500kHz.
There has always been a drive to use ever higher operating
frequencies with the aim of reducing magnetics and filter
component sizes. However, most S.M.P.S. designs still
operate below 300kHz, since these frequencies are quite
adequate for most applications. There is no reason to go
to higher frequencies unneccessarily, since very high
frequency design is fraught with extra technical difficulties.
Furthermore, although the very fast MOSFET switching
times reduce switching loss, the increased dI/dt and dV/dt
rates will generate far worse oscillations in the circuit
parasitics requiring lossy snubbers. The R.F.I. levels
generated will also be far more severe, requiring additional
filtering to bring the supply within specification. The golden
rule in S.M.P.S. square wave switching design is to use the
lowest operating frequency and switching times that the
application will tolerate.
Estimating required switching times
In the 100kHz example presented here, the typical
conduction time of the transistor will be approximately 3µs.
Aruleof thumbis to keep the sumof the turn-onand turn-off
times below 10% of the conduction time. This ensures a
wide duty cycle control range with acceptable levels of
switching loss. Hence, the target here was to produce
switching times of the order of 100ns to 150ns.
Gate drive requirements
The capacitances of the power MOSFET are related to the
overall chip size with the gate-source capacitance typically
in the range 1nF to 2nF. However, these capacitances are
very voltage dependent and are not suitable for estimating
the amount of drive current required to obtain the desired
switching times. A more accurate method is to use the
information contained in the turn-on gate charge (Q
G
)
characteristic given in the data-sheets. The graph of Q
G
for
the BUK456-800A for a maximum d.c. rated drain current
of 4A is shown in Fig. 15.
Theshapeof this characteristic needs explaining. The initial
slope shows the rise of V
GS
to the device 4A threshold
voltage V
th
. This requires very little charge, and at the top
point of this slope the MOSFET can then conduct full
current. However, further gate charge is required while V
DS
falls from its off-state high voltage to its low on-state level.
This is the flat part of the characteristic and at the end of
this region the MOSFETis fully switched on. (This is shown
for a range of initial off state voltages). The second slope
characterises any further increase in Q
G
and V
GS
that may
be employed to minimise the device on-resistance.
Note. Since the turn-off mechanism involving the removal
of gatecharge is almost identical to the turn-onmechanism,
therequiredturn-off gatechargecanalsobeestimatedfrom
the turn-on gate charge plot.
Fig. 15 Typical turn-on gate charge versus V
GS
for
BUK456-800A
Conditions: I
D
= 4A; plotted for a range of V
DS
.
In this topology the typical d.c. link voltage is 280V, hence
the MOSFET V
DS
prior to turn-on will be 280V, doubling to
560V at turn-off. From Fig. 14, for these two V
DS
levels it
can be estimated that the BUK456-800A will require 23nC
to fully turn on and 27nC to turn off. It should be noted that
this estimation of gate charge is for the 4A condition. In this
present application the peak current is under 2A and in
practice the actual Q
G
required will be slightly less.
To a first approximation the gate current required can be
estimated as follows:-
where t
sw
is the applicable switching time. If an initial value
of the turn-on and turn-off time is taken to be 125ns then
the required gate current is given by:-
In the majority of MOSFET drive circuits the peak currents
and resulting switching times are controlled by using a
series gate resistor R
G
. An initial estimation of the value of
this resistor can be found as follows:-
0 20 40
QG / nC
VGS / V
12
10
8
6
4
2
0
VDS / V =160
640
BUK4y6-800
Q
G
· I
G
t
sw
I
G(on)
·
23nC
125ns
· 0.184A; I
G(off )
·
27nC
125ns
· 0.216A
R
G
·
V
drive
− V
th
I
G(ave)
195
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
where I
G(ave)
is the average value of the turn-on and turn-off
peak gate current. In this example the gate driver I.C.4.
consists of 5 parallel T.T.L. gates in order to provide high
enough current sink and source capability. The driver
supply voltage was approximately 10V, the MOSFET
threshold voltage was 5V and the average peak gate
current was 0.2A.
This gives a value for R
G
of 25Ω. A value of 22Ω was
selected, and the resulting gate drive waveforms for TR3
under these conditions at the full 100W output power are
given in Fig. 16.
Fig. 16 PowerMOS TR3 gate drive waveforms.
Upper V
GS
=5V/div; Lower I
G
=0.2A/div
Horizontal 2µs/div.
This shows a peak I
G
of 0.17A at turn-on and 0.28A at
turn-off. The magnitudes of the turn-on and turn-off peak
gate currents in operation are slightly different to the
calculated values. This is due to the effect of the internal
impedanceof thedriver, wheretheimpedancewhilesinking
current is much lower than while sourcing, hence the
discrepancy.
These drive conditions correspond to a turn-on time of
143ns andturn-off time of 97ns, which are reasonably close
to the initial target values.
In this application, and for the majority of simple gate drive
arrangements which contain a series gate resistor (see
section 1.1.3) the total power dissipation of the gate drive
circuit can be expressed by:-
where Q
G
is the peak gate charge and V
GS
is the operating
gate-source voltage. From Fig. 15, taking Q
G
to be 43nC
for a V
GS
of 10V gives a maximum gate drive power
dissipation of only 43mW, which is very small and can be
neglected.
MOSFET losses
Switching losses
The waveforms for the drain current and drain-source
voltage at full output load for the drive conditions specified
are given in Fig. 17. In this case no transistor snubbing was
required.
Fig. 17 PowerMOS drain-source voltage and drain
current at full load.
Upper V
DS
=200V/div; Lower I
D
=1A/div
Horizontal scale 2µs/div
The waveforms of I
D
and V
DS
were found to cross at
approximately half their maximum values for both turn on
and turn-off. The switching loss can therefore be
approximated to two triangular cross-conduction pulses
shown in Fig. 18.
Fig. 18 Graphical approximation of MOSFET switching
loss.
Hence, the total switching loss can be expressed by the
following simplified equation:-
Inserting the correct values for this example gives:-
Id
Vds
turn-on energy loss
turn-off energy loss
per cycle
Vlink x Ion x ton
2 x 2 x 2
2Vlink x Ioff x toff
2 x 2 x 2
(Vlink)
(2Vlink)
Ion
Ioff
per cycle
ton toff
Power = Energy x freq
P
G
· Q
G
.V
GS
.f
P
sw
·
1
8
f (I
Don
V
link
t
on
+ I
Doff
2V
link
t
off
)
P
sw
· 0.125 × 100k(1.3 × 280 × 147n + 1.95 × 560 × 97n)
196
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
The MOSFET switching loss in this application is a very
respectable 1.73W. It should be noted that a direct
comparison with the switching loss of the earlier Bipolar
version is not practical. It was necessary to use a snubber
with the Bipolar in order to remove a large amount of the
excessive switching loss generated by the device.
Furthermore, the MOSFET switching frequency
implemented was double that of the Bipolar version.
If a direct comparison were to be made under the same
circuit conditions, the Bipolar switching loss would always
be far in excess of the low values achievable with the
MOSFET.
Conduction loss
The conduction loss for a power MOSFET is calculated by
estimating (I
D(rms)
)
2
R
DS(on)
. The drain current at full output
load is as shown in Fig. 17 and the r.m.s. value of the
trapezoidal current waveforms found in the forward
converter is given by:-
At full load, these values can be seen to be I
min
=1.25A;
I
max
=1.95A; D= 0.346. Substituting these values into the
above equation gives an I
D(rms)
= 0.95A.
The typical R
DS(on)
value for the BUK456-800A is quoted as
2.7Ω. However, this is for a junction temperature of 25˚C.
The value at higher operating junction temperatures can be
calculated from the normalisation curve given in the
data-sheets. If a more realistic operating temperature of
100˚C is assumed, the weighting factor is 1.75. Hence, the
correct R
DS(on)
to use is 4.725Ω. Therefore, the conduction
loss is given by:-
The conduction loss of 4.26W is over double the switching
loss. However, this is typical for a high voltage MOSFET
operated around this frequency. The MOSFET conduction
loss is much higher than was previously obtained using the
Bipolar transistor at 50kHz, as expected.
The total loss for the MOSFET device thus comes to 6W
i.e. 6% of the total output power.
It should be remembered that this figure has been
calculated for the full output load condition which will be a
transient worst case condition. A more realistic typical
dissipationof approximately 4Whas been estimatedfor the
half load condition, where the conduction loss is
approximately halved. This 4Wfigure should be used when
estimatingthe heatsinkrequirement. Inthis case arelatively
small heatsink with a thermal co-efficient of around 10˚C/W
would be adequate.
For more information on MOSFET switching refer to
chapters 1.2.2. and 1.2.3. of this handbook.
100kHz magnetics design
Output transformer
Doubling the switching frequency to 100kHz has allowed
theuse of the smaller sized ETD34corefor the transformer.
This transformer has been designed with a 0.1mm centre
pole air gap. The winding details are shown in Fig. 19 and
listed as follows:-
Winding
2 to 1 Regln
supply
5 to 4 +12V sec 3 x 12 turns 0.4mm e.c.w. in 1 layer.
6 to 7 -12V sec 3 x 12 turns 0.4mm e.c.w. in 1 layer.
8 r.f.i. 1 turn 0.1 x 13mm copper strip.
screen
10 to 1/2 prim 28 turns 0.355mm e.c.w. bifilar in two
12 layers.
11 to 1/2 28 turns 0.355mm e.c.w. in 1 layer.
13 demagn
12 to 1/2 prim 28 turns 0.355mm e.c.w. bifilar in 2
14 layers.
13 to 8 1/2 28 turns 0.355mm e.c.w. in 1 layer.
demagn
Interleaving:- 1turn 0.04mm insulation between each layer
except 3 turns between r.f.i. screens.
Output choke
Again the implementation of the higher frequency has
allowed the use of the smaller sized ETD39 core for the
coupled output inductor. A centre pole air-gap of 2mmwas
utilised. The winding details are shown in Fig. 20 and are
listed as follows:-
Winding
Copper strip +5V 15 turns 0.3 x 21mm copper strip.
2 to 15 -12V 45 turns 0.4mm e.c.w. in 1 layer.
1 to 16 +12V 45 turns 0.4mm e.c.w. in 1 layer.
Interleave:- 1 layer 0.04mm insulation between each strip
and winding.
· 0.67W+ 1.06W· 1.73W
I
rms
·

D
¸

¸
I
min
2
+ I
min
I
max
+ I
max
2
3
_

,
D ·
t
ON
T
P
cond
· (0.95)
2
4.723 · 4.26W
197
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Fig. 19 100kHz transformer construction. Fig. 20 100kHz inductor construction.
198
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
2.3.2 Flexible, Low Cost, Self-Oscillating Power Supply using
an ETD34 Two-Part Coil Former and 3C85 Ferrite
This sectiondescribes alow-cost, flexible, full performance,
Self Oscillating Power Supply (SOPS) using the flyback
principle.
The circuit is based around an ETD34 transformer using a
two-part coil former and3C85ferrite material. Thefeedback
regulation is controlled from the secondary side by means
of a small U10 transformer.
The circuit is described and the details of the magnetic
design using the two-part coil former is given. The
advantages of the two-part coil former are highlighted
together with 3C85 material properties. Power supply
performance of a 50W SMPS design example is given.
Introduction.
A recently developed low-cost full-performance
switched-mode power supply design is presented,
highlighting a new transformer concept using a novel
ETD34 two-part coil former and 3C85 low-loss material.
The SMPS is of the Self Oscillating Power Supply (SOPS)
typeand uses the flyback principle for minimumcomponent
count and ultra-low cost/watt.
Compliance with safety and isolation specifications has
always been a headache for magnetics designers. Now,
the introduction of the ETD34 two-part coil former solves
the problem of the 4+4mm creepage and clearance
distances by increasing the available winding area and
consequently decreasing copper losses. It also offers the
advantage of a more flexible approach with the possibility
of using a standard ’plug-in’ primary and a customised
secondary to meet any set of output requirements.
3C85 is a recently developed material superseding 3C8
and offers lower core loss, better quality control and higher
frequency operation at no extra cost.
These products are illustrated in the following 50W SMPS
design example, which is suitable for microcomputer
applications.
SOPS
The principle of the Self-Oscillating Power Supply is shown
in Fig. 1 and is based on the flyback converter principle.
Stabilisation of the output voltage against mains and load
variation is achieved by varying the duty cycle of the
powerMOS switching transistor. The on-time varies mainly
with input voltage, whereas the off-time varies only with the
load. This means that both the duty cycle and the frequency
vary due to the control circuit. The switching frequency is
therefore at a maximum for maximum input voltage and
minimum load. Regulation is achieved by varying the point
at which the POWERMOS transistor is switched off. A.C.
magnetic coupling is used in preference to opto-couplers
for long-term life stability and guaranteed creepage and
clearance. This circuit has the inherent property of self
limiting energy transfer, since the maximum energy 1/2LI
2
,
is defined by the bipolar transistor V
BE
threshold and the
source resistance value.
Fig. 1 Principle of S.O.P.S. with magnetic feedback for
isolation.
The Transformer
The transformer uses the versatile ETDsystem. This is the
range of four IEC standardised cores based on an E-core
shape with a round centre pole. This permits easy winding
especially for copper foil and standard wire. The ETD
system includes coil formers into which the cores are clip
assembled. The coil formers are designed for automatic
winding and comply with all the standard safety
specifications.
The two-part coil former was especially designed for the
ETD34, and is shown in Fig. 2. There is 25%more winding
area compared to the standard coil former yet full safety
isolation is provided so that the creepage and clearance
specifications are fully met. The inner part is a "click" fit into
the outer part, such that the former is mechanically stable
even with the cores removed. This two-part construction
leads to a very versatile winding approach where standard
primaries can be wound and assembled, yet still retaining
the flexibility for various secondaries to be added for
different requirements.
199
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Fig. 2 ETD34 Two Part Coil Former.
Leakage inductance is always a problem with flyback
transformers, but using this special construction the
increase in leakage can be almost offset by the greater
winding area of the two-part coil former when compared to
thestandardproduct with4+4mmcreepageandclearance.
Fig. 3 shows standard and two part transformer
cross-sections, where the leakage inductance is not more
than 20% greater for the two-part coil former for this 50W
design.
The transformer details for the 50W microcomputer power
supply design example are shown in Fig. 4. The primary
side consists of three windings:- a feedback winding of 5
turns, the main primary winding and a bifilar voltage clamp
winding of 92 turns. This is achieved with 4 layers to fill the
inner coil space area. The secondaries consist of a 5V
winding of 3 turns and the +12V windings of 7 turns each.
As there are so few turns, the winding area is most
effectively filled with stranded wire, copper strip or parallel
windings, and these are therefore all possible choices.
In addition to the improved windings possibilities with the
two-part coil former, the ETD core material has been
enhanced. The quality of the 3C85 material is much
improved compared to the older 3C8 type. Fig. 5 compares
curves of core loss versus frequency for 3C85 against 3C8.
The 30% improvement in 3C85 has been due to refining
thematerial compositionandtighter process qualitycontrol.
200
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Fig. 3 The two types of transformer construction compared.
Fig. 4 Transformer winding details using two part coil
former.
Fig. 5 Core loss versus frequency for 3C8 and 3C85.
Application and Operation of SOPS
The SOPS circuit is ideally suited for microcomputer
systems, where full performance at low cost is required.
The 50W output power is split between a regulated 5V
output at 5A for the logic, a +12V output at 1.8A and a -12V
output at 0.2A for the peripherals. The circuit diagram of
the power supply is shown in Fig. 6. The operating
frequency varies from 250kHz at open circuit to 35kHz at
full load. The circuit works as follows:-
The mains input is filtered (L1), rectified (D1-D4) and
smoothed (C7) to provide a d.c. rail. This supply rail utilises
a single electrolytic capacitor which is a low profile , low
cost, snap-fit 055 type.
The main switching transistor, Q1, is a TO-220 powerMOS
device, the BUK456-800A. Starting current is provided via
R1 to Q1 to start the self-oscillating operation. Feedback
current is provided by a small winding on the transformer
(T1), via C8 to maintain bias. Duty cycle control is via R5
and T2, with final control being achieved with R5, T2 and
Q2. The triangular transformer magnetising current is seen
across R5 as a voltage ramp, (see Fig. 7). This is fed to the
base of Q2, via a small U10 transformer, T2. When the
voltage becomes greater than the V
BE
of the transistor, Q2
is turned on, causing the gate of Q1 to be taken to the
negative rail, so terminating the magnetisation of the
transformer T1. The output voltage is controlled by feeding
back a turn-off pulse by means of T2, thus causing Q2 to
turn on earlier.
A voltage clamp winding is bifilar wound with the primary
to limit voltage overshoots on the drain of Q1 at turn-off,
thus ensuring that the transistor operates within its voltage
rating.
201
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Fig. 6 Circuit diagram of 50W S.M.P.S.
Maximum throughput power is determined by the value of
R5: the higher its resistance value, the lower the maximum
power. The same drive and control circuit can be used for
different throughput powers, ETD core sizes and
powerMOS transistors.
The 5V secondary uses a single plastic TO-220 Schottky
diode, the PBYR1635 shown as D8. The output filter is a
pi type giving acceptable output ripplevoltage together with
good transient response. Two electrolytic capacitors are
used in parallel, C11a/C11b (to accommodate the ripple
current inherent in flyback systems), together with a small
inductor wound on a mushroom core, L4, and a second
capacitor, C14.
The turn-off pulse is created, cycle-by-cycle, by charging a
capacitor fromthe output andcomparing it with areference,
D10andby usingthe transition signal tofeed back aturn-off
pulse via transformer T2. A potential divider is present
across the output 5V rail, consisting of R10, R11 and R12,
via Q3. The potential divider controls the base voltage of
the transistor Q4, which charges capacitor C16 via R13.
The voltage on C16 ramps up to a voltage equal to that on
the base of the transistor less the V
BE
, causing Q4 to switch
off. The capacitor continues to charge more slowly via
resistor R14, i.e. a ramp and pedestal (see Fig. 8), until the
voltage on the emitter of Q5 is equal to the voltage
determined by the band-gap reference D10 (2.45V) plus
the V
BE
drop of Q5. When this voltage is reached, Q5
switches on, causing Q6 to switch on, pulling Q5 on harder.
The edge produced is transmitted across T2 and adds to
the voltage on the base of Q2. Transistor Q3 is there to
maintain the voltage level at the end of the ’on’ period of
the waveform to prevent premature switching. Capacitor
C16 is reset by diode D9 on the edge of the switching
waveform of the schottky diode, D8.
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Fig. 7 BUK456-800A powerMOS transistor switching
waveforms.
Top trace - Drain voltage V
DS
200V/div
Bottom trace - Source current I
S
1A peak (across R5)
Timebase - 5µs/div
Fig. 8 Ramp and pedestal control waveforms across
C16 = 1V/div, 5µs/div.
Performance
The performance of the supply is as follows:- the 5V output
has load regulation of 1.2% from 0.5A to 5A load current.
The line regulation is 0.5% for 187V to 264V a.c. mains
input voltage.
The 12V secondaries are unregulated, and therefore have
an inferior regulation compared to the 5V output. Each rail
has a load regulation of 6% from open-circuit to full load.
This is adequate for typical microcomputer peripheral
requirements.
The efficiency of the power supply is typically 80%. The
ripple and noise on all outputs is less than 75mV peak to
peak. The radio frequency interference is less than 50dB
(above 1µV) from 150kHz to 30MHz and complies with
VDEO875 and BS800, based on a 150Ω V network. See
Fig. 9. The transient response of the 5V output due to a 2A
to 5A step load change gives a deviation of 100mV.
Fig. 9 Conducted R.F.I. on the supply terminals
complying with VDE0875 and BS800.
Conclusion
A novel Self Oscillating Power Supply has been introduced
featuring two recently developed products, increasing the
cost effectiveness and efficiency of low-power SMPS:-
The new ETD34 two-part coil transformer featuring:
* solving of isolation problems
* standard ’plug-in’ primaries
* suitable for automatic winding
* ETD system compatible.
The 3C85 ferrite material offers:
* 30% lower loss than 3C8
* comparable price with 3C8
* high frequency operation, up to 150kHz
* improved quality
203
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Magnetics Design
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2.4.1 Improved Ferrite Materials and Core Outlines for High
Frequency Power Supplies
Increasing switching frequency reduces the size of
magnetic components. The current trend is to promote
SMPSminiaturisation by using this method. The maximum
switching frequency used to be limited by the performance
of available semiconductors. Nowadays however, Power
MOSFETs are capable of square-wave switching at 1MHz
and beyond. The ESL of the output capacitor had until
recently limited any major size reduction in output filter
above 100kHz. The advent of multi-layer ceramic capacitor
stacks of up to 100µF removed this obstacle. This allowed
the operating frequency to be raised significantly, providing
a dramatic reduction in the size of the output filter (by an
order of magnitude). The transformer has nowbecome the
largest single component in the power stage, and reducing
its size is very important. The transformer frequency
dependent core losses are now found to be a major
contributing factor in limiting the operating frequency of the
supply.
Part 1 of this section highlights the improvements in ferrite
material properties for higher frequency operation. The
standard 3C8 with its much improved version the 3C85 are
discussed. However, the section concentrates on the new
high frequency power ferrite, 3F3. This material features
very low switching losses at higher frequencies, allowing
the process of miniaturisation to be advanced yet further.
The popular ETD system shown in Fig. 1 is also outlined,
and used as an example to compare the losses obtained
with the above three materials.
In Part 2, the new EFD (Efficient Flat Design) core shape
is introduced. These cores have been specifically designed
for applications where a very low build height is important,
such as the on-card d.c. - d.c. converters used in distributed
power systems.
Circuit topologies suitable for high frequency applications
are considered in the final part. Optimum winding designs
for the high frequency transformer, which maximise the
throughput power of the material are described.
PART 1: Improved magnetic materials
The ETD core system
The very widely used ETD core shape is shown in Fig. 1,
which also outlines the method of coil-former assembly.
The ETD range meets IEC standardisation, and is based
on an E-core shape with a round centre pole. This permits
easy winding especially for copper foil and stranded wire.
The ETD systemincludes coil-formers into which the cores
are clipped for quick, simple and reliable assembly. The
coil-formersare designed for automatic windingandenable
conformance with all standard safety specifications
including UL.
ETDcores are suitable for a wide range of transformer and
inductor designs, andarevery commonlyfeatured inoff-line
power supply transformers because the ease of winding
allows insulation and creepage specifications to be met.
Fig. 1 The ETD core and assembly system.
Core materials
Three types of ferrite core material are compared. The
standard3C8which isapplicablefor 50kHzuse, thepopular
3C85 which is usable at up to 200kHz, and the new high
frequency core material 3F3, which has been optimised for
use from 200kHz upwards.
The throughput power of a ferrite transformer is, neglecting
core losses, directly proportional to (amongst other things)
the operating frequency and the cross-sectional area of the
core. Hence for a given core, an increase in the operating
frequencyraises the throughput power, or for agiven power
requirement, raisingthe frequencyallowssmaller coresand
higher power densities. This is expressed by the following
equation:-
where W
d
is the winding parameter, C
d
is the core design
parameter, f is the switching frequency and B is the
induction (flux density) in Tesla.
Unfortunately, the core losses are also frequency
dependent, and increasing frequency can substantially
increase the core losses. Thus an increase in the core
volume is required to maintain the desired power
throughput without overheating the core. This means the
transformer bulk in a higher frequency supply could limit
the size reduction target.
P
th
· W
d
× C
d
× f × B
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The new 3F3 material with low-loss characteristics at high
frequencies will reduce this problem, allowing new levels
of miniaturisation to be obtained. An example of the
practical size (and weight) reduction possible by moving to
higher operating frequencies is given in Fig. 2. In
comparison with the 50kHz examples, there is a significant
reductionintransformer size whenswitchedat 500kHz, and
an even more impressive shrinking of the output inductor
when operated at 1MHz.
Fig. 2 Size reduction possible using 3F3 ferrite.
Note. The size of the output capacitor and inductor required
to filter the high frequency output ripple components is
greatly reduced - up to 90% smaller, resulting in excellent
volume savings and very low ripple outputs.
Fig. 3 Performance factor (f.B
max
) as a function of
frequency for material grades 3C8, 3C85 and 3F3.
The performance factor (f.B
max
) is a measure of the power
throughput that a ferrite core can handle at a loss of
200mW/cm
3
. This level is considered acceptable for a well
designed medium size transformer. The performance
factors for the three different material grades 3C8, 3C85
and3F3 are shownin Fig. 3. For frequencies below100kHz
(the approximate transition frequency, f
t
) the power
throughput is limited by core saturation and there is not
much difference between the grades. However for
frequenciesabove100kHz, coreloss isthe limitation, which
reduces the allowable throughput power level by
overheating the core. Therefore, in order to utilise higher
frequencies to increase throughput power or reduce core
size, it is important that the core losses must first be
minimised.
Reducing the losses
There are three main identifiable types of ferrite material
losses: namely, hysteresis, eddy current and residual.
Hysteresis loss
This occurs because the induced flux, B, lags the driving
field H. The B/H graph is a closed loop and hysteresis loss
per cycle is proportional to the area of the loop. This loss
is expressed as:-
where C
a
is a constant, B
pk
is the peak flux density, f is the
frequency with x and y experimentally derived values.
Eddy current loss
This loss is caused by energy from the magnetic flux, B,
setting up small currents in the ferrite which causes heat
dissipation. The energy lost is represented by:-
C
b
is aconstant, A
e
is theeffective cross-sectional corearea
and σ is the material resistivity.
Residual/Resonant loss
Residual losses are due to the reversal of the orientation
of magnetic domains in the material at high frequencies.
When the driving frequency is in resonance with the natural
frequency at which the magnetic domains flip, there is a
large peak in the power absorption. This gives:-
where
P
hyst
· C
a
× f
x
×B
pk
y
P
ec
·
C
b
× f
2
×B
pk
2
× A
e
σ
P
res
· C
c
× f × B
pk
2
×
tanδ
δ
tanδ · loss angle ·
µ"
µ’
µ · µ ’ + j µ"
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Comparison of different materials
Fig. 4 Core losses in 3C85,3C8 and 3F3 for various
temperatures at 100kHz and 100mT.
These losses (in mW/cm
3
) are now presented for the three
material grades in a partitioned form. These are given for
various operating temperatures under two different
operating conditions. Fig. 4 shows performance at 100kHz
and a peak flux density of 100mT, which is typical for the
3C8 and 3C85 materials. The hysteresis loss is clearly
dominant at this frequency. Inspectionrevealsareasonable
loss reduction when comparing 3C85 to the cheaper 3C8
grade. More significantly however, even at this lower
frequency the new 3F3 grade can be seen to offer
substantial loss reduction compared to 3C85 (especially at
lower operating temperatures).
Fig. 5 Core losses in 3F3 and 3C85 for various
temperatures at 400kHz and 50mT.
At higher operating frequencies well above 100kHz, eddy
currents and residual losses are far more dominant. Fig. 5
gives the values for 400kHz and 50mT high frequency
operation. This shows the superiority of the 3F3 material,
offering significant reductions (60% vs 3C85) in all
magnitudes, particularly in the eddy currents and residual
losses.
Figure 6 gives a comparison of the peak operating flux
density versus frequency at a core loss of 200mW/cm
3
for
each grade. This shows that the maximum allowable
operating frequency for 3F3 is always higher than for the
other two types, hence, making it much more suitable for
miniaturisation purposes. For example, at 100mT, 3F3 can
operate at 280kHz, compared to 170kHz for 3C85 and
100kHz for 3C8.
Fig. 6 Peak flux density versus frequency for 3F3,
3C85 and 3C8 at constant 200mW/cm
3
core loss.
Figure 7 compares the three types of core material in terms
of complex permeabilities µ’ and µ" over the frequency
range 1 to 10 MHz, at very low flux density levels of < 0.1
mT. It can be seen that the resonant loss peaks at a higher
frequency for 3F3, producing much lower high frequency
residual losses right up to 1MHz.
Fig. 7 Complex permeability versus operating
frequency for 3F3 and 3C85/3C8.
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Material 3C8 3C85 3F3
B
sat
(mT) at f = 25kHz ≥ 320 ≥ 320 ≥ 320
H = 250A/m
A
L
P
V
A
L
P
V
P
V
A
L
P
V
P
V
Core type t 25% Watts t 25% Watts Watts t 25% Watts Watts
nH/N
2
nH/N
2
nH/N
2
f 10kHz 25kHz 10kHz 25kHz 100kHz 10kHz 100kHz 400kHz
B 0.1mT 200mT 0.1mT 200mT 100mT 0.1mT 100mT 50mT
ETD29 - - 2100 ≤ 0.8 ≤ 1.0 1900 ≤ 0.6 ≤ 1.0
ETD34 2500 ≤ 1.6 2500 ≤ 1.1 ≤ 1.3 2300 ≤ 0.85 ≤ 1.5
ETD39 2800 ≤ 2.2 2800 ≤ 1.6 ≤ 1.9 2600 ≤ 1.3 ≤ 2.3
ETD44 3500 ≤ 3.6 3500 ≤ 2.5 ≤ 3.0 3200 ≤ 2.0 ≤ 3.7
ETD49 4000 ≤ 4.6 4000 ≤ 3.4 ≤ 4.0 3600 ≤ 2.6 ≤ 5.2
Table 1. Comparison of material properties for the ETD range
Comparison of material grade properties
for the ETD range
The values shown in Table 1 are for a core set under power
conditions at an operating temperature of 100˚C.
3F3 offers a major improvement over existing ferrites for
SMPStransformers. With reduced losses across the entire
frequency range (but most markedly at 400kHz and higher)
3F3 enables significant reductions in core volume while still
maintaining the desired power throughput.
As well as the ETD range, 3F3 is also available in the
following shapes:-
• RM core
• P core
• EP core
• EF core
• E core
• ring core
• new EFD core
The new EFD core system which also offers size reduction
capabilities shall now be described.
PART 2: The EFD core
(Economic flat design)
The newly developed EFD power transformer core system
shown in Fig. 8 offers a further significant advance in circuit
miniaturisation. Their low build height and high throughput
power density make them ideally suited to applications
where space is at a premium.
One such application is with distributed power systems,
whichisbecominganincreasingly popular method of power
conversion, especially in the telecommunication and EDP
market. Such power-systems convert a mains voltage into
an unregulated voltage of about 44 to 80V d.c. This is then
fed to individual sub-units, where d.c. - d.c. converters
produce the required stabilised voltages. These converters
are usually mounted on PCBs which in modern systems,
are stacked close together to save space. The d.c. - d.c.
converter, therefore, has to be designed with a very low
build height.
Fig. 8 The EFD core assembly and accessories.
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The low-profile design
The EFD core offers a significant reduction in transformer
core height. The ETDcore combines extreme flatness with
a very high throughput power-density. The range consists
of four coreassemblies complementedbyacompleterange
of accessories. It is planned that the EFD outline will
become a new European standard in d.c. - d.c. power
transformer design.
The four core assemblies have a maximum finished height
of 8mm, 10mm or 12.5mm. The type numbers are:-
• 8mm height - EFD 15/8/5
• 10mm height - EFD 20/10/7
• 12.5mm height - EFD 25/13/9 and EFD 30/15/9
Figure 9 shows that the EFDrange has a lower build height
than any other existing low profile design with the same
magnetic volume.
Integrated product design
Because there is no room in a closely packed PCB for
heavily built coil formers, they must be as small and light
as possible. For this reason high quality thermo-setting
plastics are used. This ensures that the connecting pins in
the base remain positioned correctly.
To ensure suitability for winding equipment the connecting
pins have been designed with a square base, saving time
in wire terminating. To allow thick wire or copper foil
windings to be easily ledout, both core andcoil former have
a cut-out at the top (see Fig. 8).
To increase efficiency and reduce size, the ferrite core has
been designed with the centre pole symmetrically
positioned within the wound coil former. This is clearly
shown in the cross-sectional view in Fig. 10.
Because of this, the full winding area can be used, resulting
in an extremely flat design which is ideally suited for
surface-mounting technology (SMT). SMT designs are
already under consideration.
Maximising throughput power-density
Besides their extreme flatness, the most important feature
of the EFD transformer is the very high throughput power
density. This is especially true when the core is
manufactured from the high-frequency low loss 3F3
material, which was described in the previous section.
Combining EFD with 3F3 can provide throughput power
densities (in terms of transformer volume) between 10 and
20W/cm
3
. Furthermore, withausablefrequency rangefrom
100kHz to 1MHz, the EFD transformer will cover most
applications.
Fig. 9 EFD build height compared to existing designs.
Fig. 10 Cross-section of EFD based transformers.
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Fig. 11 Temp rise versus P
th
for ETD based transformers Fig. 12 P
th
for forward mode transformers based on
with 3F3 material. EFD core with 3F3 material.
As described earlier, high frequency transformer design
(above 100kHz) is mainly limited by the temperature rise,
caused by heat dissipation from the high frequency core
losses as well as the power dissipation in the windings
themselves. So the extent of transformer miniaturisation at
high frequencies is limited by this rise in temperature (The
curie temperature of a typical power ferrite material is
around 200˚C). As a general rule, maximum transformer
efficiency is reached when about 40% of the loss is in the
ferrite core, and 60%in the windings. The temperature rise
for a range of throughput powers for transformers based
on the EFD range in 3F3 material is shown in Fig. 11.
In order to optimise the core dimensions and winding area,
a sophisticated computer aided design (CAD) model of a
d.c. - d.c. forward mode converter was used. This predicted
the temperature rise of the transformer as a function of
throughput power. The following parameters were
assumed:-
Ferrite core - 3F3.
V
in
= 44V to 80V; V
out
= 5V, +12V and -12V.
T
amb
= 60˚C; T
rise
= 40˚C.
Primary - Cu wire; Secondary - Cu foil.
(Split sandwiched winding with 2 screens).
The CAD program was used to find an optimised design
for the EFD transformer at well chosen frequency bands.
The dotted line in Fig. 12 indicates the theoretical result
derived from the CAD model. This shows in practice how
well the EFD range approximates to the ideal model. The
opencirclefor EFD15/8/5inFig. 12indicates the maximum
optimal switching frequency.
Fromtheseresultstherangewasgrouped, dependingupon
core size into their optimal frequency bands.
• 100 to 300kHz - EFD 30/15/9 and EFD 25/13/9.
• 300 to 500kHz - EFD 20/10/7.
• 500kHz to 1MHz - EFD 15/8/5.
These are the recommended frequency ranges for each
EFD type. The transformers can operate outside these
ranges, but at a reduced efficiency, since the ratio of their
core to winding areas would be less than ideal. Table 2 lists
the power throughput at certain frequencies for each EFD
core.
Core type 100 kHz 300kHz 500kHz 1MHz
EFD 30/15/9 90 - 100 W 110-140W -- --
EFD 25/13/9 70 - 85 W 90 - 120 W -- --
EFD 20/10/7 -- 50 - 65 W 55 - 70 W --
EFD 15/8/5 -- -- 20 - 30 W 25 - 35 W
Table 2. Power handling capacity for EFD range.
Valid for single-ended forward d.c. - d.c. converter
(V
in
= 60V; V
out
= 5V)
Typical EFDthroughput power curves giveninFig. 13 show
the performance of the low loss 3F3 material as well as
3C85. These results were confirmed from measurements
taken during tests on EFD cores in a transformer testing
set up. As expected these show that, especially above
300kHz, the 3F3 (comparedto 3C85) significantlyimproves
throughput power.
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Fig. 13 ETD performance for 3F3 and 3C85 material.
PART 3: Applications
Circuit (transformer) configurations
Forward, flyback and push-pull circuit configurations have
been used successfully for many different SMPS
applications. This includes mains-isolated square-wave
switching over the frequency range 20-100kHz, and with
output powers up to 200W. Recent transformer designs
have been developed to minimise the effects of leakage
inductance and stray capacitance upon these circuits. The
influences of the transformer characteristics on the choice
of circuit configuration for higher switching frequency
applications are now discussed.
The flyback converter
The flyback converter shown in Fig. 14 has leakage
inductance between the primary and secondary windings
which delays the transfer of power when the primary power
transistor turns off. For the example waveforms shown in
Fig. 14, the delay lasts for 600ns. During this time, power
is returned to the d.c. supply. The circulating power
increases with the switching frequency, and in this case
would produce 50W at 1MHz. This tends to limit the
maximum operating frequency for flyback converters.
The forward converter
The power transistor in the forward converter shown in
Fig. 15 normally has a snubber network (and stray circuit
capacitance) which protects the transistor at turn-off. This
is necessary because the energy stored in the leakage
inductance between the primary and secondary windings
would produce a large voltage spike at transistor turn-off.
At transistor turn-on the energy stored in the capacitance
is discharged and dissipated. For the example waveforms
giveninFig. 15, this wouldbe7.5Wat aswitchingfrequency
of 1MHz. Furthermore, as in the flyback converter, the
circulating magnetising power can also be as high as 50W
at 1MHz, hence reducing the efficiency of the transformer.
Thesecharacteristicslimit themaximumfrequency at which
forward converters can be usefully applied.
Fig. 14 Flyback converter and leakage inductance
effect.
Centre-tapped push-pull converter
The centre-tapped push-pull circuit configuration given in
Fig. 16 uses magnetic B/H loop symmetry when driving the
transformer. Therefore, when either transistor is turned off,
the magnetising current is circulated around the secondary
diodes, thereby reducing energy recovery problems or the
need for voltage clamping.
However, the transformer must be correctly "flux balanced"
by monitoring the current in the transistors to prevent
transformer saturation and subsequent transistor failure.
The draincurrent andvoltagewaveforms resultingfromtwo
examplesof push-pull transformer windingconstructionare
also shown in Fig. 16. In Fig. 16(a) (most serious case) the
leakage inductance has distorted the waveforms. In
Fig. 16(b) it is the circuit capacitance which produces the
distortion. Thesedistortions meanthat thetransistor current
Flyback
L
L - leakage inductance
500ns
500mV
2V
5mV
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sense waveforms must be adequately filtered, so that the
control circuit can vary mark/space correctly and prevent
transformer saturation.
Fig. 15 Forward converter and effects of parasitics.
As the switching frequency is increased, the accuracy of
the current balancing information is reduced by the action
of the filtering and there might be a point at which this
becomes unacceptable. The filter itself is also dissipative
and will also produce a high frequency loss.
The half-bridge converter
The half-bridge push-pull transformer shown in Fig. 17 is
inherently self-balancing. Standard winding methods for
transformer construction using this configuration are
possible at frequencies up to around 1MHz. Fig. 17 also
gives waveform examples for the half-bridge transformer.
This design allows the most flexibility when choosing a
particular switching frequency.
(a) Oscillation due to leakage inductance.
(b) Oscillation due to winding capacitance.
Fig. 16 Push-pull transformer configuration.
L
C
W1 W2
TR1 TR2
Centre-tapped push-pull
W1 - Primary Limb 1
W2 - Primary Limb 2
L
L - leakage inductance
C
TR
Lprim
C - snubber capacitor
Lprim - primary inductance
TR - transistor
Forward
50mV 1us
1V
50mV
2V 50mV 1us
200mV 500ns
5V
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Switching frequency
Whendesigningatransformer andcalculatingthecoreloss,
the exponent for frequency in the hysteresis loss equation
is assumed to be constant at all frequencies. Only the
fundamental is considered significant compared to all other
harmonics of the square wave. This is a reasonable
approximation to make from20kHz to 100kHz because the
contribution of eddy losses and resonant losses to the
overall core loss is negligible (see Fig. 4).
As the frequency increases to 1MHz and beyond, the
resonant and eddy current losses contribute proportionally
moretotheoverall coreloss. This meansthat theharmonics
of a 1MHz square wave have more significance in
determining the core loss than those at 100kHz. When the
mark/space is reduced, the harmonics increase, and the
loss will increase proportionally. This effectively limits the
upper frequency of a fixed frequency square-wave,
mark/spacecontrolled power supply. However, as outlined,
newmaterials such as 3F3 have been specially developed
to keep these high frequency transformer losses as low as
possible.
Transformer construction
In the half-bridge push-pull configuration of Fig. 17, during
the period that the two primary transistors are off, there is
zero volts across the secondary winding. Therefore, the
secondary diodes are both conducting and share the choke
current. The primarysideshouldalsohavezerovoltsacross
it, but it rings because of the stray capacitance and leakage
inductance between the primary and the secondary
windings (see waveform of Fig. 17). At 500kHz, using an
ETD29 or an EFD20 core, for example, a 1+1 copper strip
secondary winding is suitable for providing an output of 5V.
This is preferable to using more turns for the secondary
windingbecause the leakageinductance andthe amplitude
of the ringing during the period that the MOSFETs are off
is minimised. Reducing the ringing is of vital importance for
the following reasons:-
1. It prevents the anti-parallel diode inherent in the upper
MOSFETswitch fromconducting when the lower transistor
is turned on. This will increase the MOSFET dV/dt rating
typically by a factor 10, allowing the switching speed to be
maximised and the switching losses to be reduced.
2. For low voltage outputs, the ringing will only be slightly
reduced by the 1+1 construction. However, the core losses
increase significantly at the actual frequency of the ringing
(5-10MHz). Hence, any reduction in the ringing amplitude
will be beneficial to core loss.
To further optimise the operation of the transformer, and
reduce the ringing, the output clamping diodes should be
operated with the minimum of secondary leakage
inductance and mounted physically close to the
transformer.
Fig. 17 Half-Bridge transformer configuration with
typical waveforms.
Conclusions
To advance the trend towards SMPS miniaturisation,
low-loss ferrites for high frequency have been specially
developed. A new ferrite material has been presented, the
3F3, which offers excellent high-frequency, low loss
characteristics.
A wide range of power ferrite materials is now available
which offers performance/cost optimisation for each
application. The particular SMPS application slots for the
three ferrites discussed in this paper are summarised as
follows:-
• 3C8 for low-cost 20-100kHz frequency range.
• 3C85 for high performance 20-150kHz.
• 3F3 for miniaturised high performance power supplies in
the frequency range above 150kHz.
L
TR1
TR2
L
Half-bridge push-pull
prim
200mV
500ns
2V
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A new type of power core shape, the EFD was also
introduced. The use of the EFD core also allows further
SMPS miniaturisation by providing extremely low build
heights in conjunction with very high throughput power
densities. Optimum use of the EFD design can be made if
the 3F3 material grade is selected. The EFD system is
intended for applications with very low height restrictions,
and is ideal for use in the d.c. - d.c. converter designs found
in modern distributed power systems.
Different transformer winding configurations were also
described (particularly for mains isolated SMPS.) It was
found that to obtain the greatest size reduction using the
new 3F3 material at very high frequencies, the following
application ideas are useful:-
• Use the half-bridge push-pull circuit configuration.
• Minimize the transformer leakage inductance by careful
winding construction.
• Minimisethe lead-lengths fromthe transformer torectifier
diodes.
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Resonant Power Supplies
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2.5.1. An Introduction To Resonant Power Supplies
Whilst many application requirements can be satisfied by
the use of conventional switching topologies, their
shortcomings, particularly the switching losses in high
power / high frequency circuits, are becoming a serious
limitation. Some of the problems can be overcome by the
use of resonant, or quasi-resonant, converters.
A resonant converter is a switching converter in which the
natural resonance between inductors and capacitors is
used to shape the current and voltage waveforms.
There are many ways in which inductors, capacitors and
switches can be combined to form resonant circuits. Each
of the configurations will have advantages and
disadvantages in terms of stress placed on the circuit
components.
Toreduceswitchingloss, aresonant converter whichallows
the switching to be performed at zero current and low dI/dt
is needed. A range of such circuits can be produced by
taking any of the standard converter topologies and
replacing the conventional switch with a resonant switch.
Fig.1 Basic resonant switch circuits
Resonant switch
Aresonant switch consists of an active element (the switch)
plus an additional inductor, L, and capacitor, C. The values
of L and C are chosen so that, during the on time of the
switch, the resonant action between them dominates. This
ensures that the current through the switch, instead of just
increasing linearly and having to be turned off, forms a
sinusoid which rises to a peak and falls to zero again.
Two basic resonant switch configurations are shown in
Fig.1. Before the switch is closed, C is in a state where it
has a small negative charge. With the switch closed, C is
discharged into L and then recharged positively. During the
rechargingextra energy is drawn fromthe supply to replace
that delivered to the load during the previous cylce. With C
charged positively, the switch is opened. The energy in C
is now transfered to the load, either directly or via the main
inductor of the converter. In the process of this transfer, C
becomes negatively charged.
Figure 2 shows the three basic SMPS topologies - buck,
boost and buck / boost - with both conventional (a) and
resonant (b) switches. It should be noted that parasitic
inductance and capacitance could form part, or even all, of
the components of the resonant network.
Fig.2 Standard SMPS circuits using
(a) conventional switch
(b) resonant switch
Flyback converter
To showhow the resonant switch circuit reduces switching
loss we will now consider the operation of the flyback
converter, firstly with a conventional switch and then with
a resonant switch.
219
S.M.P.S. Power Semiconductor Applications
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Conventional switch
The basic flyback converter circuit is shown in Fig.3(a). If
the transformer is assumed to have negligible leakage
inductance it can be replaced by a single equivalent
inductor Lm and the circuit becomes as shown in Fig.3(b),
whichisthesameasabuck-boost converter showninFig.2.
Before the switch S is closed, a current Io will be flowing in
the loop formed by Lm, diode D and the output smoothing
capacitor Co. When S closes, voltage Es reverse biases
the diode, which switches off and blocks the flow of Io. A
current Is then flows via S and Lm. The only limitations on
the initial rate of change of current are the stray inductance
in the circuit and the switching speed of S. This means that
switching current Is rises very quickly, leading to large
turn-on losses in S and D.
Fig.3 Conventional switch flyback converter
(a) circuit
(b) equivalent circuit
The current Is rises linearly fromIo until the switch is forced
to reopen. The diode is then no longer reverse biased and
the current switches back from Is to Io via D, with Co then
acting as a voltage source. The losses in this switching will
also be very high due to the high level of Is and the rapid
application of the off-state voltage. Io now falls linearly,
delivering a charging current to Co, until the switch closes
again.
Figure 4 shows the current waveforms for Io and Is and the
current in inductor Lm.
Fig.4 Waveforms for conventional switch flyback
converter
Resonant switch
The resonant switch flyback converter circuit is shown in
Fig.5(a). The equivalent circuit (Fig.5 (b)) is the same as
that for the conventional switch except for the addition of
the inductor La and capacitor Ca whose values are very
much less than those of Lm and Co respectively.
Fig.5 Resonant switch flyback converter
(a) circuit
(b) equivalent circuit
220
S.M.P.S. Power Semiconductor Applications
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Fig.6 Resonant switch flyback converter
operating modes
(a) Mode 1: S close , D on
(b) Mode 2: S closed, D off
(c) Mode 3: S open, D off
(d) Mode 4: S open, D on
If it is assumed that the switch is closed before the current
in Lm has fallen to zero, then the initial equivalent circuit
will be as shown in Fig.6(a). The rate of rise of current in S
is determined by the value of La which, although small, is
much larger than the stray inductance that limits current
rise in a conventional switch. Turn-on losses are thus
significantly reduced. Co, being much larger than Ca, acts
as a voltage source (Vo) preventing current from flowing
intoCaandmaintaining aconstant rate of change of current
in Lm. Ia will increase linearly until it equals Im at which
time Io is zero and diode D turns off.
With D turned off, the equivalent circuit becomes as shown
in Fig.6(b). The resonant circuit, La, Ca and Lm, causes Ia
to increase sinusoidally to a peak and then fall back to zero.
S can then be opened again with very low losses.
With the switch open, the circuit is as shown in Fig.6(c).
The resonant action between Ca and Lmcauses energy to
be transferred fromthe capacitor to the inductor. Vc will fall,
passing through zero as Im reaches a peak, and then will
increase in the opposite direction until it exceeds Vo. At
which point D becomes forward biased, so it will turn on.
As D turns on (Fig.6(d)) the voltage across Ca becomes
clamped and Imnow flows into Co. Imfalls linearly until the
switch is closed again and the cycle repeats.
Voltage and current waveforms for a complete cycle of
operation are shown in Fig.7.
From the description of operation it can be seen that the
reduced switching losses result from:
- La acting as a di/dt limiter at switch on
- The resonant circuit La, Lm and Ca ensuring that the
current is zero at turn-off
These factors combine to allowthe switching devices to be
operated at higher frequencies and power levels than was
previously possible.
Circuit design
Correct operation of a resonant switch converter depends
on the choice of suitable values for the inductors and
capacitors. It is not possible to determine these values
directly but they can be selected using simple computer
models. An example of a model for a resonant switch
flyback converter is given below to demonstrate the basic
technique that can be used to analyse many different types
of resonant circuits. Writing the final computer programwill
be a simple task for anyone with proramming experience
and the model will run relatively quickly on even small
personnel computers.
Circuit analysis
Here we analyse the operation of a resonant flyback
converter circuit in mathemtical terms, assuming ideal
circuit components.
In the equivalent circuit of the flyback converter, Fig.5(b),
there are two switching elements S and D and the circuit
has four possible modes of operation:
Mode 1 S closed D on
Mode 2 S closed D off
Mode 3 S open D off
Mode 4 S open D on
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Fig.7 Waveforms for resonant switch flyback converter
Using Laplace analysis of the equivalent circuit for each
operating mode, equations can be written for Ia, Ic, Im, Io
and Vc.
J and U are the values of, Im and Vc respectively at the
start of each operating mode i.e. when t = 0.
Mode 1
Figure 6(a) shows the equivalent circuit when S is closed
and D is on. The large output capacitor Co as shown acts
as voltage source (Vo).
The equations are:
Mode 2
Figure 6(b) shows the equivalent circuit when S is closed
and D is off.
The equations are:
where,
Ia · J + A1.t +
A2 − A1
ω1
. sin(ω1.t )
Im · J + A1.t +
A3 − A1
ω1
. sin(ω1.t )
Ic · Ia − Im
Vc · U +
¸

¸
Lm.(Es − U) − La.U
La + Lm
_

,
.(1 − cos(ω1.t ))
Io · 0
Ia ·
Es − U
La
.t
A1 ·
Es
La + Lm
Im ·
U
Lm
.t + J
A2 ·
Es − U
La
Ic · 0
Vc · U
A3 ·
U
Lm Io · Im − Ia
222
S.M.P.S. Power Semiconductor Applications
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Mode 3
Figure6(c) shows the equivalent circuit when Sis open and
D is off.
The equations are:
where,
Mode 4
Figure6(d) shows the equivalent circuit when Sis open and
D is on.
The equations are
Computer simulation
Using the previous equations, it is possible to write a
computer program which will simulate the operation of the
circuit.
If S is closed before Imfalls to zero, then during a complete
cycle each of the operating modes occurs only once, in the
sequence mode 1 to mode 4.
The first functionof the programis todetermine the duration
of each mode.
Mode 1
The time between the switch turning on and the current Ia
reach Im is given by:
J1, theinitial valueof Imchosenbythedesigner, determines
the average output current. U1 is the initial value of Vc. If
Imis greater than zero, Dwill still be on so Vc and therefore
U1 will equal Vo.
Mode 2
The duration, T2, of the second mode cannot be found
directly and must be determined by numerical methods. T2
ends when Ia falls back to zero, so by successive
approximationof t inthe mode2equationfor Ia, it ispossible
to find T2.
J and U at the start of mode 2, i.e., J2 and U2, are found
by solving the mode 1 equations for Imand Vc respectivley
at t = T1.
For any given set of circuit values there is a value of J1
above which Ia will not reach zero. This condition has to be
detected by the program. Decreasing the value of La or
increasing the value of Lm or Ca will allowIa to reach zero.
Mode 3
Mode 3 operation ends when Vc = Vo. The duration, T3, is
given by:
where,
and J3 and U3 are the values of Im and Vc respectively at
the start of mode 3.
Mode 4
If the circuit operation is stable then the value of Im, when
Sis again closed, will equal J1 and the duration of the mode
will be
Where J4 and U4 are the values of Im and Vc at the start
of mode 4.
Calculation of Io and Vs
Having found the durations of the four modes, the average
output current in D can be calculated, from:
Peak, RMS and average values of the current in S (Ia) can
be determined by numerical analysis during modes 1 and
2. The voltage across S is given by
ω1 ·

¸

¸
La + Lm
Lm.Ca.La
_

,
Ia · 0
Im · J. cos(ω2.t ) +
U
Lm.ω2
. sin(ω2.t )
Ic · −Im
Vc · U. cos(ω2.t ) +
J
Ca.ω2
. sin(ω2.t )
Io · 0
ω2 ·

¸

¸
1
Lm.Ca
_

,
T3 ·
1
ω
2.
¹
'
¹
cos
−1
¸

¸
Vo
√ U3
2
+ A4
2
_

,
− tan
−1
¸

¸
A4
U3
_

,
¹
;
¹
Ia · 0
A4 ·
J3
Ca.ω2
Im · J +
U
Lm
.t
Ic · 0
Vc · U
Io · Im
T4 ·
Lm.(J4 − J1)
U4
Io(av) ·
T4.(J4 + J1) + T1.J1
2.(T1 + T2 + T3 + T4)
T1 ·
J1.Lm.La
Lm.(Es − Vo) − U1.La
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S.M.P.S. Power Semiconductor Applications
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These values will be needed when the components S and
D are chosen.
Conclusions
Resonant combinations of inductors and capacitors can be
used to shape the current and voltage waveforms in
switching converters. This shaping can be used to:
- reduce RFI and EMI,
- eliminate the effects of parasitic inductance and
capacitance,
- introduce a degree of self limiting under fault
conditions,
- reduce switching losses.
The resonant switch configuration is one way of reducing
switchinglossesinthe mainactivedevice. It canbeadapted
for use in all the standard square wave circuit topologies
and with all device types.
Although the analysis of resonant circuits is more complex
than the analysis of square wave circuits, it is still
straightforward if the operation of the circuit is broken down
into its different modes. Such an analysis will yield a set of
equationswhichcanbecombinedintoacomputer program,
toproduce amodel of the systemwhich canberunrelatively
quickly on even small computers.
Vs · Es − Vc
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S.M.P.S. Power Semiconductor Applications
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2.5.2. Resonant Power Supply Converters - The Solution For
Mains Pollution Problems
Many switch mode power supplies which operate directly
fromthe mains supply, use an electrolytic buffer capacitor,
after the bridge rectifier, to smooth the 100/120 Hz ripple
on the DC supply to the switching circuit. This capacitive
input filter causes mains pollution by introducing harmonic
currents and therefore cannot be used in supplies with
output powers above 165W. (TV, IEC norm 555-2, part 2:
Harmonics, sub clause 4.2).
The smoothing capacitor can be charged only when the
mains voltageis greater than the DCvoltage. Therefore the
input current will take the form of high amplitude, short
duration pulses. For comparison, the load current for a
220W resistive load (an RMS current of 1A for 220V
mains/line) and the load current for a 220W rectifier with
capacitive input buffer are shown in Fig. 1.
The peak value of the current with the capacitor load is 5
times higher than for the resistive load, while the RMS
current is doubled. It is understandable that the electricity
supply authorities do not like this kind of load, because it
results in high levels of harmonic current and apower factor
below 0.5. It is, therefore, necessary to find alternative
methods of generating a smooth DC voltage from the
mains.
The PRE-CONVERTER switched mode supply is one
possible solution. Such a converter can operate from the
unsmoothed rectified mains/line voltage and can produce
aDCvoltage with only asmall 100/120 Hz ripple. By adding
a HF transformer it is possible to produce any value of DC
voltage and provide isolation if necessary.
By proper frequency modulation of the pre-converter, the
input current can be made sinusoidal and in-phase with the
voltage. The mains/line now ’sees’ a resistive load, the
harmonic distortion will be reduced to very low levels and
the power factor will be close to 1.
A pre-converter has to be able to operate from input
voltages between zero (at the zero crossings) and the peak
value of mains/line voltage and still give a constant output
voltage. The SMPS converter that can fulfil these
conditions is the ’flyback’ or ’ringing’ choke converter. This
SMPSconverter has the boost and buck properties needed
by a pre-converter. However, the possibility of stability
problems under ’no load’ operation and its moderate
conversion efficiency, means that this converter is not the
most attractive solution for this application.
a) Resistive Load
b) Capacitor Filter
Fig. 1 Current taken from mains
The RESONANT POWER SUPPLY (RPS) has the right
properties for pre-converter systems. The boost and buck
properties of a resonant L-C circuit around its resonant
frequency are well known. In principle any current can be
boosted up to any voltage for a PARALLEL RESONANT
L-C circuit. Furthermore, the current and voltage wave
forms in a resonant converter are more or less sinusoidal,
resulting in a good conversion efficiency and there are no
stability problems at no load operating conditions.
Resonant pre-converter circuits
There are two basic resonant power supply (RPS)
principles that can be considered, namely:
- The SERIES RESONANT POWER SUPPLY (SRPS),
whereaseries resonant L-Ccircuit determines the noload
operation cycle time. The output power increases with
increasing operation cycle time (thus with decreasing
operation frequency).
Iin
1A/div
Iin
1A/div
225
S.M.P.S. Power Semiconductor Applications
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- The PARALLEL RESONANT POWER SUPPLY (PRPS),
where a parallel resonant L-C circuit determines the no
load operation cycle time. The output power increases
with decreasing operation cycle time (thus with increasing
operation frequency).
The basic SRPS converter circuit
A basic SRPS converter topology is shown in Fig. 2. For
simplicity in the following description, the input voltage Ep
is taken to be constant - 310 VDC for the 220VAC
mains/line. If the circuit is to appear as a ’resistive’ load to
the mains, then the output power of the pre-converter has
to be proportional to the square of the instantaneous value
of Ep. This means that the peak output power of the circuit
must be equal to twice the average output power. So a
250Wpre-converter has to be delivering 500W when Ep is
at its peak.
Fig. 2 Basic SRPS Pre-converter Circuit
In Fig. 2, the semiconductor switch S1 has an anti-parallel
diode D1 to avoid a negative voltages across S1.
Principally, a diode in series with S1 also gives a suitable
SRPS pre-converter, but it slightly increases the positive
peak voltage on S1 without giving an advantage over the
circuit with anti-parallel diode. The lower value of the RMS
current in S1 and thus the reduction in its on-state losses
is completely cancelled by increased turn-on losses in this
device.
Furthermore, stability problems can occur under no load
conditions for the circuit with series diode (infinitely small
current pulses inS1). The circuit with anti-parallel diodehas
no infinitely short current pulses under no load conditions,
because the positive current in S1 will be preceded by the
negative current in D1. As a result, no nett DC current is
supplied to the circuit at finite pulse widths.
The input inductance Lo forms the connection between the
input voltage and the switch voltage Vsw. A ’SERIES’
resonant L-C circuit, consisting of the capacitor Cp (when
bothS1andD1areOFF), the inductanceLs, the DCvoltage
blocking capacitor Cb and the capacitor Cs (when B1 is
OFF), determines the no load operation frequency. The
influence of the input inductance Lo can be neglected if its
value is several times that of Ls.
Apractical SRPSpre-converter for 250Wnett output power
(500W peak power conversion) can have component
values shown in Table 1.
Fig. 3 Waveforms of Basic SRPS Circuit
(Tcycle = 1.01 x Tref, no load, Ep = 310V)
Capacitor Cp changes the voltage waveform across switch
S1/D1 from the rectangular shape associated with SMPS
converters, to the sinusoidal shape of an SRPS converter.
Vsw
500V
/div.
Isw
5A/div
S1 D1
Lo Ls
Isw
Io
Vsw
Cb
Cs
Is
Vb
Vs
Cout
+Eo
0
Cp
Cin
+Ep
0
B1
Vs
500V
/div.
Is
5A/div
226
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Lo 4 mH 8 x Ls
Cp 16 nF Cs / 1.5
Ls 500 µH
Cs 24 nF
Cb 360 nF 15 x Cs
Tref 13.3 µs minimum cycle time
Table 1 Component Values for SRPS circuit
The output rectifier bridge B1 has been connected in
parallel with the output capacitor Cs. The whole converter
also can be viewed as a parametric amplifier, where the
switchS1or thediodeD1modulatethevalueof Cpbetween
Cp and infinity, while the output bridge B1 has similar
influence on the value of the capacitor Cs. Heavier load
means longer conduction of S1/D1 and of B1, so that some
automatic frequency adaptation of the SRPS circuit takes
place at operation frequencies below the no load resonant
frequency. The output power of the SRPS increases with
decreasing operation frequency.
Fig. 3shows time plots of someof the voltages andcurrents
of the basic SRPScircuit for theminimumONtimeof S1/D1.
Under no load operation, the voltage Vsw is a pure sine
wave superimposed on the input voltage with an amplitude
equal to this voltage. The operation cycle time is
approximately equal to the series resonant circuit cycle
time, Tref, for no load conditions. The voltage Vsw and Vs
and the current Is are sine waves with a low harmonic
distortion. The input current Io is a lowamplitude sine wave
and it has no DC component for zero load.
In order to give an impression of the boosting properties of
the SRPS converter, the no load voltages and currents for
an operation cycle time of 1.25 x Tref are plotted in Fig. 4.
Fig. 3 gives the minimum ’ON’ time condition for the S1/D1
switch and thus the minimum output voltage amplitude for
a given input voltage. The minimum ratio of the amplitude
of Vs and the input voltage Ep, with the component values
given earlier, has been found to be:
It will be obvious, that the value of the output voltage Eo
has to be in excess of the minimum amplitude of Vs. Thus:
A practical value of Eo has to be about 10% in excess of
this minimum value in order to deal with tolerances in
component values, thus:
Fig. 4 Waveforms of Basic SRPS Circuit
(Tcycle = 1.25 x Tref, no load, Ep = 310V)
To realise the situation shown in Fig. 4, the output voltage
Eo has to be increased considerably for no load operation
for the same Ep or Ep can be decreased considerably for
the same Eo. In fact, the relation between Eo and Ep in this
figure is found to be:
Vsw
500V
/div.
Isw
5A/div
Vs
500V
/div
Is
5A/div
Vs
Ep
· 0.7
Eo > 0.7 × Ep
Eo > 0.8 × Ep Eo > 2.7 × Ep
227
S.M.P.S. Power Semiconductor Applications
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Fig. 5 Waveforms of Basic SRPS Circuit
(Tcycle = 1.462 x Tref, 500W output, Ep = 310V)
Finally, Fig. 5 shows the voltages and currents for full load
(Pout = 500W) at Ep = 310V and Eo = 300V. The input
current Io is not shown but is a DC current of 1.6A with a
small ripple current. The cycle time has been increased to
1.45 x Tref to get the 500W output power, giving an
operating frequency of about 50 kHz.
It should be noted that S1 has to switch ’OFF’ a high current
at a relatively high dV/dt, resulting in significant turn-off
losses. These losses are the main reason to prefer PRPS
over SRPS for pre-converter applications.
The basic PRPS converter circuit
A basic PRPS converter topology is shown in Fig. 6. Just
as for the basic SRPS pre-converter, we will assume a DC
supply voltage Ep of 310 Vdc and a peak output power of
500W, i.e. a nett output power of 250W average.
The topology of Fig. 6 (PRPS) is almost identical to the
topology of Fig. 2 (SRPS), except for the following points:
- Diode D1 is now in series with the switch S1 instead of in
anti-parallel.
- Capacitor Cp has been omitted.
Fig. 6 Basic PRPS Pre-converter Circuit
The value of the two inductors Lo and Ls remain the same
as they were in the SRPS, but the values of Cb and Cs are
changed to obtain proper PRPS circuit operation. Having
D1 in series with S1 does not lead to ’no-load’ stability
problems because, in the PRPS circuit, both the amplitude
and the duration of the S1 current pulse are reduced as the
output power decreases.
The input inductance Lo again forms the connection
between the input voltage Ep and the switch voltage Vsw
(across D1 and S1 in series). A ’PARALLEL’ resonant L-C
circuit, consisting of the series connection of Lo and Ls, the
DC voltage blocking capacitor Cb and the capacitor Cs
(both the switch S1 and the diode bridge B1 OFF) now
determines the no load operation frequency. The value of
the input capacitor Cin is chosen to be sufficiently large with
respect to Cs to be neglected with respect to the no load
operation frequency.
Apractical PRPSpre-converter for 250Wnett output power
(500Wpeak power) can have component values as shown
in Table 2.
Vsw
500V
/div.
Isw
5A/div
S1
D1
Lo Ls
Isw
Io
Vsw
Cb
Cs
Is
Vb
Vs
Cout
+Eo
0
Cin
+Ep
0
B1
Vs
500V
/div.
Is
5A/div
228
S.M.P.S. Power Semiconductor Applications
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Lo 4 mH 8 x Ls
Ls 500 µH
Cs 24 nF
Cb 48 nF 2 x Cs
Table 2 Component Values for PRPS circuit
To be able to put a full wave rectifier across capacitor Cs,
the DC voltage blocking capacitor Cb cannot have a value
of several times Cs. Therefore, a value of only twice Cs has
been chosen for Cb. This ratio gives good practical results
in combination with an output voltage, Eo, of 450V.
The parallel L-C circuit consists of series combinations of
Lo and Ls and Cb and Cs. The output rectifier bridge now
modulates the value of the capacitor between 2/3 Cs and
2 Cs (Cb and Cs in series and Cb only). It should be noted
that the resonant frequencies of the two states differ by a
factor of .
The switch S1 modulates the inductance value of the
parallel L-C circuit between Lo + Ls and Ls. This is
combined with a change in input voltage fromzero (S1 ON)
and Ep (S1 OFF). Again, the PRPS can be seen as a
parametric amplifier, but now with both inductance and
capacitance modulation.
In contrast with the SRPS circuit, the output power of a
PRPS converter will increase with increasing operation
frequency, thus with decreasing operation cycle time.
Under no load conditions and maximum operation cycle
time, the output voltage and current will be near sinusoidal
and will have their minimum no load values. This minimum
output voltage can be calculated from
Substituting the values for Lo, Ls, Cb and Cs in the formula
gives
An output voltage choice of Eo = 450 V for Ep = 375 V will,
therefore, be amply sufficient.
The voltage Vsw, the current Isw, the output voltage Vs and
the current Is for the maximum operation cycle time, i.e.
about equal to Tref, are shown in Fig. 7.
Toget an impressionof theboosting propertiesof the PRPS
circuit, the no load voltages and currents are shown, for an
operation cycle time Tcycle = 0.975 x Tref, in Fig. 8. It can
be seen that the output voltage has been increased by a
factor 2.5 with only avery small decrease of operation cycle
time.
Fig. 7 Waveforms of Basic PRPS Circuit
(Tcycle = 0.995 x Tref, no load, Ep = 310V)
Finally, the full load voltages and currents are shown in Fig.
9 (output power 500W at Eo = 450V and Ep = 310V). It
should be noted that the operation cycle time has been
decreased to .5694 x Tref.
Vsw
500V
/div.
Isw
5A/div
√3
Vs
500V
/div.
Vs > Ep.
(Lo + Lp)
Lo
.
Cb
(Cb + Cs)
Is
5A/div
Vs > 0.75 × Ep
229
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
The significant featureof the PRPScircuit is that the current
in the main switching device S1 is brought down to zero by
the circuit and not by the device itself. Device S1 can now
be turned off without loss. The negative voltage which
causes the current to fall, is supported by diode D1, which
needs to be a fast recovery type like the BYR79. The
reverse recovery loss in D1 is small because the resonant
action of the circuit make the rate of fall of current relatively
slow - up to two orders of magnitude slower than in a
standard SMPS.
SRPS and PRPS compared
A pre-conditioner can be implemented using either an
SRPSor PRPStopology. Thecapacitor andinductor values
are roughly the same, as are the peak values of voltage
and current. The main difference between the circuits is in
the switching requirements of S1 and D1.
In the SRPS, the turn on loss of S1 is very low - the voltage
across S1 is zero and the current rises relatively slowly.
However the turn off loss is large - S1 has to turn off a large
current and, although the dVsw/dt is moderated by Cp it is
still relatively fast. On the other hand, the turn off loss in D1
is negligible - no voltage is applied to the diode until S1 is
turned off giving plenty of time for reverse recovery - but
the turn on loss may be significant because the dIsw/dt is
un-restrained.
In the PRPScircuit, however, the turn off loss in S1 is close
to zero but the recovery loss in D1 is not negligible - Isw
falls through zero and the negative voltage appears across
the diode. S1 is turned on from a high voltage so there will
be some loss in both S1 and D1 even though the rate of
rise of current is moderated by Ls.
It is generally true that reducing turn off loss produces a
bigger cost/performance benefit than reducing turn on loss.
It is also true that losses in diodes are usually much lower
than in their associated switching device. Since the PRPS
configuration reduces turn off loss in S1 to zero it appears
that PRPS is a better choice than SRPS as a resonant
pre-converter.
Therefore, the remainder of this paper will concentrate on
PRPS circuits.
PRPS transformer for >1kW
The practical PRPS circuits in this paper all use a
transformer with abuilt-in leakage inductance to give mains
isolation and inductance Ls. The inexpensive U-64 core,
used in large quantities in the line deflection and EHT
circuits in colour TV sets, can be used successfully as the
transformer core in PRPS converters with a nett output
power in excess of 1000W.
Fig. 8 Waveforms of Basic PRPS Circuit
(Tcycle = 0.975 x Tref, no load, Ep = 310V)
Fig. 10 illustrates a PRPS transformer constructed with a
pair of U-64 cores. Both the primary and secondary
windings are split into two halves. Each leg of the U-core
is fitted with a two-chamber coil former with a primary and
a secondary winding. To achieve a reasonable ’leakage
Vsw
500V
/div.
Isw
5A/div
Vs
500V
/div.
Is
5A/div
230
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
inductance’ Ls, the primary and secondary coils are
crossed. Thus each U-core has one primary and one
secondary coil.
A pre-converter transformer with this arrangement offers
several advantages over the ’standard’ SMPS transformer
using E-cores.
s
Fig. 9 Waveforms of Basic PRPS Circuit
(Tcycle = 0.5694 x Tref, 500W output, Ep = 310V)
- It will be easier to meet the mains isolation requirements,
particularly with respect to creepage distances.
- The thermal properties will be much better because the
winding is distributed over both core legs.
- The mean length of a turn is less than with a single core
leg, reducing copper loss.
- The two leg arrangement will need only 70% of the turns
of the one leg design. This is because of the active
(magnetic) fluxing of both legs.
- It is a simpler and hence less expensive transformer to
wind.
One disadvantage of this arrangement is that the windings
are not layered. This means that ’skin effect’ will have to be
overcome by using Litz wire for both the primary and
secondary windings.
a) Cross Section
b) Winding connection
Fig. 10 PRPS transformer using U-64 cores
Vsw
500V
/div.
Isw
5A/div
U64 core 3C8
U64 core 3C8
P1
P2
S1
S2
airgap
Vs
500V
/div.
S1
P1
In
In
P2
S2
Out
Out
Is
5A/div
231
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
The equivalent electrical circuit diagram of the PRPS
transformer is given in Fig. 11. It is the well known ’Tee’
circuit with primary winding(s) leakage inductance Llp, a
magnetisation inductance Lm and secondary winding(s)
leakage inductance Lls, followed by an ’ideal’ transformer
for the output voltage transformation.
Fig. 11 PRPS transformer equivalent circuit
The primary and secondary leakage inductance is
determined by the transformer construction and, in
particular, by the positioning of the windings. In the
symmetrical arrangement of Fig. 10, the values of Llp and
Lls will be equal. Llp and Lls are also proportional to the
square of the number of primary turns as is Lm. However,
Lm is also strongly dependent on the width of the ’airgap’
between the two U-cores. The airgap can be adjusted to
give a value of Lm between 2 and 100 times Llp+Lls.
The transformer can be characterised by two inductance
measurements:
- Lx, the measured primary inductance with the secondary
winding(s) shorted.
- Ly, the measured primary inductance with the secondary
winding(s) open circuit
It can be seen from the equivalent circuit diagram that,
If the transformer is assumed to be symmetrical then,
rearranging gives,
If the airgap is <50µm then Lm will be at least 100 times
the value of Llp or Lls. In this case,
and
Fig. 12 PRPS pre-converter for 250V output
A PRPS pre-converter transformer for 1250W nett output
has been constructed to the arrangement shown in Fig. 10.
It had a primary consisting of two 36 turn windings
connected in series, wound using 600 x 0.07mm Litz wire.
The number of turns on the secondary varied depending
on the required output voltage. Measurements of this
transformer gave the following values for Lx and Ly.
Lx = 200 µH
Ly = 1600 µH (Note that this value is strongly influenced by
the size of the airgap)
PRPS pre-converter for high output
voltages
The circuit shown in Fig. 12 is a PRPS pre-converter using
the type of transformer mentioned earlier. This circuit is
intended to deliver 1250W at a relatively high voltage - in
this case 250V. To achieve an final output voltage of 250V
with an effective output voltage, Eo, of 450V means having
a transformer with a turns ratio of 8:5.
Cf1 2µF 2 x 1µF
Cin 2µF 2 x 1µF
Cb1 0.2µF 2 x 0.1µF
Cb2 1.36µF 2 x 0.68µF
Cs 0.3µF 2 x 0.15µF
Lf 1600µH
Lo 1600µH
Lx 200µH
Ly 1600µH
Table 3 Component Values for High Output Voltage
PRPS circuit
Thetransformer has replacedtheinductance Lsinthe basic
circuit diagramof Fig. 6. The DCvoltage blocking capacitor
Cb has been split up into a primary blocking capacitor Cb1
and a secondary blocking capacitor Cb2. There will,
therefore, be no DC current in Tr1 so in principle the
transformer does not needan air gap. However, experience
Lx ≈ Llp + Lls
Ly ≈ Lm
S1
D1
Lo
Isw
Io
Vsw
Cb1
Cs
Vb1
Cout
+Eo
0
Cin
Cb2
Vb2
Ipr
Cf1
Lf
Isec
B1
Llp Lls
Lm
ideal
In
Out
Lx · Llp +
Lm.Lls
Lm + Lls
Ly · Llp + Lm
Llp · Lls
Llp · Ly − √ Ly
2
− Lx.Ly
Lm · √ Ly
2
− Lx.Ly
232
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Fig. 13 Waveforms of high voltage pre-converter
(Tcycle=0.7446 x Tref, 2.5kW output, Ep=310V)
has shown that a limited value of magnetisation inductance
improves the operation of the circuit, so an airgap has been
included which keeps the Ly value, of Tr1, equal to Lo.
The pre-converter circuit has been completed by the
addition of capacitor Cf1, rectifier bridge and filter inductor
Lf (an iron cored choke). The combination of Cf1, Lf, Cin
and Lo prevents a significant switching frequency signal
appearing at the mains terminals.
The component values shown in table 3 are used in the
circuit of Fig. 12. With these values the no load reference
cycle time will be 49.7 µs. Therefore, the no load operating
frequency is just over 20 kHz.
Figs. 13 and 14 show the waveforms associated with the
circuit when the input voltage is 310 V and the circuit is
delivering 2.5 kW
Ep Pout Pout % Deviation
(PRPS) (R load)
310.0 2501 2501 0.0%
308.3 2476 2474 0.1%
303.2 2389 2392 -0.1%
294.8 2249 2262 -0.6%
283.2 2068 2087 -0.9%
268.5 1857 1876 -1.0%
250.8 1621 1637 -1.0%
230.4 1375 1382 -0.5%
207.4 1128 1119 0.8%
182.2 890 864 3.0%
155.0 668 625 6.8%
126.1 472 414 14.1%
95.8 305 239 27.7%
64.5 171 108 57.9%
32.4 70 27 156.2%
Table 4 Output power of PRPS pre-converter.
Of particular interest isIobecauseit canbeeasilymeasured
with a lowvalue resistor. This current will be used to control
power output of the PRPS pre-converter. Io will be
compared with a reference, Ioref, which will be proportional
to input voltage Ep. The comparison of Io and Ioref should
be done at the right time, namely during the period when
Io has a negative slope. The switch S1 is turned ON as
soon as the value of Io drops below Ioref.
The computed values of Pout for 15 values of Ep which
would be achieved using this control strategy are given in
Table 4. As a comparison the output power for a resistive
load is also shown in Table 4.
It can be seen from Table 4, that the PRPS output power
closely matches the power of a purely resistive load except
for Ep values near the zero crossings of the mains/line
voltage.
Of course, an average output power control loop (with a
time constant far in excess of the 10 (8.3) ms cycle time of
a half mains/line period) is required to determine the
Vsw
500V
/div.
Isw
10A/div
Vs
500V
/div.
Isec
15A/div
233
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Fig. 14 Waveforms of high voltage pre-converter
(Tcycle=0.7446 x Tref, 2.5kW output, Ep=310V)
proportionalityconstant betweenthemains/linevoltageand
Ioref for the mains/line voltage variations and for the output
power control.
It can also be concluded, fromtable 4, that the PRPScircuit
can indeed fulfil the pre-converter action successfully, i.e.
a resistive load for the mains voltage can be easily
achieved, thusno mains distortion andapower factor >0.99
is possible.
The circuit shown in Fig. 12 is only suitable for high output
voltages. At low output voltages (below 100V for output
powers in excess of 1000W), the secondary blocking
capacitor Cb2 has to have a high value and pass a large
current and is, therefore, an expensive component. If a low
output voltagepre-converter isrequired, thenan alternative
arrangement is needed.
PRPS pre-converter for low output
voltages
The high cost of Cb2, in a low output voltage PRPS
pre-converter, could be avoided if it could be eliminated
from the circuit. The problem is that removing Cb2 allows
a DC current to flow in the transformer. The resulting flux
can be handled by increasing the airgap between the cores
of the transformer. This will have the additional effect of
reducingLyfrom1600 µHto800 µH. This changehas been
incorporated in the circuit shown in Fig. 15, which is
intended to deliver 1200W at 60V.
Fig. 15 PRPS pre-converter for 60V output
To get 1200Wnett froma transformer of the type shown in
Fig. 10 it is necessary to change the number of primary
turns Np andthus decrease the value of Lx. Suitable values
would be:
Np (primary turns) 2 x 28 (600 x .07 mm Litz wire)
Ns (secondary turns) 2 x 4 (flat Litz wire 7 mm2)
The air gap in the transformer should be adjusted to give
an Lx of 125 µH.
Suitable values for the other components are given in table
5. The reference cycle time, Tref, with these values will be
39 µs.
The inductance Lo can be made with either a pair of U-64
cores - with the winding distributed over both legs- or with
a pair of E-cores.
Vb1
500V
/div.
Ipr
10A/div
Vb2
500V
/div.
S1
D1
Lo
Isw
Io
Vsw
Cb1
Cs
Vb1
Cout
+Eo
0
Cin
Ipr
Cf1
Lf
Isec
B1
Io
10A/div
234
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Cf1 2µF 2 x 1µF
Cin 2µF 2 x 1µF
Cb1 0.15µF
Cs 3.75µF 5 x 0.75µF
Lf 1600µH
Lo 1600µH
Table 5 Component Values for Low Output Voltage
PRPS circuit
In practice, PRPS pre-converters produce about 150W for
each Amp(rms) flowing in the primary winding. So for a
1200W converter:
Ipr = 8A
Isec = 56A (at 60V and 20A)
The voltage and current wave forms for the circuit of Fig.
15 are similar to those shown in Figs. 13 and 14, except for
the amplitudes in the secondary side.
This configuration of PRPS pre-converter is viable for
output voltages as low as 40 V. Below this, however, the
value and current rating of Cs becomes excessive and it is
likely that alternative configurations would be more cost
effective.
Control circuit for PRPS converters
Figure 16 shows a simple control circuit for PRPS
converters. In is constructed from MOS ICs and standard
comparators. The analogue control section for the output
power stabilisation is not shown because it will, in principle,
be no different than for an SMPS converter.
The PRPS control circuit comprises of a dual sawtooth
oscillator whose frequency can be adjusted by applying a
voltage to X1. The output of this oscillator is fed to the clock
pulse input of a divide-by-8 counter. The highest oscillator
frequency needs to be just over 8x the highest expected
operating frequency of the PRPS power section.
The oscillator can be stopped by applying a hold up signal
(low) toG1. This hold-up input is used to modulate the cycle
time of the control circuit. As soon as this ’hold up’ signal
is removed (high), a pulse will sent to the divide-by-8 circuit
which then advances one position.
The counter has 8 outputs, Q0-Q7. Output Q0 will go high
either synchronously following Q7 or asynchronously with
a high on pin15. Output Q0 sets a flip-flop consisting of a
2anda3input NOR-gate. The output terminal X8thengoes
high to indicate that the main switching device S1 should
turn on.
Fig. 16 PRPS control circuit
-
+
-
+
-
+
-
+
-
+
-
+
+
+
+
+
+
+
+
+
+
+
+
+
X2
X3
X4
X5
X6
X1
X8
X7
HEF4022B
13
14
15
Q7 Q5 Q0
G1
G2
G3
G4
G5
G6
G7
-
+
-
+
235
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
The Q7 output is used to enable both the ’hold-up’ signal
for the oscillator and the reset input for the divide-by-8, i.e.
both the ’hold-up’ and the reset only can be active if there
is a ’1’ at Q7. The output flip-flop is reset either by the
negative voltage across S1-D1 - via comparator G3 - or by
the sixth position, Q5, of the counter. To prevent the
possibility of immediate reset of the flip-flop, the indication
of negative voltage across S1-D1 is blanked out while Q0
is high.
The voltage across S1-D1 is connected to terminal X6 via
a high value resistor (220 kΩ). X4 is connected to the
negative supply line of the power circuit. Comparator G3
then gives logical information about the polarity of the
voltage across S1-D1.
Information about the amplitude of this voltage is obtained
via comparator G4. A reference voltage, proportional to the
mains voltage, is connected to X5. If the attenuated S1-D1
voltage falls below this reference, and Q7 is high, the
counter will be reset and S1 will be turned ON. This is an
emergency measureincase the normal current control loop
via the comparator G2 fails to disable the ’hold up’ signal.
This could occur if there were a false current reference
signal at X2.
The best strategy for the control of a PRPS pre-converter
is by comparing the current, Io, in the input inductor, Lo,
with a mains proportional reference current. In Fig. 16 a
signal, proportional to Io, is connected to X3 and the
reference signal to X2. As soon as Io falls below the
referencevalue the ’hold-up’ signal is removed, the counter
is advanced from Q7 to Q0 and S1 is turned ON.
A ’1’ at input X7 allows the control circuit to run, whereas a
’0’ will cause the PRPS to switch OFF in a controlled
manner. When X7 goes high, the output of NAND gate G7
goes low. This signal is used to reset the counter which
takes Q0 high, turns on S1 and starts the operating cycle.
The output of G5, which was pulled high while the circuit
was stopped, is now driven low and is kept low by the RC
network as long as S1 continues to be switched. This ’low’
keeps the output of G7 high and allows the correct signal
to be fed from G4 to the counter reset. The high on X7 also
enables G6 and lets the information fromG2 - the ’current’
comparator - through to the ’hold up’ circuit.
If X7 is taken low then G6 is disabled and the signal which
would start the next switching cycle is not allowed to get
through. The counter will continue to run until Q7 goes high
at which time the circuit will be ’held up’ and the operating
cycle will be halted.
The cycle time will be adjusted by changing the reference
value at X2. This signal will be a series of half sinewaves
whose peak value is proportional to the power that the
pre-converter needs to deliver to the keep the output
voltageat the required level. This control strategy has been
tested on various PRPS circuits and fulfils all the
requirements properly.
Modelling PRPS pre-converters
There are no equations which summarise the overall
behaviour of a PRPS pre-converter circuit. Determining
factors like the throughput power of the circuit and the peak
voltages and currents, means developing a computer
model. In this model the operation of the circuit is broken
downintoitsseparatemodesandtheappropriateequations
derived for each of them.
The circuit of Fig. 6 has, basically, two switches which
determineitsmode of operation. The first isthe combination
of S1andD1- this isthe controllableswitch- andthesecond
is the bridge rectifier B1.
Therefore the circuit has four different modes of operation.
For all these modes, the time functions for the currents and
voltages can be derived by circuit analysis. The four modes
are given below:
Mode S1-D1 Bridge
I ON ON
II ON OFF
III OFF OFF
IV OFF ON
Table 6 PRPS Operating Modes
Using Laplace transformation it is possible to derive the
time functions for currents Io and Is, for the circuit in each
of its 4 modes. This method allows the initial values of the
currents and voltages to be easily introduced into the
equations. The initial conditions of Io, Is, Vb1 and Vs will
be indicated by Jo, Js, Ub1 and Us respectively.
Mode I
We will start with the derivation of the time functions for the
operation of the PRPS circuit in mode I (S1-D1 ON and B1
ON). The initial conditions are:
Calculation starts at t = 0 with the switching ON of S1-D1,
while B1 is already conducting, i.e. . The following
Laplace equations are then valid:
Io · Jo
Is · Js · −Jo
Vb1 · Ub1
Vs · Us · Eo
Jo > 0
Ep
s
+ Lo.Jo · Io.s.Lo
236
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Note: B1 is conducting, so , i.e. Cs is infinitely
large and has no influence on Is.
If we define the following:
The Laplace equations for Io and Is can then be written as:
The inverse Laplace transformation of these two equations
gives the following time functions:
To calculate the input power and the voltage Vb1 and Vs,
thesetime functions canbeintegrated togive Ioint andIsint,
thus:
The input power during the validity of mode I (i.e. during a
time interval of length T1) is equal to:
The voltages Vb1 and Vs are equal to:
In the computer program, these formulae will be stored in
a subroutine called sub1.
Mode II
The initial conditions for mode II operation (S1-D1 ON and
B1 OFF) are:
(either +Eo or -Eo)
The Laplace equations for Io and Is are now:
Define:
The Laplace functions for Io and Is are now identical to
those for mode I, so the time functions are:.
In the computer program, these formulae will be stored in
a subroutine called sub2.
Ub1 + Us
s
+ Ls.Js · Is.
¸

¸
s.Ls +
1
s.Cb1
_

,
Vs · Us · Eo
Io · Jo
Is · Js
ω ·

1
Ls.Cb1
Vb1 · Ub1
Vs · Us
F1 · Jo
F2 ·
Ep
Lo Ep
s
+ Lo.Jo · Io.s.Lo
G1 · Js
(Ub1 + Us).s + Ls.Js · Is.
¸

¸
s.Ls +
Cb1 + Cs
s.Cb1.Cs
_

, G2 ·
Ub1 + Us
Ls
ω ·

Cb1 + Cs
Ls.Cb1.Cs
Io ·
F1
s
+
F2
s
2
F1 · Jo
Is ·
G1.s
s
2
+ ω
2
+
G2
s
2
+ ω
2
F2 ·
Ep
Lo
G1 · Js
Io · F1 + F2.t
G2 ·
Ub1 + Us
Ls
Is · G1. cos(ω.t ) +
G2
ω
. sin(ω.t )
Io · F1 + F2.t
Is · G1. cos(ω.t ) +
G2
ω
. sin(ω.t )
Ioint · F1.t +
F2
2
.t
2
Ioint · F1.t +
F2
2
.t
2
Isint ·
G1
ω
. sin(ω.t ) +
G2
ω
2
.(1 − cos(ω.t ))
Isint ·
G1
ω
. sin(ω.t ) +
G2
ω
2
.(1 − cos(ω.t ))
Pin(T1) ·
Ep.Ioint
T1
Pin(T2) ·
Ep.Ioint
T2
Vb1 · Ub1 −
Isint
Cb1
Vb1 · Ub1 −
Isint
Cb1
Vs · Us −
Isint
Cs Vs · Us · Eo
237
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
Mode III
The initial conditions for mode III operation (S1-D1 OFF
and B1 OFF) are:
The correct Laplace equation for Is ( ) can be
expressed by the relationship:
Define:
The time functions can then be expressed by:
In the computer program, these formulae will be stored in
a subroutine called sub3.
Mode IV
The initial conditions for the mode IVoperation (S1-D1 OFF
and B1 ON) are given below:
The Laplace equation for current Is is now:
Define:
The time functions are given by,
In the computer program, these formulae will be stored in
a subroutine called sub4.
Program structure
The modelling program can be written around the four
subroutines. The central part of the program will make
successive calls to the appropriate subroutine. The
calculated values of current and voltage will be used to
determine when the circuit moves form one mode to the
next. The final values of Io, Is, Vb1 and Vs will be used as
the initial values, Jo, Js, Ub1 and Us, for the next mode.
The actual sequence of the modes depends upon the
operating frequency and load condition. Under full load
condition when Ep is not close to zero, the sequence of
modes will be as shown in Table 7.
One cycle of operation ends when Io falls below Ioref. This
would result in S1 being turned ON, putting the circuit in to
mode I and starting the cycle once more. At the end of each
cycle, the input power can be compared with a reference
value (Pref) and Ioref can be adjusted until the powers are
equal. It is then possible to read various important values
Vs · Us · Eo
Ub1 + Us − Ep
s
+ (Lo + Ls).Js · Is.
¸

¸
s.(Lo + Ls) +
1
(s.Cb1)
_

,
Io · Jo
Is · Js · −Jo
Vb1 · Ub1
ω ·

1
(Lo + Ls).Cb1
Vs · Us
G1 · Js
Io · −Is
G2 ·
Ub1 + Us − Ep
Lo + Ls Ub1 + Us − Ep
s
+ (Lo + Ls).Js · Is.
¸

¸
s.(Lo + Ls) +
Cb1 + Cs
s.Cb1.Cs
_

,
Is · G1. cos(ω.t ) +
G2
ω
. sin(ω.t )
ω ·

Cb1 + Cs
(Lo + Ls).Cb1.Cs
Io · −Is
G1 · Js
Isint ·
G1
ω
. sin(ω.t ) +
G2
ω
2.
(1 − cos(ω.t ))
G2 ·
Ub1 + Us − Ep
Lo + Ls
Ioint · Isint
Pin(T4) ·
Ep.Ioint
T4
Is · G1. cos(ω.t ) +
G2
ω
. sin(ω.t )
Vb1 · Ub1 −
Isint
Cb1
Io · −Is
Isint ·
G1
ω
. sin(ω.t ) +
G2
ω
2.
(1 − cos(ω.t )) Vs · Us
Ioint · Isint
Pin(T3) ·
Ep.Ioint
T3
Vb1 · Ub1 −
Isint
Cb1
Vs · Us −
Isint
Cs
Io · Jo
Is · Js · −Jo
Vb1 · Ub1
238
S.M.P.S. Power Semiconductor Applications
Philips Semiconductors
S1-D1 B1 Mode End Condition
ON ON I Is>0
ON OFF II Vs<-Eo
ON ON I Is<0
ON OFF II Isw=Io+Is<0
OFF OFF III Vs>Eo
OFF ON IV Io<Ioref
Table 7 PRPS Operating Sequence
such as the initial conditions for Io, Is, Vb1, Vs, the cycle
time, output power, RMS values of Io and Is, DC and AC
fluxes in the ferrite cores, etc.
Writing a program like this is well within the capabilities of
anyone with some experience of programming. The
calculations involved are so simple that there will be little
difficulty in using almost any programming language. A
model producedin this way will be faster andmore accurate
than could be produced with any of the standard modelling
programs.
Conclusions
The PRPS configuration is well suited to the needs of the
pre-converter application. It can boost the low mains
voltages, near zero crossing, to high levels so that some
power is delivered to the load throughout all of the mains
cycle. This helps the PRPS appear as a resistive load to
the mains.
APRPS pre-converter can deliver a DCoutput voltage with
low levels of mains ripple using only moderately sized
output smoothing capacitors. The addition of a high
frequency transformer gives mains isolation and the ability
to have a wide range of output voltages.
The transformer need not be a major additional cost. The
high operating frequency means the transformer uses
ferrite core and is relatively small (5% of the size of copper
/ iron transformer). A side by side arrangement of the
windings means the transformer is easy to wind, easy to
insulate and can have the right leakage inductance to
replace the resonant network inductor.
The resonant action of the PRPS circuit allows the main
semiconductor switching device to be turned off at zero
current. This reduces, considerably, the switching loss of
this device allowing a smaller device to be used in higher
power / frequency circuits than it could normally resulting
in a significant cost saving.
Unfortunately an overall analysis of the performance of a
PRPS pre-converter is difficult. However, by breaking the
cycle of operation into its logical modes, it becomes easy
to generate the time functions for all the currents and
voltages. It is simple to incorporate these equations into a
computer program to produce an accurate, detailed and
fast running model of the system.
The use of pre-converters is become increasingly
necessary and the characteristics of PRPS circuits mean
that there are well suited to this function. It is easy to
overcome the apparent complexity of resonant systems to
produce PRPS pre-converters which are elegant, efficient
and cost effective.
239
Preface Power Semiconductor Applications
Philips Semiconductors
Acknowledgments
We are grateful for all the contributions fromour colleagues within Philips and to the Application Laboratories in Eindhoven
and Hamburg.
We would also like to thank Dr.P.H.Mellor of the University of Sheffield for contributing the application note of section 3.1.5.
The authors thank Mrs.R.Hayes for her considerable help in the preparation of this book.
The authors also thank Mr.D.F.Haslam for his assistance in the formatting and printing of the manuscripts.
Contributing Authors
N.Bennett
M.Bennion
D.Brown
C.Buethker
L.Burley
G.M.Fry
R.P.Gant
J.Gilliam
D.Grant
N.J.Ham
C.J.Hammerton
D.J.Harper
W.Hettersheid
J.v.d.Hooff
J.Houldsworth
M.J.Humphreys
P.H.Mellor
R.Miller
H.Misdom
P.Moody
S.A.Mulder
E.B.G. Nijhof
J.Oosterling
N.Pichowicz
W.B.Rosink
D.C. de Ruiter
D.Sharples
H.Simons
T.Stork
D.Tebb
H.Verhees
F.A.Woodworth
T.van de Wouw
This book was originally prepared by the Power Semiconductor Applications Laboratory, of the Philips Semiconductors
product division, Hazel Grove:
M.J.Humphreys
C.J.Hammerton
D.Brown
R.Miller
L.Burley
It was revised and updated, in 1994, by:
N.J.Ham C.J.Hammerton D.Sharples
Preface Power Semiconductor Applications
Philips Semiconductors
Preface
This book was prepared by the Power Semiconductor Applications Laboratory of the Philips Semiconductors product
division, Hazel Grove. The book is intended as a guide to using power semiconductors both efficiently and reliably in power
conversion applications. It is made up of eight main chapters each of which contains a number of application notes aimed
at making it easier to select and use power semiconductors.
CHAPTER 1 forms an introduction to power semiconductors concentrating particularly on the two major power transistor
technologies, Power MOSFETs and High Voltage Bipolar Transistors.
CHAPTER 2 is devoted to Switched Mode Power Supplies. It begins with a basic description of the most commonly used
topologies and discusses the major issues surrounding the use of power semiconductors including rectifiers. Specific
design examples are given as well as a look at designing the magnetic components. The end of this chapter describes
resonant power supply technology.
CHAPTER 3 describes motion control in terms of ac, dc and stepper motor operation and control. This chapter looks only
at transistor controls, phase control using thyristors and triacs is discussed separately in chapter 6.
CHAPTER 4 looks at television and monitor applications. A description of the operation of horizontal deflection circuits is
givenfollowed by transistor selection guides for both deflectionand power supply applications. Deflection and power supply
circuit examples arealsogivenbasedoncircuitsdesignedbytheProduct Concept andApplicationLaboratories(Eindhoven).
CHAPTER5 concentrates on automotive electronics looking in detail at the requirements for the electronic switches taking
into consideration the harsh environment in which they must operate.
CHAPTER6 reviews thyristor andtriac applications fromthe basics of device technology and operation to the simple design
rules which should be followed to achieve maximum reliability. Specific examples are given in this chapter for a number
of the common applications.
CHAPTER 7 looks at the thermal considerations for power semiconductors in terms of power dissipation and junction
temperaturelimits. Part of this chapter is devotedto worked examples showing howjunctiontemperatures can becalculated
to ensure the limits are not exceeded. Heatsink requirements and designs are also discussed in the second half of this
chapter.
CHAPTER 8 is an introduction to the use of high voltage bipolar transistors in electronic lighting ballasts. Many of the
possible topologies are described.
Contents Power Semiconductor Applications
Philips Semiconductors
Table of Contents
CHAPTER 1 Introduction to Power Semiconductors 1
General 3
1.1.1 An Introduction To Power Devices ............................................................ 5
Power MOSFET 17
1.2.1 PowerMOS Introduction ............................................................................. 19
1.2.2 Understanding Power MOSFET Switching Behaviour ............................... 29
1.2.3 Power MOSFET Drive Circuits .................................................................. 39
1.2.4 Parallel Operation of Power MOSFETs ..................................................... 49
1.2.5 Series Operation of Power MOSFETs ....................................................... 53
1.2.6 Logic Level FETS ...................................................................................... 57
1.2.7 Avalanche Ruggedness ............................................................................. 61
1.2.8 Electrostatic Discharge (ESD) Considerations .......................................... 67
1.2.9 Understanding the Data Sheet: PowerMOS .............................................. 69
High Voltage Bipolar Transistor 77
1.3.1 Introduction To High Voltage Bipolar Transistors ...................................... 79
1.3.2 Effects of Base Drive on Switching Times ................................................. 83
1.3.3 Using High Voltage Bipolar Transistors ..................................................... 91
1.3.4 Understanding The Data Sheet: High Voltage Transistors ....................... 97
CHAPTER 2 Switched Mode Power Supplies 103
Using Power Semiconductors in Switched Mode Topologies 105
2.1.1 An Introduction to Switched Mode Power Supply Topologies ................... 107
2.1.2 The Power Supply Designer’s Guide to High Voltage Transistors ............ 129
2.1.3 Base Circuit Design for High Voltage Bipolar Transistors in Power
Converters ........................................................................................................... 141
2.1.4 Isolated Power Semiconductors for High Frequency Power Supply
Applications ......................................................................................................... 153
Output Rectification 159
2.2.1 Fast Recovery Epitaxial Diodes for use in High Frequency Rectification 161
2.2.2 Schottky Diodes from Philips Semiconductors .......................................... 173
2.2.3 An Introduction to Synchronous Rectifier Circuits using PowerMOS
Transistors ........................................................................................................... 179
i
Contents Power Semiconductor Applications
Philips Semiconductors
Design Examples 185
2.3.1 Mains Input 100 W Forward Converter SMPS: MOSFET and Bipolar
Transistor Solutions featuring ETD Cores ........................................................... 187
2.3.2 Flexible, Low Cost, Self-Oscillating Power Supply using an ETD34
Two-Part Coil Former and 3C85 Ferrite .............................................................. 199
Magnetics Design 205
2.4.1 Improved Ferrite Materials and Core Outlines for High Frequency Power
Supplies ............................................................................................................... 207
Resonant Power Supplies 217
2.5.1. An Introduction To Resonant Power Supplies .......................................... 219
2.5.2. Resonant Power Supply Converters - The Solution For Mains Pollution
Problems .............................................................................................................. 225
CHAPTER 3 Motor Control 241
AC Motor Control 243
3.1.1 Noiseless A.C. Motor Control: Introduction to a 20 kHz System ............... 245
3.1.2 The Effect of a MOSFET’s Peak to Average Current Rating on Invertor
Efficiency ............................................................................................................. 251
3.1.3 MOSFETs and FREDFETs for Motor Drive Equipment ............................. 253
3.1.4 A Designers Guide to PowerMOS Devices for Motor Control ................... 259
3.1.5 A 300V, 40A High Frequency Inverter Pole Using Paralleled FREDFET
Modules ............................................................................................................... 273
DC Motor Control 283
3.2.1 Chopper circuits for DC motor control ....................................................... 285
3.2.2 A switched-mode controller for DC motors ................................................ 293
3.2.3 Brushless DC Motor Systems .................................................................... 301
Stepper Motor Control 307
3.3.1 Stepper Motor Control ............................................................................... 309
CHAPTER 4 Televisions and Monitors 317
Power Devices in TV & Monitor Applications (including selection
guides) 319
4.1.1 An Introduction to Horizontal Deflection .................................................... 321
4.1.2 The BU25XXA/D Range of Deflection Transistors .................................... 331
ii
Contents Power Semiconductor Applications
Philips Semiconductors
4.1.3 Philips HVT’s for TV & Monitor Applications .............................................. 339
4.1.4 TV and Monitor Damper Diodes ................................................................ 345
TV Deflection Circuit Examples 349
4.2.1 Application Information for the 16 kHz Black Line Picture Tubes .............. 351
4.2.2 32 kHz / 100 Hz Deflection Circuits for the 66FS Black Line Picture Tube 361
SMPS Circuit Examples 377
4.3.1 A 70W Full Performance TV SMPS Using The TDA8380 ......................... 379
4.3.2 A Synchronous 200W SMPS for 16 and 32 kHz TV .................................. 389
Monitor Deflection Circuit Example 397
4.4.1 A Versatile 30 - 64 kHz Autosync Monitor ................................................. 399
CHAPTER 5 Automotive Power Electronics 421
Automotive Motor Control (including selection guides) 423
5.1.1 Automotive Motor Control With Philips MOSFETS .................................... 425
Automotive Lamp Control (including selection guides) 433
5.2.1 Automotive Lamp Control With Philips MOSFETS .................................... 435
The TOPFET 443
5.3.1 An Introduction to the 3 pin TOPFET ......................................................... 445
5.3.2 An Introduction to the 5 pin TOPFET ......................................................... 447
5.3.3 BUK101-50DL - a Microcontroller compatible TOPFET ............................ 449
5.3.4 Protection with 5 pin TOPFETs ................................................................. 451
5.3.5 Driving TOPFETs ....................................................................................... 453
5.3.6 High Side PWM Lamp Dimmer using TOPFET ......................................... 455
5.3.7 Linear Control with TOPFET ...................................................................... 457
5.3.8 PWM Control with TOPFET ....................................................................... 459
5.3.9 Isolated Drive for TOPFET ........................................................................ 461
5.3.10 3 pin and 5 pin TOPFET Leadforms ........................................................ 463
5.3.11 TOPFET Input Voltage ............................................................................ 465
5.3.12 Negative Input and TOPFET ................................................................... 467
5.3.13 Switching Inductive Loads with TOPFET ................................................. 469
5.3.14 Driving DC Motors with TOPFET ............................................................. 471
5.3.15 An Introduction to the High Side TOPFET ............................................... 473
5.3.16 High Side Linear Drive with TOPFET ...................................................... 475
iii
Contents Power Semiconductor Applications
Philips Semiconductors
Automotive Ignition 477
5.4.1 An Introduction to Electronic Automotive Ignition ...................................... 479
5.4.2 IGBTs for Automotive Ignition .................................................................... 481
5.4.3 Electronic Switches for Automotive Ignition ............................................... 483
CHAPTER 6 Power Control with Thyristors and Triacs 485
Using Thyristors and Triacs 487
6.1.1 Introduction to Thyristors and Triacs ......................................................... 489
6.1.2 Using Thyristors and Triacs ....................................................................... 497
6.1.3 The Peak Current Handling Capability of Thyristors .................................. 505
6.1.4 Understanding Thyristor and Triac Data .................................................... 509
Thyristor and Triac Applications 521
6.2.1 Triac Control of DC Inductive Loads .......................................................... 523
6.2.2 Domestic Power Control with Triacs and Thyristors .................................. 527
6.2.3 Design of a Time Proportional Temperature Controller ............................. 537
Hi-Com Triacs 547
6.3.1 Understanding Hi-Com Triacs ................................................................... 549
6.3.2 Using Hi-Com Triacs .................................................................................. 551
CHAPTER 7 Thermal Management 553
Thermal Considerations 555
7.1.1 Thermal Considerations for Power Semiconductors ................................. 557
7.1.2 Heat Dissipation ......................................................................................... 567
CHAPTER 8 Lighting 575
Fluorescent Lamp Control 577
8.1.1 Efficient Fluorescent Lighting using Electronic Ballasts ............................. 579
8.1.2 Electronic Ballasts - Philips Transistor Selection Guide ............................ 587
8.1.3 An Electronic Ballast - Base Drive Optimisation ........................................ 589
iv
Index Power Semiconductor Applications
Philips Semiconductors
Index
Airgap, transformer core, 111, 113
Anti saturation diode, 590
Asynchronous, 497
Automotive
fans
see motor control
IGBT, 481, 483
ignition, 479, 481, 483
lamps, 435, 455
motor control, 425, 457, 459, 471, 475
resistive loads, 442
reverse battery, 452, 473, 479
screen heater, 442
seat heater, 442
solenoids, 469
TOPFET, 473
Avalanche, 61
Avalanche breakdown
thyristor, 490
Avalanche multiplication, 134
Baker clamp, 138, 187, 190
Ballast
electronic, 580
fluorescent lamp, 579
switchstart, 579
Base drive, 136
base inductor, 147
base inductor, diode assisted, 148
base resistor, 146
drive transformer, 145
drive transformer leakage inductance, 149
electronic ballast, 589
forward converter, 187
power converters, 141
speed-up capacitor, 143
Base inductor, 144, 147
Base inductor, diode assisted, 148
Boost converter, 109
continuous mode, 109
discontinuous mode, 109
output ripple, 109
Bootstrap, 303
Breakback voltage
diac, 492
Breakdown voltage, 70
Breakover current
diac, 492
Breakover voltage
diac, 492, 592
thyristor, 490
Bridge circuits
see Motor Control - AC
Brushless motor, 301, 303
Buck-boost converter, 110
Buck converter, 108 - 109
Burst firing, 537
Burst pulses, 564
Capacitance
junction, 29
Capacitor
mains dropper, 544
CENELEC, 537
Charge carriers, 133
triac commutation, 549
Choke
fluorescent lamp, 580
Choppers, 285
Clamp diode, 117
Clamp winding, 113
Commutation
diode, 164
Hi-Com triac, 551
thyristor, 492
triac, 494, 523, 529
Compact fluorescent lamp, 585
Continuous mode
see Switched Mode Power Supplies
Continuous operation, 557
Converter (dc-dc)
switched mode power supply, 107
Cookers, 537
Cooling
forced, 572
natural, 570
Crest factor, 529
Critical electric field, 134
Cross regulation, 114, 117
Current fed resonant inverter, 589
Current Mode Control, 120
Current tail, 138, 143
Damper Diodes, 345, 367
forward recovery, 328, 348
losses, 347
outlines, 345
picture distortion, 328, 348
selection guide, 345
Darlington, 13
Data Sheets
High Voltage Bipolar Transistor, 92,97,331
MOSFET, 69
i
Index Power Semiconductor Applications
Philips Semiconductors
dc-dc converter, 119
Depletion region, 133
Desaturation networks, 86
Baker clamp, 91, 138
dI/dt
triac, 531
Diac, 492, 500, 527, 530, 591
Diode, 6
double diffused, 162
epitaxial, 161
schottky, 173
structure, 161
Diode Modulator, 327, 367
Disc drives, 302
Discontinuous mode
see Switched Mode Power Supplies
Domestic Appliances, 527
Dropper
capacitive, 544
resistive, 544, 545
Duty cycle, 561
EFD core
see magnetics
Efficiency Diodes
see Damper Diodes
Electric drill, 531
Electronic ballast, 580
base drive optimisation, 589
current fed half bridge, 584, 587, 589
current fed push pull, 583, 587
flyback, 582
transistor selection guide, 587
voltage fed half bridge, 584, 588
voltage fed push pull, 583, 587
EMC, 260, 455
see RFI, ESD
TOPFET, 473
Emitter shorting
triac, 549
Epitaxial diode, 161
characteristics, 163
dI/dt, 164
forward recovery, 168
lifetime control, 162
operating frequency, 165
passivation, 162
reverse leakage, 169
reverse recovery, 162, 164
reverse recovery softness, 167
selection guide, 171
snap-off, 167
softness factor, 167
stored charge, 162
technology, 162
ESD, 67
see Protection, ESD
precautions, 67
ETD core
see magnetics
F-pack
see isolated package
Fall time, 143, 144
Fast Recovery Epitaxial Diode (FRED)
see epitaxial diode
FBSOA, 134
Ferrites
see magnetics
Flicker
fluorescent lamp, 580
Fluorescent lamp, 579
colour rendering, 579
colour temperature, 579
efficacy, 579, 580
triphosphor, 579
Flyback converter, 110, 111, 113
advantages, 114
clamp winding, 113
continuous mode, 114
coupled inductor, 113
cross regulation, 114
diodes, 115
disadvantages, 114
discontinuous mode, 114
electronic ballast, 582
leakage inductance, 113
magnetics, 213
operation, 113
rectifier circuit, 180
self oscillating power supply, 199
synchronous rectifier, 156, 181
transformer core airgap, 111, 113
transistors, 115
Flyback converter (two transistor), 111, 114
Food mixer, 531
Forward converter, 111, 116
advantages, 116
clamp diode, 117
conduction loss, 197
continuous mode, 116
core loss, 116
core saturation, 117
cross regulation, 117
diodes, 118
disadvantages, 117
duty ratio, 117
ferrite cores, 116
magnetics, 213
magnetisation energy, 116, 117
ii
Index Power Semiconductor Applications
Philips Semiconductors
operation, 116
output diodes, 117
output ripple, 116
rectifier circuit, 180
reset winding, 117
switched mode power supply, 187
switching frequency, 195
switching losses, 196
synchronous rectifier, 157, 181
transistors, 118
Forward converter (two transistor), 111, 117
Forward recovery, 168
FREDFET, 250, 253, 305
bridge circuit, 255
charge, 254
diode, 254
drive, 262
loss, 256
reverse recovery, 254
FREDFETs
motor control, 259
Full bridge converter, 111, 125
advantages, 125
diodes, 126
disadvantages, 125
operation, 125
transistors, 126
Gate
triac, 538
Gate drive
forward converter, 195
Gold doping, 162, 169
GTO, 11
Guard ring
schottky diode, 174
Half bridge, 253
Half bridge circuits
see also Motor Control - AC
Half bridge converter, 111, 122
advantages, 122
clamp diodes, 122
cross conduction, 122
diodes, 124
disadvantages, 122
electronic ballast, 584, 587, 589
flux symmetry, 122
magnetics, 214
operation, 122
synchronous rectifier, 157
transistor voltage, 122
transistors, 124
voltage doubling, 122
Heat dissipation, 567
Heat sink compound, 567
Heater controller, 544
Heaters, 537
Heatsink, 569
Heatsink compound, 514
Hi-Com triac, 519, 549, 551
commutation, 551
dIcom/dt, 552
gate trigger current, 552
inductive load control, 551
High side switch
MOSFET, 44, 436
TOPFET, 430, 473
High Voltage Bipolar Transistor, 8, 79, 91,
141, 341
‘bathtub’ curves, 333
avalanche breakdown, 131
avalanche multiplication, 134
Baker clamp, 91, 138
base-emitter breakdown, 144
base drive, 83, 92, 96, 136, 336, 385
base drive circuit, 145
base inductor, 138, 144, 147
base inductor, diode assisted, 148
base resistor, 146
breakdown voltage, 79, 86, 92
carrier concentration, 151
carrier injection, 150
conductivity modulation, 135, 150
critical electric field, 134
current crowding, 135, 136
current limiting values, 132
current tail, 138, 143
current tails, 86, 91
d-type, 346
data sheet, 92, 97, 331
depletion region, 133
desaturation, 86, 88, 91
device construction, 79
dI/dt, 139
drive transformer, 145
drive transformer leakage inductance, 149
dV/dt, 139
electric field, 133
electronic ballast, 581, 585, 587, 589
Fact Sheets, 334
fall time, 86, 99, 143, 144
FBSOA, 92, 99, 134
hard turn-off, 86
horizontal deflection, 321, 331, 341
leakage current, 98
limiting values, 97
losses, 92, 333, 342
Miller capacitance, 139
operation, 150
iii
Index Power Semiconductor Applications
Philips Semiconductors
optimum drive, 88
outlines, 332, 346
over current, 92, 98
over voltage, 92, 97
overdrive, 85, 88, 137, 138
passivation, 131
power limiting value, 132
process technology, 80
ratings, 97
RBSOA, 93, 99, 135, 138, 139
RC network, 148
reverse recovery, 143, 151
safe operating area, 99, 134
saturation, 150
saturation current, 79, 98, 341
secondary breakdown, 92, 133
smooth turn-off, 86
SMPS, 94, 339, 383
snubber, 139
space charge, 133
speed-up capacitor, 143
storage time, 86, 91, 92, 99, 138, 144, 342
sub emitter resistance, 135
switching, 80, 83, 86, 91, 98, 342
technology, 129, 149
thermal breakdown, 134
thermal runaway, 152
turn-off, 91, 92, 138, 142, 146, 151
turn-on, 91, 136, 141, 149, 150
underdrive, 85, 88
voltage limiting values, 130
Horizontal Deflection, 321, 367
base drive, 336
control ic, 401
d-type transistors, 346
damper diodes, 345, 367
diode modulator, 327, 347, 352, 367
drive circuit, 352, 365, 406
east-west correction, 325, 352, 367
line output transformer, 354
linearity correction, 323
operating cycle, 321, 332, 347
s-correction, 323, 352, 404
TDA2595, 364, 368
TDA4851, 400
TDA8433, 363, 369
test circuit, 321
transistors, 331, 341, 408
waveforms, 322
IGBT, 11, 305
automotive, 481, 483
clamped, 482, 484
ignition, 481, 483
Ignition
automotive, 479, 481, 483
darlington, 483
Induction heating, 53
Induction motor
see Motor Control - AC
Inductive load
see Solenoid
Inrush current, 528, 530
Intrinsic silicon, 133
Inverter, 260, 273
see motor control ac
current fed, 52, 53
switched mode power supply, 107
Irons, electric, 537
Isolated package, 154
stray capacitance, 154, 155
thermal resistance, 154
Isolation, 153
J-FET, 9
Junction temperature, 470, 557, 561
burst pulses, 564
non-rectangular pulse, 565
rectangular pulse, composite, 562
rectangular pulse, periodic, 561
rectangular pulse, single shot, 561
Lamp dimmer, 530
Lamps, 435
dI/dt, 438
inrush current, 438
MOSFET, 435
PWM control, 455
switch rate, 438
TOPFET, 455
Latching current
thyristor, 490
Leakage inductance, 113, 200, 523
Lifetime control, 162
Lighting
fluorescent, 579
phase control, 530
Logic Level FET
motor control, 432
Logic level MOSFET, 436
Magnetics, 207
100W 100kHz forward converter, 197
100W 50kHz forward converter, 191
50W flyback converter, 199
core losses, 208
core materials, 207
EFD core, 210
ETD core, 199, 207
iv
Index Power Semiconductor Applications
Philips Semiconductors
flyback converter, 213
forward converter, 213
half bridge converter, 214
power density, 211
push-pull converter, 213
switched mode power supply, 187
switching frequency, 215
transformer construction, 215
Mains Flicker, 537
Mains pollution, 225
pre-converter, 225
Mains transient, 544
Mesa glass, 162
Metal Oxide Varistor (MOV), 503
Miller capacitance, 139
Modelling, 236, 265
MOS Controlled Thyristor, 13
MOSFET, 9, 19, 153, 253
bootstrap, 303
breakdown voltage, 22, 70
capacitance, 30, 57, 72, 155, 156
capacitances, 24
characteristics, 23, 70 - 72
charge, 32, 57
data sheet, 69
dI/dt, 36
diode, 253
drive, 262, 264
drive circuit loss, 156
driving, 39, 250
dV/dt, 36, 39, 264
ESD, 67
gate-source protection, 264
gate charge, 195
gate drive, 195
gate resistor, 156
high side, 436
high side drive, 44
inductive load, 62
lamps, 435
leakage current, 71
linear mode, parallelling, 52
logic level, 37, 57, 305
loss, 26, 34
maximum current, 69
motor control, 259, 429
modelling, 265
on-resistance, 21, 71
package inductance, 49, 73
parallel operation, 26, 47, 49, 265
parasitic oscillations, 51
peak current rating, 251
Resonant supply, 53
reverse diode, 73
ruggedness, 61, 73
safe operating area, 25, 74
series operation, 53
SMPS, 339, 384
solenoid, 62
structure, 19
switching, 24, 29, 58, 73, 194, 262
switching loss, 196
synchronous rectifier, 179
thermal impedance, 74
thermal resistance, 70
threshold voltage, 21, 70
transconductance, 57, 72
turn-off, 34, 36
turn-on, 32, 34, 35, 155, 256
Motor, universal
back EMF, 531
starting, 528
Motor Control - AC, 245, 273
anti-parallel diode, 253
antiparallel diode, 250
carrier frequency, 245
control, 248
current rating, 262
dc link, 249
diode, 261
diode recovery, 250
duty ratio, 246
efficiency, 262
EMC, 260
filter, 250
FREDFET, 250, 259, 276
gate drives, 249
half bridge, 245
inverter, 250, 260, 273
line voltage, 262
loss, 267
MOSFET, 259
Parallel MOSFETs, 276
peak current, 251
phase voltage, 262
power factor, 262
pulse width modulation, 245, 260
ripple, 246
short circuit, 251
signal isolation, 250
snubber, 276
speed control, 248
switching frequency, 246
three phase bridge, 246
underlap, 248
Motor Control - DC, 285, 293, 425
braking, 285, 299
brushless, 301
control, 290, 295, 303
current rating, 288
v
Index Power Semiconductor Applications
Philips Semiconductors
drive, 303
duty cycle, 286
efficiency, 293
FREDFET, 287
freewheel diode, 286
full bridge, 287
half bridge, 287
high side switch, 429
IGBT, 305
inrush, 430
inverter, 302
linear, 457, 475
logic level FET, 432
loss, 288
MOSFET, 287, 429
motor current, 295
overload, 430
permanent magnet, 293, 301
permanent magnet motor, 285
PWM, 286, 293, 459, 471
servo, 298
short circuit, 431
stall, 431
TOPFET, 430, 457, 459, 475
topologies, 286
torque, 285, 294
triac, 525
voltage rating, 288
Motor Control - Stepper, 309
bipolar, 310
chopper, 314
drive, 313
hybrid, 312
permanent magnet, 309
reluctance, 311
step angle, 309
unipolar, 310
Mounting, transistor, 154
Mounting base temperature, 557
Mounting torque, 514
Parasitic oscillation, 149
Passivation, 131, 162
PCB Design, 368, 419
Phase angle, 500
Phase control, 546
thyristors and triacs, 498
triac, 523
Phase voltage
see motor control - ac
Power dissipation, 557
see High Voltage Bipolar Transistor loss,
MOSFET loss
Power factor correction, 580
active, boost converted, 581
Power MOSFET
see MOSFET
Proportional control, 537
Protection
ESD, 446, 448, 482
overvoltage, 446, 448, 469
reverse battery, 452, 473, 479
short circuit, 251, 446, 448
temperature, 446, 447, 471
TOPFET, 445, 447, 451
Pulse operation, 558
Pulse Width Modulation (PWM), 108
Push-pull converter, 111, 119
advantages, 119
clamp diodes, 119
cross conduction, 119
current mode control, 120
diodes, 121
disadvantages, 119
duty ratio, 119
electronic ballast, 582, 587
flux symmetry, 119, 120
magnetics, 213
multiple outputs, 119
operation, 119
output filter, 119
output ripple, 119
rectifier circuit, 180
switching frequency, 119
transformer, 119
transistor voltage, 119
transistors, 121
Qs (stored charge), 162
RBSOA, 93, 99, 135, 138, 139
Rectification, synchronous, 179
Reset winding, 117
Resistor
mains dropper, 544, 545
Resonant power supply, 219, 225
modelling, 236
MOSFET, 52, 53
pre-converter, 225
Reverse leakage, 169
Reverse recovery, 143, 162
RFI, 154, 158, 167, 393, 396, 497, 529, 530,
537
Ruggedness
MOSFET, 62, 73
schottky diode, 173
Safe Operating Area (SOA), 25, 74, 134, 557
forward biased, 92, 99, 134
reverse biased, 93, 99, 135, 138, 139
vi
Index Power Semiconductor Applications
Philips Semiconductors
Saturable choke
triac, 523
Schottky diode, 173
bulk leakage, 174
edge leakage, 174
guard ring, 174
reverse leakage, 174
ruggedness, 173
selection guide, 176
technology, 173
SCR
see Thyristor
Secondary breakdown, 133
Selection Guides
BU25XXA, 331
BU25XXD, 331
damper diodes, 345
EPI diodes, 171
horizontal deflection, 343
MOSFETs driving heaters, 442
MOSFETs driving lamps, 441
MOSFETs driving motors, 426
Schottky diodes, 176
SMPS, 339
Self Oscillating Power Supply (SOPS)
50W microcomputer flyback converter, 199
ETD transformer, 199
Servo, 298
Single ended push-pull
see half bridge converter
Snap-off, 167
Snubber, 93, 139, 495, 502, 523, 529, 549
active, 279
Softness factor, 167
Solenoid
TOPFET, 469, 473
turn off, 469, 473
Solid state relay, 501
SOT186, 154
SOT186A, 154
SOT199, 154
Space charge, 133
Speed-up capacitor, 143
Speed control
thyristor, 531
triac, 527
Starter
fluorescent lamp, 580
Startup circuit
electronic ballast, 591
self oscillating power supply, 201
Static Induction Thyristor, 11
Stepdown converter, 109
Stepper motor, 309
Stepup converter, 109
Storage time, 144
Stored charge, 162
Suppression
mains transient, 544
Switched Mode Power Supply (SMPS)
see also self oscillating power supply
100W 100kHz MOSFET forward converter,
192
100W 500kHz half bridge converter, 153
100W 50kHz bipolar forward converter, 187
16 & 32 kHz TV, 389
asymmetrical, 111, 113
base circuit design, 149
boost converter, 109
buck-boost converter, 110
buck converter, 108
ceramic output filter, 153
continuous mode, 109, 379
control ic, 391
control loop, 108
core excitation, 113
core loss, 167
current mode control, 120
dc-dc converter, 119
diode loss, 166
diode reverse recovery effects, 166
diode reverse recovery softness, 167
diodes, 115, 118, 121, 124, 126
discontinuous mode, 109, 379
epitaxial diodes, 112, 161
flux swing, 111
flyback converter, 92, 111, 113, 123
forward converter, 111, 116, 379
full bridge converter, 111, 125
half bridge converter, 111, 122
high voltage bipolar transistor, 94, 112, 115,
118, 121, 124, 126, 129, 339, 383, 392
isolated, 113
isolated packages, 153
isolation, 108, 111
magnetics design, 191, 197
magnetisation energy, 113
mains filter, 380
mains input, 390
MOSFET, 112, 153, 33, 384
multiple output, 111, 156
non-isolated, 108
opto-coupler, 392
output rectifiers, 163
parasitic oscillation, 149
power-down, 136
power-up, 136, 137, 139
power MOSFET, 153, 339, 384
pulse width modulation, 108
push-pull converter, 111, 119
vii
Index Power Semiconductor Applications
Philips Semiconductors
RBSOA failure, 139
rectification, 381, 392
rectification efficiency, 163
rectifier selection, 112
regulation, 108
reliability, 139
resonant
see resonant power supply
RFI, 154, 158, 167
schottky diode, 112, 154, 173
snubber, 93, 139, 383
soft start, 138
standby, 382
standby supply, 392
start-up, 391
stepdown, 109
stepup, 109
symmetrical, 111, 119, 122
synchronisation, 382
synchronous rectification, 156, 179
TDA8380, 381, 391
topologies, 107
topology output powers, 111
transformer, 111
transformer saturation, 138
transformers, 391
transistor current limiting value, 112
transistor mounting, 154
transistor selection, 112
transistor turn-off, 138
transistor turn-on, 136
transistor voltage limiting value, 112
transistors, 115, 118, 121, 124, 126
turns ratio, 111
TV & Monitors, 339, 379, 399
two transistor flyback, 111, 114
two transistor forward, 111, 117
Switching loss, 230
Synchronous, 497
Synchronous rectification, 156, 179
self driven, 181
transformer driven, 180
Temperature control, 537
Thermal
continuous operation, 557, 568
intermittent operation, 568
non-rectangular pulse, 565
pulse operation, 558
rectangular pulse, composite, 562
rectangular pulse, periodic, 561
rectangular pulse, single shot, 561
single shot operation, 561
Thermal capacity, 558, 568
Thermal characteristics
power semiconductors, 557
Thermal impedance, 74, 568
Thermal resistance, 70, 154, 557
Thermal time constant, 568
Thyristor, 10, 497, 509
’two transistor’ model, 490
applications, 527
asynchronous control, 497
avalanche breakdown, 490
breakover voltage, 490, 509
cascading, 501
commutation, 492
control, 497
current rating, 511
dI/dt, 490
dIf/dt, 491
dV/dt, 490
energy handling, 505
external commutation, 493
full wave control, 499
fusing I
2
t, 503, 512
gate cathode resistor, 500
gate circuits, 500
gate current, 490
gate power, 492
gate requirements, 492
gate specifications, 512
gate triggering, 490
half wave control, 499
holding current, 490, 509
inductive loads, 500
inrush current, 503
latching current, 490, 509
leakage current, 490
load line, 492
mounting, 514
operation, 490
overcurrent, 503
peak current, 505
phase angle, 500
phase control, 498, 527
pulsed gate, 500
resistive loads, 498
resonant circuit, 493
reverse characteristic, 489
reverse recovery, 493
RFI, 497
self commutation, 493
series choke, 502
snubber, 502
speed controller, 531
static switching, 497
structure, 489
switching, 489
viii
Index Power Semiconductor Applications
Philips Semiconductors
switching characteristics, 517
synchronous control, 497
temperature rating, 512
thermal specifications, 512
time proportional control, 497
transient protection, 502
trigger angle, 500
turn-off time, 494
turn-on, 490, 509
turn-on dI/dt, 502
varistor, 503
voltage rating, 510
Thyristor data, 509
Time proportional control, 537
TOPFET
3 pin, 445, 449, 461
5 pin, 447, 451, 457, 459, 463
driving, 449, 453, 461, 465, 467, 475
high side, 473, 475
lamps, 455
leadforms, 463
linear control, 451, 457
motor control, 430, 457, 459
negative input, 456, 465, 467
protection, 445, 447, 451, 469, 473
PWM control, 451, 455, 459
solenoids, 469
Transformer
triac controlled, 523
Transformer core airgap, 111, 113
Transformers
see magnetics
Transient thermal impedance, 559
Transient thermal response, 154
Triac, 497, 510, 518
400Hz operation, 489, 518
applications, 527, 537
asynchronous control, 497
breakover voltage, 510
charge carriers, 549
commutating dI/dt, 494
commutating dV/dt, 494
commutation, 494, 518, 523, 529, 549
control, 497
dc inductive load, 523
dc motor control, 525
dI/dt, 531, 549
dIcom/dt, 523
dV/dt, 523, 549
emitter shorting, 549
full wave control, 499
fusing I
2
t, 503, 512
gate cathode resistor, 500
gate circuits, 500
gate current, 491
gate requirements, 492
gate resistor, 540, 545
gate sensitivity, 491
gate triggering, 538
holding current, 491, 510
Hi-Com, 549, 551
inductive loads, 500
inrush current, 503
isolated trigger, 501
latching current, 491, 510
operation, 491
overcurrent, 503
phase angle, 500
phase control, 498, 527, 546
protection, 544
pulse triggering, 492
pulsed gate, 500
quadrants, 491, 510
resistive loads, 498
RFI, 497
saturable choke, 523
series choke, 502
snubber, 495, 502, 523, 529, 549
speed controller, 527
static switching, 497
structure, 489
switching, 489
synchronous control, 497
transformer load, 523
transient protection, 502
trigger angle, 492, 500
triggering, 550
turn-on dI/dt, 502
varistor, 503
zero crossing, 537
Trigger angle, 500
TV & Monitors
16 kHz black line, 351
30-64 kHz autosync, 399
32 kHz black line, 361
damper diodes, 345, 367
diode modulator, 327, 367
EHT, 352 - 354, 368, 409, 410
high voltage bipolar transistor, 339, 341
horizontal deflection, 341
picture distortion, 348
power MOSFET, 339
SMPS, 339, 354, 379, 389, 399
vertical deflection, 358, 364, 402
Two transistor flyback converter, 111, 114
Two transistor forward converter, 111, 117
Universal motor
back EMF, 531
ix
Index Power Semiconductor Applications
Philips Semiconductors
starting, 528
Vacuum cleaner, 527
Varistor, 503
Vertical Deflection, 358, 364, 402
Voltage doubling, 122
Water heaters, 537
Zero crossing, 537
Zero voltage switching, 537
x
Motor Control Power Semiconductor Applications
Philips Semiconductors
CHAPTER 3
Motor Control
3.1 AC Motor Control
3.2 DC Motor Control
3.3 Stepper Motor Control
241
Motor Control Power Semiconductor Applications
Philips Semiconductors
AC Motor Control
243
Motor Control Power Semiconductor Applications
Philips Semiconductors
3.1.1 Noiseless A.C. Motor Control: Introduction to a 20 kHz
System
Controlling an a.c. induction motor by the technique of
sinewave-weighted pulse-width modulation (PWM)
switchinggivesthe benefitsof smooth torqueat lowspeeds,
andalsocompletespeedcontrol fromzerouptothenominal
rated speed of the motor, with only small additional motor
losses.
Traditional power switches such as thyristors need
switching frequencies in the audible range, typically
between 400 and 1500Hz. In industrial environments, the
small amount of acoustic noise produced by the motor with
this type of control can be regarded as insignificant. By
contrast, however, the same amount of noise in a domestic
or office application, such as speed control of a ventilation
fan, might prove to be unacceptable.
Now, however, with the advent of power MOSFETs,
three-phase PWM inverters operating at ultrasonic
frequencies can be designed. A three-phase motor usually
makes even less noise when being driven from such a
system than when being run directly from the mains
because the PWM synthesis generates a purer sinewave
than is normally obtainable from the mains.
The carrier frequency is generally about 20kHz and so it is
far removed from the modulation frequency, which is
typically less than 50Hz, making it economic to use a
low-pass filter between the inverter and the motor. By
removing the carrier frequency and its sidebands and
harmonics, the waveformdelivered via the motor leads can
be made almost perfectly sinusoidal. RFI radiated by the
motor leads, or conducted by the winding-to-frame
capacitance of the motor, is therefore almost entirely
eliminated. Furthermore, because of the high carrier
frequency, it is possible to drive motors which are designed
for frequencies higher than the mains, such as 400Hz
aircraft motors.
This section describes a three-phase a.c. motor control
systemwhich is powered fromthe single-phase a.c. mains.
It is capable of controlling a motor with up to 1kW of shaft
output power. Before details are given, the general
principles of PWM motor control are outlined.
Principles of Pulse-Width Modulation
Pulse-width modulation (PWM) is the technique of using
switching devices to produce the effect of a continuously
varying analogue signal; this PWM conversion generally
has very high electrical efficiency. In controlling either a
three-phase synchronous motor or a three-phase induction
motor it is desirable to create three perfectly sinusoidal
current waveforms in the motor windings, with relative
phase displacements of 120˚. The production of sinewave
power via a linear amplifier system would have low
efficiency, at best 64%. If instead of the linear circuitry, fast
electronic switching devices are used, then the efficiency
can be greater than 95%, depending on the characteristics
of the semiconductor power switch.
Fig.1 Half-bridge switching circuit
Fig.2 Waveforms in PWM inverter
(a) Unmodulated carrier
(b) Modulated carrier
(c) Current in inductive load
The half-bridge switching circuit in Fig.1 is given as an
example: the switches can be any suitable switching
semiconductors. If these two switches are turned on
alternately for equal times, then the voltage waveform
across the load is as shown in Fig.2a. The mean value of
this waveform, averaged over one switching cycle is 0. This
square wave with a constant 50% duty ratio is known as
the ’carrier’ frequency. The waveform in Fig.2b shows the
effect of a slow variation or ’modulation’ of the duty ratio;
the mean voltage varies with the duty ratio. The waveform
of the resultant load current depends on the impedance of
the load Z. If Z is mainly resistive, then the waveform of the
current will closely follow that of the modulated square
wave. If, however, Z is largely inductive, as with a motor
winding or a filter choke, then the switching square wave
V/2
V/2
+
+
Z
-V/2
V/2
0
0
-V/2
V/2
0
I
(a)
(b)
(c)
245
Motor Control Power Semiconductor Applications
Philips Semiconductors
will be integratedby the inductor. The result isaload current
waveform that depends mainly on the modulation of the
duty ratio.
If the duty ratioisvariedsinusoidallyintime, thenthe current
in an inductive load has the form of a sinewave at the
modulationfrequency, laggingin phase, and carryingripple
at the switching frequency as shown in Fig.2c. The
amplitude of the current can be adjusted by controlling the
depth of modulation, that is, the deviation of the duty ratio
from 50%. For example, a sinewave PWM signal which
varies from5%to 95%, giving 90%modulation, will produce
a current nine times greater than that produced by a signal
which varies only from 45% to 55%, giving only 10%
modulation.
For three-phase a.c. motor control, three such waveforms
arerequired, necessitatingthreepairs of switches likethose
shown in Fig. 1, connected in a three-phase bridge. The
inductance required to integrate the waveform can usually
be provided by the inductance of the stator windings of the
motor, although in some instances it might be provided by
the inductance of a separate low-pass filter. The
modulations in the three switching waveforms must be
maintained at a constant relative phase difference of 120˚,
so as to maintain motor current sinewaves which are
themselves at a constant 120˚ phase difference. The
modulation depth must be varied with the modulation
frequency so as to keep the magnetic flux in the motor at
approximately the design level.
In practice, the frequency of the modulation is usually
between zero and 50Hz. The switching frequency depends
on the type of power device that is to be used: until recently,
the only devices available were power thyristors or the
relatively slow bipolar transistors, and therefore the
switching frequency was limited to a maximum of about 1
kHz. With thyristors, this frequency limit was set by the
need to provide forced commutation of the thyristor by an
external commutation circuit using an additional thyristor,
adiode, acapacitor, andaninductor, in aprocess that takes
at least 40µs. With transistors, the switching frequency was
limited by their switching frequency and their long storage
times.
In this earlier type of control circuit, therefore, the ratio of
carrier frequency to modulation frequency was only about
20:1. Under these conditions the exact duty-ratios and
carrier frequencies had to be selected so as to avoid all
sub-harmonic torques, that is, torque components at
frequencies lower than the modulation frequency. This was
done by synchronising the carrier to a selected multiple of
the fundamental frequency; the HEF4752V, an excellent
IC purpose-designed for a.c. motor control, uses this
particular approach. The 1kHz technique is still extremely
useful for control of large motors because whenever shaft
output powers of more than a few kW are required,
three-phase mains input must be used, and there are, as
yet, few available switching devices with combined high
voltage rating, current rating, and switching speed.
However, using MOSFETs with switching times of much
less than 1µs, the carrier frequency can be raised to the
ultrasonic region, that is, to 20kHz or more. There are
obvious system benefits with this higher frequency, but
there are also several aspects of PWM waveform
generation that become easier. It is possible to use a fixed
carrier frequency because the sub-harmonics that are
produced as a result of the non-synchronisation of the
carrier frequency with a multiple of the fundamental are
insignificant when the ratio of the carrier frequency to the
fundamental frequency is typically about 400:1.
Fig.3 20kHz AC motor controller
246
Motor Control Power Semiconductor Applications
Philips Semiconductors
To maintain good waveform balance, and thus avoid any
d.c. in the motor, and therefore also avoid parasitic torques,
adigital waveformgenerationtechniqueis appropriate. The
waveform can be stored as a ’look-up’ table of numbers
representing the sinewave. To generate the three phases,
this table can be read at three points that have the correct
120˚ phase relationship. The numbers taken fromthe table
represent the duty ratios corresponding to 100%
modulation: these numbers can then be scaled down by
multiplication or some equivalent technique to give the
correct duty-ratio numbers for the modulation depth
required.
The speed of the motor is controlled by the rate at which
the reading pointers scan the look-up table and this can be
as slow as desired. If the pointers are stationary, then the
system will be ’frozen’ at a particular point on the
three-phase sinewave waveform, giving the possibility of
obtaining static torque from a synchronous motor at zero
speed. The rate at which the numbers are produced by this
read-out process from the look-up table is constant and
determines the carrier frequency.
To convert these three simultaneous parallel digital
numbers into time lengths for pulses, three digital counters
are needed. The counters can be designed to give
double-edged modulation, such that both the leading edge
and the trailing edge of each pulse move with respect to
the unmodulated carrier. The line-to-line voltage across the
load will have most of its ripple at a frequency of twice the
switching frequency, and will have a spectrum with
minimum even harmonics and no significant component
below twice the switching frequency. Motor ripple current
is therefore low and motor losses are reduced.
There is a further advantage to be obtained from the high
ratio of carrier to modulation frequency: by adding a small
amount of modulation at the third harmonic frequency of
thebasic fundamental modulationfrequency, the maximum
line-to-line output voltage obtainable from the inverter can
beincreased, for thefollowingreason. The effect of the third
harmonic on the output voltage of each phase is to flatten
the top of the waveform, thus allowing a higher amplitude
of fundamental while still reaching a peak modulation of
100%. When the difference voltage between any two
phases is measured, the third harmonic terms cancel,
leavingapuresinewave at the fundamental frequency. This
allows the inverter output to deliver the same voltage as the
mains input without any significant distortion, and thus to
reduce insertion losses to virtually zero.
Overview of a practical system
The principles outlined above are applied to a typical
systemshown in Fig.3. The incoming a.c. mains is rectified
and smoothed to produce about 300V and this is fed to the
three-phase inverter via a current-sensing circuit. The
inverter chops the d.c. to give 300V peak-to-peak PWM
waves at 20kHz, each having low-frequency modulation of
its mark-space ratio. The output of the inverter is filtered to
remove the 20kHz carrier frequency, and the resultant
sinewaves are fed to the a.c. motor.
Fig.4 Waveform generator circuit
247
Motor Control Power Semiconductor Applications
Philips Semiconductors
The six switches in the inverter are under the command of
a waveform-generation circuit which determines the
conduction time of each switch. Because the control
terminals of the six switches are not at the same potential,
the outputs of the waveform-generation circuits must be
isolated and buffered. A low-voltage power supply feeds
the signal processing circuit, and a further low-voltage
power supply drives a switch-mode isolating stage to
provide floating power supplies to the gate drive circuits.
Signal processing
Fig.4 shows a block diagram of the circuit which generates
the PWM control signals for the inverter. The input to the
system is a speed-demand voltage and this is also used
for setting the required direction of rotation: the analogue
speed signal is then separated from the digital direction
signal. The speed-demand voltage sets the frequency of
the voltage-controlled oscillator (VCO). Information to
determine the modulation depth is derived from the
speed-control signal by a simple non-linear circuit and is
then converted by an analogue-to-digital converter into an
8-bit parallel digital signal.
A dedicated IC, type MAB8051, receives the clock signals
from the VCO, the modulation-depth control number from
the A/D converter, the direction-control logic signal, and
logic inputs from the ’RUN’ and ’STOP’ switches. By
applying digital multiplication processes to internal look-up
table values, the microcomputer calculates the ’on-time’ for
eachof the six power switches, andthis process is repeated
at regular intervals of 50µs, giving a carrier frequency of
20kHz. The pulses fromthe VCOare used for incrementing
the pointers of the look-up table in the microcomputer, and
thus control the motor speed.
The output signals of the microcomputer are in the form of
three 8-bit parallel numbers: each representing the
duty-ratio for the next 50µs switching cycle for one pair of
inverter switches, on a scale which represents 0%to 100%
on-time for the upper switch and therefore also 100%to 0%
on-time for the complementary lower switch. A dedicated
logic circuit applies these three numbers from the
microcomputer to digital counters and converts each
number to a pair of pulse-widths. The two signals produced
for each phase are complementary except for a small
’underlap’ delay. This delay is necessary to ensure that the
switch being turned off recovers its blocking voltage before
its partner is turned on, thus preventing ’shoot-through’.
Fig.5 DC link, low voltage and floating power supplies
248
Motor Control Power Semiconductor Applications
Philips Semiconductors
Other inputs to the microcomputer are the on/off switches,
the motor direction logic signal, and the current-sensing
signal. Each input triggers a processor interrupt, causing
the appropriate action to be taken. The STOP switch and
the overcurrent sense signals have the same effect, that of
causingthe microcomputer toinstruct all six power switches
in the inverter to turn off. The RUN switch causes the
microcomputer to start producing output pulses. Any
change in the direction signal first stops the microcomputer
which then determines the new direction of rotation and
adjusts its output phase rotation accordingly.
D.C. link and power supplies
The d.c. link and the low-voltage power supplies for the
systemare shown in Fig.5. The high voltage d.c. supply for
the inverter is derived froma mains-fed bridge rectifier with
a smoothing capacitor; the capacitor conducts both the
100Hzripplefromtherectifiedsingle-phasemains, andalso
the inverter switching ripple. A resistor, or alternatively a
thermistor, limits the peak current in the rectifier while the
capacitor is being charged initially. This resistor is shorted
out by a relay after a time delay, so that the resistor does
not dissipate power while the motor is running. As a safety
measure, a second resistor discharges the d.c. link
capacitor when the mains current is removed.
Oneof thed.c. link lines carriesalow-valueresistor tosense
the d.c. link current. Asimple opto-isolation circuit transmits
a d.c. link current overload signal back to the signal
processing circuit.
The logic circuitry of the waveform generator is powered
conventionally by a 50Hz mains transformer, bridge
rectifier, and smoothing capacitor. The transformer has two
secondary windings; the second one provides power to a
switched-mode power supply (SMPS), in which there is a
switching transistor driven at about 60kHz to switch power
through isolating transformers. Rectifying the a.c. outputs
from the isolating transformers provides floating power
supplies for the inverter gate drive circuits. As will be seen
below, one supply is needed for the three ’lower’ power
switches (connected to a common d.c. link negative line),
but three separate power supplies are needed for the three
’upper’ switches (connected to the three inverter outputs).
Thus four isolating transformers are required for the gate
supply circuits. For low power systems the gate supplies
can be derived directly from the d.c. link without excessive
loss.
To prevent spurious turn-on of any inverter switch during
the start-up process, the floating power supply to the lower
threegate-drive circuits is connectedonly after a delay. The
same delay is used for this as is used for the d.c. link
charging-resistor bypass switch.
Fig.6 Signal isolation, gate drive, inverter and filter (one phase of three)
15 V
HEF40097
2k2
2k2
10T 20T
47 pF
18 k
1 k c18v
100R
FX3848
8 uF
2n2
15 V
HEF40097
2k2
2k2
10T 20T
47 pF
18 k
1 k c18v
100R
FX3848
8 uF
2n2
249
Motor Control Power Semiconductor Applications
Philips Semiconductors
Signal isolation, gate drive, and inverter
The most important part of the system is the power inverter
and it is the use of MOSFETs, with their short switching
times, which makes it possible for the inverter to switch at
20kHz. It is in the area of the drive circuits to the power
switches that usingMOSFETs gives asaving inthe number
of components needed. Driving MOSFETs is relatively
easy: the total power needed is very small because all that
must be provided is the capability to charge and discharge
the gate-source capacitance (typically between 1 and 2nF)
byafewvolts in ashort time (less than100ns). This ensures
that the quality of the waveform is not degraded, and that
switching losses are minimised.
In this circuit the six pulse outputs from the dedicated logic
part of the waveform generator section are coupled to the
MOSFET gate driver stages via pulse transformers. (see
Fig.6). Each gate drive circuit is powered from one of the
four floating power supplies described above. The three
’lower’ stages share acommonpower supply, as thesource
terminals of the three ’lower’ MOSFETs are all at the same
potential. Each of the three ’upper’ stages has its own
floating power supply. The isolated signals are coupled to
the gate terminals of the six MOSFETs by small amplifiers
capableof deliveringafewamperes peak current for ashort
time. Alternative gate driver circuits may use level shifting
devices or opto-couplers. (Refer to "Power MOSFET Gate
Drive Circuits" for further details.)
It will be seen from Fig.6 that each MOSFET has two
associated diodes. These are necessary because the
MOSFETs have built-in anti-parallel diodes with relatively
long reverse-recovery times. If these internal diodes were
allowed to conduct, then whenever load current
commutated froma diode to the opposite MOSFET, a large
current would be drawn fromthe d.c. supply for the duration
of the diode reverse-recovery time. This would greatly
increase the dissipation in the inverter. To avoid this, an
external fast epitaxial diode is connected in anti-parallel
with the MOSFET. Because the internal diode of the
MOSFET has a very low forward voltage drop, a second
low-voltageepitaxial diodemust beconnectedinseries with
each MOSFET to prevent the internal diode from
conducting at all. Thus, whenever the MOSFET is
reverse-biased, it is the external anti-parallel diode which
conducts, rather than the internal one. FREDFETs have
internal diodes which are much faster than those of
MOSFETs, opening the way for a further cost-saving by
omitting the twelve diodes from the 3-phase inverter.
Output low-pass filter
For conventional, lower frequencyinverters thesize, weight
and cost of output filter stages has held back their
proliferation. An advantage of the constant high carrier
frequency is that a small, economical low-pass filter can be
designed to remove the carrier from the inverter output
waveform. Compared with lowfrequency systems the filter
component has been reduced by an order of magnitude,
and can often be eliminated completely. In unfiltered
systems cable screening becomes an important issue
although on balance the increased cost of screening is less
than the cost and weight of filter components.
A typical filter arrangement was shown in Fig.6. As an
example, for a 50Hz motor-drive the filter would be
designed with a corner-frequency of 100Hz, so that the
attenuation at 20kHz would be about 46dB. The carrier
frequency component superimposed on the output
sinewave would therefore be only a few mV in 200Vrms.
Fig.7 shows the relative spectral characteristics of different
types of inverter switching strategies.
Fig.7 Spectral characteristics for different inverter
switching strategies
(a) Quasi-square
(b) 1kHz, 15 pulse, Synchronous
(c) 20kHz, Non-synchronous
There are two main advantages in supplying the motor with
pure sinewave power. First, the motor losses are small,
because there is no rms motor current at the switching
frequency, and second, there is less radio-frequency
interference(RFI), becausetheswitchingfrequencycurrent
components circulate entirely within the inverter and filter
and do not reach the outside world.
Advantages of a 20 kHz system
The principal advantages of the systemdescribed hereare:
-Controller and motor are acoustically quiet.
-PWM waveform is simple and thus easy to
generate.
-Output filter for removal of carrier is economic.
-RFI is low because of output filter.
-No snubbers are required on power devices.
-High efficiency is easily obtainable.
-No insertion loss.
f(Hz) 100 1k 10k 100k
Power (W)
1kW
10W
100mW
f(Hz) 100 1k 10k 100k
Power (W)
1kW
10W
100mW
f(Hz) 100 1k 10k 100k
Power (W)
1kW
10W
100mW
(a)
(b)
(c)
250
Motor Control Power Semiconductor Applications
Philips Semiconductors
3.1.2 The Effect of a MOSFET’s Peak to Average Current Rating
on Inverter Efficiency
The control of induction motors using a synthesised
sinewave generated using pulse width modulation (PWM)
control is becoming increasingly popular. The peak current
requirement of switches used for the inverter bridge is
based on the maximum current when the output is short
circuited. The overcurrent during a short circuit fault is
limitedby an inductor connected inseries withthe switches.
There is therefore a trade off between the peak current
carryingcapability of the switch andthe size of the inductor.
It is demonstratedinthis notethat the efficiency of thecircuit
during normal operation of the inverter is affected by the
size of this choke. The ratio of peak to average current
carrying capability of Philips Powermos is typcially about
four. This compares favourably with the typical ratio of
Insulated Gate Bipolar Transistors (IGBTs) which is about
three.
A simplified diagram of the inverter and the windings of the
inductionmotor isshowninFig. 1. TheMOSFETs aredriven
with a PWM signal as shown in Fig. 2. The voltages at the
outputs of each leg of the inverter are smoothed using a
low pass filter and the inductance of the motor windings.
The system has the following advantages; it uses an
induction motor which is relatively cheap and maintenance
free and it has the facility for 0 to 100% speed control. The
near perfect sinewaves generated by the PWM technique
produce a smooth torque, audible noise is reduced and
filtering is made easier since MOSFETs make possible the
use of switching frequencies above 20 kHz.
Fig. 1 A simplified diagram of the inverter
Fig. 2 PWM drive signal for the inverter MOSFETs
If the output of the inverter is short circuited there will be a
rapidriseof current inthe switches. Tolimit this peakcurrent
an inductor, L
s,
is often connected in each leg of the inverter
as shown in Fig 3. The rate of rise of current under short
circuit conditions, is then given in equation 1.
(1)
Fig. 3 Inverter bridge leg with dI/dt limiting inductor
V
dc
0
V
dc
2
dI
T
dt
=
V
D
L
s
V
D
M1
M2
D1
D2
C
S
R
S
I
motor
0V
I
M1
L
S
251
Motor Control Power Semiconductor Applications
Philips Semiconductors
When the MOSFETs turn this fault current (I
SC
) off the
energy in the inductor is transferred to a snubber capacitor,
C
S
. The overvoltage across the MOSFETs is given by
equation 2.
(2)
The presence of inductor L
S
affects the normal operation
of the inverter. When the MOSFET M1 in Fig. 3 turns off
the diode D2 does not turn on until the voltage across C
S
is equal to the d.c. link voltage, V
D
. If the diode did turn on
then the rate of rise of current in L
S
would be given by
equation 3.
(3)
This would be greater than the rate of rise of motor current
so I
M1
> I
motor
and the diode would have to conduct in the
reverse direction, which is clearly not possible.
During the time when the capacitor C
S
is charging up to V
D
,
the voltage across L
S
will always be such as to increase the
current in the bottom MOSFET, I
M1
. When V
CS
=V
D
the
voltage across L
S
will reverse and I
M1
will fall. Diode D2 will
nowturn on. The energy stored in L
S
will nowbe transferred
toC
S
. This energy will subsequently be dissipated in R
S
and
the MOSFET.
If the ratio of peak to average current carrying capability of
the switch is large then it follows from equation 1 that L
S
can be made smaller. This reduces the energy that is
transferred to C
S
when the MOSFETs switch off during
normal operation. Hence the efficiency of the inverter is
improved.
The short circuit fault current can be limited by connecting
an inductor in the d.c. link as shown in Fig. 4. In this case
analysis similar to that outlined above shows that the
excellent ratio of peak toaverage current carryingcapability
of Philips Powermos again reduces the losses in the
inverter. It has been shown that components chosen to
ensuresafeshutdownof inverters for motor drives canhave
deleterious effects on the efficiency of the inverter. In
particular the additionof an inductor tolimit the peak current
through the semiconductor switches when the output is
short circuited can increase the switching losses. The high
peak to average current carrying capability of Philips
Powermos reduces the size of this choke and the losses it
causes.
Fig. 4 Modified inverter circuit to limit short circuit
current
V =
√
L
s
C
s
. I
SC
dI
M1
dt
=
V
D
−V
CS
−V
diode
L
s
252
Motor Control Power Semiconductor Applications
Philips Semiconductors
3.1.3 MOSFETs and FREDFETs for Motor Drive Equipment
The paper discusses the properties of the FREDFET, a
technology which yields a MOSFET with a very fast built-in
reverse diode with properties similar to a discrete fast
epitaxial rectifier. It is shown that its characteristics make
the device an excellent choice for high frequency bridge leg
systems such as 20 kHz AC motor control systems.
Investigations have been carried out in dedicated test
circuits as well as in a 20 kHz ACMC system which show
that the FREDFET exhibits very low diode losses. It
comparesfavorably with adiscrete solution, usingtwoextra
diodes to overcome the slow speed of the standard built-in
diode, and also with devices from the present standard
ranges.
Introduction
The Power MOSFET has inherent in its structure a large
built-indiodewhichispresent betweenthesource anddrain
of the device. Under single switch applications such as
forward and flyback converters, this diode isn’t forward
biased and consequently its presence can be ignored. In
the case of bridge legs, however, this diode is forced into
forward conduction and the properties of the diode become
of prime importance. The reverse recovery of the built-in
diode is relatively slow when compared with discrete fast
recovery epitaxial diodes (FRED’s). As aconsequence, the
currents flowing through the MOSFET and its diode can be
high and the losses considerable.
Fig.1. ACMC bridge leg.
Theselosses can be reduced through the application of two
extra diodes as discussed in section 2. A more elegant
solution is a MOSFET with a built-in diode which exhibits
properties similar to discrete fast epitaxial rectifiers. The
FREDFET has been designed to satisfy this requirement.
This paper presents the results of studies, carried out with
new FREDFETs, comparing them with both the
conventional MOSFET and the discrete solution.
MOSFETS in half bridge circuits
MOSFETS have gained popularity in high frequency AC
motor controllers, since they enable frequencies above
20kHz to be used. The short on-times required in ACMC
systems make the use of bipolar devices very difficult, due
to the storage times. Both the short switching times and the
ease of drive of the MOSFET are essential ingredients in
the design of a ultrasonic ACMC. Difficulties can arise,
however, when trying to use the built in source to drain
diode of the MOSFETs.
Onebridge legof an ACMCis shown inFig.1. When current
is flowing out of the load, MOSFET T1 and freewheel diode
D2 conduct alternately. Conversely, when flowing into the
load, the current alternates between TR2 and D1. Consider
the case when current is being delivered by the load, such
that thepair TR1/D2carriesthecurrent. Whenthe MOSFET
conducts current, the voltage at the drain is almost zero
and the diode blocks. When the MOSFET is turned off by
the drive circuit, the inductive load forces the voltage to
increase making diode D2 conductive. Associated with
conduction of the diode is a volume of stored charge which
must be removed as the MOSFET TR1 returns to its
on-state.
Fig.2. Recovery waveforms
Top: VDS, ID of TR1 turning on
Bottom: VD, ID of D2. (t=200ns/div)
The waveforms appropriate to this situation can be found
in Fig.2. One may observe that during the diode recovery
time, the voltage across the MOSFET remains high whilst
at the same time its current increases rapidly. Temporarily
the drain current will increase to a level higher than the load
current since the diode recovery current is added to it. Long
recovery times and excessive charge storage result in a
very high power dissipation in the MOSFET.
253
Motor Control Power Semiconductor Applications
Philips Semiconductors
Fig.3. Network with extra diodes.
Using the inherent source drain diode of a conventional
MOSFET as the freewheel diode results in considerable
losses, since it is not optimised for fast switching or low
stored charge. To avoid such losses the internal diode is
usuallydeactivatedbymeansof aspecial circuit (seeFig.3).
This circuit, using two diodes D2 and D3, ensures that all
freewheel current is flowing through the external diode D2
and not through the internal diode D1. When the MOSFET
is switched on, the current flows via D3. This circuit is
required for each MOSFET in the bridge. The FREDFET,
which has a fast built-in diode offers the prospect of a much
neater solution for these kind of circuits.
Technology of the FREDFET
Fig.4. FREDFET cross section.
The power MOSFET is a majority carrier device and
features fast turn-on and, in particular, fast turn-off. There
are no charge storage effects such as in bipolar devices.
In bridge leg applications the internal diode can become
forward biased and the N- epitaxial region (see Fig.4) is
flooded with holes, which must later be removed when the
source becomes negatively biased again with respect to
the drain.
The stored charge can be removed by holes diffusing from
the N- epilayer into the P+ and P-body regions, and also
by recombination of holes and electrons in the N- epitaxial
region. A significant reduction in the stored charge Qrr can
be achieved by doping the devices with heavy metal atoms
to introduce recombination centres. A standard MOSFET
will normally have a low concentration of recombination
centres. In the FREDFET the heavy metal doping does not
have any significant effects on the threshold voltage or the
transconductance, however, the efficiency with which the
extra recombination centres remove the stored charge is
improved substantially. This can be observed when
comparing Qrr and trr results for killed and non-killed
devices as described in the next section.
FREDFET measurements
A comparison of the reverse recovery characteristics of the
internal diode has been made for a BUK637-500B
FREDFETandasimilar competitor conventional MOSFET.
The devices were tested using an ’LEM 20 A Qrr’ gear.
Fig.5. Reverse recovery waveforms, t=200ns/div;
T=25˚C
Oscillograms are presented in fig.5. showing the test
waveforms for both the FREDFET and the conventional
device. The diode turn-off process commences at t=t
0
,
where upon the forward current (set at 10A) is reduced at
a preset 100A/usec. The current falls through zero and the
diode passes into reverse conduction signifying the
removal of stored charge. At t=t
2
sufficient charge has been
removed for the formation of a depletion layer across the
p-n junction. The dI/dt starts to fall and a voltage builds
across an inductance in the source circuit such that the
source becomes negatively biased with respect to drain.
254
Motor Control Power Semiconductor Applications
Philips Semiconductors
Beyond t
2
the dI/dt reverses and the diode current begins
to fall as the drain-source voltage rises to the clamp setting.
The moment t
3
identifies the point at which the diodecurrent
has fallen to 10% of its peak value, Irrm.
The reverse recovery time, trr is defined as t
3
-t
1
while the
total stored charge Qrr is equal to the area of the shaded
region, fig.5. A direct comparison of the diode reverse
recovery at 25˚C is shown in fig.6. The respective values
for trr, Qrr and Irrm are presented in Table 1.
T
j
= 25˚C trr (ns) Qrr (uC) Irrm (A)
BUK637-500B 193 1.2 8
Conventional device 492 7.5 23
Table 1.
It can be seen that Qrr is 84 %lower for the FREDFET while
Irrmand trr approximately 60 %less. Fig.7 shows the same
comparison measured at a junction temperature of 150˚C.
Corresponding values of trr, Qrr and Irrm are shown in
Table 2.
Fig.6. Comparison of diode reverse recovery
(t=100ns/div; T
j
=25˚C)
Fig.7. Comparison of diode reverse recovery
(t=100ns/div; T
j
=150˚C)
T
j
= 150˚C trr (ns) Qrr (uC) Irrm (A)
BUK637-500B 450 4.5 17
Conventional device 650 10.5 26
Table 2.
While higher temperatures are known to reduce the
effectiveness of recombination centres, it is clear that
significant improvementsstill exist even at thepeak junction
temperature with savings of 55 % in Qrr and over 30 % in
Irrm and trr evident for the FREDFET
Performance in a bridge circuit
The circuit of Fig.8 is a simplified representation of a bridge
circuit, and was used to evaluate the performance of the
BUK637-500BFREDFETagainst aconventional MOSFET
and a conventional MOSFET configured with both series
and parallel diodes.
Fig.8. Simplified bridge circuit.
In each case the MOSFET in the bottom leg was switched
on until the load current reached the desired value, at which
point it was switched off, forcing the load current to flywheel
throughthe inverse diodeof theupper leg. The lower device
was then switched on again to obtain reverse recovery of
the upper diode. The current levels were set to simulate the
conditions found in a 20 kHz 1 kVA ACMC. The device in
the upper leg was mounted on a temperature controlled
heatsink and the test was performed at very low duty cycle
such that T
case
approximated to T
j
.
Oscillograms of current and voltage in relation to the lower
leg are shown for the conventional device, conventional
device plus external diodes andthe FREDFETin Fig.9. The
freewheel current in the upper diode is related to current in
the MOSFET as shown in Fig.2. Also presented are the
power waveforms for both the upper and lower legs in each
case.
255
Motor Control Power Semiconductor Applications
Philips Semiconductors
Fig.9. Waveforms (100ns/div; T
j
=110˚C)
The superior performance of the FREDFET when
compared to the conventional device is clear with the
current overshoot kept to below8 A compared to over 18 A
using the latter. The lower reverse recovery current and
faster trr are reflected in the power waveforms with nearly
double the peak power being dissipated in the lower leg
using a conventional device compared to that dissipated
using the FREDFET. The power dissipated by the internal
diode of the FREDFET is also observed to be remarkably
reduced in comparison with the conventional MOSFET.
The performance of the three device implementations is
summarised in table 3 which shows the total energy
dissipated during switching in both legs for each case.
It can be seen that using a conventional MOSFET without
the external diode circuitry involves a six fold increase in
the energy dissipated in the MOSFET. However if a
FREDFET implementation is used the turn-on energy is
only a factor of two above the minimumachievable with the
extradiodes. Energy lossinthediodeitself isrelativelysmall
for boththe FREDFETandthe external diodeconfiguration,
T
j
= 110˚C Energy Dissipated
Lower Leg Upper Leg
(mJ) (mJ)
Conventional MOSFET 1.2 0.533
MOSFET plus external 0.2 0.035
diodes
BUK637-500B FREDFET 0.4 0.095
Table 3.
being less than 25 % that dissipated in the lower leg. For
the conventional device the diode loss is more significant,
equal to 44 %of the power dissipated during turn-on in the
lower leg. The energy value presented above represent
only the losses during turn-on, in addition to these are the
on-state losses which for the external diode configuration
include the extra power dissipated by the series diode.
256
Motor Control Power Semiconductor Applications
Philips Semiconductors
Fig.10. Simplified circuit output stage circuit diagram (One phase shown)
20 kHz ACMC with FREDFETS
The three device options discussed above have each been
implemented in a 20 kHz AC Motor Control circuit. The
inverter provides a three phase 1 kVA output from a single
phasemains input. Asimplified diagramof one of the output
stages is presented in Fig.10.
Figure 11 shows the current waveforms as the load current
commutates from the upper leg (anti-parallel diode in
conduction) to the lower leg (turn-on of the MOSFET) for
each device option. In each case the load current is 4.5 A.
Fig.11aillustrates the largeovershoot current obtainedwith
aconventional devicewhileFig.11bshowswhat isachieved
when the two external diodes are incorporated. Finally
Fig.11c shows the current waveform for the FREDFET
implementation where the current overshoot is kept below
1.5 A by the built-in fast recovery diode of the device.
Conclusions
It has been shown that the FREDFET compares favorably
in ACMC systems compared with the standard MOSFET.
The normally employed extra diodes can be omitted thus
saving considerable costs in the system. The fast internal
diode is seen to be comparable with the normally used fast
epitaxial rectifiers and enables a simple ultrasonic ACMC.
Fig.11. Current waveforms in 20 kHz ACMC
(t=200ns/div; ID=2A/div).
257
Motor Control Power Semiconductor Applications
Philips Semiconductors
3.1.4 A Designers Guide to PowerMOS Devices for Motor
Control
This section is intended to be used as a designers guide to
the use and selection of power MOSFETS and FREDFETS
in a.c. motor control (ACMC) applications. It is particularly
concerned with the variable speed operation of induction
motors using pulse width modulation (PWM) techniques.
One of the most important considerations in the design of
ACMC inverters is the optimum choice of power switching
device and heatsinking arrangement. Other factors which
relate to the losses in the power switch are switching speed
and design of suitable gate drive circuits. This section
addresses each of these factors and presents a series of
design graphs relating system operating temperature to
devicetype andheatsinksize for systems ratedup to2.2kW
and operated from a single phase supply.
It should be noted that this article refers to some products
which may not be available at this time.
Introduction
Variable speed control of induction motors is a widespread
requirement in both industrial and domestic applications.
The advantages of an induction motor drive over alternative
systems such as d.c. motor controllers include:
-high reliability and long life
-low maintenance requirements
-brushless operation
-availability of standard machines.
With the advent of power switching devices able to provide
the required ratings for ACMC applications and the
availability of fast PWM pattern generation circuits these
advantages have lead to an increasing number of
applications where the inverter-fed induction motor system
produces a cost effective drive. Before considering in detail
the use of MOSFETs and FREDFETs in ACMC inverters it
is worth briefly considering the principles and operation of
the induction motor, the PWM method of voltage control
and the characteristics of the switching devices.
The induction motor
Induction motors are three phase machines where the
speedof rotation of the stator field (the synchronous speed,
N
s
) is determined by the number of poles, p, and the
frequency of the applied voltage waveforms, f
s
.
(1)
Torque production in an induction motor is due to the
interaction of the rotating stator field and currents in the
rotor conductors. Torqueisdevelopedwhentherotor speed
’slips’ behind the synchronous speed of the stator travelling
field. Fig.1 shows the torque-speed characteristic of an
induction motor where ω
s
is the speed of the stator field

s
=2πf
s
) and ω
r
is the rotor speed. The difference between
the two is usually relatively small and is the slip speed. The
solid portion of the characteristic is the main region of
interest where the motor is operating at rated flux and at
low slip. In this region the rotor speed is approximately
proportional to the stator supply frequency, except at very
low speeds. The operating point of the motor on its
torque-speed characteristic is at the intersection of the load
torque line and the motor characteristic. For small amounts
of slip and at constant airgap flux the motor torque is
proportional to the slip speed.
Fig.1 AC induction motor, Torque-Speed characteristic.

Fig.2 Torque-Speed characteristics, Variable speed
operation.
Torque
Speed
Te
Rated flux
Load
torque
Motor
torque
Slip
w w
r s
Torque
Speed
Te
Load
torque
f
1
f
2
f
3
w w w w w w
r1 s1 r2 s2 r3 s3
V/f = constant
N
s
=
120.f
s
p
(rpm)
259
Motor Control Power Semiconductor Applications
Philips Semiconductors
Inavariablespeedsystemthe motor is operatedon aseries
of torque-speed characteristics as the applied frequency is
increased. Fig.2 shows a set of characteristics for three
conditions, ω
s1
, ω
s2
andω
s3
. The correspondingrotor speeds
are ω
r1
, ω
r2
and ω
r3
. However in order that the airgap flux in
the motor is maintained at its rated value then the applied
voltage must be reduced in proportion to the applied
frequency of the travelling field. This condition for constant
airgap flux gives the constant v/f requirement for variable
speed control of a.c. induction motors. At low speeds this
requirement may be modified by voltage boosting the
supply to the motor in order to overcome the increased
proportion of ’iR’ voltage drop in the motor windings which
occurs at low speeds.
The PWM Inverter
A variable voltage, variable frequency three phase supply
for the a.c. induction motor can be generated by the use of
a pulse width modulated (PWM) inverter. A schematic
diagram of the system is shown in Fig.3. The system
consists of a rectified single phase a.c. supply, which is
usually smoothed to provide the d.c. supply rails for the
main switching devices. Alternate devices in each inverter
leg are switched at a high carrier frequency in order to
provide the applied voltagewaveforms to the motor. During
each switching cycle the motor current remains
approximately constant due to the inductive nature of the
AC motor load.
Fig.3 PWM inverter, block diagram.
In the circuit of Fig.3 the main switching devices are
MOSFETs and each MOSFET has a freewheeling diode
connected in antiparallel. The motor load current is
determined by the circuit conditions. When the load current
in a particular phase is flowing into the motor then
conduction alternates between the top MOSFET and the
bottom freewheel diode in that inverter leg. When the load
current is flowing from the motor then the bottom MOSFET
and top diode conduct alternately. Fig.4 shows a typical
Fig.4 PWM phase voltage waveform.
sinusoidal PWM voltage waveform for one motor phase.
The three phases are maintained at 120˚ relative to each
other.
Both the frequency and amplitude of the fundamental
component of the output voltage waveform can be varied
by controlling the timing of the switching signals to the
inverter devices. Adedicatedi.c. is usuallyused togenerate
the switching signals in order to maintain the required v/f
ratio for a particular system.
(1)
The PWM algorithm
introduces a delay between the switching signal applied to
the MOSFETs in each inverter legwhich allows for the finite
switching times of the devices andthus protects the system
from shoot-through conditions.
Additional harmonic components of output voltage, such as
the third harmonic, can be added to the PWM switching
waveform.
(2,3)
The effect of adding third harmonic to the
output voltage waveform is to increase the amplitude of the
fundamental component of output voltage from a fixed d.c.
link voltage. This is shown in Fig.5. The third harmonic
component of output phase voltage does not appear in the
output line voltage due to the voltage cancellation which
occurs in a balanced three phase system. Using this
technique it is possible to obtain an output line voltage at
the motor terminals which is nearly equal to the voltage of
the single phase supply to the system.
For many applications the PWMACMCsystemis operated
at switching speeds in the range 1kHz to 20kHz and above.
Operation at ultrasonic frequencies has advantages that
the audible noise and RFI interference are considerably
reduced. The advantages of PowerMOS devices over
bipolar switching devices are most significant at these
switching speeds due to the low switching times of
PowerMOS devices. Additional advantages include good
overload capability and the fact that snubber circuits are
not usually required. It is usually straightforward to operate
PowerMOS devices in parallel to achieve higher system
currents than can be achieved with single devices. This is
because the devices have a positive temperature
coefficient of resistance and so share the load current
V
dc
0
V
dc
2
Mains
input
Rectifier Filter Three phase
inverter
Induction
motor
A
B
C
PWM pattern
generator
Gate drivers
260
Motor Control Power Semiconductor Applications
Philips Semiconductors
Fig.5 Addition of third harmonic to output voltage
waveform.
equally. The simple gate drive requirements of PowerMOS
devices means that a single gate circuit can often be used
for a range of devices without modification.
MOSFETs and FREDFETs in ACMC
One of the features associated with the transfer of
conduction between the switching devices and the
freewheel diodes in an inverter circuit is the reverse
recovery of the freewheel diode as each conducting
MOSFET returns to its on-state. Reverse recovery current
flows due to the removal of stored charge from a diode
following conduction. Fig.6 shows the device current paths
in an inverter leg when conduction is transferred from the
top diode to the bottom MOSFET.
The switching waveforms are shown in Fig.7 where the
diode reverse recovery current is I
rr
and the time taken for
the reverse recovery currents to be cleared is t
rr
. The
amount of stored charge removed from the body of the
diode is represented by the area Q
rr
. The reverse recovery
current flows through the MOSFET which is being turned
on in addition to the load current and thus causes additional
turn-onlosses. The amount of storedcharge increases with
increasing temperature for a given diode. Both the
magnitude of the reverse recovery current and its duration
must be reduced in order to reduce the switching losses of
the system.
This effect is important because inherent in the structure of
a power MOSFET is a diode between the source and drain
of the device which can act as a freewheeling diode in an
inverter bridge circuit. The characteristics of this diode are
not particularly suited to its use as a freewheel diode due
to its excessive charge storage and long recovery time.
These would lead to large losses and overcurrents during
the MOSFET turn-on cycle.
Fig.6 Inverter bridge leg.
Fig.7 Diode reverse recovery waveforms.
Fig.8 Circuit to deactivate MOSFET intrinsic diode.
In inverter applications the internal diode of a MOSFET is
usually deactivated by the circuit of Fig.8. Conduction by
the internal MOSFET diode is blocked by the series
Schottky diode (D3). This series device must carry all the
MOSFETcurrent and so contributes to the total conduction
losses. The external diode, usually a fast recovery epitaxial
0 30 60 90 120 150 180
0
1
No 3rd harmonic Added 3rd harmonic
Fundamental component Fundamental + 3rd harmonic
V
dc
I
L
I
rr
I
L
I
L
MOSFET
current
Diode
current
Output
voltage
I
rr
t
rr
Time
Time
Time
I
L
+ I
rr
V
dc
Q
rr
D1
D2
D3
261
Motor Control Power Semiconductor Applications
Philips Semiconductors
diode (FRED), carries the freewheel current. This device is
chosensuch that its lowvaluesof I
rr
andt
rr
reducetheoverall
switching losses.The FREDFET is essentially a MOSFET
with a very fast built-in diode, and hence can replace the
network of Fig.8 with a single device giving a very compact
ACMCinverter design using only six power switches.
(4)
The
reverse recovery properties of a FREDFET diode are
similar to those of a discrete FRED thus giving a
considerably neater circuit without any loss in switching
performance.
ACMC design considerations
Voltage rating
The first selection criteria for a PowerMOS device in an
inverter application is the voltage rating. For a 240V a.c.
single phase supply the peak voltage is 340V. Assuming
that the rectifier filter removes the voltage ripple
components which occur at twice the mains frequency, and
dependent on the values of the filter components and
rectifier conduction voltage, then the dc link voltage will be
around 320V. Devices with a voltage rating of 500V will
allow sufficient capability for transient overvoltages to be
well within the capability of the device. Thus the dc link
voltage is given by:
V
dc
= √2.V
ac
(2)
where V
ac
is the rms ac input line voltage.
The output phase voltage, shown in Fig.4, switches
between the positive and negative inverter rail voltages.
The mean value of the output voltage is V
dc
/2. Neglecting
the delays which occur due to the finite switching times of
the devices then the maximum rms output phase voltage
is given by:
(3)
and hence the rms output line voltage is:
(4)
Comparing equations (2) and (4) shows that:
V
line
= 0.866.V
ac
(5)
This shows that the fundamental rms line output voltage is
13% less than the rms ac input voltage. Adding third
harmonic tothe PWMoutput waveformcan restore this rms
output voltage to the ac input voltage. In a practical system
the effect of switching delays and device conduction
voltages can reduce the output voltage by upto 10-15%.
Current rating
The nameplate rating of an induction motor is usually
quoted in terms of its power (W) and power factor (cosϕ).
The VArequirement of the inverter is found fromthe simple
equation:
Power(W) = η.cosϕ.VA (6)
where η is the efficiency. In terms of the rms motor line
voltage (V
line
) and output current (I
L
):
VA = √3.V
line
.I
L
(7)
The efficiency of small ac induction motors can be quite
high but they usually run at quite poor power factors, even
at rated conditions. For small induction motors (<2.2kW)
the efficiency-power factor product is typically in the range
0.55 to 0.65. The exact value will vary from motor to motor
and improves with increasing size. Thus fromequations (6)
and (7) it is possible to calculate the approximate rms
current requirement. The peak device current for sinusoidal
operation is given by equation (8). (NB. The devices will
experience currents in excess of this value at switching
instants.)
I
max
=√2.I
L
(8)
Device package
The device package chosen for a particular application will
depend upon device rating, as discussed above, as well as
circuit layout and heatsinking considerations. Philips
PowerMOS devices are available in a range of package
types to suit most applications.
Drive considerations
Unlike bipolar devices the MOSFET is a majority carrier
device and so no minority carriers must be moved in and
out of the device as it turns on and off. This gives the fast
switching performance of MOSFET devices. During
switching instants the only current which must be supplied
by the gate drive is that required to charge and discharge
the device capacitances. In order to switch the device
quickly the gate driver must be able to rapidly sink and
source currents of upto 1A. For high frequency systems the
effect of good gate drive design to control switching times
is important as the switching losses can be a significant
proportion of the total system losses.
Fig.9 shows an equivalent circuit of the device with the
simplest gate drive arrangement. The drain-source
capacitance does not significantly affect the switching
performance of the device. Temperature only has a small
effect onthe valuesof thesecapacitances andsothedevice
switchingtimes areessentiallyindependent of temperature.
The device capacitances, especially C
GD
, vary with V
DS
and
this variation is plotted in data for all PowerMOS devices.
V
ph
=
1
√2
.
V
dc
2
V
line
= √3. V
ph
= √3.
V
dc
2. √2
262
Motor Control Power Semiconductor Applications
Philips Semiconductors
Fig.9 MOSFET capacitances and basic gate driver
Turn-on (Fig.10)
A turn-on gate voltage pulse commences at t
0
. The gate
voltage v
GS
rises as current flows into the device via R
GG
.
C
GS
starts to charge up until v
GS
reaches its threshold value
v
GS(TO)
at time t
1
. The device is now operating in its active
region with a relatively high power loss. The MOSFET
current, rises as a function of v
GS
-v
GS(TO)
and causes a
corresponding fall in the diode current. Thus the rate of fall
of diode current, and hence the amount of diode reverse
recovery current, is controllable by the rate of rise of v
GS
.
At time t
4
the diodehas recovered and the MOSFETcurrent
is equal to the load current, I
L
. V
GS
is clamped to v
GS(IL)
and
so the gate current is given by:
(9)
This current flows through C
GD
, discharging it and so the
rate of fall of output voltage is given by:
(10)
The fall in v
DS
commencing at time t
3
is not linear, principally
because C
GD
increases with reducing v
DS
. At time t
5
C
GD
is
fully discharged and the device is on. The gate voltage
continues to charge up to its final value, v
GG
. It is usual to
have a value of v
GG
significantly higher than v
GS(IL)
because
r
DS(on)
falls with increasing v
GS
. Additionally a high value if
v
GG
speeds up the turn-on time of the device and provides
some noise immunity.
Switching losses occur during the period t
1
to t
5
. The
minimum turn-on time is usually governed by the dv/dt
capability of the system. Reducing the turn-on time
increasesthe amount of diodereverserecovery current and
hence increases the peak power dissipation, however the
total power dissipated tends to reduce.
Fig.10 MOSFET turn-on waveforms
Fig.11 MOSFET turn-off waveforms
Turn-off (Fig.11)
Unlike the conditions which occur at turn-on there is no
interaction between the switching devices at turn-off. The
switching waveforms are, therefore, relatively
straightforward. The gate voltage is switched to ground or,
if very fast turn-off is required, to a negative voltage. During
the delay time t
0
to t
1
the gate voltage falls to the value
required to maintain the output current, I
O
. From time t
1
to
t
2
the gate supply is sinking current and C
GD
charges the
drain up to the positive rail voltage. V
GS
then continues to
fall and so the device current falls between times t
2
and t
3
,
At t
3
the gate voltage falls belowits threshold value and the
device turns off. The rate of rise of output voltage is:
C
DS
C
GD
C
GS
D
S
G
R
GG
V
GG
t0 t1 t2 t3 t4 t5 t6
v
GG
v
GS
i
DIODE
i
D
v
DS
V
GG
V
GG
I
L
v
GG
v
GS
i
D
v
DS
t0 t1 t2 t4
V
dc
t3
i
G
=
v
GG
− v
GS
(IL)
R
GG
dv
DS
dt
=
i
G
C
GD
=
(v
GG
−v
GS
(IL)
)
R
GG
. C
GD
263
Motor Control Power Semiconductor Applications
Philips Semiconductors
(11)
Parasitic turn-on
In a high frequency system the device switching times are
necessarily short and so the rates of change of inverter
output voltage are high. The high values of dv/dt which
occur when one device turns on can cause a sufficiently
high voltage at the gate of the other device to also turn it
on. The coupling occurs via C
GD
and C
GS
. If the rate of
change of output voltage due to one device turning on is
given by dv
DS
/dt then the voltage that would be seen at the
gate of the other device if it were left open circuit is:
(12)
If C
GS
is shorted out by a zero impedance, then clearly
dV
GS
/dt can be reduced to zero. In practiceachieving a zero
impedance in the gate-source circuit is extremely difficult
and dV
GS
/dt will not be zero. In the worst case this rising
gate voltage will turn the device fully on and a destructive
shoot-through condition occur. If the conditions are less
severethentheMOSFETmay onlyturn onfor ashort period
of time giving rise to an additional overcurrent in the turn-on
cycleof the device being switched. Parasitic turn-on, as this
effect is referred to, must be prevented by either limiting
dv
DS
/dt or by ensuring that v
GS
is clamped off. In systems
wherethe off-state gate-sourcevoltage is negativethen the
possibility of parasitic turn-on can be reduced.
Gate drive circuits for ACMC inverters
The previous section discussed device switching
waveformsusingaresistive gatedrive circuit. In this section
variousalternativegatedrivecircuits for ACMCapplications
arepresented andcompared. The discussionassumes that
eachMOSFETgate drivecircuit isisolated anddrivenusing
aCMOSbuffer capableof sinkingandsourcingtherequired
gate current. In unbuffered gate drive circuits the leakage
inductance of an isolating pulse transformer can increase
the gate impedance, thus reducing the maximum possible
switching rate and making the MOSFET more susceptible
to parasitic turn-on. A zener diode clamp protects the
gate-source boundary from destructive overvoltages.
Identical drivers are used for the top and bottom devices in
each inverter leg. The gate drive circuits presented here
were tested using BUK638-500A FREDFETS and
BUK438-500A MOSFETS in a 20kHz, 2.2kW ACMC
system.
Figure 12 shows the simplest arrangement which gives
independent control of the turn-on and turn-off of the
MOSFET. Increasingthe gateimpedanceto reducedV
DS
/dt
levels will raise the susceptibility to parasitic turn-on
problems. The gate-source voltage can be clamped off
Fig.12 Gate drive circuit with different turn-on and
turn-off paths
Fig.13 Gate drive circuit with improved parasitic turn-on
immunity
more effectively if the dynamic impedance between gate
and source is reduced as shown in the circuit of Fig.13. The
additional gate-source capacitance ensures that v
GS
does
not rise excessively during conditions when parasitic
turn-on could occur (Equation 12). The external capacitor
C
GS
‘ must be charged up at turn-on. If C
GS
‘ is made too large
then the current required may be beyond the rating of the
drive buffer. The speed-up diode, D2, ensures that the
turn-on is not compromised by C
GS
‘and R
GGR
. At turn off the
additional capacitance slows down dI
D
/dt since the
gate-sourceRCtimeconstant is increased. It must benoted
that one effect of the turn-off diode, D1, is to hold the
off-statevalueof v
GS
above0V, andhencesomewhat closer
to the threshold voltage of the device.
An alternative circuit which may be used to hold the
MOSFET off-state gate-source voltage below its threshold
value is shown in Fig.14. The pnp transistor turns on if the
gate-source voltage is pulled up via C
GD
and C
GS
and thus
the device remains clamped off.
dv
DS
dt
=
i
G
C
GD
=
v
GS
(IL)
R
GG
. C
GD
RGGF 100R
RGGR 10R
D1
dv
GS
dt
=
C
GD
C
GS
+C
GD
.
dv
DS
dt
RGGF 100R
RGGR 10R
CGS’
10nF
D2
D1
264
Motor Control Power Semiconductor Applications
Philips Semiconductors
Fig.14 Alternative gate drive circuit with improved
parasitic turn immunity
Parallelling of PowerMOS devices
Moving to a system using parallelled MOSFETs requires
only slight modifications to the gate drive circuit. One
consideration may be the capability of the drive buffer to
provide the currents required at the switching instants. The
switching speed of the system can be maintained. using a
lower impedance gate drive. It is recommended that small
differential resistors, as shown in Fig.15, are used to damp
out any oscillations which may occur between the switching
devices and the rest of the circuit. The circuit of Fig.13 can
be modified for operation with parallelled devices to that
shown in Fig.16.
Circuit layout considerations
The effects of poor circuit design and layout are to increase
RFI and noise and to compromise the performance and
speed of the system due to stray inductances. The
precautions which must be taken to minimise the amount
of stray inductance in the circuit include:
- positioning the gate drive circuits, especially zener diodes
and dv/dt clamping circuits as close as possible to the
power MOSFETs.
- reducing circuit board track lengths to a minimum and
using twisted pairs for all interconnections.
- for parallelled devices, keeping the devices close to each
other and keeping all connections short and symmetrical.
Fig.15 Gate drive circuit for parallelled devices
Fig.16 Gate drive circuit for parallelled devices with
improved parasitic turn-on immunity
Modelling of parasitic turn-on
Using the simple MOSFET model of Fig.9 it is possible to
study the susceptibility to parasitic turn-on of alternative
gate drive circuits. Considering the switching instant when
the bottom MOSFET is held off and the top MOSFET is
switched on, the voltage across the bottom MOSFET
swings from the negative inverter rail to the positive one.
The switching transient can be modelled by an imposed
dv
DS
/dt across C
GD
and C
GS
and hence the effect of gate
circuit designanddv
DS
/dt onv
GS
canbestudiedusingsimple
SPICE models.
Typical data sheet values of C
GD
and C
GS
for a 500V
MOSFET were used. The simulated results assume
constant dv
DS
/dt, that freewheel diode reverserecovery can
be neglected and that the off-state gate drive buffer output
is at 0V with a sink impedance of around 5Ω. In practice
the dv
DS
/dt causing parasitic turn-on is not constant and is
only at its maximum value for a small proportion of the
voltage transition. Thus the results shows here represent
a’worst-case’ condition for thealternativegatedrive circuits
used to clamp v
GS
to below its threshold value, typically 2V
to 3V. (The simple circuit model used here ceases to
become valid once v
GS
reaches v
GS(TO)
(time t
1
in Fig.10)
when the MOSFET starts to turn on.)
Fig.17 shows the relevant waveforms for the circuit of Fig.9
with R
GG
=100Ω. The top waveform in Fig.17 shows an
imposed dv
DS
/dt of 3.5V/ns and a dc link voltage of 330V.
The centre trace of Fig.17 shows that v
GS
rises quickly
(reaching 3Vin 25ns); at this point the MOSFETwould start
toturn on. The bottomtrace shows the C
GD
charging current
sinking through the gate drive resistor R
GG
. For the circuit
of Fig.12with R
GGF
=100ΩandR
GGR
=10Ω, Fig.18shows that
the gate source voltage is held down by the reduced drive
impedance but still reaches 3V after 35ns.
RGGF 47R
RGG’ 10R
RGG’ 10R
CGS’
20nF
RGGF 47R
RGG’ 10R
RGG’ 10R
265
Motor Control Power Semiconductor Applications
Philips Semiconductors

Fig.17 Parasitic turn-on waveforms for circuit of Fig.9
Fig.19 Parasitic turn-on waveforms for circuit of Fig.13,
C
GS
‘=10nF
Fig.21 Parasitic turn-on waveforms for circuit of Fig.16,
C
GS
‘=20nF
Fig.18 Parasitic turn-on waveforms for circuit of Fig.12
Fig.20 Parasitic turn-on waveforms for circuit of Fig.13,
C
GS
‘=4.7nF
Fig.22 Parasitic turn-on waveforms for circuit of Fig.16,
L
s
=20nH

stray inductance
0 2E-08 4E-08 6E-08 8E-08 1E-07
0
5
10
15


0 2E-08 4E-08 6E-08 8E-08 1E-07
0
100
200
300
400


0 2E-08 4E-08 6E-08 8E-08 1E-07
0
0.05
0.1
0.15


v
DS
(V)
v
GS
(V)
i
GG
(A)
0 2E-08 4E-08 6E-08 8E-08 1E-07
0
2
4
6


0 2E-08 4E-08 6E-08 8E-08 1E-07
0
100
200
300
400


0 2E-08 4E-08 6E-08 8E-08 1E-07
0
0.1
0.2
0.3
0.4


v
DS
(V)
v
GS
(V)
i
GG
(A)
0 2E-08 4E-08 6E-08 8E-08 1E-07
-0.1
0
0.1
0.2
0.3


0 2E-08 4E-08 6E-08 8E-08 1E-07
0
100
200
300
400


0 2E-08 4E-08 6E-08 8E-08 1E-07
0
1
2
3
4
5


i
CG’
i
RGGR
v
DS
(V)
v
GS
(V)
i
GG
(A)
0 2E-08 4E-08 6E-08 8E-08 1E-07
0
100
200
300
400


0 2E-08 4E-08 6E-08 8E-08 1E-07
0
1
2
3
4


0 2E-08 4E-08 6E-08 8E-08 1E-07
-0.1
0
0.1
0.2
0.3
0.4


i
RGGR
i
CG’
v
DS
(V)
v
GS
(V)
i
GG
(A)
0 2E-08 4E-08 6E-08 8E-08 1E-07
0
100
200
300
400






0 2E-08 4E-08 6E-08 8E-08 1E-07
0
1
2
3
4


0 2E-08 4E-08 6E-08 8E-08 1E-07
-1
-0.5
0
0.5
1


v
DS
(V)
v
GS
(V)
v
Ls
(V)
0 2E-08 4E-08 6E-08 8E-08 1E-07
0
1
2
3
4


0 2E-08 4E-08 6E-08 8E-08 1E-07
0
100
200
300
400


0 2E-08 4E-08 6E-08 8E-08 1E-07
0
0.2
0.4
0.6
0.8


i
CG’
i
GG
v
DS
(V)
v
GS
(V)
i
GG
(A)
266
Motor Control Power Semiconductor Applications
Philips Semiconductors
Figure 19 shows the response of the circuit of Figure 13
with C
GS
‘=10nF. Here the gate-source voltage is held down
during the parasitic turn-on period and so the MOSFET
stays off. If the value of C
GS
‘ is reduced to 4.7nF then the
results given in Fig.20 showthat v
GS
reaches 3V after 55ns
thus reducing immunity to parasitic turn-on.
Figures 21 and 22 show the conditions for parallel
connected MOSFETs using the circuit of Fig.16. In Fig.21,
for R
GG1
=47Ω, R
GG
‘=10Ω and C
GS
‘=20nF, the bottom trace
in the figure shows that a potential parasitic turn-on
condition is avoided and v
GS
is held below its threshold
value. The bottom trace in Fig.21 shows most of the
parasitic turn-on current is taken by C
GS
‘. Figure 22 shows
the effect of stray inductance between the gate drive circuit
and the PowerMOS device. The circuit of Fig.16 has been
modified by the addition of 20nH of stray inductance
between the gate node and the dv/dt clamping network.
During switching of the top device with dv/dt=3.5V/ns the
stray inductance develops over 0.6V due to coupling via
C
GD
. Clearly this could significantly affect the performance
of the drive during normal turn-on, and increase the
prospect of the bottom MOSFET being subject to parasitic
turn-on problems.
These results show that immunity to parasitic turn-on can
be greatly improved by alternative gate circuit design. The
SPICE modelled circuits showthe worst case conditions of
constant dv
DS
/dt and show that v
GS
can be held below its
threshold voltage using the circuits shown in the previous
section. Experimental measurements have confirmed
these results in a prototype 20kHz ACMC system.
Device losses in ACMC inverters
It is important to be able to calculate the losses which occur
in the switching devices in order to ensure that device
operating temperatures remain within safe limits. Cooling
arrangementsfor the MOSFETs or FREDFETs inanACMC
system will depend on maximum allowable operating
temperatures, ambient temperature and operating
conditions for the system. The components of loss can be
examined in more detail:
MOSFET Conduction losses
When a MOSFET or FREDFET is on and carrying load
current from drain to source then the conduction ’i
2
R’ loss
can be calculated. It is important to note that the device
current is not the same as the output current, as
demonstratedbythewaveformsof Fig.23. Thefigureshows
a sinusoidal motor load current waveform and the top and
bottomMOSFET currents. The envelopes of the MOSFET
currents are half sinusoids; however the actual device
currents are interrupted by the instants when the load
current flows through the freewheel diodes. For the
purposes of calculating MOSFET conduction losses it is
acceptable to neglect the ’gaps’ which occur when the
freewheel diodes are conducting for the following reasons:
Fig.23 Motor current and device current waveforms in a
PWM inverter
-Whenthe motor load current is near its maximumvalue
the switching duty cycle is also near its maximum and
so the proportion of time when the diode conducts is
quite small and can be neglected.
-When the motor load current is near zero then the
switching duty cycle is low but the MOSFET is only
conducting small amounts of current. As the MOSFET
current is low then the contribution to total conduction
loss is small.
Thus if the MOSFET is assumed to be conducting load
current for the whole half-periodthen the conduction losses
can be calculated using the current envelope of Fig.23.
These losses will be overestimated but the discrepancy will
be small. The conduction losses can be given by:
P
M(ON)
= I
T
2
.R
DS(ON)
(T
j
) (13)
where I
T
is the rms value of the half sinusoid MOSFET
current envelope.
and: R
DS(ON)
(T
j
) = R
DS(ON)
(25˚C).e
k(Tj-25)
(14)
where k=0.007 for a 500V MOSFET, and k=0.006 for a
500V FREDFET.
I
T
is related to the rms motor current, I
L
, by:
(15)
i
L
i
T1
i
T2
Load current
Top MOSFET current
Bottom MOSFET current
I
T
=
I
max
2
=
I
L
√2
267
Motor Control Power Semiconductor Applications
Philips Semiconductors
Fig.24 Selection graphs for a 1.7A motor
NB. Device selection notation: 1X655-A denotes a single BUK655-500A FREDFET, etc.

PHILIPS 500V FREDFETS
Frequency = 5kHz
0 0.4 0.8 1.2 1.6 2
40
50
60
70
80
90
100
Heatsink size, Rth_hs-amb (K/W)
Heatsink temperature, T_hs

PHILIPS 500V MOSFETS (+ diode network)
Frequency = 5kHz
0 0.4 0.8 1.2 1.6 2
40
50
60
70
80
90
100
Heatsink size, Rth_hs-amb (K/W)
Heatsink temperature, T_hs

PHILIPS 500V MOSFETS (+ diode network)
Frequency = 20kHz
0 0.4 0.8 1.2 1.6 2
40
50
60
70
80
90
100
Heatsink size Rth_hs-amb (K/W)
Heatsink temperature, T_hs

PHILIPS 500V FREDFETS
Frequency = 20kHz
0 0.4 0.8 1.2 1.6 2
40
50
60
70
80
90
100
Heatsink size Rth_hs-amb (K/W)
Heatsink temperature, T_hs
655-A 655-B 637-A 637-B 638-A 638-B
655-A 655-B 637-A 637-B 638-A 638-B
455-A 455-B 437-A 437-B 438-A 438-B
455-A 455-B 437-A 437-B 438-A 438-B
Additionally in a MOSFET inverter the series blocking
Schottky diode (D3 of Fig.8) has conduction losses. The
current in this diode is the main MOSFET current and so
its loss is approximated by:
P
Sch(ON)
= V
f
(T
j
).I
T
(16)
Diode conduction losses
In a MOSFET inverter the freewheel diode losses occur in
a discrete device (D2 of Fig.8) although this device is often
mounted on the same heatsink as the main switching
device. In a FREDFET circuit the diode losses occur in the
main device package. The freewheeling diode carries the
’gaps’ of current shown in Fig.23 during the periods when
its complimentary MOSFET is off. Following the argument
used above the diode conduction loss is small and can be
neglected. Using this simplification we have effectively
transferred the diode conduction loss and included it in the
figure for MOSFET conduction loss.
MOSFET switching losses
During the half-cycle of MOSFET conduction the load
current switched at each instant is different (Fig.23). The
amount of current switched will also depend on the reverse
recovery of the bridge leg diodes and hence on the
268
Motor Control Power Semiconductor Applications
Philips Semiconductors
Fig.25 Selection graphs for a 3.4A motor
NB. Device selection notation: 1X655-A denotes a single BUK655-500A FREDFET, etc.

PHILIPS 500V FREDFETS
Frequency = 5kHz
Heatsink size, Rth_hs-amb (K/W)
Heatsink temperature, T_hs

PHILIPS 500V MOSFETS (+ diode network)
Frequency = 5kHz
Heatsink size, Rth_hs-amb (K/W)
Heatsink temperature, T_hs

PHILIPS 500V MOSFETS (+ diode network)
Frequency = 20kHz
Heatsink size Rth_hs-amb (K/W)
Heatsink temperature, T_hs

PHILIPS 500V FREDFETS
Frequency = 20kHz
Heatsink size Rth_hs-amb (K/W)
Heatsink temperature, T_hs
655-A 655-B 637-A 637-B 638-A 638-B
655-A 655-B 637-A 637-B 638-A 638-B
455-A 455-B 437-A 437-B 438-A 438-B
455-A 455-B 437-A 437-B 438-A 438-B
0 0.2 0.4 0.6 0.8 1
40
50
60
70
80
90
100
0 0.2 0.4 0.6 0.8 1
40
50
60
70
80
90
100
0 0.2 0.4 0.6 0.8 1
40
50
60
70
80
90
100
0 0.2 0.4 0.6 0.8 1
40
50
60
70
80
90
100
temperature of the devices. The total turn-on loss (P
M(SW)
)
will be a summation of the losses at each switching instant:
(17)
MOSFET turn-off times are usually only limited by dv/dt
considerations and hence are as short as possible. The
turn-off loss of the MOSFETs or FREDFETs in an inverter
is small compared with the turn-on loss and can usually be
neglected.
Diode switching losses
Diode turn-off loss (P
D(SW)
) is calculated in a similar manner
to the MOSFET turn-on loss. The factors which affect the
diode turn-off waveforms have been discussed earlier.
Diode turn-on loss is usually small since the diode will not
conduct current unless forward biassed. Thus at turn-on
the diode is never simultaneously supportinga high voltage
and carrying current.
Gate drive losses
Someloss will occur in the gatedrive circuit of aPowerMOS
device. As the gate drive is only delivering short pulses of
current during the switching instants then these losses are
negligibly small.
P
M(SW)
= ∑
n = 0

f (T
j
, I
n
)
269
Motor Control Power Semiconductor Applications
Philips Semiconductors
Fig.26 Selection graphs for a 6.8A motor
NB. Device selection notation: 1X638-A denotes a single BUK638-500A FREDFET, etc.

PHILIPS 500V FREDFETS
Frequency = 5kHz
Heatsink size, Rth_hs-amb (K/W)
Heatsink temperature, T_hs

PHILIPS 500V MOSFETS (+ diode network)
Frequency = 5kHz
Heatsink size, Rth_hs-amb (K/W)
Heatsink temperature, T_hs

PHILIPS 500V MOSFETS (+ diode network)
Frequency = 20kHz
Heatsink size Rth_hs-amb (K/W)
Heatsink temperature, T_hs

PHILIPS 500V FREDFETS
Frequency = 20kHz
Heatsink size Rth_hs-amb (K/W)
Heatsink temperature, T_hs
1X 638-A 2X 637-A 3X 637-A 2X 638-A 3X 638-A 1X 617-AE 1X 438-A 2X 437-A 2X 438-A 3X 437-A 3X 438-A 1X 417-AE
1X 638-A 2X 637-A 3X 637-A 2X 638-A 3X 638-A 1X 617-AE 1X 438-A 2X 437-A 2X 438-A 3X 437-A 3X 438-A 1X 417-AE
0 0.2 0.4 0.6 0.8 1
40
50
60
70
80
90
100
0 0.2 0.4 0.6 0.8 1
40
50
60
70
80
90
100
0 0.2 0.4 0.6 0.8 1
40
50
60
70
80
90
100
0 0.2 0.4 0.6 0.8 1
40
50
60
70
80
90
100
System operating temperatures
In this section the device losses discussed in the previous
section are calculated and used to produce a design guide
for the correct selection of Philips PowerMOS devices and
appropriateheatsink arrangements for ACMCapplications.
The following factors must be take into account when
calculating the total system loss, P
LOSS
:
-Device characteristics
-Switching frequency
-Operating temperature
-Load current
-Number of devices used in parallel.
-Additional snubber or di/dt limiting networks.
P
LOSS
= P
M(ON)
+P
M(SW)
+P
D(SW)
+P
Sch(ON)
(18)
For the results presented here the device parameters were
taken for the Philips range of 500V MOSFETs and
FREDFETs. The on-state losses can be calculated from
the equations given above. For this analysis the device
switching losses were measured experimentally as
functions of device temperature and load current. As there
are six sets of devices in an ACMC inverter then the total
heatsink requirement can be found from:
T
hs
= T
ahs
+ 6.P
LOSS
.R
th(hs-ahs)
(19)
T
j
=T
hs
+ P
LOSS
.R
th(j-hs)
(20)
270
Motor Control Power Semiconductor Applications
Philips Semiconductors
Fig.27 Selection graphs for a 10A motor
NB. Device selection notation: 2X638-A denotes two parallelled BUK638-500A FREDFETs, etc.

PHILIPS 500V FREDFETS
Frequency = 5kHz
Heatsink temperature, T_hs

PHILIPS 500V MOSFETS (+ diode network)
Frequency = 5kHz
Heatsink size, Rth_hs-amb (K/W)
Heatsink temperature, T_hs

PHILIPS 500V MOSFETS (+ diode network)
Frequency = 20kHz
Heatsink size Rth_hs-amb (K/W)
Heatsink temperature, T_hs

PHILIPS 500V FREDFETS
Frequency = 20kHz
Heatsink size Rth_hs-amb (K/W)
Heatsink temperature, T_hs
2X 638-A 3X 637-A 3X 638-A 4X 637-A 4X 638-A 1X 617-AE 2X 438-A 3X 437-A 3X 438-A 4X 437-A 4X 438-A 1X 417-AE
40
50
60
70
80
90
100
Heatsink size, Rth_hs-amb (K/W)
0 0.1 0.2 0.3 0.4 0.5 0.6
0 0.1 0.2 0.3 0.4 0.5 0.6
40
50
60
70
80
90
100
0 0.1 0.2 0.3 0.4 0.5 0.6
40
50
60
70
80
90
100
0 0.1 0.2 0.3 0.4 0.5 0.6
40
50
60
70
80
90
100
2X 638-A 3X 637-A 3X 638-A 4X 637-A 4X 638-A 1X 617-AE 2X 438-A 3X 437-A 3X 438-A 4X 437-A 4X 438-A 1X 417-AE
Equations 18 to 20 can be used to find the heatsink size
(R
th(hs-ahs)
) required for a particular application which will
keeptheheatsinktemperature(T
hs
) withinarequireddesign
value. Results are plotted in Figures 24 to 27 for motor
currents of I
L
= 1.7A, 3.4A, 6.8A and 10.0A. These currents
correspond to the ratings of several standard induction
motor sizes. The results assume unsnubbed devices, an
ambient temperature of T
ahs
=40˚C, and are plotted for
inverter switching frequencies of 5kHz and 20kHz.
Two examples showing howthese results may be used are
given below:
1) -The first selection graph in Fig.24 shows the possible
device selectionsfor 500VFREDFETs ina 5kHz ACMC
system where the full load RMS motor current is 1.7A.
Using a BUK655-500A FREDFET, T
hs
can be
maintained below 70˚C with a total heatsink
requirement of 1.2K/W(if each FREDFETwas mounted
on a separate heatsink then each device would need a
7.2K/W heatsink). The same heatsinking arrangement
will give T
hs
=50˚C using a BUK638-500A. Alternatively
T
hs
can be maintained below 70˚C using a 2K/W
heatsink (12K/W per device) and the BUK637-500B.
2) -In Fig.27 the selection graphs for a 10A system are
given. The fourth selection graph is for a 20kHz
switching frequency using 500V MOSFETs. Here two
BUK438-500A devices connected in parallel for each
switch will require a total heatsink size of 0.3K/W if the
271
Motor Control Power Semiconductor Applications
Philips Semiconductors
heatsink temperature is to remain below 90˚C. The
same temperature can be maintained using a 0.5K/W
heatsink and a single BUK417-500AE ISOTOP device.
For different motor currents or alternative PWM switching
frequencies the appropriate device and heatsink
arrangement for a particular application can be found by
interpolating the results presented here.
Conclusions
This section has outlined the basic principles and operation
of PWM inverters for ACMC applications using Philips
PowerMOS devices. MOSFETs and FREDFETs are the
most suitabledevices for ACMCsystems, especiallyat high
switching speeds. This section has been concerned with
systems rated up to 2.2kW operating from a single phase
supply and has shown that there is a range of Philips
PowerMOS devices ideally suited for these systems.
The characteristics and performance of MOSFETs and
FREDFETs in inverter circuits and the effect of gate drive
designon their switching performance has been discussed.
The possibility of parasitic turn-on of MOSFETs in an
inverter bridge legcan be avoidedby appropriate gatedrive
circuit design. Experimental and simulated results have
shown that good switching performance and immunity to
parasitic turn-on can be achieved using the Philips range
of PowerMOS devices in ACMC applications . Using the
device selection graphs presented here the correct
MOSFET or FREDFET for a particular application can be
chosen. This guide can be used to select the heatsink size
and device according to the required motor current,
switching frequency and operating temperature.
References
1. Introduction to PWM speed control system for 3-phase
AC motors: J.A.Houldsworth, W.B.Rosink: Electronic
Components and Applications, Vol 2, No 2, 1980.
2. A new high-quality PWM AC drive: D.A.Grant,
J.A.Houldsworth, K.N.Lower: IEEE Transactions, Vol
IA-19, No 2, 1983.
3. Variable speed induction motor with integral ultrasonic
PWM inverter: J.E.Gilliam, J.A.Houldsworth, L.Hadley:
IEEE Conference, APEC, 1988, pp92-96.
4. MOSFETs and FREDFETs in motor drive equipment:
Chapter 3.1.3.
272
Motor Control Power Semiconductor Applications
Philips Semiconductors
3.1.5 A 300V, 40A High Frequency Inverter Pole Using
Paralleled FREDFET Modules
Introduction
Voltage source inverters which are switched using some
formof pulse width modulation are now the standard in low
to medium rated AC and brushless DC variable speed
drives. At present, because of device limitations the
switching (modulation) frequencies used in all but the
lowest drive ratings are restricted to a few kHz. There is
however astrongtechnical advantageinusing muchhigher
ultrasonic switching frequencies in excess of 20 kHz, the
benefits of which include:
i) The low frequency distortion components in the inverter
output waveform are negligible. As a result there is no
longer a need to derate the electrical machine in the drive
as a consequence of harmonic loss.
ii) The supply derived acoustic noise is eliminated.
iii) The DC link filter component values are reduced.
The device best suited for high switching frequencies is the
power MOSFET because of its extremely fast switching
time and the absence of secondary breakdown. However,
being surface conduction devices, high power rated
MOSFETs are difficult and expensive to manufacture and
at present single MOSFETs are only suitable for inverter
ratings of typically 1-2 kVA per pole. Although higher rated
power devices such as bipolar transistors and IGBTs can
be switched at medium to high frequencies, the switching
losses in these circuits are such that frequencies in excess
of 20 kHz are at present difficult to achieve.
Switches with high ratings and fast switching times can be
constructed by hard paralleling several lower rated power
devices. MOSFETs are particularly suitable because the
positive temperature coefficient of the channel resistance
tendstoenforcegoodsteady-statecurrent sharing between
parallel devices. However to achieve good dynamic current
sharing during switching, considerable care must be taken
in the geometric layout of the paralleled devices on the
common heatsink. In addition, the device characteristics
may need to be closely matched. As a result modules of
paralleled MOSFETs are often expensive.
Fig.1
+
-
1 2 N
DC
Rail
Within each mdule: Good transient + steady state load sharing
Isolated drive circuit
Pole
Output
273
Motor Control Power Semiconductor Applications
Philips Semiconductors
An alternative approach to paralleling is to use small
switching aid networks which overcome the constraints of
hard paralleling by improving the dynamic load sharing of
the individual devices. It is possible to envisage an inverter
design where each pole consists of a number of identical
pole modules which share a common supply and have
outputs connected in parallel, as shown in Fig.1. Each
module is designed to operate individually as an inverter
pole and contains two power MOSFETs with associated
isolated gate drive circuitry. When the modules are
connected in parallel their design is such that they will
exhibit good transient and steady-state load sharing, the
onlyrequirement beingthat they aremountedon acommon
heatsink. In this manner any inverter volt-amp rating can
beaccommodatedby parallelingasufficient number of pole
modules.
Pole module
The power circuit diagram of an individual pole module
which is suitable for the second formof paralleling is shown
in Fig.2. The design makes use of the integral body diode
of the main switching devices and for this purpose the fast
recovery characteristics of FREDFETs are particularly
suitable. Two snubber circuits and a centre tapped
inductanceareincludedinthecircuit. Thesesmall switching
aid networks perform a number of functions in the circuit:
Fig.2
274
Motor Control Power Semiconductor Applications
Philips Semiconductors
i) They act to improve the dynamic current sharing between
the pole modules when connected in parallel.
ii) They ensuresafe operationof the MOSFETintegral body
diode. The central inductance controls the peak reverse
current of the diode and the snubber network prevents
secondary breakdown of the MOSFET parasitic internal
transistor as the integral body diode recovers.
iii) They reduce the switching losses within the main power
devices and thus allows maximum use of the available
rating.
Fig.3
The operation of the circuit is typical of this form of inverter
pole. The commutation of the integral body diode will be
discussed in detail since it is from this section of the
operation that the optimal component values of the
switching aid network are determined. The value of the
inductor L is chosen to give a minimum energy loss in the
circuit and the snubber network is designed to ensure safe
recovery of the integral diode at this condition. For example
consider the case when there is an inductive load current
I
L
flowing out of the pole via the integral body diode of the
lower MOSFET just prior to the switching of the upper
MOSFET. With reference to Fig.3, the subsequent
operation is described by the following regions:
Region A: Upper MOSFET is switched on. The current in
the lower integral body diode falls at a rate (dI/dt) equal to
the DC link voltage V
DD
divided by the total inductance L of
the centre tapped inductance.
Region B: The diode current becomes negative and
continues to increase until the junction stored charge has
been removed, at which stage the diode recovers
corresponding to a peak reverse current I
RR
.
Region C: The voltage across the lower device increases
at a rate (dV/dt) determined by the capacitance C
s
of the
lower snubber network. The current in the upper MOSFET
and the inductor continues to increase and reaches a peak
when the voltage across the lower device has risen to the
DC link value. At this point the diode D
c
becomes forward
biased and the stored energy in the inductor begins to
discharge through the series resistance R
c
.
The energy E
1
gained by the switching aid networks over
the above interval is given by:
and is ultimately dissipated in the network resistors R
s
, R
c
.
For a given forward current, the peak reverse current I
RR
of
the diode will increase with increasing dI/dt and can be
approximately represented by a constant stored charge,
(Q
RR
) model, where:
Although in practice I
RR
will tend to increase at a slightly
faster rate than that given by equation (2).
Since in the inverter pole circuit
Inspection of equations (1) and (4) shows that the energy
loss E
1
remains approximately constant as L is varied.
During the subsequent operation of the inverter pole when
the upper MOSFET is turned off and the load current I
L
returns to the integral body diode of the lower device, an
energy loss E
2
occurs in the inductor andthe upper snubber
equal to:
This loss can be seen to reduce with L. However as L is
reducedbothI
RR
andthe peakcurrent intheupper MOSFET
will increase and result in higher switching loss in the diode
and higher conduction loss in the channel resistance of the
upper device.
The value of L which gives minimumenergy loss in the pole
occurs when there is an optimal balance between the
effects described above. Typical measured dependencies
of the total energy loss on the peak reverse diode current
as L is varied are shown in Fig.4. The characteristics of a
similarly rated conventional MOSFET and a fast recovery
FREDFET are compared in the figure. In both cases the
minimum energy loss occurs at the value of L which gives
a reverse recovery current approximately equal to the
design load current. However the loss in the FREDFET
circuit is considerably lower than with the conventional
device. The optimal value of L can be found from the
manufacturers specified value of stored charge using
equation (4), where
I
RR
=
√
2



dI
dt



Q
RR
(2)
I
L
Diode
current
I
rr
t
rr
Time
Q
rr
A B C
dI/dt
dI
dt
=
V
DD
L
(3)
I
RR
=
√
2V
DD
Q
RR
L
(4)
E
2
=
1
2
I
L
2
L +
1
2
C
s
V
DD
2
(5)
E
1
=
1
2
I
RR
2
L +
1
2
C
s
V
DD
2
(1)
275
Motor Control Power Semiconductor Applications
Philips Semiconductors
Fig.4
The snubber capacitor value C
s
is chosen to limit the dV/dt
across the integral body diode as it recovers. Experience
has shown that a value of 1V/nS will ensure safe operation,
hence:
The resistive component of the switching aid networks are
chosen in the usual manner.
Parallel operation of pole modules
The principle behind the ‘soft’ paralleling adopted here is
to simply connect the outputs of the required number of
modules together and feed them with a common DC link
andcontrol signals. The transient load sharing between the
parallel modules will be influenced by the tolerances in the
individual inductor and snubber capacitor values and any
variations in the switching instances of the power devices,
the latter being as a result of differences in device
characteristics and tolerances in the gate drive circuitry.
These effects were investigated using the SPICE circuit
simulation package. The SPICE representation of the
modules is shown in Fig.5, in which the upper MOSFET
channel is modelled by an ideal switch with a series
resistance R
DS
. The full SPICE diode model is used for the
lower MOSFET integral body diode, however ideal diode
representations are sufficient for the devices in the
switching aid networks. The load is assumed to act as a
constant current sink over the switching interval.
Fig.5
From the SPICE simulation an estimate of the peak
transient current imbalance between the MOSFETs of the
two modules was obtained for various differences in the
inductors, capacitors anddevice turn-on times. It was found
that the transient current sharing was most sensitive to
unequal device switching times. An example of the results
obtained froma simulation of two paralleled modules using
BUK638-500B FREDFETs are shown in Fig.6. With good
gate drive design the difference between device switching
timesisunlikelytoexceed50nSresultinginapeak transient
current mismatch of less than 10%. The load sharing would
improve if the value of inductor is increased but this has to
be traded off against the increase in switching loss. The
effect of the tolerance of the inductor values on the load
sharing is given for the same module in Fig.7, where it can
be seen that a reasonable tolerance of 10% results in only
a7%imbalance inthe currents. The loadsharing was found
to be relatively insensitive to tolerances in the snubber
capacitor values.
0 0.2 0.4 0.6 0.8 1 1.2 1.4
0
20
40
60
80
100
NORMALISED RECOVERY CURRENT (IRR/IL)
POWER LOSS (W)
STANDARD
EQUIVALENT
MOSFET
BUK638-500B
MODULE
L
opt
=
2V
DD
Q
RR
I
L
2
(6)
C = (I
L
) nF (7)
276
Motor Control Power Semiconductor Applications
Philips Semiconductors
Fig.6
277
M
o
t
o
r
C
o
n
t
r
o
l
P
o
w
e
r

S
e
m
i
c
o
n
d
u
c
t
o
r

A
p
p
l
i
c
a
t
i
o
n
s
P
h
i
l
i
p
s

S
e
m
i
c
o
n
d
u
c
t
o
r
s
F
i
g
.
7
2
7
8
Motor Control Power Semiconductor Applications
Philips Semiconductors
A 300V, 10A pole module design using
BUK638-500B FREDFETs
The circuit diagram of a 300V, 10A pole module based on
BUK638-500B FREDFETs is given in Fig.8. The inductor
value was chosen using the criteria discussed in Section
2.
The conventional R-C snubber network has been replaced
by the active circuit shown in Fig.9 and involves the use of
asecond, lowratedBUK455-500BMOSFETwhich ismade
to act as a capacitance by invoking the ‘Miller’ effect. The
active snubber is more efficient at low load currents
because it tends to maintain a constant (dV/dt) regardless
of the load, and thus the snubber loss is proportional to the
current, as opposed to the conventional circuit in which the
loss remains constant. In addition the active circuit is
compact and lends itself more readily to a hybrid assembly.
The major component costs are the secondary MOSFET
and a low voltage power diode and compare favourably
with those of the conventional high voltage capacitor and
high voltage diode.
Fig.8
279
Motor Control Power Semiconductor Applications
Philips Semiconductors
The gate drive circuits are given in Fig.10 and are based
upon the pulse transformer configuration described in
chapter 1.2.3. A PNP transistor has been added between
the gate and source to reduce the drive off-state
impedance, toimprove the switching andprevent any Miller
effect in the main device.
Fig.9
FREDFET module performance
The typical voltage and current waveforms of the upper and
lower switching devices are shown in Figures 11 and 12 for
the case of a single pole module sourcing the rated current
of 10 Amps froma 300V DC link. Fig.12 illustrates howthe
use of the series inductor and active snubber gives a
controlled recovery of the fast integral body diode of the
FREDFET.
Fig.10
5 A/div
50 V/div
200 ns/div
Fig.11 Top - turn-on of the lower diode
Bottom - turn-off of the MOSFET
The losses of an individual module switched at 20 kHz are
plottedin Fig.13as afunctionof output current. Theymainly
stemfromconduction loss, the switching loss representing
only a third of the maximum loss. Because the switching
loss occurs mainly in the aidnetworks the main FREDFETs
can be used at close to their full rating. Similarly operation
at higher frequencies will not result in a substantial
reductioninefficiency, for exampleat 40kHz, 10Aoperation
the losses are 95W.
280
Motor Control Power Semiconductor Applications
Philips Semiconductors
5 A/div
50 V/div
200 ns/div
Fig.12 Top - turn-off of the lower diode
Bottom - turn-on of the MOSFET
Four modules were connected in parallel and mounted on
a common heatsink. The modules operated successfully at
300V with total loads in excess of 40A, four times their
individual rating. The common heatsink, which had a
thermal resistance to ambient of 0.33˚C/W was sufficient
to achieve the full 40A, 300V continuous rating of the
parallel units at 20kHz. The current waveforms of the upper
FREDFETs in each module are overlaid in Fig.14, where it
can be seen that the load sharing is very even, particularly
after the initial switching transients.
Fig.13
5 A/div
2 µs/div
Fig.14 FREDFET current waveforms
281
Motor Control Power Semiconductor Applications
Philips Semiconductors
Conclusion
Parallel, separate MOSFET pole modules provide a
method of designing medium rated inverter poles, which
can be switched efficiently at frequencies in excess of 20
kHz. The approach is flexible since a single pole module
design can be used to achieve a range of inverter volt-amp
ratings by paralleling a sufficient number of units.
Through the use of small switching aid networks it is
possible to obtain excellent transient and steady-state
current sharing between the paralleled modules. The
current sharing remains good even if there are substantial
variations in component tolerances and the power device
switching times. The switching aid networks also reduce
the switching losses in the main devices and allows them
to be used to their full rating.
The presented design of a 300V, 10A module based on
BUK638-500B, FREDFETs has a full load loss of only 70W.
Four of these modules connected in parallel and mounted
on a 0.33˚C/W heatsink gave an inverter pole with a 300V,
40A continuous rating when switched at 20 kHz. Excellent
current sharing between these modules was observed and
as a result there would seem to be no technical reasons
whyfurther modules couldnot beparalleledtoachieveeven
higher ratings.
282
Motor Control Power Semiconductor Applications
Philips Semiconductors
DC Motor Control
283
Motor Control Power Semiconductor Applications
Philips Semiconductors
3.2.1 Chopper circuits for DC motor control
DC motor drives are used for many speed and position
control systems where their excellent performance, ease
of control and high efficiency are desirable characteristics.
DCmotor speedcontrol canbeachieved usingswitchmode
DC-DC chopper circuits. For both mains-fed and battery
supplied systems, power MOSFETs and FREDFETs are
the ideal switching devices for the converter stage. The
Philips range of PowerMOS devices includes devices
suitable for most DC-DC converters for motor control
applications. Additionally, due to the ease with which
MOSFETs and FREDFETs can be parallelled, Philips
PowerMOS devices can easily be used in chopper circuits
for both low power and high power DC motor drives for
vehicle, industrial or domestic applications.
Introduction to DC motor drives
Ina DCmotor, the static field flux is establishedusing either
permanent magnets or a stator field winding. The armature
winding, ontherotor of adcmachine, carriesthemainmotor
current. The armature winding is a series of coils, each
connected to segments of a commutator. In order that the
motor develops constant torque as the rotor moves,
successive armature coils must be connected to the
external dc circuit. This isachievedusingapair of stationary
brushes held in contact with the commutator.
The motor torque is produced by the interaction of the field
flux and the armature current and is given by:
(1)
The back emf developed across the armature conductors
increases with the motor speed:
(2)
Permanent magnet DCmotors are limited in terms of power
capability and control capability. For field wound DCmotors
thefieldcurrent controls theflux andhencethe motor torque
and speed constants. The field winding can be connected
in series with the armature winding, in shunt with it, or can
be separately excited. For the separately excited dc motor,
shown in Fig.1 the field flux is controlled and the motor can
be made to operate in two distinct modes: constant torque
operation up to the rated speed of the motor, and then
constant power operation above rated speed, as shown in
Fig.2. The steady state operation of the motor is described
by:
(3)
For normal motor operation E
a
and I
a
are positive and the
motor is operating in its ’first quadrant’. The motor is said
to be operating in its second quadrant, that is braking or
regenerating, by reducing V
a
below E
a
such that I
a
is
negative. These two quadrants are shown in Fig.3a). If the
polarity of the applied voltage is reversed then motoring
and regenerating operation can occur with the direction of
rotation reversed. Thus by controlling the armature voltage
and current polarities, full four-quadrant operation, as
shown in Fig.3b), can be achieved.
Fig.1. Separately excited DC motor
Fig.2. DC motor, operating characteristics
Va
Ra La
Ea
Lf
Rf
If
Vf
Ia
T
e
α I
a
Rated (base)
speed
Speed
Speed
Speed
Va
Ea
Ia
If
Torque
Flux,
CONSTANT
TORQUE
CONSTANT
POWER
E
a
α ω
m
V
a
= E
a
+R
a
. I
a
285
Motor Control Power Semiconductor Applications
Philips Semiconductors

a) Two quadrant operation
b) Four quadrant operation
Fig.3. Torque speed characteristics for DC motor
Converter topologies for DC motor drives
Single quadrant (step down) converter
For single quadrant operation the chopper circuit of Fig.4
canbe used. The average voltageappliedto the motor, and
hence its speed, is controlled by varying the duty cycle of
the switch, S. Fig.5 shows the switching waveforms for the
circuit. During the on time, t
on
, the supply voltage, V
dc
, is
applied to the motor and the armature current starts to
increase. Neglecting the on-state resistance of the switch
andthe armature winding resistance the voltage across the
armature inductance is V
dc
-E
a
and so the rate of rise of
armature current is given by:
(4)
When the switch turns off the energy stored in the armature
inductance must be dissipated. The polarity of the voltage
across L
a
reverses, the diode D becomes forward biased
and the armature current continues to flow. Assuming that
the motor speed remains constant and neglecting the
forward voltage drop of the freewheeling diode the inductor
voltage is equal to -E
a
. The rate of fall of armature current
is given by:
(5)
Fig.4. Single quadrant chopper circuit
Fig.5. Single quadrant chopper, switching waveforms
If this switching sequence is repeated at some frequency,
then the motor voltage can be controlled by altering the
relative duration of the on period and off period. Variation
of the duty cycle of the switch (t
on
/T) to control the motor
voltage is referred to as Pulse Width Modulation (PWM)
control. As the average voltage across the inductor over a
period must be zero then:
(6)
The integral of inductor voltage for the interval t
on
correspondstothe shadedarea1inFig.5, whilst theintegral
of inductor voltage for the t
off
interval corresponds to the
shadedarea2in theFigure. Thesetwoareas must be equal
and so from equations 4 to 6 or Fig.5 the transfer function
of the controller is given by:
(7)
Ea
Ia
REGENERATING
Ea
Ia
MOTORING
Torque,
Current
Speed,
Voltage
Va
Ra La
Ia
V
La
Ea
S
Vdc
D
Ea
Ia
REGENERATING
Ea
Ia
MOTORING
Torque,
Current
Speed,
Voltage
Ea
Ia
REGENERATING
Ea
Ia
MOTORING
Switch, S ON ON ON OFF OFF
t
t
t
t
t
t
on
t
off
T
voltage, V
a
current, I
a
voltage, V
La
current, I
D
current, I
S
V
dc
E
a
V
dc
- E
a
-E
a
I
max
I
min
I
a
1
2
Motor
Motor
Inductor
Diode
Switch


0
T
v
L
. dt =


0
t
on
v
L
. dt +


t
on
T
v
L
. dt = 0
dI
a
dt
=
V
dc
−E
a
L
a
V
a
=
t
on
T
. V
dc
dI
a
dt
= −
E
a
L
a
286
Motor Control Power Semiconductor Applications
Philips Semiconductors
Two quadrant, half-bridge converter
Figure 6 shows a half bridge circuit for two quadrant dc
drive. For motoring operation S1 and D2 operate as
described above for the single quadrant controller. The
freewheel diodeD2 may be the internal diode of a MOSFET
or FREDFET, or a discrete device. For regenerative
operation the DC motor acts as the active power source
and the power flow is from right to left in Fig.6. The
regenerating current is controlled by varying the duty cycle
of S2. When S2 is on, the negative armature current
increases through the switch and the armature inductance.
When S2 is turned off D1 becomes forward biased and the
current regenerates into the supply. The relevant circuit
waveforms are shown in Fig.7, showing the equal areas of
the inductor volt-seconds over each period of the switching
cycle. During regeneration the transfer function of the
converter is given by:
(8)
Fig.6. Two quadrant half bridge chopper circuit
Fig.7. Two quadrant half bridge chopper, switching
waveforms
Four quadrant, full-bridge converter
If motoring and regenerating operation are required with
both directions of rotation then the full bridge converter of
Fig.8is required. Using this configuration allows the polarity
of the applied voltage to be reversed, thus reversing the
direction of rotation of the motor. Thus in a full bridge
converter the motor current and voltage can be controlled
independently. The motor voltage Va is given by:
(9)
whereV
12
is controlledby switchingS1 andS2as described
above, andV
34
byswitching S3andS4. Theusual operating
mode for a full bridge converter is to group the switching
devices so that S1 and S3 are always on simultaneously
and that S2 and S4 are on simultaneously. This type of
control is then referred to as bipolar control.
Fig.8. Four quadrant full bridge circuit
MOSFETs and FREDFETs in bridge
circuits
In a bridge circuit, conduction transfers between the
switching devices and freewheeling diodes as the load
current is controlled (eg. switch S2 and diode D1 in Fig.4).
Associated with the transfer of conduction between the
freewheel diodes and the switching devices is the reverse
recovery of the diode as each conducting MOSFET returns
to its on-state. Reverse recovery current flows due to the
removal of storedcharge fromadiodePNjunction following
conduction. Fig.9 shows the device current paths in a half
bridge circuit when conduction is transferred from the top
diode to the bottom MOSFET.
The switching waveforms are shown in Fig.10 where the
diode reverse recovery current is I
rr
and the time taken for
the reverse recovery currents to be cleared is t
rr
. The
amount of stored charge removed from the body of the
diode is represented by the area Q
rr
. The reverse recovery
current flows through the MOSFET which is being turned
on in addition to the load current and thus causes additional
turn-onlosses. The amount of storedcharge increases with
increasing temperature for a given diode. Both the
V
a
= V
12
−V
34
V
a
=



1 −
t
on
T



. V
dc
Ra
La
Ia
V
La
S2
Vdc
S1
D1
D2
S3
S4
D4
D3
Ea
Va
Va
Ra La
Ia
V
La
Ea
S2
Vdc
S1
D1
D2
Switch, S2 ON ON ON OFF OFF
t
t
t
t
t
t
on
t
off
T
voltage, V
a
current, I
a
voltage, V
La
current, I
D1
current, I
S2
V
dc
E
a
V
dc
- E
a
-E
a
I
max
I
min
I
a
1
2
Motor
Motor
Inductor
Diode
Switch
287
Motor Control Power Semiconductor Applications
Philips Semiconductors
magnitude of the reverse recovery current and its duration
must be reduced in order to reduce the switching losses of
the system.
This effect is important because inherent in the structure of
a power MOSFET there is a diode between the source and
drain of the device which can act as a freewheeling diode
when forward biased. For most DC motor control
applications the reverse recovery characteristics of the
MOSFET intrinsic diode are acceptable and do not
compromise the switching performance of the half bridge
circuit. However, the characteristics of a MOSFET intrinsic
diode are not optimised for minimum reverse recovery and
so, especially in high frequency systems, the FREDFET is
more suitable for use in half bridge circuits.
Fig.9 Current paths in half bridge circuit.
Fig.10 Diode reverse recovery waveforms.
The FREDFET is essentially a MOSFET with a very fast
built-in diode where the reverse recovery properties of a
FREDFET diode are similar to those of a discrete fast
recovery epitaxial diode (FRED). This gives improved
switching performance in high frequency applications.
Considerations for converter driven DC
motors
Device current rating
The power electronic converter must be matched to the
requirements of the motor and the load. DC motor drives
can be used to provide torques in excess of the maximum
continuous rated torque of the motor for short intervals of
time. This is due to the long thermal time constants of the
motor. The peak torque requirement of the motor will
determine its peak current demand, and hence the peak
current requirement for the power switches. The current
rating of a PowerMOS device is limited by the maximum
junction temperature of the device, which should not be
exceeded even for short periods of time due to the short
thermal time constant of the devices. The devices must
thereforeberatedfor thispeakcurrent condition of thedrive.
Operation at maximum current usually occurs during
acceleration and deceleration periods necessary to meet
the performance requirements of DC servo systems.
Device voltage rating
The voltage rating of the power switches will be determined
by the power supply DC link voltage and the motor emfs,
including those which occur when the motor is operating in
its constant power region at above rated speed but below
rated torque.
Motor performance
It can be seen from the waveforms of Figures 5 and 7 that
the armature current supplied to the motor by the switching
converter is not constant. The presence of ripple current in
addition to the normal DC current affects the performance
of the motor in the following ways:
Torque pulsations. Ripple in the motor current waveform
will cause a corresponding ripple in the motor output torque
waveform. These torque pulsations may give rise to speed
fluctuations unless they are damped out by the inertia of
themechanical system. The torquepulsations occur at high
frequencies where they may lead to noise and vibration in
the motor laminations and mechanical system.
Losses. Winding losses in a DC motor are proportional to
i
RMS
2
, whereas the torque developed by the motor is
proportional to i
DC
. Ripple in the motor current will increase
the RMS current and thus give rise to additional losses and
reduce the system efficiency.
Overcurrents. If the ripple current is large then the peak
device current will be significantly higher than the design
DC value. The devices must then be rated for this higher
current. Current ripple will also increase the current which
must be handled by the motor brushes possibly increasing
arcing at the brush contacts.
V
dc
I
L
I
rr
I
L
I
L
MOSFET
current
Diode
current
Output
voltage
I
rr
t
rr
Time
Time
Time
I
L
+ I
rr
V
dc
Q
rr
288
Motor Control Power Semiconductor Applications
Philips Semiconductors
The amount of current ripple depends primarily upon the
switching frequency and amount of motor inductance (See
equations 4 and 5). Increasing L
a
and f
s
will both reduce the
amount of current ripple. The motor inductance is fixed by
the motor selection but can be increased by the addition of
a discrete component. Increasing the switching frequency
of the system will reduce the amount of current ripple but
will increase the switching losses in the power devices.
Using PowerMOS devices in DC drives
For many applications the motor control systemis operated
at switching speeds in the range 1kHz to 20kHz.
PowerMOS devices are ideally suited for this type of
converter giving the following advantages:
Switching performance
Unlike bipolar devices the MOSFET is a majority carrier
device and so no minority carriers must be moved in and
out of the device as it turns on and off. This gives the fast
switching performance of MOSFET devices. However, at
higher switching speeds the switching losses of the system
become important and must be considered in addition to
the device on-state losses. The device conduction loss
depends on the MOSFET on-state resistance, RDS(ON),
which increases with the temperature of the device.
Switching times are essentially independent of device
temperature. PowerMOS devices have good overload
capability and Safe Operating ARea (SOAR) which makes
them easy to us in a chopper circuit, although the need for
snubber circuits will depend on the system operating and
performance requirements.
Fig.11. MOSFET capacitances and basic gate driver
Ease of use
PowerMOSdevices are essentially voltagedriven switches
and so the gate drive circuits required to switch the devices
are usually relatively simple low power circuits. It is only
during switching instants that the gate drive is that required
provide current in order to charge and discharge the device
capacitances (shown in Fig.11) and thus switch the device.
In order to switch the device quickly the gate driver must
be able to rapidly sink and source currents of up to 1A. For
thesimplest gate drive circuit the MOSFETcanbe switched
using a resistive drive and some gate-source overvoltage
protection, as shown in Fig.11. Alternative MOSFET gate
drive circuits are discussed more fully elsewhere in this
handbook.
Parallelling of PowerMOS devices
It is usually straightforward to operate PowerMOS devices
in parallel to achieve higher system currents than can be
achieved using single devices. The problems of parallelling
PowerMOS are much less than those which occur when
using bipolar devices. MOSFETs and FREDFETs have a
positive temperature coefficient of R
DS(ON)
and so tend to
share the total load current equally. Any discrepancy in
device or circuit resistance which causes one device to be
carrying a higher proportion of the total current will cause
the losses in that device to increase. The device carrying
the increased current will then heat up, its resistance will
increase and so the current carried will be reduced. The
total load current will therefore be equally shared out
between all the parallelled MOSFETs. Current sharing
duringdynamic(switching) instants isachieved by ensuring
good circuit design and layout.
Fig.12. Gate drive circuit for parallelled devices
Moving to a system using parallelled MOSFETs requires
only slight modifications to the gate drive circuit. One
consideration may be the capability of the drive circuit to
provide the currents required at the switching instants. It is
recommended that small differential resistors, as shown in
Fig.12, are used to damp out any oscillations which may
occur between the switching devices and the rest of the
circuit.
RGGF 47R
RGG’ 10R
RGG’ 10R
C
DS
C
GD
C
GS
D
S
G
R
GG
V
GG
289
Motor Control Power Semiconductor Applications
Philips Semiconductors
Fig.13. DC drive system - schematic arrangement
+ +
_ _
Voltage
Error
Amplifier
Speed
Command
SPEED FEEDBACK
CURRENT FEEDBACK
Current
Limit
Motor/
Regenerate
Amplifier
MOTORING
REGENERATING
Gate
drive
Isolation
and gate
drive
V
dc
Current
Command
Motor Tacho
Controller
Circuit layout considerations
The effects of poor circuit design and layout are to increase
RFI and noise and to compromise the performance and
speed of the system due to stray inductances. The
precautions which must be taken to minimise the amount
of stray inductance in the circuit include:
• positioning the gate drive circuits as close as possible to
the power MOSFETs.
• reducing circuit board track lengths to a minimum and
using twisted pairs for all interconnections.
• for parallelled devices, keeping all connections short and
symmetrical.
DC motor control system
Figure 13 shows a schematic arrangement for a two
quadrant controller, showing the outer speed control loop
and the inner current control loop. The speed feedback
signal is derived from a tachogenerator (TGF), although
alternatively an approximation to the motor speed can be
derived by feeding back a signal proportional to the motor
voltage, (AVF). Position feedback canbe included for servo
applications by usinga position encoder on the motor shaft.
The speed feedback loop compares the tacho- output
voltage with a speed reference signal. The voltage error
signal gives the current reference command.
The current command signal is compared with the actual
motor current in the inner control loop. This control loop
includes a current limit setting which protects the motor and
the devices from overcurrents. If the controller demands a
large speed change then the current demand is maintained
below the maximum level by this current limit setting.
Motoringor regenerating operationis detected directly from
thepolarity of thevoltageerror signal andusedtodetermine
whether it is the top or bottomMOSFETwhich is controlling
thecurrent. Themotoring/regeneratinglogic circuit includes
some hysteresis to ensure that control does not oscillate
betweenthemotoringandregeneratingmodesat lowmotor
currents.
Thereareseveral possibleways of controllingmotor current
by controlling the switching sequences to the main
PowerMOS devices. In tolerance band control the motor
current is compared with the reference signal and an
allowed current ripple tolerance. During motoring operation
if the actual current is greater than the allowed maximum
value of the tolerance band then the output comparator
turns off the gate drive to the power MOSFETthus allowing
the motor current to fall. The current then freewheels until
it reaches the lower limit of the tolerance band, when the
comparator turns the MOSFET back on. Using this current
control strategy the effective switching frequency is
variable, depending on the rate at which the armature
current changes, but the peak to peak current ripple in the
system is constant. Alternatively the devices can be
290
Motor Control Power Semiconductor Applications
Philips Semiconductors
switched a constant frequency using a PWM method
current control. Here the current error signal is compared
with a fixed frequency triangular wave and the comparator
output is then used to provide the signal for the main
switching devices. When the error signal is greater than the
triangular wave then the power device is switchedon, when
the error signal is less than the triangular carrier then the
device is switched off.
Conclusions
DC motor controllers using PowerMOS devices can be
used in many speed control and servo applications giving
excellent drive performance. The advantages of
PowerMOS devices include their simple gate drive
requirements, rugged performance and their ease of use
in parallel configurations. The intrinsic diode between the
drainandsourceof MOSFETs andFREDFETs canbeused
as the freewheel diode in half bridge and full bridge circuit
configurations giving a cost effective, compact design with
the minimum of switching devices. PowerMOS choppers
can operate at much higher switching frequencies than
thyristor or power transistor controllers, giving reduced
current ripple, reduced noise and interference and good
dynamic system response. Using higher switching
frequencies reduces the need for additional discrete
inductances in the motor circuit whilst still achieving low
ripple currents in separately excited, permanent magnet
and series connected field wound motors.
291
Motor Control Power Semiconductor Applications
Philips Semiconductors
3.2.2 A switched-mode controller for DC motors
The purpose of this paper is to demonstrate the use of an
integrated switched-mode controller generally used for DC
power conversion as the primary control and element in a
practical Pulse Width Modulated (PWM) DC drive. Basic
principles relating to DC motor specifications and drive
frequency are presented. The PWM method of
switched-mode voltage control is discussed with reference
to armature current control, and hence output torque
control, of DC motors. A series of circuit configurations are
shown to illustrate velocity and position servo applications
using a switched mode driver IC. Philips Semiconductors
produce a wide range of control ICs for Switched Mode
Power Supply (SMPS) applications which can also be used
as controllers for PWM driven DC motors. This paper
demonstrates how one switched-mode controller, the
NE5560, can be used to give a velocity and position servo
systems using Philips power MOSFETs as the main power
switches. Additional application ideas using the NE5560
controller for constant speed andconstant torque operation
are also presented.
Fig.1 DC motor, equivalent circuit
Principles of the PWM DC motor drive
Pulse width modulated drives may be used with a number
of DC motor types: wound field or permanent magnet. The
discussion here will be particularly concerned with
permanent magnet excited DC motors. This does not
impose a restriction on the applicability of switched mode
control for DC drives since permanent magnet motors are
availableinawiderangeof sizes, ratingsandconfigurations
to suit many applications. The design of a pulse width
modulated drive is affected by the characteristics of the DC
motor load, and this will now be considered in more detail.
The permanent magnet DC motor may be represented by
the simplified equivalent circuit shown in Fig.1. L
a
represents the total armature inductance, R
a
is the
equivalent series resistance, andE
a
the armature back emf.
This induced emf represents that portion of the total input
energy which is converted to mechanical output. The
magnitude of the armature emf is proportional to motor
speed.
Motor inductance, which may vary from tens of µH to mH,
will have a significant effect on PWM drive designs. This is
due to the fact that average motor current is a function of
theelectrical time constant of the motor, τ
a
, where. τ
a
=L
a
/R
a
.
For aPWMwaveformwith aperiod Tthe ratioof pulse width
to switching period is denoted by δ. The average pulse
current will dependupon theratioof the current pulse-width,
δT, to the motor electrical time constant, τ
a
.
Fig.2 Instantaneous motor current waveforms
a) High inductance motor, τ
a
= 5T
b) Low inductance motor, τ
a
= T/2
Figure 2 shows the conditions for two different motors and
afixed periodPWMwaveform. For the casewhen themotor
time constant is much greater than the pulse width, in
Fig.2(a) then the current cannot be established in the
inductive motor windings during the short duration of the
applied pulse. For a low inductance motor and the same
pulse width, Fig.2(b), the armature current is easily
established. In most instances a motor which has high
armature inductance will require a lower PWM drive
frequency in order to establish the required current levels,
andhence develop the necessary torque. A lowinductance
motor allows the use of a high switching drive frequency
thus resulting in an overall faster system response.
In general, to achieve optimum efficiency in a PWM motor
drive at the highest practical frequency, the motor should
have an electrical time constant, τ
a
, close to the duration of
the applied waveform T. ( τ
a
= kT where k is small). The
printed circuit motor is one of the lowest inductance DC
motors available since the armature is etched from a flat
disc-like material much like a double-sided printed circuit
board. Consequential these low inductance, low inertia
dT
T
V
dc
dT
T
V
dc
a) b)
v
a
v
a
i
a
i
a
Va
Ra La
Ea
Ia
293
Motor Control Power Semiconductor Applications
Philips Semiconductors
motors also exhibit very fast response with quite high
torque. Electrical time constants in the order of 100µs allow
these motors to be used with switching rates as high as
100kHz, with typical drive circuits being operated at 10kHz.
Thus an appropriate choice of switching frequency and
motor inductance ensures a high average motor current
during each switching pulse. Motor current control, and
hence torque control, is achieved by varying the width of
the applied pulsed waveforms. As the base, or carrier,
frequency is held constant then the pulse width relays
torque control information to the motor. Torque is
dependent on average motor current (equation 1) which, in
turn, is controlled by duty cycle.
(1)
Fig.3 Simplified PWM DC motor controller
PWM motor control
The PWM method of current control will be considered by
examining the conditions at motor start-up for a simple
arrangement, shown in Fig.3, where the duty cycle is
controlled using the DC control voltage, V
REF
. At start-up
theduty cycleisadjustedtobelongenoughtogivesufficient
motor starting torque. At zero rotational velocity (ω=0) the
back emf, E
a
, is zero and so the full DC voltage appears
across the series R
a
/L
a
impedance. The initial motor current
is determined according to the equation:
(2)
If the duty cycle ratio, controlled using V
REF
, is given by δ,
then the duration of the ’ON’ pulse is simply given by δT.
Duringthis interval theriseof motor current prior toarmature
rotation is shown by Equation 3.
(3)
The current in the motor windings rises exponentially at a
rate governed mainly by average supply voltage and motor
inductance. If the pulse width is close to the time constant
of the motor then the current at the end of the first pulse
will reach nearly 60% of its maximum value, I
max
= V
dc
/R
a
.
This is shown as I
1
in Fig.4. For the remainder of the PWM
cycle switch S1 is off and motor current decays through the
diode at a rate dependant upon the external circuit
constants and internal motor leakage currents, according
to the equation:
(4)
The motor current at the end of the period, T, remains at a
level I
2
, which is then the starting current for the next cycle,
as shown in Fig.4. As the switching sequence repeats,
sufficient current begins to flow to give an accelerating
torque and thus cause armature rotation. As soon as
rotationbegins, back emf isgenerated whichsubtracts from
the supply voltage. The motor equation then becomes:
(5)
Thecurrent drawn fromthesupply will consequently beless
than that drawn at start-up due to the effect of the motor
back emf term, E
a
. For a given PWM duty cycle ratio, δ, the
motor reaches a quiescent speed governed by the load
torque and damping friction. Maximum motor torque is
required at start-up in order to accelerate the motor and
load inertias to the desired speed. The current required at
start-up is therefore also a maximum. At the end of the
starting ramp the controller duty cycle is reduced because
less current is then needed to maintain the motor speed at
its steady state value.
Fig.4 Motor current waveforms at start-up
i
a
= I
1
.e
−(t − δT) /τ
a
T
e
= K
T
I
a
V
dc
Motor
PWM
PULSE WIDTH
ADJUST
V
REF
Load
T
e
I
a
L
a
.
di
a
dt
+ R
a
.i
a
= V
dc
−E
a
V
dc
v
a
i
a
I
max
I
1
I
2
dT
T
t
t
L
a
.
di
a
dt
+ R
a
.i
a
= V
dc
i
a
=
V
dc
R
a
.

1 − e
−t /τ
a


294
Motor Control Power Semiconductor Applications
Philips Semiconductors
Fig.5 Motor current waveform, τ
a
<< T
For a low inductance motor where the electrical time
constant is much less than the duty cycle then the motor
current waveform will closely follow the applied voltage
waveform, as shown in Fig.5. An approximate expression
for the average motor current is given by:
(6)
Insummary, the principle control variablein thePWMmotor
control system is ’duty cycle’, δ. Motor torque and velocity
can be tightly controlled by controlling the PWM duty cycle
and motor current.
The switched mode controller
For the remaining portion of the paper integrated
switched-mode control will be considered with specific
reference to the NE/SE5560 controller IC. This device
incorporates control andprotection functions for SMPSand
DC motor control applications including internal
temperature compensation, internal reference voltages, a
sawtooth waveform generator, PWM amplifier and output
stage. Protection circuitry includes cycle-by-cycle current
limiting, soft start capability, overcurrent protection, voltage
protection and feedback loop protection circuits. In the
following sections some of the features of the controller will
be examinedand its use in a number of motor drive designs
will be presented.
Current
Voltage V
dc
E
a
Motor emf
t
I
ave
= δ.
(V
dc
−E
a
)
R
a
295
Motor Control Power Semiconductor Applications
Philips Semiconductors
Fig.6 NE5560 Block diagram
Fig.7 Unipolar switched mode motor drive (SMMD) using the NE5560
296
Motor Control Power Semiconductor Applications
Philips Semiconductors
The device (see Fig.6) contains an internal voltage
reference which is connected to the non-inverting input of
the error amplifier. The feedback signal is obtained from
either a tachogenerator (TGF - tachogenerator feedback)
or from a signal proportional to the armature voltage less
the winding iR voltage drop (AVF - armature voltage
feedback). This feedback signal must be scaled to centre
about the internal voltage reference level. The error
amplifier output, in addition to being available for gain
adjustment and op amp compensation, is connected
internally to the pulse-width modulator. Frequency may be
fixed at any value from 50Hz to 100kHz and duty cycle
adjusted at any point from 0 to 98%. Automatic shut-down
of the output stage occurs at low supply threshold voltage.
The error amplifier has 60dB of open loop gain, is stable
for closed loop gains above 40dB and can also can be
compensated for unity gain. The single ended switching
output is from either the emitter or collector of the output
stage. The device has protective features such as high
speed overcurrent sense which works on a cycle-by-cycle
basis to limit duty cycle, plus an additional second level of
slow start shutdown. It is this input which can be adapted
to act as a motor torque limit detector.
a) Unipolar drive b) Bipolar drive
Fig.8 Constant speed servo configurations
V
dc
Motor Load
T
e
Tacho
V
REF
+V
dc
Motor Load
T
e
Tacho
V
REF
-V
dc
297
Motor Control Power Semiconductor Applications
Philips Semiconductors
Fig.9 Basic unidirectional drive with dynamic braking
Open loop PWM control using the NE5560
For a given application the switched-mode controller
frequencyshould beset toallowthebest dynamicresponse
considering the starting current requirement and motor
electrical time constant, as discussed previously. The main
drive transistors or MOSFETs must be capable of carrying
the peak motor current requirement which occurs at
start-up. Device protection using snubber networks and
transient suppression networks will depend on the choice
of switching device, system ratings and the application
requirements. Power MOSFETs provide an excellent
solution to many DC drive designs since very low drive
power is required and they are self-protected fromreverse
transientsbyan internal intrinsic diode. PowerMOSdevices
may be parallelled for added power handling capability.
Figure 7 shows a simple unipolar drive capable of driving
a low voltage motor supplied from an external DC voltage
and PWM controlled using the NE5560.
Constant velocity servo
Figure 8 shows in block form the general circuit used to
obtain a constant speed switched mode motor drive
(SMMD) servo. Figure 8(a) shows a unipolar drive using
DCtachometer feedback tothe PWMerror amplifier. Figure
8(b) shows a bidirectional drive in a half-bridge
configuration. In this case the duty cycle controls the
direction of motor rotation in addition to the motor speed.
A 50% duty cycle corresponds to the standstill condition. If
the average duty cycle is greater than 50%(CWcommand)
then the motor accelerates clockwise, and vice-versa for
CCW rotation when the duty cycle is less than 50%. This
circuit configuration can be used for both velocity and
position servo-designs. The reversing switch allows the
tachogenerator output to match the polarity of the PWM
reference, which is always positive.
The unipolar drive circuit in Fig.9 uses the NE5560 to
develop a SMMD with constant speed control suitable for
a small DC motor. The switching device is a single Philips
BUK456-100A Power MOSFET capable of over 30 A, with
a voltage rating of 100VV
DS
and R
DS(ON)
=0.057Ω. The PWM
drive from the NE5560 is applied to the gate at a nominal
10kHz, althoughmuchhigher frequenciesarepossible. The
peak gateto source voltage, V
GS
, is 15Vto ensureminimum
R
DS(ON)
and hence minimum loss in the PowerMOS switch.
A sense resistor is placed in the source lead to monitor
motor drive current on a cycle-by-cycle basis. The value of
this resistor is set to develop the error amplifier threshold
voltage at the desired maximum current. The NE5560 then
automatically limits the duty cycle, should this threshold be
exceeded. This is therefore used as an auto torque limit
featureinaddition tosimply protecting the switching device.
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Motor Control Power Semiconductor Applications
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A slow start network (Pins 2,5,6) gradually ramps up the
duty cycle at power on. Fixed braking duty cycle control is
achieved by forcing the input error amplifier during braking
conditions. The over-current circuit is still active during
braking.
SMMD Position servo with µP control
By couplingtheswitchedmode motor drive inabidirectional
configuration as shown in Fig.10, and then sensing linear
position with a potentiometer or LVDT connected to a lead
screw, for instance, the position feedback loop can be
closed to give a position servo. The input to control position
of the mechanical stage may be fed as a DC offset to a
summing amplifier whose output is fed to Pin 5 of the
NE5560, as shown. Forward lead-lag compensation may
becombinedwith thesumming amplifier functiontoachieve
a stable response. A velocity loop may be closed through
the error amplifier at Pin 3. The controller may easily be
interfaced to a microprocessor by means of a unipolar D/A
converter working in the 1 to 6V output range as an input
to Pin 5.
Conclusions
Theswitched-mode motor drive, SMMD, usingsmall, easily
available, monolithic integrated control devices designed
for switched-mode power applications may easily be
adapted to performa number of useful and efficient torque,
velocity and position control operations. The ready
availability of good controller ICs, easilycompatible with the
Philipsrange of switchingpower devicesin bothbipolar and
PowerMOS technologies makes such designs even more
effective and easily attainable by the control systems
designer.
Fig.10 Microprocessor control of PWM drive with four quadrant control
S2
S1
D1
D2
S3
S4
D4
D3
POSITION
VELOCITY
ERROR
D/A
P
DIRECTION
LOGIC
NE5560
V
dc
0V
MOTOR
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Motor Control Power Semiconductor Applications
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3.2.3 Brushless DC Motor Systems
In recent years the number of drive systems available to
designers has increased considerably. The advent and
increasinguseof stepper motors, inverter-fedac machines,
switched reluctance motors and brushless machines have
all addressed particular applications and in some cases
these application areas overlap. The correct choice of a
drive system for a particular application depends not only
upon the speed and torque requirements but also on
performance, response, complexity and cost constraints.
The brushless DC motor (BDCM) system is emerging as
one of the most useful drive options for a wide range of
applications ranging from small, low power fans and disc
drives, through medium size domestic appliance motors
and up to larger industrial and aviational robotic and servo
drives.
This section will review the theory and operation of
brushless DC motors and describe some of the
considerations to be made when designing BDCM drive
systems using PowerMOS devices as the main inverter
switches.
Background
The principal advantage of a conventional DC machine
compared to an AC machine is the ease with which a DC
motor can be controlled to give variable speed operation,
including direction reversal and regenerative braking
capability. The main disadvantage of a DC machine is that
the carbon brushes of a DC motor generate dust and also
require maintenance and eventual replacement. The RFI
generated by the brushgear of a DC motor can be quite
large and, in certain environments, the sparks themselves
can be unwelcome or hazardous. The brushless DC motor
was developed to achieve the performance of a
conventional DCmachine without the problems associated
with its brushes.
The principal advantages of the BDCM system are:
• Long life and high reliability
• High efficiency
• Operation at high speeds and over a wide speed range
• Peak torque capability from standstill up to high speeds
• Simple rugged rotor construction
• Operation in vacuum or in explosive or hazardous
environments
• Elimination of RFI due to brush commutation
DC motor configurations
In a conventional DC motor the field energy is provided by
either a permanent magnet or a field winding. Both of these
arrangements involve quite large, bulky arrangements for
the field. In the case of wound field DC motors this is due
to large number of turns needed to generate the required
electromagnetic field in the airgap of the machine. In the
case of permanent magnet DC machines the low energy
density of traditional permanent magnet materials means
that large magnets are required in order to give reasonable
airgap fluxes and avoid demagnetisation. If either of these
two options are used with the field excitation on the rotor
of the machine then the inertia and weight of the rotor make
the machine impractical in terms of its size and dynamic
response.
Aconventional DCmachinehas alargenumber of armature
coils on the rotor. Each coil is connected to one segment
of a commutator ring. The brushes, mounted on the stator,
connect successive commutator segments, and hence
armaturecoils, totheexternal DCcircuit asthemotor moves
forward. This is necessary to maintain maximum motor
torque at all times. The brush/commutator assembly is, in
effect, a rotating mechanical changeover switch which
controls the direction and flow of current into the armature
windings.
In a BDCM the switching of current to the armature coils is
carried out statically and electronically rather than
mechanically. The power switches are arranged in an
inverter bridge configuration in order to achieve
bidirectional current flow in the armature coils, i.e. two
power switches per coil. It is not possible to have a large
number of armature coils, as is the case for a conventional
DC motor because this would require a large number of
switching devices and hence be difficult to control and
expensive. An acceptable compromiseisto have only three
armature coils and hencesix power switches. Reducing the
number of armature coils means that the motor is more
prone to developing ripple torque in addition to the required
DCtorque. This problemcan be eliminated by good design
of the motor. The armature of a three coil brushless DC
machine in fact looks similar to the stator of a three phase
AC machine and the term ’phase’ is more commonly used
to describe these three separate coils.
The development of brushless DC machines has made
possible by developments in two other technologies:
namely those of permanent magnet materials and power
semiconductor switches.
Permanent magnet materials
Traditional permanent magnet materials, such as AlNiCo
magnets and ferrite magnets, are limited either by their low
remanence giving rise to a low airgap flux density in
electrical machines, or by their susceptibility to
demagnetisation in the presence of high electric fields.
However in recent years several new permanent magnet
materials have been developed which have much higher
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Motor Control Power Semiconductor Applications
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a) Conventional DC motor
b) Brushless DC motor
Fig.1 DC motor configurations
Stator core
Field magnet
Armature
coils
I
a
Rotor
Commutator
Brush
Stator core
winding
Field
magnet
Rotor
A
B
C
Phase
I
I
I
remanent flux densities, and hence airgap flux densities,
and high coercivities, making them resistant to
demagnetisation under normal operating conditions.
Amongst these materials, called ’rare earth’ magnets,
Samarium Cobalt (SmCo
5
and Sm
2
Co
17
) and Neodymium-
-Iron-Boron (Nd-Fe-B) are the most common. These
materials, although still quite expensive, give vastly
superior performance as the field excitation for a brushless
machine.
Due to the increased energy density of rare earth magnets
the amount of magnet material required by the application
is greatly reduced. The magnet volume using rare earths
is small enough that it is feasible to have the permanent
magnet field on the rotor of the machine instead of on the
stator. The gives a low inertia, high torque motor capable
of high performance operation. This resulting motor design,
with the armature on the stator and the field on the rotor
and shown in Fig.1, can be considered as a conventional
DC motor turned ’inside out.’
Power electronic switches
For the ’inside out’ BDCM is it still necessary to switch the
armature current intosuccessive armature coils as the rotor
advances. As the coils are nowon the stator of the machine
the need for a commutator and brushgear assembly has
disappeared. The development of high voltage and high
current power switches, initially thyristors, bipolar power
transistors and Darlingtons, but more recently MOSFETs,
FREDFETs, SensorFETs and IGBTs, has meant that
motors of quite large powers can be controlled
electronically, giving a feasible BDCM system. The
question of appropriate device selection for brushless DC
drives will be considered later.
System description (Fig.2)
DC power supply
The fixed DCvoltageis derived fromeither abattery supply,
low voltage power supply or from a rectified mains input.
The input voltage may be 12V or 24V as used in many
automotive applications, 12V-48V for applications such as
disc drives or tape drives, or 150V-550V for single-phase
or three-phase mains-fed applications such as domestic
appliances or industrial servo drives or machine tools.
Inverter
The inverter bridgeis the main power conversion stage and
it is the switching sequence of the power devices which
controls the direction, speed and torque delivered by the
motor. The power switches can be either bipolar devices
or, more commonly, PowerMOS devices. Mixed device
inverters, for example systems using pnp Darlingtons as
thehigh side power switches andMOSFETs as the lowside
switches, are also possible. The freewheel diodes in each
inverter leg may be internal to the main power switches as
in the case of FREDFETs or may be separate discrete
devices in the case of standard MOSFETs or IGBTs.
Detailed considerations of inverter design, gate drive
design and layout have been considered in separate
articles.
The inverter switching speed may be in the range 3kHz to
20kHz and above. For many applications operation at
ultrasonic switching speeds (>15-20kHz) is required in
order to reduce system noise and vibration, reduce the
amplitude of the switching frequency currents and to
eliminate switching harmonic pulsations in the motor.
Because of the high switching speed capability of
PowerMOSdevices they are often the most suitable device
for BDCM inverters.
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Motor Control Power Semiconductor Applications
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Fig.2 BDCM system
S2
S1
D1
D2
S4
S3
D3
D4
S6
S5
D5
D6
DC Power
Supply
Controller Current set
Speed set
N
S
Hall
Effect
devices
Gate drives
Motor
i
c
i
b
i
a
Inverter
The first choice for the inverter devices might appear to be
one with an N-channel MOSFET for the bottom device in
each inverter leg and a P-channel device in the top half of
each leg. The disadvantage of P-channel devices is that
they require around three times more silicon area than
equivalent N-channel MOSFETs toachieve the samevalue
of R
DS(ON)
. This makes P-channel devices uncompetitively
expensive for many applications. However, using
N-channel devices for both the top and bottom switches in
an inverter leg means that some sort of floating drive is
required for the upper device. Transformer coupled or
optically coupled gate driver stages are required, or
alternatively, circuits such as the bootstrap circuit shown in
Fig.3 can be used to provide the drive for the top device.
In the circuit of Fig.3 the bootstrap capacitor is charged up
viathe diode Devery time the bottomMOSFETis on. When
this device turns off the capacitor remains charged up to
the gate supply voltage as Dis nowreverse biassed. When
a turn-on pulse is applied for the upper MOSFET the
bootstrap capacitor provides the necessary gate source
voltage to turn the device on.
Motor
A two pole BDCM with the field magnets mounted on the
surface of the rotor andwith a conventional stator assembly
was shown in Fig.1. Machines having higher numbers of
poles are often used depending upon the application
requirements for motor size, rotor speed and inverter
frequency. Alternative motor designs, such as disc motors
or interior magnet rotor machines, are also used for some
applications. The motor phases are usually connected in a
star configuration as shown in Fig.2. Rotor position sensors
are required in order to control the switching sequence of
the inverter devices. The usual arrangement has three Hall
effect sensors, separated by either 60˚ or 120˚, mounted
on the stator surface close to the airgap of the machine. As
the rotor advances the switching signals from these Hall
Effect latches are decoded into rotor position information
in order to determine the inverter firing pattern.
In order to minimise torque ripple the emf induced in each
motor phase winding must be constant during all instants
intime when that phase isconducting current. Any variation
in a motor phase emf whilst it is energised results in a
corresponding variation in the torque developed by that
phase. The so-called ’trapezoidal emf’ motor, shown in
Fig.4, has a constant induced emf for 120˚ and so is a
practical motor design which gives optimum performance
in a BDCM system.
Controller
Theinverter iscontrolledinorder tolimit the devicecurrents,
and hence control the motor torque, and to set the direction
and speed of rotation of the motor. The average ouput
torque is determined by the average current in each phase
when energised. As the motor current is equal to the DC
link current (Fig.2) then the output torque is proportional to
the DC input current, as in a conventional DC motor. The
motor speed is synchronous with the applied voltage
waveforms and so is controlled by setting the frequency of
the inverter switching sequence.
Rotor position feedback signal are derived from the Hall
effect devices as discussed earlier or from opto-
transducers with a slotted disc arrangement mounted on
the rotor shaft. It is also possible to sense rotor position by
monitoring the emfs in the motor phase windings but this
is somewhat more complex. In some applications the Hall
effect sensor outputs can be used to provide a signal which
is proportional to the motor speed. This signal can be used
in a closed loop controller if required.
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Motor Control Power Semiconductor Applications
Philips Semiconductors
Fig.3 Bootstrap driver circuit for upper device in
inverter bridge leg
Fig.4 Trapezoidal emf motor
Fig.5 Motor waveforms for BDCM system
The controller also requires a current feedback signal.
Usually this is taken from the DC link of the inverter as
shown in the Fig.2. The current is controlled using either
PWM techniques or hysteresis type of control. A current
reference command is compared with the current feedback
signal and then used to determine the switching signal to
the main power devices. Additional controller functions
include undervoltage protection, thermal protection and
current ripple limit controls, error amplifier inputs for
incorporation in closed loop servos and microprocessor
compatible inputs.
Several IC manufacturers offer dedicated ICs providing all
the functions for PWMcontrol of brushless DCmotors. The
Philips version of the NE5570 CMOS controller is one such
device which can be used for three phase BDCM systems
using a serial data input command from a microprocessor
controller. This device contains the PWM comparator and
oscillator, dynamic current loop controller and output
pre-drivers suitable for a MOSFET power stage. Its
operation is describedmore fully in Philips Application Note
AN1281.
Brushless DC motor operation
The operation of a BDCM system can be explained with
reference to Fig.5. At any instant in time the rotor position
is known by the output states of the three airgap mounted
Hall effect devices. Theoutput stateof oneHall effect device
switches for every 60˚ of rotation, thus defining six
conduction zones as shown in the figure. The switching of
the inverter devices is arranged to give symmetrical 120˚
intervals of positive and negative constant current in each
motor phase winding. The position of the sensors and
controller logic ensures that the applied currents are in
phase with the motor emfs in order to give maximummotor
torque at all times.
Referring to Figures 2 and 5, during the first 60˚ conduction
zone switches S1 and S4 are on and the current flows
through the ’A’ and ’B’ phase windings. The ’C’ phase is
inactiveduringthis interval. At the endof this 60˚ conduction
zone one of the Hall effect devices changes state and so
switchS4turnsoff andS6turnson. Theswitchingsequence
continues as the motor advances. At any instant in time two
motor phases are energised and one motor phase is off.
Themotor phasecurrent waveforms aredescribedasbeing
’quasi-square’ in shape. The motor windings are energised
for two thirds of the total time and the maximumswitch duty
cycle ratio is one third.
The other function of the controller is to maintain the motor
phasecurrents at their desired constant value for each 120˚
interval that a particular phase is energised. The precise
method of current limiting depends upon the controller
algorithm. In order to limit the current to its desired value
either one or both of the conducting devices are switched
off thus allowing the motor current to freewheel through the
S2
S1 D1
D2
D
C
V
out
15V
V
dc
0V
60 120 180 240 300 360
e
A
e
B
e
C
(wt)
(wt)
(wt)
S1
S4
S1
S6
S3
S6
S3
S2
S5
S2
S5
S4
O 60 120 180 240 300 360
i
A
i
B
i
C
Sensor
outputs
Phase
currents
Active
Devices
304
Motor Control Power Semiconductor Applications
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bridge leg diodes. The current is limited by controlling the
switch duty cycle to ensure that device current ratings and
themotor current rating arenot exceeded, especially during
start-up conditions or low speed operation. The amount of
current ripple is controlled by the switching frequency of a
PWM waveform or by the width of a hysteresis band.
Power Semiconductor switches for
Brushless DC motors
Philips Semiconductors produce a range of power
semiconductor devices suitable for use in BDCM systems.
The include transistors, MOSFETs, FREDFETs, Logic
Level MOSFETs (L
2
FETs) and IGBTs. These devices are
available in a variety of current and voltage ratings and a
range of packages, to suit individual applications.
FREDFETs
For higher voltage applications the FREDFET is an
appropriate device for the inverter switches in a brushless
DCdrive. The FREDFET is a PowerMOSdevice where the
characteristics of the MOSFET intrinsic diode have been
upgraded to those of a discrete fast recovery diode. Thus
the FREDFET is ideally suited to bridge circuits such as
that shown in Fig.2 where the recovery properties of the
bridgediodes significantly affect the switchingperformance
of the circuit. Fig.6 shows a conventional MOSFETinverter
bridge circuit, where the MOSFETs intrinsic diode is
disabled by a series Schottky diode. A discrete antiparallel
FRED carries the motor freewheeling current. Using the
FREDFET reduces the component count and circuit layout
complexity considerably.
MOSFET inverter leg FREDFET inverter leg
Fig.6 MOSFET and FREDFET half bridge legs
L
2
FETs
For many lower voltage applications logic level FETs
(L
2
FETs) can be used to interface the power circuit with
standard TTL or CMOS drive circuits without the need for
level shifting stages. L
2
FETs require gate source voltage
of only 5V to be fully turned on and typically have V
GS(th)
=
1-2V. Using Philips L
2
FETs in BDCM applications such as
tape or disc drives where the MOSFETs are driven directly
by a controller IC produces an efficient overall design with
the minimum of gate drive components.
IGBTs
IGBTs are especially suited to higher power applications
wheretheconductionlossesof aMOSFETbegintobecome
prohibitive. The IGBT is a power transistor which uses a
combination of both bipolar and MOS technologies to give
adevice which has lowon-state losses and is easy to drive.
The IGBT is finding applications in mains-fed domestic and
industrial drive markets. By careful design of the device
characteristics the switching losses of an IGBT can be
minimised without adversely affecting the conduction
losses of the device too severely. Operation of BDCM
inverters is possible at switching speeds of up to 20kHz
using IGBTs.
Device selection
The first selection criterion for an inverter device is the
voltage rating. Philips PowerMOS devices have excellent
avalanche ruggedness capability andso are able to survive
transient overvoltages which may occur in the inverter
circuit. This gives the circuit designer the freedomtochoose
appropriately rated devices for the application without
suffering from the extra device conduction losses which
occur when using higher voltage grade devices. In noisy
environments or where sustained overvoltages occur then
some external protection circuitry will usually be required.
For low voltage and automotive applications 60V devices
may be adequate. For mains-fed applications then the DC
link voltage is fixed by the external mains supply. A 240V
supply will, depending on the DClink filtering arrangement,
give a link voltage of around 330V. Using 450V or 500V
MOSFETs will allow sufficient margin for transient
overvoltages to be well within the device capability.
The current rating of a device is determined by the worst
case conditions that the device will experience. These will
occur during start-up, overload or stall conditions and
should be limited by the BDCM controller. Short circuit
protection must be provided by using appropriate fusing or
overcurrent trip circuitry.
Inaddition tothe normal motor currents the inverter devices
will experience additional currents due to diode reverse
recovery effects. The magnitude of these overcurrents will
depend on the properties of the freewheel diodes and on
the switching rates used in the circuit. Turn-on overcurrents
can often be greater than twice the normal load current.
The peak to average current capability of MOSFETs is very
good (typically 3 to 4) and so they are able to carry
overcurrents for short periods of time without damage. For
high power applications PowerMOS devices can easily be
V
dc
V
dc
V
out
V
out
305
Motor Control Power Semiconductor Applications
Philips Semiconductors
parallelled to give the required current ratings providing the
circuit is suitably arranged in order to ensure good current
sharing under both dynamic and static conditions.
Conclusions
The brushless DCmotor has already become an important
drive configuration for many applications across a wide
range of powers and speeds. The ease of control and
excellent performance of the brushless DC motors will
ensure that the number of applications using them will
continue to grow for the foreseeable future. The Philips
range of PowerMOS devices which includes MOSFETs,
FREDFETs, L
2
FETs and IGBTs are particularly suited for
use in inverter circuits for motor controllers due to their low
loss characteristics, excellent switching performance and
ruggedness.
306
Motor Control Power Semiconductor Applications
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Stepper Motor Control
307
Motor Control Power Semiconductor Applications
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3.3.1 Stepper Motor Control
A stepper motor converts digital information into
proportional mechanical movement; it is an
electro-mechanical device whose spindle rotates in
discrete steps when operated from a source that provides
programmed current reversals. After the appearance of the
stepper motor in applications traditionally employing digital
control, the advantages of precise and rapid positioning of
objects using stepper motor drive systems became more
obvious and this, in turn, led to a greater variety of
applications. These now include:
• paper and magnetic tape drives,
• camera iris control and film transport,
• co-ordinate plotters, printers, chart recorders and
variable speed chart drives,
• medical equipment,
• fuel control, valve control and variable speed pumps,
• meters, card readers, production line pulse counters
• automatic weighing and labelling systems,
• digital to analogue converters and remote position
indicating equipment.
All of these applications have one thing in common -
controlled motion. Wherever controlled movement and/or
positioning is necessary, the stepper motor can be used to
give a fast, flexible and accurate system.
Fromamechanical viewpoint, the stepper motor has simple
positional control, reliability and precision. Previously,
simple, mechanically operated switches often provided
adequate control for many positioning systems but
increasedperformance requirements have forced the need
for abetter drive systems. The advantages of stepper motor
systems have been gained at the expense of controller
simplicity. The combination of fast controller ICs, low cost,
high power, high efficiency switches, particularly
MOSFETs, and the ease of use of stepper motors has lead
to their current widespread use.
The full benefit of a stepper motor can only be realised if it
is correctly driven. It requires a dc supply, an electronic
switch and a source of control pulses (digital information).
The appropriate dc supply is directed into the motor via a
power electronic switching network. In effect, the motor
moves through one step for each control pulse applied to
the power stage electronic switches. The angle of the step
depends upon the type of motor and can be from as little
as 1.8˚ to as much as 15˚. Consequently, if 24 pulses are
fed to the switching network, the shaft of a motor with a 15˚
step-angle will complete one revolution. The time taken for
this action is entirely a function of the rate at which control
pulses are applied. These may be generated by an
oscillator with adjustable frequency or from a dedicated
controller IC.
Principles of operation
Stepper motors can be divided into three principle types:
• permanent magnet stepper motors
• variable reluctance stepper motors
• hybrid stepper motors.
a)
b)
Fig.1 Unipolar 4-phase motor
Permanent magnet stepper motors
The step angle of a permanent magnet stepper motor
depends upon the relationship between the number of
magnetic poles on its stator assembly and the number of
magnetic poles on its rotor. Since the latter is a cylindrical
permanent magnet, the poles are fixed, and their number
is limited, due to the characteristics of the magnetic
material. Enlarging the magnet diameter to provide for a
larger number of rotor poles results in a drastic increase in
the rotor inertia. This reduces the starting capabilities of
such a motor beyond practical use. With a permanent
magnet rotor, only relatively large step angles can be
obtained. However, the operating step angle can be
reduced by using more than one stator stack along the
length of the machine and then by offsetting the separate
stacks.
P
Q
R S
S1
S2
+
N
S
N S
N
S
S3
S4
R
P
Q
S
S1
S2
+
S
N
N S
N
S
S3
S4
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Motor Control Power Semiconductor Applications
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Fig.2 Unipolar 4-phase system
a) Circuit layout, b) Switching waveforms
The stator assembly comprises two or more stators, each
having a coil through which current is passed to form a
magnetic field. By reversing the direction of current flowing
in a coil the north and south poles developed by the coils
can be transposed. Reversing the current flow through
successive stator coils creates a rotating magnetic field
which the permanent-magnet rotor follows. Speed of
rotationis thus governed by the rate at which the stator coils
(and hence the electromagnetic poles) are switched and
the direction of rotation by the actual switching sequence.
There are two methods by which the current flow through
stator coils can be reversed and this has led to two classes
of stepper motor: those designed for unipolar drive and
those for bipolar drive. For ease of description, illustrations
in this section which give a diagrammatic representation of
apermanent magnet stepper motor showonlya2-polerotor
although it could have as many as 24: the operating
principles, however, are the same.
Motors for Unipolar drive
Each stator coil of a motor designed for unipolar drive is
provided with a centre-tap which is connected to one side
of the supply. The direction of current flowing through a coil
is then determined by the end to which the other supply line
is connected via a switching device. Switching between the
coil halves results in the magnetic poles of the relevant
stator being reversed.
Figure1(a) showsa4-phase stepper motor in whichphases
P and R are energised. The north poles at P and R cause
the rotor to align in the position indicated. If switch S1 is
turned off and S3 turned on, so that phases Q and R are
now energised, then the stator field is repositioned and so
the conditions illustrated in Fig.1(b) are obtained, ie. the
rotor has moved through 90˚ to align with the stator field.
From this it can be seen that by altering the switching
sequence for switches S1, S2, S3 and S4 the rotor can be
made to advance in either direction.
Figure 2(a) shows the drive configuration for a unipolar
4-phase motor. The switching sequence of the power
switches is shown in Fig.2(b). Two motor phases are
energised at any one time thus giving the rotation of the
stator field and required stepping motion.
a)
b)
Fig.3 Bipolar 4-phase motor
Motors for Bipolar drive
The stator coils of a motor designed for bipolar drive have
no centre-tap. Instead of using alternate coil-halves to
produce a reversal of current-flow through the stator
windings, the current is nowreversedthrough the entire coil
by switching both supply lines. Operation of a motor with
bipolar drive is identical to that of one with unipolar drive,
and is shown in Fig.3. Here, when the polarity of current in
phase P is reversed using switches S1 to S4 the stator field
realigns and the rotor moves accordingly. Figure 4(a)
shows the drive configuration for a bipolar 4-phase motor.
The devices are always switched as pairs, i.e. S1 and S4,
S2 and S3. The switching waveforms for this configuration
are shown in Fig.4(b).
The advantages of using motors with bipolar drive are
shown in Fig.5. This compares the performance of a
unipolar motor with its bipolar equivalent. Unipolar motors
P Q R S
S1 S3 S2 S4
S1
S2
S3
S4
Rotor
position
a)
b)
+
N
S
S N
S
N
P
Q
S2 S1 S3 S4
S5 S6 S8 S7
+
S
N
S N P
Q
N
S
S2 S1 S3 S4
S5 S6 S8 S7
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Fig.4 Bipolar 4-phase system
a) Circuit layout, b) Switching waveforms
develop less torque at low stepping rates than their bipolar
counter-parts, although at higher stepping rates the torque
developed by both types of motor is nearly the same.
The 4-phase unipolar motor shown in Fig.1 has two coils
per phase which must be wound on one bobbin for each
stator (bifilar winding), ie. four coils in total. Because the
two coils occupy the same space as a single coil in
equivalent bipolar types, the wire is thinner and coil
resistance higher. Bipolar motors have only one coil per
bobbin so that 2-stator motors have two coils and 4-stator
motors four coils. Unipolar motors require only a simple
drive circuit - only four power transistors instead of eight.
Moreover, the switching time requirements are less severe
for unipolar drives. For a bipolar drive, care must be taken
with switching times to ensurethat two opposing transistors
are not switched on at the same time, thus shorting out the
supply. Properly operated, bipolar windings give optimum
motor performance at low to medium stepping rates.
Variable reluctance stepper motors
In a variable reluctance stepper motor the motion is
achieved by using the force of attraction between a
magnetised component (the stator pole excited by a
controlledcurrent) andapassivesteel component (the rotor
pole). As successive stator poles are energised different
rotor poles are attracted towards the nearest active pole,
thus giving the required stepping motion. Figure 6 shows
the simplest variable reluctancemotor configurationhaving
six stator poles and four rotor poles. The rotor is simply a
shaped steel shaft. The stator winding is arranged so that
one stator phase winding is on each stator pole.
Figure 6(a) shows the condition when the ’A’ phase of the
motor is energised and rotor pole 1 is aligned with the
energised winding. If stator phase ’A’ is switched off and
phase ’B’ is switched on then rotor pole 2 (which is the
nearest rotor pole to any ’B’ phase pole) experiences an
attractive force due to the energised ’B’ phase. The rotor
advances to the position shown in Fig.6(b).
S3
S2, S3
S6, S7
S1, S4
S5, S8
Rotor
position
S1
S4
S2
S7
S5
S8
S6
a)
b)
P Q
Fig.5 Torque vs. stepping rate characteristic
A) Unipolar motor B) Bipolar motor
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Motor Control Power Semiconductor Applications
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If, subsequentally, phase ’C’ is energised then rotor pole 1
will align with the ’C’ phase, as shown in Fig.6(c). The step
angle of a variable reluctance motor can be reduced by
having more than one set of offset rotor poles which are
built up along the stack length of the machine. Different
offset rotor poles align with the stator poles at each step
position.
Fig.6 Variable reluctance motor
Hybrid stepper motors
The usual configuration for ahybrid stepper motor operates
using the torque production methods found in both
permanent magnet and variable reluctance motors. This
gives a higher performance system with a low volume, and
hence a low rotor inertia, and small step angles. The rotor
of a hybrid stepper motor consists of an axially aligned
magnet and a pair of toothed discs, one at each end of the
rotor stack. The general layout is shown in Fig.7. The teeth
of the discs are misaligned with respect to each other with
the result that as the stator phase windings are energised
different teeth align with the stator poles, in a similar way
to those in a variable reluctance motor. The addition of the
permanent magnet on the rotor introduces a polarity in the
way that the rotor teeth align with the stator poles. Again
multi-stack motors are used to reduce the step length
further. Alternative hybrid stepper motor configurations
have the magnets on the stator, but operate in a broadly
similar manner.

Fig.7 Hybrid stepper motor, cross sectional view
Stepper motor systems
Proper selection of the right stepper motor for a specific
application calls for a thorough understanding of the
characteristics of the motor and its drive circuitry. Figure 8
shows schematically the four constituent parts of a stepper
motor system together with the most important aspects of
each. These will be briefly considered below.

Fig.8 Stepper motor system block diagram
The stepper motor
Typical standard step motor angles are shown below:
Step angle Steps per revolution
0.9˚ 400
1.8˚ 200
3.6˚ 100
3.75˚ 96
7.5˚ 48
15.0˚ 24
The no load step angle accuracy is specified for each type
of motor For example, a motor having a step angle of 7.5˚
and will typically position to within 20’ (i.e. 5%) whether the
motor is made to move for 1 step or 1000 steps. The step
angle error is non-cumulative and averages to zero every
four steps, i.e. 360˚. Every four steps the rotor returns to
the same position with respect to magnetic polarity and flux
paths. For this reason, when very accurate positioning is
required, it is advisable to divide the required movement
into multiples of four steps. This is known as the 4-step
mode of operation.
Torque
Three torques are used to define stepper motor operation:
Holding torque
At standstill, when energised, a certain amount of torque
is required to deflect a motor by one step. This is known
as the holding torque. When a torque is applied that
exceeds the holding torque the motor will rotate
continuously. The holding torque is normally higher than
the working torque and acts as a strong brake in holding
a load in position.
Detent torque
CONTROL
LOGIC
D.C. SUPPLY
POWER DRIVER
STEPPER
MOTOR
- Oscillator
- Half step
- Full step
- Ramping
- Battery
- Transformer, rectifier
- Unipolar
- Bipolar
- Chopper
- Step length
- Step length accuracy
- Holding torque
- Detent torque
- Dynamic torque
A
A’
1
2
3
4
B’
B
1
2
3
4
C
C’
a) b) c)
A phase energised B phase energised C phase energised
Rotation
1
2
3
4
Case
Windings
Stator
Shaft
Rotor disc
Magnet
Airgap
N
N S
S
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Motor Control Power Semiconductor Applications
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Due to their permanent magnets, hybrid stepper motors
and permanent magnet stepper motors have a braking
torque even when the stator windings are unenergised.
This is referred to as the detent torque.
Working (dynamic) torque
The dynamic characteristics of a stepper motor are
described by the curves of torque versus stepping rate.
Typical curves were shown in Fig.5. The pull-in curve
shows the load a motor can start and stop without losing
steps when operated at a constant stepping rate. The
pull-out curve shows the torqueavailable when the motor
is gradually accelerated to and decelerated from its
required working speed. The area between the two
curves is known as the slew range. The characteristic
curves are used to define the correct motor selection for
any particular application.
Overshoot
After executingeachsinglesteptherotor tends toovershoot
and oscillate about its final position as shown in Fig.9(a).
This is normal behaviour for any pulsed dynamic system.
The actual response depends on the load and on the power
input provided by the drive. The response can be modified
by increasing the frictional load or by adding mechanical
damping. However, mechanical dampers such as friction
discs or fluid flywheels add to system cost and complexity
and so it is usually better to damp electronically.
Fig.9 Dynamic step response
a) Single step undamped response
b) Electronically damped response
Two methods of electronic damping are commonly used -
the simplest being to delay the final pulse in an incremental
pulse train such that the effective length of the final step is
reduced. Alternatively, every pulse, or just the final pulse
in a train, can be modified into three stages, as shown in
Fig.9(b). Using this method of damping a forward pulse is
applied at time t
0
, a reverse pulse is applied at t
1
in order
to slow the rotor down and then finally a second forward
pulse is applied at t
2
which ensures the rotor comes to rest
at the desired position. The accelerating torque which is
developed from this final pulse is less than that for a full
step and so the shaft overshoot is significantly reduced.
Multiple stepping
There are often several alternatives available in order to
make a desired incremental movement. For example, a
rotation of 90˚ can be reached in 6 steps of a 15˚ motor, 12
steps of 7.5˚ motor or in 50 steps of a 1.8˚ motor. Generally,
a movement executed in a large number of small steps will
result in less overshoot, be stiffer and more accurate than
one executed in smaller number of large steps. Also there
is more opportunity tocontrol the velocity by starting slowly,
accelerating to full speed and then decelerating to a
standstill with minimum oscillation about the final position
if small step lengths are used.
Fig.10 Controlled acceleration and deceleration profiles
A voltage controlled oscillator and charging capacitor are
usually used for acceleration (or ramp) control of the motor.
The RC time constant of the ramp controller is used to give
different ramp rates. Figure 10 shows atypical curveof step
rate against time for an incremental movement with equal
acceleration and deceleration times.
Resonance
A stepper motor operated at no-load over its entire
operatingfrequencyrangewill exhibit resonancepoints that
are either audible or can be detected by vibration sensors.
If any areobjectionable thenthesedrive frequenciesshould
be avoided, a softer drive used, or alternatively extra inertia
or external damping added.
Drive methods
Thenormal drivemethod isthe 4-stepsequencementioned
above. However, other methods can be used depending
on the coil configuration and the logic pattern in which the
coils are switched:
Wave drive
Energising only one winding at a time is called wave
excitationandproduces the samepositionincrement as the
4-step sequence. Figure 11 shows the stepping sequence
for the bipolar 4-phase motor, which was discussed earlier
and shown in Fig.4. Since only one winding is energised,
time
Stepping
rate
Max stepping
rate
t
acc
t
run
t
dec
Final
position
Final
position
time
time
a)
b)
t0 t1 t2
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Motor Control Power Semiconductor Applications
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holding torque and working torque are reduced by 30%.
This can, within limits, be compensated by increasing
supply voltage. The advantage of this formof drive is higher
efficiency, but at the cost of reduced step accuracy.
Half-step mode
It is also possible to step a motor in a half-step sequence,
thus producing half steps, for example 3.75˚ steps from a
7.5˚ motor. A possible drawback for some applications is
that the holding torque is alternately strong and weak on
successive motor steps. This is because on ’full’ steps only
one phase winding is energised whilst on the ’half’ steps
two stator windings are energised. Also, because current
and flux paths differ on alternate steps, accuracy will be
worse than when full stepping. The switching sequence for
a 4-phase bipolar drive is shown in Fig.12.
Fig.11 Wave drive switching for 4-phase bipolar
stepper motor
Fig.12 Half stepping switching for 4-phase bipolar
stepper motor
Supply considerations
When a motor is operated at a fixed rated voltage its torque
output decreases as step rate rises. This is because the
increasing back EMF and the rise time of the coil current
limits the power actually delivered to the motor. The effect
is governed by the motor time constant (L/R). Because of
their higher winding resistance unipolar motors have a
better L/R ratio than their bipolar equivalents. The effect
can be compensated by either increasing the power supply
voltage to maintain constant current as stepping rate
increases, or by increasing supply voltage by a fixed
amount and adding series resistors to the circuit.
Adding series resistors to the drive circuit can improve the
motor performance at high stepping rates by reducing the
L/R ratio. Adding a series resistor three times the winding
resistance would give a modified ratio of L/4R. Supply
voltage would then have to be increased to four times the
motor rated voltage to maintain rated current. The addition
of the extra resistance greatly reduces the drive efficiency.
If the increased power consumption is objectionable some
other drive method such as a bi-level voltage supply or a
chopper supply should be used.
Bi-level drive
With a bi-level drive the motor is operated below rated
voltage at zero step rate (holding) and above rated voltage
when stepping. It is most efficient for fixed stepping rates.
The high voltage may be turned on by current sensing
resistors or, as in the circuit of Fig.13, by means of the
inductively generated turn-off current spikes. At zero step
rate the windings are energised from the low voltage. As
the windings are switched in the 4-step sequence, diodes
D1, D2, D3 and D4 turn on the high voltage supply
transistors S1 and S2.
Fig.13 Unipolar bi-level drive
Chopper drive
A chopper drive maintains current at an average level by
switching the supply on until an upper current level is
reached and then switching it off until a lower level is
reached. A chopper drive is best suited to fast acceleration
andvariablefrequency applications. It is more efficient than
an analogue constant current regulated supply. In the
chopper circuit shown in Fig.14, V+ would be typically 5 to
10 times the motor rated voltage.
Spike suppression
When windings are turned-off, high voltage spikes are
induced which could damage the drive circuit if not
suppressed. They are usually suppressed by a diode
across each winding. A disadvantage is that torque output
S2, S3
S6, S7
S1, S4
S5, S8
Rotor
position
S2, S3
S6, S7
S1, S4
S5, S8
Rotor
position
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Motor Control Power Semiconductor Applications
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is reduced unless the voltage across the transistors is
allowed to build up to about twice the supply voltage. The
higher this voltagethe faster the inducedfields andcurrents
collapse and performance is, therefore, better. For this
reason a zener diode or series resistor is usually added as
in Fig.15.
Fig.14 Unipolar chopper drive
Fig.15 Voltage suppression circuit
Performance limitations
At standstill or lowstep rates, increasing the supply voltage
produces proportionally higher torque until the motor
magnetically saturates. Near saturation the motor
becomes less efficient so that increased power in
unjustifiable. The maximum speed of a stepper motor is
limited by inductance and eddy current losses. At a certain
step rate the heating effect of these losses limits any further
attempt toget morespeedor torqueout of amotor bydriving
it harder.
Terminology
Detent Torque: The maximum torque that can be applied
to the spindle of an unexcited motor without causing
continuous rotation. Unit: Nm.
Deviation: The changeinspindlepositionfromtheunloaded
holding position when a certain torque is applied to the
spindle of an excited motor. Unit: degrees.
Holding Torque: The maximum steady torque that can be
externally appliedto the spindle of an excited motor without
causing continuous rotation. Unit: Nm.
Maximum Pull-In Rate (Speed): The maximum switching
rate (speed) at which an unloaded motor can start without
losing steps. Unit: steps/s (revs/min).
Maximum Pull Out Rate (Speed): The maximum switching
rate (speed) which the unloaded motor can follow without
losing steps. Unit: steps/s (revs/min)