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Open Defects in CMOS RAM
Address Decoders
Philips Research Laboratories

Field failures of
embedded SRAMs led
the author to identify
open defects that escape
detection by
conventional march tests.
Appropriate decodertesting and DFT
strategies can uncover
these hard-to-detect



MEMORIES enjoy a
strategic position in the microelectronics industry. In many respects, RAM testing is different from conventional logic testing. RAMs
are the largest and densest circuits produced. Their small feature size and huge
chip size result in an enormous critical area
for defects.1 High complexity and defect sensitivity have pushed RAM test costs to the extreme. To cope with these economic and
qualitative issues, researchers have proposed a variety of test solutions (van de Goor
provides an overview2).
A common method of testing RAMs is to
perform what are known as march tests.2 In
a march test, individual march elements traverse all RAM addresses and perform a specified combination of read and write
operations. For example, a typical march element first reads each RAM address location
and then writes back the complement of expected data values. Together, all the march
elements should cover all the likely faults in
a given RAM.
After compiling the likely faults into a
RAM fault model, the test engineer develops
a test algorithm to cover it. The total number
of memory operations performed by all
march elements for a given RAM address determines a test algorithm’s overall complexity. The complexity of march test algorithms
is linear with respect to the address space;

0740-7475/97/$10.00 © 1997 IEEE

hence, they are also known as linear algorithms. Algorithms designated 13N, 6N, and
9N3,4 are examples of march tests.
Conventional wisdom suggests that we
can map RAM decoder defects as RAM array faults and detect them by testing the
RAM array.5 Hence, it would seem, address
decoders need no special testing. Recently,
however, Philips researchers came across
some open defects in RAM address decoders
that march tests did not detect and that resulted in field failures. This development
prompted us to look into the test implications of such defects.
Open defects, or stuck-open transistor
faults, cause sequential behavior in CMOS
circuits and require a two-pattern test sequence, T1 and T2, for their detection.6 Open
defects in RAM matrixes appear as cell read
failures, row/column read failures, or cell
stuck-at (SA) faults, 3,4 all detectable by
march tests. But march tests fail to detect one
class of open defects in address decoders.
Transistor and logic testability for stuckopen faults has received considerable
attention, resulting in a number of design-fortestability (DFT) solutions.6,7 However, performance and area constraints make
application of these solutions to RAM decoders unlikely. Furthermore, address decoder defects are not directly observable. The
tester must excite them in a way that makes


Phix: timing signal. the fault is a RAM.. A: address bits. the an NMOS decoder. address decoder from accessing the addressed cell.A5 Inputs veloping efficient test algorithms for a variety of fault models. owing to addressingsequence constraints. and testing for these faults remains a challenge. existing DFT solutions are impractical for RAM decoders. In contrast. In the case of multiple access. a fully static CMOS in its operation. An NMOS logic gate uses a unique RAM cell for each given RAM address. Thatte and Abraham’s position is that decoder faults switching transistor causes the gate to remain inactive when manifest themselves as RAM-matrix faults. But it reaches the inactive state validity for the newer technology. In addition. active for the rest. In the case of no access. WL: word line. little attention to faults in address decoders or other RAM building blocks. These fault models Phix A11 ranged from simple SA faults (b) to complex pattern-sensitive faults in the RAM array. In simple activating the gate. The rest by the input addresses. In CMOS technology. On the However. Hence. the cell contains either an SA0 or In NMOS technology. dress decoder behaves in one of two ways: An address decoder selects a word line according to the input address.pulls up the output to the inactive state when inputs are not matrix coupling fault between different cells.logic gate consists of an equal number of enhancementmode PMOS and NMOS transistors. for the NAND gates in Figure including the addressed cell. such a defect prevents the using conventional algorithms. This requires logic gate outputs in the address ■ no access—the decoder will not access the addressed cell. 1. A typical address decoder with NMOS (a) and CMOS (b) five-input NAND gate However. A CMOS logic gate in the address decoder arrives at the accause logic SA faults. Figure 1 illustrates a typical address decoder. only by several parallel paths (depending on the fan-in) selected a subset of open defects cause logic SA behavior. Motivation: CMOS WL63 A10 A9 Output WL62 WL61 Inputs WL60 A8 (a) A7 WL03 A6 WL02 Output WL01 Most previous research on WL00 RAM testing focused on de. They assumed that RAM array tests would detection by march tests. Thatte and Abraham conducted their study on other hand. and inactive (logic 1) in the rest of the cases. with NMOS test address decoder faults implicitly. Assuming a depletion-mode NMOS load transistor and switching enthat a faulty address decoder does not become sequential hancement-mode transistors. it may access nonaddressed cell(s). An address decoder is a combinational circuit that selects and CMOS logic implementations. Thatte and Abraham5 held that a faulty ad. For these reasons. For example. We shall see later that open defects cause sequential behavior in logic gates and thus escape in these parallel paths to inactivation cause the problem. decoder to be active only for a unique input address and in■ multiple access—the decoder will access multiple cells. APRIL–JUNE 1997 27 . them detectable via a read operation in the RAM. Open defects in NMOS address decoders logic gate remains active. the depletion-mode load transistor SA1 fault. Finally. the output is active (logic 0) only if all the gate’s inputs are high. we propose test and testability strategies for their detection. researchers did not reevaluate the prevailing assumption’s tive state in the same manner. resulting in a multiple-access fault. which we can test it should be active. march tests cannot ensure the detection of these open defects. Figure 1. if there is an open defect in the load transistor. researchers paid implementations. As the technology changed to CMOS. In other words. An open defect in an NMOS logic gate’s terms.

The second observation shows that cell C is sensitive only when address bits A5. The figure shows three SRAM cells. In our experiment. Furthermore. cannot detect the fault. the failure occurs. and the 28 other three bits select the column (or bit) line. 2. Furthermore. showing the matrix and the word-line and column decoders. For a DRAM process. All of these characteristics make present and future CMOS RAMs especially vulnerable to open defects. Cell C yields a read failure when address bits A5. 4. the association expects the contact/via aspect ratio to become 10. The read operation on cell C yields the wrong data value only if certain address bits (A5. Address bits A7–A3 decode the word lines. According to the Semiconductor Industry Association’s semiconductor technology roadmap. The corresponding word line controls cell C. and A3 remain unchanged.5:1 for a typical DRAM process. it overwrites cell C as well. The third observation strengthens the implications of the first. Different bits of a word are not close to each other. If any of these bits changes. It diagrams part of an embedded SRAM. Failure and analysis Figure 2 helps explain the undetected faults in address decoders. 5. The SRAM address space is 8 bits wide (256 addresses) and has a word size of 8 bits. we made the following observations: 1. RAM matrix 00110 B 10110 C Figure 2. In other words. the increase means that in future CMOS devices in general. and C. 2. which is wrong. the RAM behaves normally. B. 00110 111. it appears that enabling cell B after accessing cell C somehow also enables (or does not disable) cell C. used in the SRAM’s original testing.8 the contact/via height-width aspect ratio is 4. and 10110 111. low-resistance contacts. The 6N march test algorithm. On the basis of the first observation. increasing the sensitivity to open defects. Observation: None of the address inputs A3. A4. Consider a situation in which an operation enables word lines B and C. so there is no possibility of intraword coupling faults.5:1. Write A (00100 111) with logic 0. A4. not all cells in the column are capable of introducing a fault in cell C. and DRAMs in particular. In future DRAM generations. 3. which is correct. and writing in cell C does not affect the contents of other cells in any manner. A. There are two possible explanations for all the symptoms and subsequent observations: 1) Enabling cell B’s word line enables cell C’s word line. Read C: result is logic 0. Therefore. or 2) enabling cell B does not dis- IEEE DESIGN & TEST OF COMPUTERS . Write B (00110 111) with logic 0. it is 2. a subsequent read operation on cell C results in a read failure. A missing contact or via is a dominant source of open defects in CMOS technology. Hence. RAM ADDRESS DECODERS A2 A1 A0 Column decoder 111 A7 A6 A5 A4 A3 Word-line decoder 00100 1. A4. Write C (10110 111) with logic 1. and A3 have not changed. 3. Read C: result is logic 1. and A3) remain unchanged between write and read operations to cell C. A4. most contact locations have no room for multiple contacts.5:1 and the logic aspect ratio to become 6. for which the addresses (A7–A0) are 00100 111. it will be much harder to make good. The fault causes only the read failure in cell C. The failure does not write data into another cell. From the failure symptoms and further tests. Analysis. or A5 have changed. producing the following observed symptoms: 4.8 Effectively. If a write operation writes data complementary to the contents of cell C into cell B.. Cell C failed conditionally. for a typical logic process. A failure in an embedded SRAM. the contact depth is much higher than in a logic process. All three cells have the same column address (111). the fault is completely data independent.2:1. it seems to be a read-only error. A Observation: Address input A4 has changed. DRAMs require the tightest metal pitch and the highest packing density. The projected increase in aspect ratio is a compromise to alleviate the large increase in per-unit interconnect resistance and to prevent cross talk. the read operation to cell C yields the expected data value.

such an ocWL23 currence could result from a Cell C WL30 decoder design error or a low-resistance bridging fault WL22 10110 between the word lines of A5 cells B and C.the fault will not become active. However.. Our analysis demonstrated that the transistor had a stucktor with A7 as its input is disconnected from VDD. such a deOpen defect WL08 fect is a typical case of a decoder fault mapped onto WL00 the matrix coupling fault. writes logic 1 in each RAM cell in ascending address order.A4 Cell A tions. the second possi. A periodic timing signal. ticular word line. A4. Now. all high logic inputs put n-chan. Why doesn’t the popular and time-tested the word line corresponding to cell C. by selecting erate true and complement values. the transistor cannot pull the word line high (disable it) The binary address following word line C (address 10110) is 29 . In a decoder ing contact between source (or drain) diffusion and metal consisting of NAND gates. The Bit line Bit line WL31 first possibility is very un. Word-line decoder. A5 To understand that arguA7 ment. Now. March 1 reads the initialized value and paths has an open defect in the transistor’s source or drain. The first step initializes the RAM (depending on the fan-in of the NAND gate). A missduce the same results with the defect on cell C. The figure does not show the word-line drivers and input buffers. A4 Therefore. the dis. if an operation accesses cell A after cell C.1 is the most likely cause. A5.Phix bility is the likely cause.6N SRAM march test detect this fault? Figure 4 (next page) abling on that particular path can occur through four paths illustrates the 6N algorithm. A6 Output which would be detected by A3 the 6N march test algorithm.word line through the faulty path (for example.A3 tional. We can rule out a decoder design error. Moreover. consider Figure 3. a read operation to cell C. if we repeat our earlier experiment. Another possibility is an open denel transistors in conduction fault caused by a missing source-to-VDD contact. A3 and 0 on A6 select Why tests fail. Therefore. If one of the with logic 0. Cell B WL14 since this would cause a large number of devices to WL06 00110 fail under the test condi. results in deforms the third input to the NOR gates. The NOR gate out. Let’s assume for a moment that the NAND gate in cell C’s NAND gate can disable the corresponding word line. The buffered address bits gen. with RAM cells and the defective NAND gate. a quires the help of the four-input NAND gates. However. APRIL–JUNE 1997 111 111 able cell C’s word line. write operation to another selected cell also writes to cell the three-input NOR gates decode the outputs of the NAND C.A7 likely. since WL04 00100 the fault would be bidirec.fect in the metalization layer. depending on the origgates with address bit A6. which illustrates part of the word-line address-decoding Figure 3.cell B). Address decoding re. phix. If a read/write operation disables the decoder has a 5-bit address. it selects two cells at the same time. The low-resistance WL12 bridging fault explanation also seems unlikely. For example. hence enabling the par. Next. another parallel p-channel path in the faulty puts are buffered to drive the word lines. However. The word-line through that path.tection of a fault. Subsequently. 1111 on A7. inal stored data value and new data value. and word-line decoder has an open defect: a p-channel transis. we easily see that we can pro. logic and corresponding bit lines.

Such defects are generic to decoders implemented with static CMOS logic gates.W(0). Similarly. the basic assumption that under faulty conditions address decoders remain combinational is untrue. it effectively causes an IEEE DESIGN & TEST OF COMPUTERS . which modifies the A3 bit. at least one RAM cell cannot be addressed and therefore appears to have a stuck-at fault. they may result in sequential behavior. To determine which open defects these are and devise a test only for them.R(0) R(0). RAM address decoder testing is becoming a quality and economics issue. open defects in an address decoder occur either between or inside logic gates. For example. we usually choose either an ascending or a descending address.W(1) R(1).R(0) Figure 4. Arguably. If an intragate open defect disconnects all paths between the output and VDD (or VSS). In other words.. March 2 proceeds in descending address order. WL63 A10 WL62 A9 2 WL61 WL60 A8 3 A7 1 A6 4 WL03 WL02 meet this condition and so are not detected by march tests. As a result. A march test may use any address order. These defects cause a break in an interconnect line. It must remain activated until a read operation to the cell detects it. Address bit A11 determines the selected quadrant. disabling word line C as in a fault-free case (Figure 3). The 6N SRAM march test algorithm. which modifies the A4 and A3 bits. In other words. complex algorithms for neighborhood patternsensitive faults cannot ensure open-fault detection in decoders. Shading indicates faults the 6N algorithm cannot detect. A typical word-line address decoder.W(1) R(1). companies are making significant efforts to reduce RAM matrix test costs by using parallel test techniques. no addressing sequence is likely to detect all open defects in an address decoder. however. as long as it accesses all addresses. Then. parallel techniques test for address decoder faults less vigorously. Furthermore.9. March 1 neither activates nor detects the fault. Instead of four-input NAND gates. WL01 A5 WL00 Phix A11 Figure 5. Generally. most open defects in NAND gates do not 30 Proposed test procedure March tests fail to detect only a subset of all open defects in an address decoder. and periodic timing signal phix controls the timing of the word-line decoder. no linear test algorithm will detect such defects because they change the address decoder into a faulty sequential circuit usually requiring a two-pattern test: fault sensitizing and evaluation. As a result. As a result. The decoder decodes a 6-bit address (A10–A5) to 64 word lines. RAM test algorithms other than march tests are also unlikely to detect these defects because they do not ensure a two-pattern test sequence for all potential defects. intragate open defects (defects 3 and 4) are difficult to detect because they may influence only a single transistor. The doubleheaded arrow indicates that the same operation is repeated over the entire address space (0 → N − 1). A march test (or a linear algorithm) can detect this type of fault only if the next word-line address activates the fault in at least one march direction. depending on the original and overwritten data values.W(0).10 Unfortunately. a Galpat (galloping pattern) algorithm2 of complexity O(n2) will detect these defects. applying this algorithm even for moderate-size RAMs is impossible due to its excessively long test time.W(0). In decoders implemented with dynamic logic (or NMOS). Hence. and march tests such as the 6N algorithm detect their effects. For simplicity. RAM ADDRESS DECODERS Address 0 1 Initialize March 1 March 2 R(1). the next word-line address is 10101. However. intergate open defects do not cause sequential behavior.W(1) Wr(0) Wr(0) R(0). these faulty conditions may not arise. word line C becomes disabled once again. After word line C activates.6 Thus. However. and the fault goes undetected. 10111. a march test can detect the defect. However. Defects 1 and 2 in Figure 5 exemplify the intergate class. March 2 does not detect the fault.R(0) N−1 Wr(0) R(0). Instead. we consider the embedded-RAM row decoder shown in Figure 5. this decoder uses 32 five-input NAND gates. In general. as well as 64 two-input NOR gates to further decode the sixth bit (A5).

The situation becomes grave as the number of inputs to a gate rises to three or more. To test for the hard-to-detect opens. and the number of word lines is 2m. A10–A6 = 00001. The following is an algorithm for testing the address decoder in Figure 5: Column_address = 0 For i = 0 to 2(m−1) Do Base_address = 2 ∗ i Write “0” to Base_address For j = 0 to M Do Write_address = Base_address XORbinary 2j Write “1” to Write_address Read “0” from Base_address End For End For This algorithm executes the inner loop m−1 times for each i and consists of one write and one read operation. Next. keep A5 = 0 and A11 (if available) = 0 Let A10–A6 = 00000. Let’s assume that defect 3 causes a disconnection from VSS of an n-channel transistor in a two-input NOR gate. Layout measures: DFT. Write(1). we apply the following test sequence for the five-input NAND gate (shaded) containing defect 4 in Figure 5: APRIL–JUNE 1997 Keep Y decoder address constant. Supplementary test algorithm. We appended a small loop to the 6N algorithm to detect the hard-to-detect address decoder stuck-open faults. if it disconnects only one path between the output and VDD (or VSS). Therefore. However. Let’s assume that m is the number of input bits of the wordline decoder. A10–A6 = 00000. Using the reasoning of the previous section. address bit A11 and the decoded A10–A5 bits should change in Gray code manner. There is only one other n-channel transistor in parallel to the defective transistor. it is possible to develop an algorithm for a given address decoder that can supplement any RAM test algorithm. A10–A6 = 00100. A subsequent read operation to cell D will detect a read failure and hence the open defect. we can select any arbitrary column address for read and write operations. we can conclude that a march test does not guarantee detection of all open defects in a logic gate with three or more inputs. this loop is specific to address decoders and is independent of the 6N march test algorithm. In the algorithmic description.576 read or write operations. The decoder’s 32 NAND gates give rise to at least 96 potentially undetected defects. In this example. bit A5) is a don’t care and remains 0 during the test. Then. we change the word-line address such that only one address bit changes (say A6). To test the row-decoding logic. either the ascending March 1 or the descending March 2 will detect the defect. This allows a particular p-channel transistor in the NAND gate to disable that NAND gate. However. The least significant bit (in Figure 5. at least three open defects in each five-input NAND gate will escape detection (the other two will be detected by descending or ascending march elements). we consider a RAM with 6 bits devoted to column decoding and another 6 bits to word-line decoding. we must test the NAND gates in the decoding logic sequentially. we devised a test solution. Read(1). A10–A6 = 00010. depending on which transistor is faulty. output SA0 (or SA1) fault and is detected by the march test. Read(1). Read(1). Layout improvement is probably the simplest and most effective way to reduce the oc- 31 . Write(0). For example. Write(0). The 6N algorithm performs 6 × 212 = 24. A condition of this detection is that the inputs to the faulty gate must change in Gray code manner—that is. This makes the algorithm’s total complexity (2m−1) × 2(m−1) read or write operations. In this case. We can expect that similar open defects in the column decoder and the block decoder (Z) also cause hard-todetect faults. In the following algorithm. it causes sequential behavior. In general. we set the column address to 0. A10–A6 = 00000. We repeat this procedure for all address bits to NAND gates and for all NAND gates. Read(1). This algorithm performs only 11 × 25 = 352 read or write operations. For each NAND gate. If the p-channel transistor has an open defect. so it can be added to any other march or linear test algorithm. A10–A6 = 01000. A10–A6 = 00000. To compare this algorithm’s complexity with that of the 6N algorithm. A10–A6 = 10000.. Write(0). A10–A6 = 00000. Write(0). we write a logic 1 to the new address location (say E). the address values in the read and write operations correspond to the binary code at the word-line decoder’s input bits (A10–A5). Once we knew of all likely fault detection escapes. only one input should change at a time. So the additional test complexity is less than 2% that of the 6N test. the corresponding word line (remember that bit A5 is set to 0) writes a logic 0 to the selected cell (say D). cell D is still enabled and the write operation to cell E can also overwrite the content of cell D. We can analyze these decoders and devise similar test algorithms for them. The main loop executes 2(m−1) times and takes one extra write operation. A10–A6 = 00000. Read(1). Write(0).

can reduce the occurrence of open defects in sensitive decoder locations. Therefore. This transformation is similar to one proposed by Levitt and Abraham. simple layout modifications can ease test generation. which activates the word-line address.. but they cannot eliminate their occurrence completely. We also add a corresponding n-channel transistor to avoid logical conflicts and effectively make the gate a six-input NAND gate. This transistor provides an alternative path for word-line disabling by disabling all NAND gates before application of a new address. we propose using logical measures to build fault tolerance into key decoder locations. the number of hard-to-detect faults decreases drastically. Circuit layout greatly affects testability. currence of hard-to-detect open defects. By fault tolerance we mean that the decoder as well as the RAM functions correctly in spite of a defect. Layout transformation for open-defect testability of a four-input NAND gate: original (a) and modified layout (b). The p-channel network provides the disabling paths to the word lines (since a particular word line is selected if and only if the corresponding NAND gate’s output is logic 0).12 Logical measures: fault tolerance.12 In the unmodified layout. Building in fault tolerance has not changed the decoder’s logical function. we can add an extra p-channel transistor in each five-input NAND gate. The inputs of these transistors are driven by the phix timing signal. Although the transformed gate’s area and delay may increase fractionally. A row decoder with built-in fault tolerance against hard-to-detect open defects. the p-channel transistor selects no word line. For example. WL63 A10 WL62 A9 WL61 WL60 A8 A7 WL03 A6 WL02 WL01 WL00 A5 Phix A11 Figure 7. Figure 7 illustrates the concept of logical measures. By preventing hard-to-detect faults. The literature documents these layout techniques well. We can optimize the design for correct tim- IEEE DESIGN & TEST OF COMPUTERS . This diagram is the same as Figure 5 except for the shaded areas. and an additional net (the broken line). The decoder needs the extra inverter to invert the timing signal. A simple test may not detect such an open defect.12 Future RAM decoder designs will require such layout techniques for two 32 reasons: 1) Manufacturers test decoder circuitry implicitly by testing only the matrix. phix now controls the address decoder’s timing through address bits A10–A6 instead of A5 and A11 (see Figure 4). placing multiple contacts at hard-to-detect defect locations (parallel transistors) in the decoder will make these locations robust against open defects. RAM ADDRESS DECODERS VDD A A B B C C D D VSS (a) (b) Diffusion Poly Contact Metal Figure 6. Effectively. Figure 6 shows the modification of a four-input NAND gate. Thus. In other words. A decoder using five-input NOR gates instead of NAND gates doesn’t need the extra inverter. Therefore. an open at a contact can occur at any branch of a set of parallel transistors or metal line. an inverter. the transformation results in a robust layout as well as simpler test generation for open defects. in principle. and all the parallel branches must be tested separately. we conclude that opens affecting only single p-channel transistors in five-input NAND gates are hard to detect. Together with layout transformations. Layout techniques.11. From our earlier reasoning. 2) They often test RAMs with march algorithms that restrict decoder excitation so as to cover the fault model in only a few operations. We can assume that the probability of an open defect due to a poor contact is greater than the probability of an open defect due to a break in diffusion. The figure shows the modified NAND gates as shaded. fault tolerance also enhances the decoder’s robustness.

J. John Wiley & Sons.J. and DFT techniques for analog and digital circuits. Yervant Zorian. Y. Japan. Prof. India. “Optimal Layout to Avoid CMOS Stuck-Open Faults.. pp. Los Alamitos.V. 191-202. ONLINE TEST Academic Research and Industrial Needs: How Do They Correlate? The growing complexity of electronic systems has produced increasing reliability needs in various application domains. S. The National Technology Roadmap for Ravi Iyer. For improved effectiveness. often implemented with march test algorithms. “Design of CMOS Circuits for Stuck-Open Fault Testability.” IEEE J. References 1. IEEE CS Press. He has written several technical papers for conferences and journals.” J. 3.. 1991. “Physical Design of Testable VLSI: Techniques and Experiments. Philips Research Laboratories. Abraham.” Proc.E. 6. and his PhD from Brunel University. 322-326. 8. Int’l Test Conf. “Development of a Fault Model and Test Algorithms for Embedded DRAMs. No. Testing Semiconductor Memories. Built-in self-test is an efficient methodology for testing RAMs. pp. working on various aspects of IC design. 10. Semiconductor Industry Association. 2. Sachdev received his BE in electronics and communication engineering from the University of Roorkee. He holds 12 granted and pending patents in VLSI design and test. Thijssen. France. 12. Sachdev and M. 58-61.P. of Technology.. Nanya.” Proc. “A New Array Architecture for Parallel Testing in VLSI Memories. F. Calif. 18:10-19:30 Check time and room number at registration. 6.” Proc. 1990. Jain and V. M. Koeppe. No.” Proc. R. Apr. Electronic Testing: Theory and Applications (JETTA). Y. “Fault Modeling and Test Algorithm Development for Static Random Access Memories. Publication 232. The Netherlands. IEEE CS Press. sachdev@natlab. Beenker. Levitt and J. LogicVision. M. boards. van de Goor.. European Conf. IEEE Third International On-Line Test Workshop The workshop and IEEE Design & Test of Computers coorganized the panel. logical modifications reduce the shaded three-input NOR gates to two-input NOR gates. San Jose. pp. pp. A. to discuss these issues.. Dekker. Vol. 33 . 474-481. Piscataway. Tokyo Inst. 1993. 5656 AA Eindhoven. IEEE Computer Society Press.A. Rajsuman. USA. His responsibilities and research interests include defect and fault modeling. Chakrabourty.D. S. A. 11.. research.” IEEE J. IEEE CS Press. Electronic Design Automation. UK. 343-352. pp. This has created a corresponding demand for viable online test solutions for use in chips.A. 65-70. Malaiya.M. IEEE.. 5. 2. Fault-Tolerant Computing. WAY 41. and systems. Holstlaan 4. Jan. USA.. ICS AND SYSTEMS ARE BECOMING increasingly complex and RAM intensive. “Testing of Semiconductor Random Access Memories. pp. Nicolaidis. S. Eindhoven. New York. “Test Generation for MOS Circuits Using D-Algorithm.. This panel will provide an informal forum to address today’s industrial needs for online test solutions and to compare their overlap with the ongoing research in online test in the academic domain. RAM testing procedures must focus on likely manufacturing defects. 24th Design Automation Conf. pp. 94-99. 1983. 7. 9. memory testing. pp.K. A panel will meet this July at the IEEE Third International Online Test Workshop in Aghia Pelaghia Headland. 4. 815-824. 1988. IEEE CS Press. Theory and Practice. 171-173. Verstraelen. Furthermore. 81-87. and T. 829-835. 26. 2. pp.K. 25. Lucent Technologies. We cannot meet IC quality and system reliability requirements without adequately testing RAMs. 1997. 1995. Vol. SolidState Circuits. pp. TIMA. University of Illinois. pp. 1977. 1987. ing without sacrificing the gains achieved through logical measures. IEEE CS Press. Agrawal. APRIL–JUNE 1997 Address questions or comments about this article to Manoj Sachdev. Sachdev. he was with SCL in India and SGS-Thomson in Italy. 20th Design Automation Conf. and L. 1. and R. Solid-State Circuits. Calif. Greece. Vol.” Proc.” Proc. Apr. Int’l Conf. IEEE Int’l Test Conf. Abraham. No.” Proc. 1989. the Netherlands. “Reducing the CMOS RAM Test Complexity with Voltage and IDDQ Testing. M. Thatte and J. “Computation of the Critical Area in Semiconductor Yield Theory. Matasuda et al. will lead the discussions with panel members T. He is a senior member of the IEEE. M. Jayasumana. A. these algorithms must take into account the schematic characteristics of address decoders. Join us July 7. Previously. using both testing and DFT strategies. 1984. Manoj Sachdev is a scientific staff member in the VLSI Design Automation and Test Group at Philips Research Laboratories. IEEE Int’l Test Conf. 1994.. 1991. Ferris-Prabhu. N.