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Electrical Characterisation of Novel

Silicon MOSFETs and finFETs.

By

Stephen Michael Thomas

Thesis
Submitted to the University of Warwick
for the degree of
Doctor of Philosophy

Department of Physics
April 2011

Contents
List of Tables........................................................................................................ viii
List of Figures ......................................................................................................... x
Acknowledgements .............................................................................................. xxi
Declaration .......................................................................................................... xxii
Publications ........................................................................................................ xxiii
Abstract ............................................................................................................... xxv
List of Symbols .................................................................................................. xxvi
Abbreviations and Acronyms............................................................................. xxxi
Chapter 1 : Introduction .............................................................................................. 1
1.1

Semiconductor industry .............................................................................. 1

1.1.1 Silicon ........................................................................................................ 2
1.2 CMOS scaling ................................................................................................... 2
1.2.1 Constant field/Dennard scaling .................................................................. 2
1.2.2 Departure from constant field scaling ........................................................ 3
1.2.3 SOI ............................................................................................................. 5
1.2.4 Multi-gate transistors – the finFET ............................................................ 6
1.3 Current investigation......................................................................................... 8
Chapter 2 : Theoretical Considerations..................................................................... 10
2.1 The MOS capacitor ......................................................................................... 10
2.2 The metal-oxide-semiconductor-field-effect-transistor .................................. 15
2.2.1 On state .................................................................................................... 16
2.2.2 Off state.................................................................................................... 19
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2.3 Si band structure.............................................................................................. 20
2.3.1 Conduction band ...................................................................................... 20
2.3.2 Valence band............................................................................................ 22
2.4 Carriers in the MOSFET inversion layer ........................................................ 22
2.4.1 Confinement............................................................................................. 23
2.5 Carrier scattering in the inversion layer .......................................................... 31
2.5.1 Scattering theory ...................................................................................... 33
2.5.2 Local Coulomb scattering (LCS) ............................................................. 35
2.5.3 Local roughness scattering (LRS)............................................................ 37
2.5.4 Ionised impurity scattering (IIS) .............................................................. 39
2.5.5 Screening.................................................................................................. 40
2.6 MOS dielectrics............................................................................................... 41
2.6.1 Origin of permittivity ............................................................................... 41
2.6.2 Dielectric requirements ............................................................................ 43
2.6.3 Capacitance of high-κ dielectrics ............................................................. 45
2.6.4 Hafnium based dielectrics ........................................................................ 46
2.6.5 High-κ mobility degradation .................................................................... 48
2.7 Gate electrode.................................................................................................. 51
2.8 The short channel effect .................................................................................. 53
2.9 Silicon on insulator (SOI) technology ............................................................ 55
2.10 Multiple gate technology .............................................................................. 58
2.10.1 Channel control ...................................................................................... 58
2.10.2 The finFET ............................................................................................. 59

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2.10.3 FinFETs in inversion.............................................................................. 60
2.10.4 Confinement effects on Vt...................................................................... 64
2.10.5 Carrier mobility in finFETs.................................................................... 64
2.10.6 Fin access resistance .............................................................................. 67
Chapter 3 : Electrical Characterisation Techniques .................................................. 68
3.1 Measurement apparatus................................................................................... 68
3.2 Current-voltage measurements ....................................................................... 70
3.3 Capacitance-voltage measurements ................................................................ 71
3.3.1 Capacitance-voltage profile ..................................................................... 76
3.3.2 Split C-V .................................................................................................. 78
3.4 Extraction techniques ...................................................................................... 81
3.4.1 Interface trap density................................................................................ 81
3.4.2 Flat-band voltage...................................................................................... 87
3.4.3 Inversion charge, depletion charge and vertical field .............................. 88
3.4.4 Doping profile .......................................................................................... 90
3.4.5 Drain current correction in the presence of significant gate leakage current
........................................................................................................................... 91
3.4.6 Threshold voltage..................................................................................... 92
3.4.7 Source-drain resistance ............................................................................ 94
Chapter 4 : Improved Mobility Extraction in MOSFETs ......................................... 96
4.1 Introduction ..................................................................................................... 96
4.2 Conventional extraction .................................................................................. 96
4.3 Improved extraction- bulk MOSFET .............................................................. 98

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................. 130 5.........5 Experimental application to an SOI MOSFET ...4............................................................................ 117 5...2 Threshold voltage.....3 Sub-threshold slope.2..............................6 Summary ....4.........1 Ex-field and diffusion correction....................................... 106 4............................................... 120 5....3 µeff extraction.............................................. 128 5.........1 Transconductance.....................3....................................... 102 4...........................................................................................................5...............Vgs ................ 117 5.............................................3......3.........1 Device layout ........................................... 131 5.................. 132 5...............2 Cgc ..........Vgs ...................................................5......................................................................4 Mobility extraction in SOI MOSFETs and finFETs ............................... 119 5........... 133 5..........2 Device overview..5 p-MOSFET current – voltage measurements............5...................... 120 5....................................................3 Substrate doping profiles.......2 Finite drain bias correction.... 98 4.............. 106 4.................. 99 4................................4 Extraction of Rsd and ∆L........................................6 n-MOSFET current-voltage measurements ........... 116 Chapter 5 : Si MOSFETs on (100) and (110) orientated substrates ..............................................3..................................1 Diffusion and Ex-field correction ..3.................................................1 Introduction ..... 127 5................................................. 105 4....................................................... 110 4..1 Id .............5................ 118 5....................................... 134 v .................................................. 125 5...........................................1 Split CV...........................................................................2 Flat-band voltage and interface trap density .................................5................................................................................................................................ 101 4.......3 Capacitance – voltage measurements.....5.................

.............7...................................................................3 Sub-threshold slope...................................................................................6...........7........................... 168 6............ 172 6...................7........................ 165 6.3 p-MOSFETs – Variation of hole µeff with orientation .5.........................................4 Volume or surface inversion .......................................... 148 5........2 p-finFETs ........... 161 Chapter 6 : Si finFETs with high-κ dielectrics and metal gates.................. 141 5................ 136 5..................................5....................................5 300 K effective mobility ........................7........7 Effective mobility...1 Introduction ..................6....4 p-MOSFETs – Variation of hole µeff with Eeff/Ninv.....................................................................................9 Summary .....................................................................5..1 Transconductance...................................................................................................3.................. 165 6...............................6 Strain characterisation...........................2 Device overview...................................7.1 n-finFETs .1 n-MOSFETS ..............................................................2 n-MOSFETs – Variation of µeff with Eeff ...................... 138 5..............................3 Gate – channel capacitance and threshold voltage.............. 135 5...........................5 Improved effective mass calculation and 300 K hole µeff analysis ....................................................................1 n-finFETs .............................Variation of µeff with channel direction and surface orientation .............. 174 vi ................ 167 6.................. 137 5.............................................................................................. 162 6...............................................6........................... 147 5.. 169 6........................................ 169 6....... 162 6... 139 5.............. 162 6..........8 4 K effective mobility modelling ....................2 p-finFETs ................................................................................2 Threshold voltage............................3......... 144 5. 152 5..............................................................

..9 Summary ..............................................3 Chapter 6 ................ 192 7.................................. 179 6...... 192 7......................................... 179 6..............................7............ 198 vii ............... 181 6..............7................................................................................................................................................................................................................................................................................. 190 Chapter 7 : Conclusion................................................................................................................................. 193 7......................6.....................................1 Chapter 4 ........2 Chapter 5 ..........................................................8 4 K modelling of quasi-planar finFETs ............................. 183 6..................................... 194 7............. 196 Bibliography.............................................................................................2 p-finFETs ............................4 Further work.7 4 K effective mobility ................................................................................................1 n-finFETs ...........

................... 144 Table 5........................... Total resistance.................... 125 Table 5......................................... ............. Ctot is the total capacitance of the device which is composed of the gate oxide capacitance and source/drain junction and parasitic capacitances (adapted from [2]) ..7 µm MOSFETs in strong inversion............... Vfb is accurate to within 50 mV............................... The scaling factors are derived from constant field scaling.1 MOSFET scaling parameters..................2 Summary of Rsd and ∆L for the n............. 139 Table 5.List of Tables Table 1........... 3 Table 2.....and p-MOSFETs on (100) and (110) orientations................. Since Vgs was incremented in 50 mV steps...3 Electron effective masses for the (100) and (110) orientations ................ 129 Table 5......................................... 145 Table 5. 159 viii .. 30 Table 5..................... 154 Table 5.....5 Effective masses calculated by 4 band k•p for the HH sub-band (calculated by Dr Jeremy Watling).. No values for (110)/<100> and <110> have been reported .........................1 Electron effective masses[22-23]. The key metric for MOSFET performance is the intrinsic delay time..................................7 Fitting parameters used in the modelling of (100) electron and hole 4 K µeff............................... 27 Table 2...............4 Literature values of hole effective masses calculated at k = 0................................and p-MOSFETs on (100) and (110) wafers...... R is for the OA 25 µm x 4.....................................1 Flat-band voltages for n.................................................................................................2 HH and LH effective masses of Si................6 4 K effective masses used in the modeling of 4 K hole µeff.........

.........................................................1 Parameters used in the mobility modelling of quasi planar n........... 186 ix ................................................................................... 160 Table 6......................................................Table 5..and pfinFETs..8 Fitting parameters used in the modelling of (110)/<100> and <110> 4 K hole µeff ...........

......................................... .............. .....1 Schematic of a finFET............. EMA: constant Effective Mass Approximation (sourced from [24])28 Figure 2............................................................................................................................................5 Constant energy surfaces of the Si conduction minima in the (110) plane........ ...........8 Constant energy surfaces of the lowest lying HH................... 15 Figure 2....... (sourced from [24])...... 26 Figure 2.......................................10 Charged interface states in strong inversion for a (a) p-MOSFET and an (b) n-MOSFET ..... 27 Figure 2. LH and SO sub-bands in the (100) and (110) surface orientations................................ 13 Figure 2................................ This novel 3D transistor is usually fabricated on an SOI substrate...................... 7 Figure 2................................... 28 Figure 2....... 30 Figure 2................ 21 Figure 2.............9 Elastic scattering event where k = k' (sourced from [39]).......................1a) n-MOS capacitor in accumulation and b) inversion..................................6 Conduction band E-k relation showing the non-parabolicity in the [110] direction.............................................................7a) Energy splitting of the ∆2 and ∆4 sub-bands b) Ground ∆2 sub-band energy as a function of inversion charge density (Ns in this figure)........... 34 Figure 2......... (adapted from [29]).........................2 n-MOSFET schematic showing the electrical connections ...............3 Constant energy surfaces of the conduction band minima ..... 36 x ............................4 Constant energy surfaces of the Si conduction minima in the (100) plane..List of Figures Figure 1.....

............. 44 Figure 2................... .......... 61 Figure 2.... (adapted from [104]) ......................................... (sourced from [50])....... ψ(z) in square..................... 43 Figure 2................. 57 Figure 2.....13 Static and high frequency dielectric constant of Hf1-xSixO2 as a function of x.... extracted from the Clausius-Mossotti relation (adapted from [53]) ................. The electron concentration is proportional to ψ(z)2.....15 Cross section of a fully depleted double-gate MOSFET..........11 Conduction and valence band offsets of various dielectrics with respect to Si band-gap... increases with decreasing Wfin...........12 Band-gap energy as a function permittivity for a range of dielectrics [48]... the potential at the middle of the fin.................. weak parabolic and strong parabolic potential wells formed by the two dielectric interfaces and conduction band edge in a double gate finFET.......................... ψc ............................................... Note sub-wells are created at both interfaces in the strong parabolic case.......... The band diagram of a bulk n-MOSFET is shown for comparison................... 59 Figure 2.......... increasing the electron concentration throughout the fin.............................................. 63 xi ...17 Four first energy levels and two first wave functions. ...................................16 Energy-band diagram of two double-gate n-finFETs of different Wfin in inversion (Vgs > 0 V applied to both gates).................................................................................................. confining the lowest energy states...... .......... 47 Figure 2. The electric fields (arrows) and corresponding depletion charges from both gates and the source and drain are shown..................Figure 2.................. ............................14 Charge distribution in long and short channel bulk and FDSOI MOSFETs......

7:Gate-channel and gate-body split CV profiles for an n-MOSFET........2 Parasitic resistance in series with the parallel equivalent circuit.............................................................................. 86 xii ..................... The microcontroller calculates C and G from Ic’ and Ip’ respectively........................................... G = 0 for an ideal capacitor and θ = 90°. The 90° phase separator then splits the current I into Ic’ and Ip’...... 75 Figure 3...................................... AC and DC voltages applied by the “high terminal” and resulting current.................................... Cit........................4: Equivalent circuit of a MOSFET Cox.............. 84 Figure 3. 76 Figure 3. 79 Figure 3.. Cit2 is the interface trap capacitance at the Si/BOX interface and CBOX is the buried oxide capacitance..................5: CV profile of a n-MOSFET.... depletion..........Figure 3..................6 Electrical connections to measure the split CV of a MOSFET....................... measured by the “low terminal”....... A: accumulation. ......... 79 Figure 3...... Cdep..... accumulation........... . I.. A thick box (small CBOX) ensures a near ideal sub-threshold slope. 72 Figure 3........................ interface trap and inversion capacitances respectively...9 Comparison of the equivalent circuits of a a) bulk and b) FDSOI MOSFET........1: Operation of the LCR meter modelling the MOSFET as a capacitor in parallel with a resistor..... B: depletion and C: inversion........ Cinv are the dielectric (oxide)..........8a) Equivalent circuit of a MOSFET in depletion including an interface trap of time constant τit = RitCit b) parallel equivalent circuit .. 74 Figure 3..3: Phasor diagram of the admittance of the parallel equivalent circuit.. Cacc............... 77 Figure 3..........................................................

........................................................ approximately half the gate current flows from the source and half from the drain..... 92 Figure 4..6 Threshold voltage extracted from the max slope of transconductance measured as a function of drain bias . 106 Figure 4.Figure 3........................................ Below 10 kHz measurement noise was unacceptably high.........................................................5 Extracted mobility at 300 K showing the effect of increasing drain bias from 10 mV to 100 mV..... b) Corresponding phase angles........................................................................................................................................... For small Vds..................................3 Gate-channel capacitance measured at 100 kHz and calculated inversion charge density............................................................................................ 110 Figure 4.......................... 109 Figure 4.1 a) Gate leakage correction Idm and Ig are the measured drain current and gate leakage currents b) Corrected drain current data for a range of drain biases at 300 K ....... 107 Figure 4..............................8 Variation of drain current with drain bias in strong inversion from which the zero bias conductance can be extrapolated .....4 Effect of subtracting the offset capacitance on effective mobility extraction....................................................... 111 Figure 4.......................................... 113 xiii .................... gate current Ig and the measured drain current Idm.......2 a) Gate-channel capacitance for measurement frequencies in the range 10 kHz – 1 MHz.........................................10 MOSFET cross section showing the true drain current Id..........................9 300 K mobility showing the effect of the various corrections................ 112 Figure 4... 109 Figure 4.............. 112 Figure 4.............................7 Semi-log variation of drain conductance with drain bias in the subthreshold region enabling the zero bias conductance to be extracted as the intercept.

...... 125 xiv .......7 µm (100) p-MOSFETs ................................. 121 Figure 5..............11 Id/Vds in strong inversion at 4 K ......................10 4 K extracted mobility showing the effect of increasing drain bias from 10 mV to 100 mV..S.........1 a) Peak gm vs Vt b) S....................................... vs Vt measured on 10 µm x 10 µm p-MOSFETs across the (100) and (110) wafers........................... No frequency dispersion was observed in the 25 µm x 4...... Measurement noise was unacceptably high for frequencies below 10 kHz............ 114 Figure 4.............7 µm (100) n-MOSFETs................... The variation in peak gm is 5% and 10% for the (100) and (110) wafers indicating good uniformity............. 124 Figure 5.....7 µm n-MOSFET........ ....Figure 4....... b) Corresponding phase angles....................2 Cgc as a function of frequency for 100 µm x100 µm and 25 µm x 4...................................and n-MOSFETs on the (100) and (110) orientations ...............................12 4 K effective mobility showing the effect of the various corrections................................................. 123 Figure 5.................... ................. The drop at high Vgs is due to gate leakage current ..S..7 µm n-MOSFET.... 122 Figure 5.....................7 µm p-MOSFET included for comparison .......................... Cgc branch from 25 µm x 4..6 Split CV characteristics for the p..5 a) Split CV for the (100) 100 µm x 100 µm n-MOSFET and the Cgc branch for the 25 µm x 4............... 115 Figure 4................4 Cgc measured as a function of frequency for 100 µm x 100 µm and 25 µm x 4............ 120 Figure 5......................................... A more negative Vt is correlated to a smaller peak gm and higher S.....................................3 Split CV and phase angles for a (100) 100 µm x 100 µm p-MOSFET.... 115 Figure 5........ most probably due to a variation in Dit...

.............................and p-MOSFETs on (100) and (110) orientations............... 128 Figure 5................7 µm (100)/<100> and (110)/<100> n-MOSFETs..................... 135 Figure 5.. 134 Figure 5............................................. 131 Figure 5..........................................................................9a) Linear regressions (Vgt = Vgs ................................................................................................................................................7 µm (100) and (110) n-MOSFETs ......10 Linear Id vs Vgt characteristic for 25 µm x 4..................................7 µm (100) and (110) p-MOSFETs............................8 Extracted doping profiles for 100 µm x 100 µm n.................................. Shaded areas indicate regions close to flat-band where large round-off errors can occur due to the subtraction of high and low frequency capacitances..............7 µm (100) and (110) p-MOSFETs ..................................... 127 Figure 5...................7 µm (100) and (110) nMOSFETs ................ ....................................... 132 Figure 5........16 Vt vs channel direction/angle for 25 µm x 4.....7 µm (100) and (110) pMOSFETs ...................................................................................7 µm (100)/<100> and (110)/<110> p-MOSFETs...................Vt) and b) second regression to extract Rsd and ∆L for (100) p-MOSFETs................Figure 5.......................7 Dit extracted on 100 µm x 100 µm n.................. 133 Figure 5..............11 a) Peak gm vs channel direction/angle b) gm vs Vgt for 25 µm x 4...........15 a) Peak gm vs channel direction/angle b) gm vs Vgt for 25 µm x 4.....12 Vt vs channel direction/angle for 25 µm x 4..13 Sub-threshold slope vs channel direction/angle for 25 µm x 4... 137 xv ............. 136 Figure 5......and p-MOSFETs as a function of silicon band gap energy.14 Linear Id vs Vgt characteristic for 25 µm x 4................................. 129 Figure 5...........

..............7 µm (100) and (110) n-MOSFETs.................. (Calculations performed by Luca Donetti and Prof.1x1016 cm-3) is included for comparison b) Hole µeff vs Ninv......... one plot is shown as µeff is independent of channel direction............... For the (100) orientation... 149 xvi .. 143 Figure 5........ 143 Figure 5.........7 µm (100) and (110) p-MOSFETs...7 µm (100) and (110) n-MOSFETs.21a) Peak hole µeff and b) µeff at Ninv = 1x1013 cm-2/Eeff = 0................ These ratios show the same trend as Uchida et al......6 MVcm-1 vs channel direction/angle for 25 µm x 4..... mtran was calculated from an average over the k-plane for Ninv = 1x1013 cm-2........23 mtran in the HH sub-band as a function of channel direction on (100) and (110) orientations................... Note η = ⅓ is used in the calculation of Eeff.. ........19 Electron µeff vs Eeff extracted at 300 K and 4 K..............................Figure 5.........) ...................... 147 Figure 5......... Francisco Gamiz..........22a) Hole µeff vs Eeff........ Takagi et al.................6 MVcm-1 vs channel direction/angle for 25 µm x 4.................... 138 Figure 5.’s[154] (100)/<110> data (Nd = 5..’s data (Na = 1x1017 cm-3 for (110)[155] and 7.......................18a) Peak electron µeff and b) electron µeff at Eeff = 0....... 146 Figure 5..........[24].’s[119] (110)/<110> and <100> data (Nd ~ 1015 cm-3?) is included for comparison....... ...............................2x1016 cm-3 for (100)[154]) is included for comparison..... Note η = ⅓ is used in the calculation of Eeff. Takagi et al.......... ...20 Electron µeff <100>/µeff <110> vs Eeff at 300 K and 4 K on the (110) orientation.... 141 Figure 5...17 Sub-threshold slope vs channel direction/angle for 25 µm x 4........... Irie et al.............. The variation on the (110) orientation is comparable to the variation in the experimental µeff...............

........................ 156 Figure 5......... ............................................. 160 Figure 6...................25 mconf vs Eeff (calculations performed by Luca Donetti and Francisco Gamiz).......... LCS and LRS ......................24a) mtran in the HH sub-band as a function of Ninv The variation explains the difference in µeff between the (100) and (110) orientations b) mscat as a function of Ninv.. (calculations performed by Luca Donetti and Francisco Gamiz).................Figure 5............................ b) 4 K hole µeff vs Ninv ..........................30 Calculated µLRS as a function of Ninv for different values of ∆ and Λ for a (100) n-MOSFET ......... 300 K average doping concentration shown for comparison ..........................................1 Illustration of the patterned Si fins (10 in parallel) of a prospective finFET.......................................... fabricated on a BOX.......... 152 Figure 5.........33 Modelling of the 4 K (110)/<100> hole µeff in terms of IIS. 156 Figure 5.............................................29 Calculated µLCS as a function of Ninv for different values of nimp for a (100) n-MOSFET .......31 Modelling of the 4 K (100) electron µeff in terms of IIS............................................... 163 xvii ....... 160 Figure 5............................................................................ 159 Figure 5.............28 Doping profile extracted from CV at 4 K.................................................................. 152 Figure 5................26a) 4 K hole µeff vs Eeff.................... 153 Figure 5..................................................................... LCS and LRS .................................................... 154 Figure 5................................... LCS and LRS ...................32 Modelling of the 4 K (100) hole µeff in terms of IIS.................... 159 Figure 5.......27a) mtran as a function of Ninv b) mscat as a function of Ninv at 4 K .......................... 155 Figure 5...............................34 Modelling of the 4 K (110)/<110> hole µeff in terms of IIS.......................... LCS and LRS .......................................................

. ....... for p-finFETs with Wfin ranging from 1864 nm to 12 nm and L = 10 µm.......................................8 Hole µeff for Wfin ranging from 12 to 1866 nm...... 168 Figure 6..8x1015 cm-3)[155] bulk MOSFET data included for comparison.. for n-finFETs with Wfin ranging from 1872 nm to 16 nm and L = 10 µm... width and length directions...................... Vt is extracted from the maximum slope of gm............9x1015 cm-3) [154] and (110) (Na =2............................................................................ 173 Figure 6......... b) Corresponding CETs.... 170 Figure 6............... 166 Figure 6. Simulation is for the (110) sidewalls of a n-finFET at Ninv = 8x1012 cm-2........................ Simulation is for the (110) sidewalls of a pfinFET at Ninv = 8x1012 cm-2 (Simulations performed at DIEGM.............. Takagi et al.................................. 166 Figure 6..................... ........................ 167 Figure 6........4 Vt for n-finFETs with Wfin in the range 16 nm – 1872 nm..... Irie et al.......... Vt is extracted from the maximum slope of gm.................................. b) Corresponding CETs............... ................................................................... 175 Figure 6...5a) Cgc characteristics....9 Simulated electron mobility change induced by stress components in the fin height...........................2 Cross sectional TEM image of a 20 nm wide finFET ... 164 Figure 6.... Figure sourced from [223])... Figure sourced from [223]). (100) (Na = 3............... (Simulations performed at DIEGM.............7 Electron µeff for Wfin ranging from 16 nm to 1872 nm............................6 Vt for p-finFETs with Wfin in the range 12 nm – 1872 nm................... width and length directions............3a) Cgc characteristics.........................Figure 6....10 Simulated hole mobility change induced by stress components in the fin height......’s[119] planar bulk (100)/<110> and (110)/<110> p-MOSFET data is included for reference......................... 175 xviii ..... ............

......... Bulk (100)/<110> and (110)/<110> n-MOSFET data (dashed lines) included for comparison....................11 The impact on the electron and hole FinFET mobility of the three device stress components....... (Simulation performed at DIEGM..... France....................... There is a large compressive strain component in the fin height direction (shown in green).......... ....... (Adapted from [223]) ........... (110)/<110> and (100)/<110> bulk p-MOSFET data (dashed lines) included for comparison........12 Holographic measurement of the strain pattern........... 178 Figure 6........................ Strain in the channel direction is negligible in long channels..Figure 6..... Measurement was performed at CEMES-CNRS......... according to mobility simulations at DIEGM...................... induced by the metal gate in a 10 nm fin cross section......................... The formula on the top axis expresses the relative energy shift of the ∆2 valleys with respect to the ∆4 valleys as a function of the fin height stress component...... 182 xix .............15 Hole µeff measured at 4 K for p-finFETs with Wfin ranging from 1872 nm to 22 nm.. and also a weaker tensile strain component in the fin width direction (shown in red).......... 180 Figure 6........ 177 Figure 6..... There are stress configurations that can simultaneously improve both electrons and hole mobility....... .......................... (Sourced from [223])176 Figure 6... Note a tensile TfL for electrons and compressive TfL for holes stress may be exploited to further enhance FinFET mobility.......................14 Electron µeff measured at 4 K for Wfin ranging from 1872 nm to 16 nm................. Figure sourced from [223])....13 Occupancy of the ∆2 and ∆4 in (110) silicon at Ninv = 8x1012 cm-2 as a function of fin-height stress..

...... Keeping with...... LRS is included in all simulations.......................... 186 Figure 6................. Yang and Henson’s notation.............. z1 is the interfacial oxide thickness............ remote Coulomb and local roughness scattering mechanisms...................... ..............18 4 K hole µeff of a quasi-planar p-finFET (Wfin = 1872 nm) modelled in terms of ionised impurity.... 187 Figure 6................. Remote charge density.... 189 xx ....... LCS and RCS are independently shown...............Figure 6.......................... local Coulomb....... The remote charge density extracted at 4 K............. is used in the modelling of RCS with the resulting mobility within 12% of the measured mobility........ Takagi et al.....................19 Multi sub-band Monte Carlo simulations of the 300 K electron mobility of a quasi-planar n-finFET (performed at DIEGM). nr is modelled as a sheet of charge at the high-κ/SiO2 interface.......... ............’s bulk Si/SiO2 (100)/<110> data is shown for reference..17 4 K electron µeff of a quasi-planar n-finFET (Wfin = 1872 nm) modelled in terms of ionised impurity........................ remote Coulomb and local roughness scattering mechanisms.... The effects of phonon scattering (bulk and remote) PS.... 185 Figure 6. local Coulomb...16 Schematic of a high-κ gate stack............

University of Glasgow) for their unstinting help and expertise. David Esseni. Jeremy Watling (Device Modelling Group. for their support and encouragement. I should like to thank my supervisors Prof. Italy). a big thank you must go to Dr. Evan Parker. Lander and Dr. Luca Donetti (Departamento Electronica. this thesis would not have been possible. David Leadley and Prof. Last but not least. xxi . I must also thank Prof. Nicola Serra (University of Udine. Of course a thank you must go to various group members of the Nano-Si group for their help and advice. Francisco Gamiz and Dr. Terry Whall. I should like to thank my family and friends. Dr. Without their guidance over the last 4 years. Dr. Spain) and Dr.Acknowledgements Firstly. Georgios Vellianitis (NXP Semiconductors. Dr. Belgium) for their expertise and helpful discussions which lead to a very successful collaboration. Universidad de Granada. Rob. Secondly.

xxii .Declaration This thesis is submitted to the University of Warwick in support of my application for the degree of Doctor of Philosophy. Except where specifically stated. all of the work described in this thesis was carried out by the author or under his direction.

S. 2009. E. L. Vellianitis. Watling. T. Vellianitis.. T.J. R... Palestri.C...J. Parker. Whall... Doornbos.R.. T.. M. M.E. Lander. Leadley. D. Hikavyy. R.J. G.R. T. G....J. M.H. S... E.” Solid-State Electronics.E.R.J.P.. W. Serra.. “Low temperature effective mobility measurements and modelling of high-κ gated Si n-MOS and p-MOS devices” ULIS 2010: 11th International Conference on Ultimate Integration of Silicon xxiii . Lander.. Whall.C. Selmi.. Watling. Thomas... R. F. J. Parker.H. A. Conzatti. Leadley. Snoeck. P. Lee.. J. Whall...C. N.. Whall. Thomas. G. C... T. Duriez.E.H. D.” 2009 IEEE International Electron Devices Meeting: 63-66. E.. D.. B.H... Wang...P.J. Hytch.P. E. L.R.. Leadley. 53(12): 1252-1256.J. M. F. Parker. R.R. S. Witters. G. Vellianitis.. M.Publications Thomas. De Michielis. Prest..C. Houdellier..S.J. Watling. D. J. Leadley.. Vellianitis.. Esseni. D. Lander..H.” ULIS 2009: 10th International Conference on Ultimate Integration of Silicon Thomas.P.R. Beer. “Improved effective mobility extraction in MOSFETs. van Dahl.C. “Experimental and physics-based modeling assessment of strain induced mobility enhancement in FinFETs. G. M.. “Accurate effective mobility extraction in SOI MOS transistors.R. E. E.M. S.. Parker. Lander.

N. Whall. E. L.J. G. G.. T.M.E.. G. A.. Lee.. Donetti. M. Vellianitis.. Serra. Parker. L.. De Michielis. Doornbos..E.. Palestri.. Wang.. R.... D..H.R.J.. W. P. D.R. Leadley.. Lander. T. Whall. Thomas.J. van Dahl..M. xxiv . “Investigation of strain engineering in finFETs comprising experimental analysis and numerical simulations.P. S. P. F. T. “On the effective mass of holes in inversion layers” ULIS 2011: 12th International Conference on Ultimate Integration of Silicon Further publications arising from this thesis are in preparation. Ostling... Snoeck. M. F..J. Paussa.Conzatti.. Gamiz.C. L. Esseni.. Thomas.. Hellstrom... E. Hytch. M.-E.H.. Malm. D. Leadley. Witters. Selmi. M.C.” Accepted for publication in IEEE Transactions on Electron Devices. S.

necessary to increase computing power and the manufacture of more compact circuits. It is further shown that the lateral field and diffusion corrections. Novel transistor architectures and materials are currently being researched vigorously. In depth analysis of the electron and hole mobility was performed at 300 K and 4 K. Fins have a height of 65 nm with widths in the range of 1872 nm (quasi-planar) to 12 nm. xxv . Scattering from these charges was shown to be the dominant scattering mechanism in the quasi-planar n-finFET mobility at 300 K. RMS (root mean squared) roughness values in the range 0. This was attributed to the damage caused by the dry etch. The 4 K mobilities were modelled in terms of ionised dopant impurity. ionised dopant impurity.Abstract To enable the advancement of Si based technology.38 nm and correlation lengths of 2.34 − 0. in fact cancel each other.and pfinFETs were then modelled in terms of remote charge. local SiO2/Si interface charge and roughness scattering mechanisms. The results are composed of three parts. A novel technique is suggested that corrects the difference in drain bias during current-voltage and capacitance-voltage measurements. used to pattern the fins. which enhanced the electron mobility by 60% above the (110) reference. Remote charge densities of 8x1012 cm-2 were subsequently extracted. Firstly. which are commonly neglected. Fin top surface and sidewalls are in the (100) and (110) planes respectively. on the electrical characterisation of non-standard orientated MOSFETs and multi-gate transistors displays detailed insight into the carrier transport and resulting performance limiting mechanisms.MOSFETs fabricated on (100) and (110) substrate orientations with the full range of channel directions. A model for remote charge scattering at the HfSiO2/SiO2 interface was developed. This thesis. whilst leaving the hole mobility unaffected. The second part is based on the electrical characterisation of n+poly-Si/SiO2/Si nand p. local SiO2/Si interface charge and roughness scattering mechanisms.3 nm were extracted revealing comparable interface quality between the (100) and (110) surfaces. significant changes to the current planar transistor are a necessity. The third part examines the electrical characterisation of TiN/HfSiO2/Si n. Qualitative analysis of the 4 K mobilities suggests that roughness is higher on the sidewalls than on the top surface.and pfinFETs. The efficacy of the proposed technique is demonstrated by application to data measured on a quasi-planar SOI finFET at 300 K and 4 K. 4 K mobilities from the quasi-planar n. Detailed analysis revealed vertical compressive strain induced by the gate into the fin sidewalls.0 − 2. the standard method of extracting carrier effective mobility from electrical measurements on MOSFETs is reviewed and the assumptions implicit in this method are discussed.

Note areal means “per area”.List of Symbols All symbols. abbreviations and acronyms have been defined in the text and are listed here for convenience. α C C0 Cacc CBOX Cdep Cgb Cgc C gcmeas Cgc0 Chf CHigh-κ Cinv Cit Cit2 Clf Cox CSi CSiO2 Ctot D Dit δz ∆ ∆L length e E E0 Ec Econf confinement Eeff EF EHH Ei ET coefficient of proportionality/Maclaurin series expansion term of an exponential function capacitance offset capacitance areal accumulation capacitance areal capacitance of buried oxide (BOX) areal depletion capacitance areal gate-body capacitance areal gate-channel capacitance gate-channel capacitance quasistatic or low frequency gate-channel capacitance areal high frequency capacitance areal capacitance of high-κ dielectric areal inversion charge capacitance areal interface trap capacitance at the dielectric/Si interface areal interface trap capacitance at the Si/BOX interface areal low frequency capacitance areal gate oxide capacitance areal capacitance of silicon film areal capacitance of SiO2 interfacial oxide total MOSFET capacitance diffusion coefficient density of interface traps remote charge delta distribution rms fluctuation of interface roughness difference between the masked channel length and real channel electron charge band edge energy ground eigen-energy level conduction band edge set of discrete energy levels (eigen-energies) associated with effective field produced by Vgs Fermi level (or Fermi energy) energy of the heavy hole sub-band Intrinsic Fermi level total energy of carrier xxvi .

T ) F(Vgs) Fz(Vgs) gd gm gv G G(q) Git Gp Hfin ħ i I I0 I1 I2 Ic Ic’ Id Idiffusion Idm Idrift Idsat Ig Ip Ip’ k k k’ energy of a free carrier parallel to the interface valence band edge electric field along the channel permittivity of free space dielectric screening function diffusion energy permittivity of a high-κ gate dielectric permittivity of a gate dielectric/oxide static (low frequency) permittivity of a gate dielectric (used in place of εox when comparing to the optical permittivity) optical (high frequency) permittivity of a gate dielectric (static) permittivity of Si optical permittivity of silicon permittivity of SiO2 measurement frequency of AC voltage Fermi-Dirac distribution F-function F-function drain conductance transconductance degeneracy conductance local field correction in Hubbard’s approximation conductance associated with the loss of an interface trap equivalent parallel conductance of interface traps fin height reduced Planck’s constant eigen-energy index total current sub-threshold current pre-factor current through source and drain current through substrate quadrature current quadrature current after phase separator on current/drain current in linear regime diffusion current component of drain current measured drain current in presence of significant gate leakage current drift current component of drain current drain current in saturation gate leakage current in phase current in phase current after phase separator Boltzmann constant carrier wavevector carrier wavevector after scattering event xxvii .Etran Ev Ex ε0 ε(q) εd εHigh-κ εox ε ox0 ε ox∞ εSi ε si∞ εSiO2 f f (E .

HH n ni nimp nr Na Nd Ndep Ninv Ninv(0) Npoly η P ρ2D ψ(z) ψb ψc ψs q qs Qdep Qg Qinv Qinv(x) Qs R Rch Rd Rit Fermi wavevector wavevector along the channel (x direction) wavevector in y direction wavevector in transport plane MOSFET scaling factor/ dielectric constant/ ratio of diffusion to drift current gate/channel length Debye length correlation length of interface roughness effective mass free electron mass effective mass in confinement direction longitudinal electron effective mass average effective mass in channel plane transverse electron effective mass effective mass in transport direction effective mass in transport direction for HH sub-band capacitor divider ratio/ number of fins intrinsic carrier concentration impurity charge sheet density at dielectric/Si interface remote charge sheet density acceptor doping concentration donor doping concentration total depletion charge density total inversion charge density inversion charge density at the source doping concentration of a polysilicon gate empirical factor referring to the averaging of the electric field over the carrier distribution in the inversion layer power dissipation per MOSFET density of states in a sub-band band perturbation potential /electron wavefunction potential in the bulk potential in centre of fin potential at semiconductor surface difference between wavevectors k and k’ Thomas-Fermi screening wave number total areal depletion charge total areal gate charge total areal inversion charge areal inversion charge at point x total areal charge in semiconductor total MOSFET resistance channel resistance drain resistance resistance associated with interface trap loss xxviii .kF kx ky k|| κ L LD Λ m m0 mconf ml mscat mt mtran mtran.

S. thigh-κ tox tr tSi tSiO2 T TfH TfL TfW τch τit τsub τ τk momentum relaxation time scattering angle / phase angle (loss tangent) θ U (q ) µ µeff µIIS µLCS µLRS µRCS µTot v V V(z) Vcs Vds Vfb Vgs Vgs0 Vgt Vox Vt W Wdep Wdepm Wfin 2 average random potential of scattering mechanism carrier mobility effective carrier mobility ionised impurity scattering limited mobility local Coulomb scattering limited mobility local roughness scattering limited mobility remote Coulomb scattering limited mobility total modelled mobility carrier velocity along the channel supply voltage potential well channel potential with respect to source drain bias flat-band voltage gate bias with respect to substrate gate bias corresponding to C0 gate overdrive voltage (Vgs-Vt) Voltage across gate oxide/dielectric threshold voltage channel width depletion region width maximum depletion width fin width xxix .parallel resistance in equivalent circuit series resistance in equivalent circuit/ source resistance total source and drain resistance substrate resistance power spectral density sub-threshold slope thickness of high-κ gate dielectric thickness of gate oxide carrier transit time from source to drain thickness of silicon film thickness of SiO2 interfacial oxide Temperature stress component in fin height stress component along channel stress component in fin width channel time constant interface trap time constant substrate time constant mean free time Rp Rs Rsd Rsub S (q ) S.

ω

ω SO
x
xj
Xc
y
Y
z
zav
ξ

angular frequency
angular frequency of the interface longitudinal-optical phonon
distance along the channel x=0 at source x = L at drain
source/drain junction depth
reactance of capacitor in equivalent circuit
distance perpendicular to channel
admittance
distance parallel to oxide interface
average distance of the inversion charge from the gate dielectric
chemical potential

xxx

Abbreviations and Acronyms
AFM
BOX
CET
CFM
CMOS
CV
EOT
FDSOI
GV
HH
IIS
LCS
LH
LO
LRS
MOCVD
MOSFET
OA
PDSOI
PS
RCS
RF
RPS
RRS
RTA
SIMOX
SO
SOI
TEM
TO
VLSI

Atomic Force Microscopy
Buried OXide
Capacitive Equivalent Thickness
Cubic Feet per Minute
Complimentary Metal Oxide Semiconductor
Capacitance-Voltage
Equivalent Oxide Thickness
Fully Depleted Silicon On Insulator
Conductance-Voltage
Heavy Hole
Ionised Impurity Scattering
Local Coulomb Scattering
Light Hole
Longitudinal Optical
Local Roughness Scattering
Metal Organic Chemical Vapour Deposition
Metal Oxide Semiconductor Field Effect Transistor
Orientated Angle
Partially Depleted Silicon On Insulator
Phonon Scattering
Remote Coulomb Scattering
Radio Frequency
Remote Phonon Scattering
Remote Roughness Scattering
Rapid Thermal Anneal
Separation by IMplantation of OXygen
Split-Off/Surface Optical phonon mode
Silicon On Insulator
Transmission Electron Microscopy
Transverse Optical
Very Large Scale Integration

xxxi

Chapter 1 : Introduction

1.1 Semiconductor industry
Invented 60 years ago, the metal-oxide-semiconductor-field-effect-transistor
(MOSFET) is a key building block of today’s digital world. Perhaps the most
important invention of the 20th century, this electronic switch is the fundamental
component in integrated circuits (also known as chips) which are found in nearly all
electronic devices. CMOS (complimentary metal-oxide-semiconductor) technology,
used in microprocessors, is comprised of pairs of n and p-type MOSFETs to carry
out logic functions.

In 1975, Gordon Moore, co-founder of industry leader Intel, predicted that the
number of transistors on a chip would double about every two years.[1] This is
known as Moore’s law. Moore’s law has fuelled a technology revolution as the
number of transistors integrated into microprocessor chips has exponentially
increased for greater computing power. In 1971, the groundbreaking Intel 4004
processor contained 2300 transistors. At the end of 2009, Intel launched their
Westmere processor containing over 1.9 billion transistors. Over the next decade,
processors will contain 50-100 billion transistors.

1

1.1.1 Silicon
Silicon has formed the basis of the semiconductor industry, almost since its birth and
has remained the material of choice since it superseded germanium, which was used
to make the first transistors. Silicon has the advantages of being easily obtainable
(comprising a quarter of the Earth’s crust), therefore inexpensive. Secondly it has
good physical properties that allow easy definition of complex device structures.
Lastly its oxide is a very good electrical insulator and, unlike that of germanium, is
insoluble in water which reduces processing complexity. These factors combine to
provide a cheap platform on which to fabricate reliable MOSFETs.

1.2 CMOS scaling
1.2.1 Constant field/Dennard scaling
Historically, the increase in the number of transistors on a chip was achieved by
scaling down the transistor’s dimensions by a constant factor 1/κ. In accordance with
Moore’s law, κ = 2 was applied every two years when a new generation of chips
was manufactured for the first time. This results in a chip with a greater functionality
in the same area (or equivalently a chip with the same functionality in a smaller
area). Since fabrication costs for a wafer are relatively fixed, the cost per transistor is
reduced. Table 1.1 lists the MOSFET parameters and the effects of their scaling on
the MOSFET and chip performance.

2

enabling the chip to operate faster (at a higher clock frequency) whilst the power density remains constant (i.Scaling parameters Derived device parameters Derived chip parameters MOSFET device and chip parameters Device dimensions (tox.2. lower power consumption per MOSFET). The scaling factors are derived from constant field scaling. This is achieved by scaling down the supply voltage in proportion with the dimensions and scaling up the substrate doping concentration. Ctot is the total capacitance of the device which is composed of the gate oxide capacitance and source/drain junction and parasitic capacitances (adapted from [2]) The scaling factors are derived from constant field scaling whereby the vertical and horizontal electric fields in the MOSFET are kept constant. as fundamental technological and physical limits of existing processes and materials 3 . L.1 MOSFET scaling parameters.e. W. The key metric for MOSFET performance is the intrinsic delay time. xj) Substrate doping concentration (Na/Nd) Supply voltage (V) Electric fields Depletion-layer width ( W dep ∝ 1 N a ) Gate oxide capacitance (Cox = WLεox/tox) On current (Id ) Intrinsic delay time (CtotV/Id) Power dissipation (P = VId) Transistor density ( ∝ 1 / WL ) Power density or areal power consumption (P/WL) Clock/operating frequency (Id/CtotV) Scaling factor 1/κ κ 1/κ 1 1/κ 1/κ 1/κ 1/κ 1/κ2 κ2 1 κ Table 1. 1. the MOSFET intrinsic delay time is reduced.[3] Note that in addition to the increased transistor density on a chip.2 Departure from constant field scaling Scaling has become more challenging with each successive MOSFET generation.

This has motivated research into increasing the conductivity of the MOSFET to increase the on current. In particular the oxide thickness (or equivalently the areal oxide capacitance) and source/drain junction depths have ceased to be scaled in proportion with the channel length. this increases the power density. However high doping reduces carrier mobility thereby degrading the on current (increase in intrinsic delay time). scaling down of the supply voltage has been reduced to compensate and increase the on current. resulting in the loss of electrostatic control of the channel by the gate. reducing the operating speed of chips. This led to it being replaced by a thicker high-κ (hafnium-based κ~ 20) dielectric in conjunction with a 4 .are being reached.[5] Leakage current through it due to quantum mechanical tunnelling of electrons from the channel was now a serious issue. which prevent the gate abruptly switching the MOSFET off. resulting in chips running at increasingly higher temperatures. Constant field scaling ended in 2003 and since then numerous innovations have enabled the continuation of Moore’s law. However. and to reduce leakage current in the “off state”. Intel announced the integration of strained silicon to improve the on current of transistors in the 90 nm technology node. This has led to a new set of scaling rules and subsequently trade offs between on current (or drive current) and scalability. Since it is desirable for chips to operate faster than the previous generation. at a lower supply voltage. In 2003.[4] In 2005 (65 nm node) the silicon dioxide gate dielectric had been scaled to a thickness of 1.1 nm. For example substrate doping concentration has to be scaled up further to reduce so called “short channel length effects”.

The implementation of silicon-on-insulator (SOI) technology. state of the art chips use 4th generation strained silicon and 2nd generation high-κ /metal gate technology with transistor channel lengths of around 35 nm (same length used in the 45 nm node). Intel’s first 22 nm node processors will be in production.[8] Short channel effects and off state leakage current are expected to be severe. allow for an increase in the physical thickness of the gate dielectric. 1. However. the result of years of research and development. where the benefits of exponentially lowered leakage current density are achieved while the necessary gate oxide capacitance is attained. the classic bulk MOSFET is expected to run out of steam.[7] At the end of 2011. The change in process was no minor feat and has been hailed as the biggest advancement in transistor technology since the late 1960s. the details of which have not yet been released. in 2008 (45 nm node)[6]. Currently (32 nm node). already employed by IBM and AMD. High-κ gate dielectrics.2.metal gate. is one of several strategies employed to follow Moore's law [9]. partly due for compatibility. Fabricating MOSFETs on a layered thin silicon film-insulator-silicon substrate in place of a conventional silicon substrate helps the gate to retain electrostatic control 5 . below channel lengths of 15-20 nm. the latter causing unacceptably high idle power consumption.3 SOI Silicon based scaling is predicted to continue beyond the 11 nm node (2017-18) with channel lengths of 12-18 nm expected.

i. SOI substrates are far more expensive than conventional silicon substrates and as yet.[8] From a fabrication perspective. requiring a film thickness of ~67 nm.2.1) thus allow for further channel length scaling and may even supersede the SOI MOSFET. However. a silicon film thickness of about a quarter of the channel length is required.of the channel and provides numerous other advantages. The distinguishing characteristic of the finFET is that the gate 6 . an SOI-based process may be implemented without modification of equipment or significant retooling of an existing fabrication plant. Multi-gate transistors.[10-11] 1. Thus the film thickness is an additional parameter to the gate oxide for suppressing short channel effects and off state leakage current. for example the tri-gate or finFET (figure 1. This allows SOI MOSFETs to be scaled more aggressively than the classic bulk silicon MOSFET without requiring high substrate doping concentrations.e. short channel effects and off state leakage current can be suppressed much more effectively than by using an SOI substrate. Intel have managed to avoid using them though eventually the advantages they present may soon justify the cost. To achieve good switch off characteristics.4 Multi-gate transistors – the finFET By modifying the MOSFET architecture and using multiple gates. SOI substrates are compatible with most conventional processes. At the 22 nm node (late 20112012) channel lengths are expected to reach 25 nm.

straddles a thin. the fin width is an additional scaling parameter to the gate oxide. fin shaped body. As the channel length is scaled down. 7 .e. enabling finFETs to be packed more densely than planar MOSFETs. Figure 1. This novel 3D transistor is usually fabricated on an SOI substrate. forming three self-aligned channels along the top and vertical sidewall surfaces of the fin. The vertical nature of a finFET provides a greater device width per wafer area. Thus akin to the film thickness of an SOI MOSFET.1 Schematic of a finFET. a fin width of ~15 nm is required. The fin width should be roughly half the channel length. Thus the width of the fin. The use of three gates surrounding the fin ensures excellent electrostatic control. short channel effects and off-state leakage current are suppressed by scaling down the width of the fin. for the 22 nm node. i. is the minimum dimension in a finFET. which is defined by lithography.

the latter chapter dealing with the necessary characterisation techniques. These issues will become increasingly important for successive finFET generations. Mobility is usually extracted on long channel devices.3 Current investigation This thesis is an investigation into the electrical properties of silicon MOSFETs and finFETs.and p-channel devices is highly sought after. Another challenge is the implementation of high levels of strain into the fins to boost the on current. In particular a single strain configuration that benefits both n. its physical interpretation and modelling. Such study is relevant to continue the advancement of silicon based technology. reducing the on current. high series resistance and absence of substrate contact in some SOI technology. However accurate extraction is becoming increasingly difficult due to high gate leakage in large area devices. In chapters 2 and 3 the relevant background material to this investigation is covered. there are still a number of aspects that require further research. 1. fabrication of uniform narrow fins is one of the primary challenges in fabricating finFETs. Also a physical understanding of hole mobility on the different surfaces and in different channel directions is currently lacking. 8 . narrow fins create a high access resistance. Emphasis is placed on extraction of carrier mobility. Regarding the device performance. Whilst there has already been substantial investment by industry giants in finFET technology.However.

New insights into the dependence of mobility on channel direction and surface orientation are obtained. In chapters 5 and 6 particular attention is on low temperature measurements (down to 4.2 K) from which the various mobility limiting scattering mechanisms are analysed. 9 . Chapter 6 presents original work on the electrical characterisation of state of the art strained silicon finFETs with high-κ dielectrics and metal gates.Chapter 4 analyses the common assumptions that are so often blindly applied when extracting mobility. In chapter 5. A novel extraction technique is proposed and applied to a quasiplanar SOI finFET. planar bulk MOSFETs fabricated on (100) and (110) substrate orientations are electrically characterised.

Very little band bending occurs in the metal due to the abundance of free carriers. Band bending changes with the applied bias and the bands become flat when we apply the so-called flatband voltage to compensate for the difference in work functions. The Fermi level remains constant inside the semiconductor. An n-MOS capacitor will enter the 10 .) Oxide and interface trapped charges can also contribute to an appreciable amount of band bending.Chapter 2 : Theoretical Considerations 2. EF. All potentials are with respect to the substrate/bulk which is grounded. of the gate and semiconductor. For simplicity of discussion. independent of biasing conditions as there is no net current flow in the direction perpendicular to the interface owing to the very high resistance of the dielectric layer.1 The MOS capacitor A MOS capacitor consists of a conducting metal layer (metal or heavily doped polysilicon) on top of a dielectric grown or deposited on a semiconductor substrate. the bulk of which can be doped n-type (p-MOS capacitor) or p-type (n-MOS capacitor). the bending of the energy bands. Vgs is now considered. this is ignored here. necessary to align the Fermi levels. (Band bending signifies a change in electric potential and therefore the existence of an electric field. At zero applied bias. is ideally determined by the difference in the work functions of the metal and the semiconductor. The operation of an n-MOS capacitor under gate bias.

This continues until it becomes energetically favourable for electrons to populate the 11 .accumulation regime of operation when the voltage applied between the metal and the semiconductor is more negative than the flat-band voltage (Vfb <0). Electrons in the gate are displaced towards the semiconductor and holes in the semiconductor displaced towards the gate. Figure 2. The positive bias lowers the metal Fermi level with respect to the semiconductor Fermi level. corresponding to a much higher hole concentration at the surface than the equilibrium hole concentration in the bulk. the electron potential energy) with respect to the semiconductor Fermi level and creates an electric field from the substrate. through the oxide (just like an ordinary parallel plate capacitor) into the gate. Holes in the semiconductor move away (depleted) from the interface. leaving a net negative charge from the acceptor ions. When Vgs > Vfb. The Fermi level at the surface is now much closer to the valence band than the Fermi level in the bulk. The field in the semiconductor causes the bands to bend upward. The bands in the semiconductor bend downwards. As Vgs increases. holes continue to be depleted from the interface leaving behind more acceptor ions resulting in more depletion charge and a wider depletion region.1a) shows the energy bands in accumulation. The negative bias raises the metal Fermi level (i. The electric field is now in the direction from the gate to the substrate. This is known as depletion charge. The valence band at the surface is now farther away from the Fermi level than the valance band in the bulk expressing the lower hole concentration at the surface than the equilibrium hole concentration in the bulk.e. the capacitor will enter the depletion regime of operation.

the Fermi level at the surface is as far above the intrinsic level. The additional field lines from the gate now terminate on the inversion charge rather than the depletion charge. 12 . The process of electrons populating the conduction band at the surface in a p-type semiconductor is known as surface inversion and the surface behaves like an n-type material.1b) shows the energy band diagram when the MOS capacitor is in the inversion regime. Vt. The resulting sheet of electrons at the surface is referred to as the inversion layer. This condition is known as the threshold inversion point and the corresponding gate voltage known as the threshold voltage. we enter into strong inversion where more inversion charge will be generated whilst the band bending remains essentially constant. On the energy band diagram.conduction band at the surface. Thus the electron concentration at the surface is the same as the hole concentration in the semiconductor. In the figure. the bands bend downward so much so. Ei. Figure 2. thereby screening the semiconductor from any further band bending. When Vgs>Vt. as the Fermi level is below the intrinsic level in the bulk semiconductor. that the conduction band approaches the Fermi level expressing the much higher electron concentration. At this point all holes are depleted from the surface and the depletion charge ceases to increase.

The band perturbation potential as a function of distance perpendicular to the interface. as the difference between the intrinsic Fermi-level (in V) at the surface and its bulk level. valence band and intrinsic Fermi-level band are equal. ψ(z) is a parabolic function.1a) n-MOS capacitor in accumulation and b) inversion The gate voltage at inversion is related to the flat-band voltage. Qinv and Qdep respectively. Note that the perturbations of the conduction band. At the surface (z = 0) the band perturbation 13 . At the edge of the depletion region. as inversion charge density Ninv and depletion charge density Ndep (normalised with respect to electron charge). Vfb. Vox and the semiconductor ψs V gs = V fb + Vox + ψ s = V fb + Qs +ψ s C ox (2.1) where Cox is the areal oxide capacitance and Qs is the areal total surface charge at the semiconductor-oxide interface. the “surface potential”. It is common to express Qinv and Qdep. composed of the areal inversion and depletion charges. We explicitly define ψs.Figure 2. voltage across the oxide. ψ(z = Wdep) = 0.

Vt can be expressed in the following form.1. Combining the equations above. Depending on the regime of device operation. certain terms will dominate allowing the expression to be simplified.2) At threshold.6) C ox 14 .2) Where εSi is the semiconductor relative permittivity.5) obtained by substituting eqn.4) into eqn. Integrating Poisson’s equation from the bulk to the interface gives an expression for dψ(z)/dz. Wdepm = 4ε Si ε 0 kT ln( N a ni ) e2 N a (2.3) The surface potential at the onset of strong inversion: ψ s = 2ψ b = 2 kT  N a ln e  ni    where the bulk potential ψ b = (2. the depletion region reaches its maximum width Wdepm. The depletion charge per unit area is approximately: Qdep = eN aWdep (2. Wdep = 2ε Si ε 0ψ s eN a (2. (2. T the temperature When in inversion. which is normally approximately equal to the substrate doping concentration. (2. ni is the intrinsic e carrier concentration.4) E F − Ei as shown in Figure 2. Wdep is the width of the depletion region. k the Boltzmann constant.potential is equal to the surface potential ψ (z = 0) = ψs. e the electron charge. Qs = Qdep. and Na is the ionised acceptor concentration. From which. Vt = V fb + 2ψ b + 2ε 0 ε Si eN a (2ψ b ) (2.

2 n-MOSFET schematic showing the electrical connections A standard semiconductor MOSFET consists of a MOS capacitor with a highly doped source and drain region either side. When Vds is applied an electron current will flow from the source to the drain. Figure 2. The gate can 15 .2. and allows more current to flow. When Vgs < Vt.2 The metal-oxide-semiconductor-field-effect-transistor Figure 2. the semiconductor surface is inverted to n-type. the p-type substrate is either in accumulation or depletion and no current can flow between the source and drain even when in the presence of the bias Vds. each with a respective metal contact. An n-channel “enhancement mode” MOSFET has a p-type semiconductor and n+ source and drain regions and a p-channel MOSFET has a n-type semiconductor and p+ source and drain regions.2 is a schematic of an n-channel MOSFET including the electrical connections. The MOSFET acts like two back-to-back p-n junction diodes. forming a conducting channel between the n+ source and drain. Note the source and substrate are grounded. When Vgs>Vt. Increasing the gate bias increases the concentration of electrons at the semiconductor surface.

To simplify the description of effects within a MOSFET. Thus it can be written: Qinv ( x ) = C ox (V gs − Vt − Vcs ( x )) (2. Thus Wdep at a point x along the channel is given by the potential at that point using the simple one-dimensional results in section 2. 16 .1.therefore be used to modulate the current flow between source and drain. Ex of the MOSFET is much smaller than the vertical electric field and enables the use of the one-dimensional form of Poisson’s equation. Vcs = 0 at the source and Vcs =Vds at the drain.2. at the drain end. 2. This assumes that the electric field along the channel. giving rise to the switching operation in integrated circuits. Under the charge-sheet approximation. it is further assumed that all the inversion charges are located at the semiconductor surface in a sheet.y and z directions.2 the geometry of the MOSFET is different in the x. Therefore a proper analysis requires the study of charge flow in the three dimensions requiring complex numerical techniques. This approximation is good if the gate/channel length L is larger than the Wdep. and there is no potential drop or band bending across the inversion layer.7) where Vcs(x) is the channel potential with respect to the source.1 On state As can be seen from Figure 2. the gradual channel approximation is commonly made. x = 0 at the source end and equal to L.

If the velocity of the carriers is constant between the source and drain. Id is a drift current caused by Ex. tr = L v (2. is related to Ex by the carrier mobility.10) By combining equations (2. or drain current. Id = QinvWL tr (2. µ.8) where W is the channel width and tr the carrier transit time.12) 0 The drain current is constant along the channel and for Vds<<Vgs-Vt.9) where the carrier velocity along the channel. v. 17 .10): I d = C ox µW dVc (Vgs − Vt − Vcs (x )) dx (2. Vcs(0) = 0) to drain (x = L.11) By integrating from source (x = 0. the final expression for Id is obtained: Id = µ W  V2  C ox (V gs − Vt )Vds − ds  2 L  (2. which for now is assumed to be constant and independent of Ex: v = µE x = µ dVcs ( x ) dx (2.13) This equation captures the basic on-state behaviour of a MOSFET.The electron flow in the channel. Vcs(L) = Vds) Vds L ∫I d dx = C ox µW 0 ∫ (V gs − Vt − Vcs ( x ))dVcs (2.Vt the drain current increases linearly with Vgs since the quadratic term can be ignored. which starts at Vgs ≥ Vt and provided 0 < Vds < Vgs .7)-(2.

10). This was assumed to be constant to convey the basic physics of MOSFET operation. The momentum relaxation time is the mean time 18 . µ = 1500 cm2V-1s-1 for electrons and 450 cm2V-1s-1 for holes at 300 K. is given by: I dsat = µ W 2 C ox (V gs − Vt ) for Vds > V gs − Vt 2L (2. The average time between these collisions is known as the mean free time τ . The drain current remains essentially constant and the MOSFET is said to be in the saturation region. µ is usually much smaller as carriers suffer collisions from various scattering sources (detailed in section 2. a carrier may still have a net momentum in its direction prior to being scattered.7)) creating a non uniform distribution of Qinv along the channel. the carrier mobility µ was introduced as the proportionality coefficient in the dependence of drift velocity on the applied field.[12] In a MOSFET channel however. Qinv at the drain end of the channel reaches zero.9). Further increase in Vds results in an extension of the pinch-off point towards the source and the extra potential is dropped across this increasing resistance.This is called the linear region and is often simplified to: Id = µ W C ox (V gs − Vt )Vds L [ ] (2. µ is dependent on the effective mass of the carriers which is calculated from the band structure of the semiconductor. Depending on the scattering source. The saturation current.14) As Vds is increased. Once Vds = Vgs-Vt. Id increases but Qinv at the drain decreases (equation (2. Idsat. and the channel is said to be pinched off. In bulk silicon. creating a region of high resistance.15) In equation (2.

which exists for Vgs ≤ Vt is known as the sub-threshold current and occurs when the channel is weakly inverted corresponding toψ b < ψ s < 2ψ b .16) mtran Since Id is proportional to µ. The reciprocal slope of this line is known as the sub-threshold slope. higher µ corresponds to faster switching circuits instigating research into ways to decrease mtran and increase τ k . Their concentration is very small and rapidly decays as Vgs is reduced below Vt. The current Id.S. µ= e τk (2. 2 I d = µC ox W (n − 1) kT  e e (Vg −Vt ) nkT 1 − e −eVds L  e  ( kT ) (2. 19 .17) where n = 1 + C dep C ox A plot of ln(Id) as a function Vgs gives a linear behaviour in the sub-threshold regime. Qinv does not abruptly equal zero when Vgs ≤ Vt. S. The transition from full depletion to strong inversion is in fact more gradual as there are mobile carriers in the channel even for sub-threshold Vgs. mtran. Nonetheless they account for the gradual decay of Id from above threshold toward zero. The electrons have to overcome the potential barrier formed by the n+ source and p-substrate. 2. Consequently a diode-like exponential current-voltage equation is used to model the sub-threshold current. µ is related to the momentum relaxation time τ k and the effective mass in the transport direction.2.for a carrier to lose all its momentum via scattering.2 Off state Experimentally.

1 Conduction band The effective mass of a carrier.which is a measure of the efficacy of Vgs in modulating Id. m is calculated from the energy band structure E-k relationship using: 2 1 1 ∂ E = 2 m h ∂k 2 (2. k is the direction dependent wave vector and m is expressed in units of the free electron mass.1. the sub-threshold current is reduced to the leakage current of the source/drain junctions. m0. This determines the off-state leakage current and therefore the standby power dissipation in CMOS circuits. the reader is referred to the texts by Taur and Ning[2]. For further analysis of the MOS capacitor and MOSFET.18) where h is the reduced Planck’s constant. High quality source and drain junctions are therefore an important requirement. Sub-threshold slope and its extraction is discussed in detail in section 3. For an analysis of carrier transport in the Si MOSFET inversion layer.3.3 Si band structure 2. For a very small Vgs. A small sub-threshold slope (steep transition from off state to on state) is desirable for the ease of switching the transistor current off. 2. Dimitrijev[13] and Nicollian and Brews[14].4. accurate description of the E-k relationship near the conduction – or valence band minima (band-edges) is sufficient 20 .

e. typically the mass in the z direction. mtran = mscat.916m0. the minima can be approximated as parabolas enabling a constant effective mass to be assigned. The constant energy surfaces of these minima are ellipsoids as shown in Figure 2. The conduction band edge is composed of 6 degenerate minima located along the <100> directions (referred to as ∆ minima). the average mass in the xy plane. mtran are important when considering carrier transport. Note if the constant energy surface is a circle in the xy plane. With regards to a MOSFET. ml = 0. The mass within the plane normal to the symmetry axis is the transverse mass.3.providing Ex is low. 21 . z [001] y [010] [110] x [100] Figure 2. the mass is independent of direction (isotropic) in this plane i. mscat and the transport direction. mconf.190m0. mt = 0.3 Constant energy surfaces of the conduction band minima For a given direction.[15] The mass along the symmetry axis of the ellipsoids (<100> directions) is called the longitudinal mass.

The constant energy surface of the HH band can be visualized as a cube with dented in faces.4 Carriers in the MOSFET inversion layer In sections 2. 2.2. separated from the HH and LH by 44 meV. The LH and HH bands are anisotropic meaning the effective mass depends on crystallographic direction. In reality carriers are confined in a potential well formed by the dielectric barrier and the semiconductor minority carrier band edge. we cannot make this approximation. 1.3.1 and 2. the light-hole band (LH). A detailed description of Si band structure is given by Kittel[16]. The SO band is higher in hole energy. However. The close proximity of the bands produces significant non-parabolicity of the variation of E with k. With increasing energy.2 Valence band The valence band consists of three strongly interacting sub-bands: the heavy-hole band (HH). which bends down severely towards the interface due to the gate field. A good description is given in Dobrovolsky 22 .1 eV below the conduction band minima. the inversion layer was approximated as a 2D-sheet at the dielectric/channel interface. in order to study the physics of carriers within the inversion layer.2. This gives rise to energy quantization and carriers are confined some distance away from the interface. a quantum mechanical approach has to be used. The HH and LH bands are degenerate at the Brillouin zone centre (Γ point). Therefore for a precise description. especially in the HH case. and the spin-orbit/split-off band (SO). the dents become more pronounced.

4. with the pioneering work carried out by Stern and Howard[18]. Econf. Stern[19] and Ando et al. These are known as sub-bands. we must first understand the dependence of the energy levels on Vgs. more explicitly the electric field.1 Confinement Quantum confinement splits the degeneracy of the energy bands. Econf is a set of discrete energy levels associated with confinement and Etran is the energy associated with free carrier motion parallel to the interface.20) 2mtran where mtran is isotropic in the xy plane. ET of a carrier. Carrier motion perpendicular (z direction) and parallel (xy plane) to the interface must now be considered separately and the respective energies calculated and summed to give the total allowed energy. ET = E + E conf + Etran (2. The values of the minima determine the occupation of the sub-bands. Thus the total available energies of a carrier consist of parabolas/valleys with their minima coinciding with discrete energy levels.[20] 2.19) where E is the classical energy of the band edge in a bulk 3D semiconductor. 23 . So before we can understand carrier transport along the channel.and Litovchenko[17]. For example: Etran = ( h 2 k x2 + k y2 ) (2. and on the Si band structure in the confinement direction.

The two ellipsoids along the z direction have their longitudinal effective 24 .[19] 1 E conf  h2 =  2mconf  2 3 3  3   πeE eff  i + 3      2  4   (2.23) where i = 0. the separation of which increases with increasing Eeff and decreasing mconf.For an electron confined within the well. for a p-MOSFET. and then the valence band.21) Here ψ(z) is the electron wavefunction. Conduction band Figure 2. for an n-MOSFET.4 shows the orientation of the constant energy ellipsoids in the <100> direction.3) Thus equation (2. 21] We assume that the potential barrier at the dielectric/semiconductor interface is infinite and the potential decreases linearly from the interface: V ( z ) = − zEeff (2.22) where Eeff is the effective field a carrier experiences. its wave function and allowable energies can be found by solving the 1D Schrödinger equation: 2   d2 − h + V ( z )ψ ( z ) = E conf ψ ( z ) 2  2m  conf dz   (2.4. We shall use equation (2. (calculation of Eeff is given in section 3.23) to gain a semi-quantitative understanding of the confinement effects in silicon starting with the conduction band.2… This gives rise to a series of discrete energy levels. The potential well can be modelled as an infinitely deep triangular well (the well known triangular well approximation).[19.21) can be solved to give the eigen-energies.1.

24) 25 .190m0 because their transverse effective mass is perpendicular to the surface.916m0. E1’. The other four respond with the transverse effective mass. Each set of eigen-energies. For both values. The density of states is constant for each sub-band and is given by ρ 2D = g v m scat πh 2 (2.23) has to be evaluated twice. and primed sub-bands are labelled E0’. In this case unprimed sub bands have a degeneracy. can be visualised as a ladder. of two as there are two ellipsoids in this group. equation (2. E2 etc. once for mconf = ml and again for mconf = mt. So they respond to Eeff with their longitudinal mass. E2’ etc. E0 is commonly referred to as the ground state and is the reference for the other subband energies. a series of eigen-energies will be obtained (i = 0. Unprimed subbands are labelled E0. In general sub-bands corresponding to the larger mconf are called unprimed sub-bands and sub-bands from the other ladder are called primed sub-bands. Most carriers will occupy the ground sub-band as it is lowest in energy. gv.mass perpendicular to the surface.). 0. Thus to calculate the eigen-energies.. 0.1. (also commonly referred to as ∆2 sub-bands) and the sub-bands of the primed ladder have a degeneracy of 4 (∆4 sub-bands). E1. Therefore its corresponding value of mtran is largely responsible in determining µ.2.

190m0 ∆4 mtran = 0.916m0 (100) Orientation mtran = 0.5 shows the orientation of the constant energy ellipsoids in the <110> direction.190m0 ∆2 <100> (100) orientation (into page) <100> mconf = 0. The reader is referred to chapter 5 for detailed analysis of the dependence of electron mobility as a function of direction on the (100) and (110) orientations. Note on the (110) orientation the unprimed sub-bands have a degeneracy of 4 and the primed sub-bands have a degeneracy of 2.4 Constant energy surfaces of the Si conduction minima in the (100) plane. 26 .1 lists the various masses and degeneracy factors for the (100) and (110) wafer orientations. Figure 2.190m0 Figure 2.916m0 <100> mtran = 0. Electron mobility is highest on the (100) wafer orientation. Table 2.<100> mconf = 0.

<110> mconf = 0.190/0.315/0.553m0 <100> mtran = 0.1 eV above the conduction band minima.190m0 <110> (110) orientation (into page) <110> mconf = 0.1 Electron effective masses[22-23] Uchida et al.190 0.190 0.916m0 <110> mtran = 0.[24] shows that the conduction band in the <110> direction. is non-parabolic.190 0. especially for energies larger than 0.916 0.190 0. i.315 0. Surface Orientation (100) (110) <100> <110> mtran/m0 mtran/m0 0.916 0.324 0.417 ∆2 ∆4 ∆4 ∆2 Table 2. the quantization direction for a (110) wafer.190 0.315m0 ∆4 <110> mtran = 0.190m0 (110) Orientation <100> ∆2 <100> mtran = 0.553 0.553 0.190 mconf/m0 mscat/m0 gv 0.417 0. 27 .916 0.190 (Modulated by confinement) 0.190m0 Figure 2.e.6.5 Constant energy surfaces of the Si conduction minima in the (110) plane. This is shown in Figure 2.

the ∆2 ground sub-band exceeds this energy and only becomes occupied when Ninv > 2x1012 cm-2. mconf of the ∆2 sub-bands is heavier because of the “nonparabolicity”.7a) Energy splitting of the ∆2 and ∆4 sub-bands b) Ground ∆2 sub-band energy as a function of inversion charge density (Ns in this figure).Under confinement.[22. analyse with respect to Ninv rather than Eeff) Thus. EMA: constant Effective Mass Approximation (sourced from [24]) Figure 2. 24-25] Figure 2.7 shows the resulting decrease in energy splitting between the ∆2 and ∆4 sub-bands as a function of Ninv. (sourced from [24]) 28 . Figure 2.6 Conduction band E-k relation showing the non-parabolicity in the [110] direction. (Here Uchida et al.

In comparison to the conduction band in this orientation.Valence band Figure 2. are continuously being developed. With increasing Ninv/Eeff. 29 . accurate calculations of the various effective masses as a function Ninv/Eeff require repeated solutions of the k•p equation and Poisson’s equation. calculated at k = 0 (i.20m0 respectively. single values of mtran. Values reported for the (100) and (110) substrate orientations in the literature are shown in Table 2. carriers occupy higher energies and the energy surfaces change shape. This is computationally very expensive requiring large computer resources. Due to the complex nature of the valence band.2. To the author’s knowledge. For the (100) orientation. the HH and LH subbands respond to Eeff with effective masses 0.29m0 and 0.e. mscat and mconf. for use in Monte Carlo simulations of hole transport.8 shows 2D schematics of the constant energy surfaces for the lowest lying HH. Under confinement the split-off sub-band is increased further in energy beyond the HH and LH sub-bands and can be ignored as it is scarcely populated. Techniques to compute the valence band structure with greater accuracy. LH and SO sub-bands.[29-31] For experimental interpretation of mobility and other device measurements. at a very low Ninv/Eeff ) are widely used. a relatively small splitting occurs due to the small difference in mconf. substantial simplifications have to be made. no values for mscat or mtran have been published for the (110) orientation.[26-28] As a result.

0.) HH 0. Saitoh et al.) 0.) HH 0.) (110) LH Table 2.15 (Saitoh et al.28 (Saito et al.20 (Takagi et al. No values for (110)/<100> and <110> have been reported 30 .29 (Takagi et al.58 (Saito et al. (adapted from [29]) Surface Orientatio n (100) mtran/m0 <100> mtran/m0 <110> mscat/m0 mconf/m0 Subband 0.) 0.2 HH and LH effective masses of Si.) LH 0.50.8 Constant energy surfaces of the lowest lying HH.17 (Takagi et al.15 (Saito et al.[34].Figure 2.[32]) 0.[33]) 0.43 (Takagi et al.) 0. LH and SO sub-bands in the (100) and (110) surface orientations.20 (Saito et al.[35]) 0.59 (Mizuno et al.

the most simplistic analysis is presented where all carriers are confined to the ground sub-band (the electrical quantum limit). This greatly simplifies scattering analysis as all carriers are represented by the same wavefunction. E F > kT (2.Hole mobility is highest along the <110> direction on the (110) wafer orientation. 2. Coulomb scattering from ionised dopants in the substrate and scattering from a non-uniform dielectric/Si interface. where T = 0 K. 31 . namely Coulomb scattering from charge at the dielectric/Si channel interface.2 K where typically. At T = 0 K. The reader is referred to chapter 5 for detailed analysis of the dependence of hole mobility as a function of direction on (100) and (110) orientations. We approximate this condition by cooling to 4. states around EF will be partly filled and therefore only these are important as far as transport is concerned. In each case. Therefore only scattering at EF need be considered. the Fermi distribution is a step function where states below EF are completely filled and states above EF are empty.25) Due to the finite temperature.5 Carrier scattering in the inversion layer We now consider some of the scattering mechanisms that degrade the carrier mobility along the channel. This is known as a degenerate distribution or degenerate gas in the case of an inversion layer.

Lattice vibrations are much like the vibrations of a harmonic oscillator such the energy of each normal mode must be quantised. we are able to relate the measurable.27) and (2.20) can be written. The quantum of energy is viewed as a particle called a phonon. Such vibrations are caused by thermal agitation of the lattice which disrupts the periodicity of the crystal. It is possible for carriers to emit or absorb phonons. kF and Fermi energy. creating disorder. 1  2πN inv k F =   gv 2   (2.29) 32 .26) (2. h 2 k F2 EF = 2m scat (2. Ninv to the Fermi wavevector. The degree of phonon scattering depends on the number of phonons present which is a strong function of temperature.24). EF. In the electrical quantum limit. equation (2.Not considered in the following sub sections is scattering by lattice vibrations.27) N inv For an isotropic mass in the xy plane. EF N inv = ∫ρ EF 2D dE = 0 EF = πh 2 g v m scat ∫ 0 g v mscat dE πh 2 (2. Using equation (2.28) gives. Phonons can be thought of as particles which propagate through the crystal with well defined energy and momentum.28) Equating equations (2. Therefore at very low temperatures phonon scattering can be neglected.

9. to the dielectric. equations are given in SI units. it is common to make this approximation at 300 K. Lets consider the case where a electron with wave vector k is elastically scattered by some disorder to k’ as shown in Figure 2.31) The average distance of the inversion charge from the dielectric can be estimated using.5. 33 .[37-38] 2. Conservation of energy requires that the wave vectors before and after the collision have the same magnitude.30) where  12e mconf  11  b= 2 N inv + N dep     h ε ε  32   0 Si  2 1 3 (2.e.Computations show the electrical quantum limit is valid for electrons and holes on a (100) orientation at T = 77 K. so the vectors lie on a circle in k-space. the smaller zav i.1 Scattering theory In the following theory.32) Note the larger mconf. 1 b3  2  bz  ψ ( z ) =   z exp −   2 2 (2.[36] However. z av = 3 b (2. on average. the nearer the carriers are. The Stern-Howard[18] wavefunction for carriers in the ground sub-band of a triangular well given is by.

ε(q) the dielectric screening function defined later.Figure 2. k = k’ and considering scattering takes place at EF with wave vector kF we can write. q 2 = k 2 + k ' 2 −2kk ' cos(θ ) (2. θ  q = 2k F sin   2 (2.9 Elastic scattering event where k = k' (sourced from [39]) From simple trigonometry.[20] give the scattering rate as.35) 2 0 is the average random potential and contains the relevant information pertaining each scattering mechanism.e. (1− cos θ ) is a weighting factor to account for change in momentum in the x direction. 34 .34) Ando et al. m = scat3 τ k 2πh 1 U (q ) 2 2π U (q ) 2 ∫ ε (q ) (1 − cos(θ ))dθ (2.33) Provided momentum is conserved i.

The probability of occupation of a state by an electron is determined by its energy relative to EF.5.10. its occupancy can change depending on band bending. Depending on their proximity to the interface.2. In the case of a nMOSFET in strong inversion. These states can capture electrons from the conduction and valence bands and thus become charged depending on Vgs and the nature of the state. States in the top half of the band-gap are acceptor-like (neutral when unoccupied by an electron) and states in the bottom half donor-like (neutral when occupied by an electron). states below which are occupied. they can scatter carriers in the inversion layer via the Coulomb force. a variety of fabrication induced charged impurities are present. In the case of a p-MOSFET in strong inversion. the termination of the Si lattice creates states with energies distributed throughout the Si band-gap. the charged interface states are positively charged donors. At the Si/dielectric interface. Since the energy of a state is fixed relative to the Si band edges. 35 . the charged interface states are negatively charged acceptors. Such states are called interface states or interface traps.2 Local Coulomb scattering (LCS) Within the gate dielectric. These two cases are shown in Figure 2.

A quantitative treatment of scattering from charged impurities has been given by Gold and Dolgopolov[40]. The random potential representing the interaction of a 2D gas with a sheet of impurities is 2 U (q ) 2  e2 1   [Fi (q )]2 = nimp  ε ε 2 q  Si 0  (2.36) where nimp is the impurity charge sheet density at the dielectric/Si interface and Fi(q) is a form factor  q Fi (q ) = 1 +   b −3 (2.10 Charged interface states in strong inversion for a (a) p-MOSFET and an (b) nMOSFET A detailed description of the types of charges in a SiO2 gate dielectric is given in Taur and Ning[2].37) 36 .Figure 2.

gives rise to variation in the eigenenergies. which in turn. then the perturbation of the energy levels constitutes an effective scattering mechanism for carriers confined along the interface. The morphology of the roughness is described by the power spectral density S (q ) which is related to the random potential by. U (q ) 2 = q s2 E F2 (1 + 2 N dep N inv ) S (q ) 2 (2. We will refer to roughness scattering at the dielectric/Si interface as local roughness scattering (LRS).3 Local roughness scattering (LRS) Any deviation from an abrupt dielectric/Si interface causes a change in the width of the quantum well. the correlation length of the roughness oscillations in the xy plane. ∆ the rms fluctuation in z from the mean position of the interface (z = 0) and Λ.This scattering mechanism is referred to as local Coulomb scattering (LCS) due to its proximity to the channel to distinguish it from remote Coulomb scattering (RCS) which is considered in section 2.5.6. Despite 40 years of research. Roughness is characterized by two parameters. it is fair to say that the morphology of the SiO2/Si interface is still under debate.5. If such roughness is located at random sites across the interface.38) 37 . 2. Interface roughness scattering is most effective at high Ninv/Eeff where carriers are confined close to the rough interface.

[36.39) Later Goodnick et al. The exponential random potential is given by[36]. first proposed by Ando et al. they show that the Gaussian surface is compatible with the dimensions of lattice steps at the Si<100> surface. U (q ) 2 = π∆2 Λ2 q s2 E F2 (1 + 2 N dep N inv ) 2   Λ2 q 2 1 +    2 3  2   (2. They argue that the choice between the two spectral shapes cannot be made relying on high resolution TEM and AFM measurements.[41] studied roughness at a (100) SiO2/Si interface using TEM (transmission electron microscopy) and found that an exponential model was more suitable. Even if the roughness was measured accurately. 43] put forward the argument that physical characterization techniques are not sensitive enough to measure interface roughness. They argue that it is unlikely that the potential perturbing the carrier motion at the interface can feature such high- 38 . 38. 42]. in the absence of actual structural data. By generating 1D random spatial patterns from Gaussian and exponential models.A Gaussian morphology. was adopted as the standard means of characterising roughness.[20]. The Gaussian random potential is[40] U (q ) 2 = π∆2 Λ2 q s2 E F2 (1 + 2 N dep N inv ) e −q Λ 2 2 2 4 (2. Pirovano et al. the surface described by the exponential model shows spikes on distances shorter than the lattice steps.40) Both models continue to be used and intermediary models have been proposed by some groups[36. On the contrary. such microscopy techniques are not able to sense the surface potential which enters into scattering calculations.

z i )]2 = N a   2ε Si ε 0 q  2 (2.45) (b + q )2 q(b − q ) a1 = (b + q ) (2. a Gaussian model is used in this work. 2 U (q )  e2 1   [Fi (q. F (q. the random potential for IIS is. 2. Similar to LCS. We adopt the model used by Ando et al..42) where P(z i ) = a0 = a1 = b3 (b − q ) 3 ( [e 2q 3b 2 + q 2 − qz ( ) ] − a 0 + a1 z + a 2 z 2 e −bz ) (2.4 Ionised impurity scattering (IIS) The ionised donors or acceptors that make up the depletion region in a MOSFET scatter carriers in the inversion layer via the Coulomb force.41) this time we assume a uniform ionised doping concentration. Following the argument of Pirovano et al.[20] and Karavolas[44]. z i ) = 1  ε SiO 2  1 ε 1 +  P( z i ) + 1 − SiO 2 2 ε Si  2 ε Si  −qzi  P0 e  (2.46) 39 .frequency components. thereby concluding a Gaussian model is more accurate. originally formulated by Stern and Howard[18].43) 2 (2. Na (or Nd for a pMOSFET) and use the form factor.5.44) (b + q ) 3 4bq(b − q ) (2.

5. carriers can rearrange themselves.5 Screening In this section we define the screening parameters used in the previous sections. The dielectric function is given as ε (q ) = 1 + qs F (q )[1 − G (q )] q (2.P0 = b3 (2.50) F(q) is the form factor to take account of the finite extension of the electron wave function from the interface. lowering their overall energy and so screen these fluctuations. m = scat3 τ k πh 1 ∫ 2π dz ∫ dθ U (q ) 0 0 ε (q )2 Wdepm 2 (1 − cos(θ )) (2.49) where qs is the Thomas-Fermi screening wave number qs = g v m scat e 2 2πε 0ε Si h 2 (2.51) . Although perturbations in the potential lead to scattering events. F (q ) = 1  ε SiO 2  9 q 3 q 2  1 + 1 +  + 2  ε Si  8 b 8 b 2   q 1 +   b 3 + 1  ε SiO 2 1 − 2  ε Si  q 1 +   b    6 G(q) is the local field correction in Hubbard’s approximation. 40 (2.47) (b + q )3 We now not only integrate over θ but over Wdepm.48) 2.

When a dielectric is placed in an electric field. The review papers by Robertson[47-48] also provide a good comprehensive overview. 2. The dielectric constant. of an insulator is a relative measure of its polarisability which depends upon its composition and crystal 41 .1 Origin of permittivity A dielectric is an electrical insulator that may be polarised by the action of an applied electric field.G (q ) = 1 2g v q (q 2 +k (2. In this thesis εox is used to denote the permittivity/dielectric constant of a dielectric in general (be it SiO2 or a high-κ dielectric). This creates an internal electric field which opposes the applied field inside the dielectric.6. as in a conductor.positive charges are displaced in the direction of the field and negative charges displaced in the opposite direction. For a detailed discussion on nearly every aspect of SiO2 and high-κ gate dielectrics. the reader is referred to the excellent books by Huff and Gilmer[45] and Houssa[46]. The ‘κ’ or ‘K’ in high-κ dielectric are just alternative notations of permittivity.6 MOS dielectrics Presented in this section is a brief review of gate dielectrics/oxides pertinent to the results in chapter 6. but only slightly shift from their average equilibrium positions causing polarisation. electric charges do not flow through the material.52) 1 2 2 F ) 2. or permittivity.

Metal-oxides have a much higher static dielectric constant compared to SiO2 which was historically used for the gate dielectric. due to highly polarisable (soft) metal-oxygen bonds.[16] Each of these contributions takes a finite amount of time to respond to the applied field. This yields a large difference between ε ox0 and ε ox∞ .5. As a result it is usually much less than the static response and not too different from that of SiO2. The electronic contribution arises from the displacement of the electron shell relative to a nucleus. Insulators. ε ox∞ are quoted for a dielectric. The static dielectric constant of a metal oxide results from the contribution of ionic and electronic polarisation. The ionic contribution comes from the displacement of a charged ion with respect to other ions. Electronic polarisation is roughly inversely proportional to the square of the band gap. Thus if the field is oscillating. In contrast. Typically a static (low frequency) dielectric constant. the contribution of each of these polarisabilities depends on frequency therefore so does the permittivity. SiO2 has weakly polarisable (hard) covalent silicon-oxygen bonds resulting in its small static dielectric constant of 3. have large band gaps so the large dielectric constant stems from a larger ionic polarisation. ionic and dipolar. The total polarisability may usually be separated into three parts: electronic. by definition.structure. The dipolar polarisability arises from molecules with a permanent electric dipole moment that can change orientation in an applied electric field. The optical dielectric response is mainly electronic since heavier and slower ions cannot respond fully at high frequencies.9 and optical dielectric constant of 2.[49] 42 . ε ox0 and an optical (high frequency) dielectric constant.

1 eV thereby providing a high barrier for electrons and holes.11 Conduction and valence band offsets of various dielectrics with respect to Si bandgap. Unfortunately. 43 . the band gaps of many of the high-κ oxides of interest are considerably less than the 9 eV of SiO2 as shown in Figure 2.2 Dielectric requirements SiO2 is an excellent gate insulator as it has a band gap of 9 eV that is well centered around silicon’s bandgap of 1.2.[47] Figure 2.11.12. The barrier heights (band offsets) at both the valence and conduction band must be over about 1 eV to prevent significant gate leakage current. (sourced from [50]) Unfortunately band gap tends to vary inversely with κ as shown in Figure 2.6.

there are a number of other requirements for the dielectric to act as a satisfactory gate insulator.. In addition to having a high enough permittivity and sufficiently large band offsets to act as barriers for electrons and holes. The wafers are held at that temperature for ~5 seconds and then cooled rapidly.S. These dopant ions do not participate in conduction of carriers until they are activated (made to occupy substitutional lattice sites). to prevent the degradation of MOSFET electrical properties (i. it may also have to withstand high annealing temperatures necessary for dopant activation. 44 .[45] In the standard CMOS process flow. Activation is done via a process known as rapid thermal annealing (RTA).Figure 2. Vt instability). S. The wafers are placed in a furnace that reaches temperatures of 1000 °C-1050 °C in seconds. after the gate dielectric is grown or deposited there are various ion implantation steps in which dopants are implanted into the silicon substrate. Depending on the process flow. It must be thermodynamically stable in contact with the substrate and have a low defect density not only within the material but also ideally at its interface with the substrate and gate.12 Band-gap energy as a function permittivity for a range of dielectrics [48]. µ.e.

This can be intentional or unintentional. tox and permittivity by C ox = ε ox ε 0 (2. The CET of a dielectric is often quoted as it is calculated from a capacitance measurement of a MOS capacitor or MOSFET in strong inversion. This is called the equivalent oxide thickness (EOT).53) t ox i.κ material in consideration.6. Accounting for the inversion layer not being confined exactly at the interface.3 Capacitance of high-κ dielectrics Cox is related to its thickness. Many high-κ dielectrics have thermally unstable interfaces with Si which results in the thin interfacial layer growing between the high-κ layer and the silicon. 45 . respectively. When dealing with high-κ dielectrics it is more instructive to interpret EOT as the thickness of SiO2 that would be required to achieve the same areal capacitance as the high. This is caused by the diffusion of oxygen from the high-κ oxidising with the silicon substrate during the activation anneal rather than during the high-κ deposition. EOT = ε SiO 2 t High −κ (2. we get the capacitive equivalent thickness (CET). an oxide with a higher dielectric constant allows the use of a physically thicker layer but with the same capacitance per unit area as that required by SiO2.e.[45] An interfacial layer of SiO2 often exists between the Si channel and the high-κ layer.2.54) ε High −κ where thigh-κ and εHigh-κ are the thickness and relative dielectric constant of the high-κ material. Oxygen diffusion can be reduced by alloying the high-κ with SiO2 as the silicon atoms are covalently bonded to oxygen.

e.5). 1 1 1 = + C ox C SiO 2 C High −κ (2. interfacial layers are undesirable as they lower the achievable oxide capacitance i.[54] Like SiO2.4 Hafnium based dielectrics There has been a world wide consolidation towards hafnium based dielectrics.6. t t High −κ EOT = ε SiO 2  SiO 2 + ε  SiO 2 ε High −κ     (2. In hafnium oxide. it is interesting to observe from Figure 2.56) Despite the fact that it increases the EOT. its thickness can be well controlled and ensures a good quality (low roughness and interface charge) channel interface. hafnium oxide becomes crystalline or poly-crystalline at low temperatures (the exact 46 . For that reason a SiO2 interfacial layer can intentionally be thermally grown prior to the high-κ deposition.55) From this we can derive an expression for the EOT of this composite gate stack. indicating that it will insulate holes better than electrons. an interfacial layer does have some beneficial qualities with regard to carrier mobility in the device channel. However. From a scaling point of view.11 that the barrier for holes is over double that for electrons. hafnium based dielectrics are amorphous.6. The thermal growth of SiO2/Si is well understood.Addition of nitrogen can also be used to lower diffusion rates further. A SiO2 layer separates the channel from the high-κ dielectric which reduces the influence of the various scattering sources in the latter [51-53] (detailed in section 2. the overall oxide capacitance consists of the two dielectrics in series. 2.

but its dielectric constant decreases.6 0. grain size and orientation vary randomly throughout the film which can lead to significant variations in κ.[47. extracted from the Clausius-Mossotti relation (adapted from [53]) The addition of nitrogen to hafnium silicate (HfSiON) increases both the dielectric constant and its crystallisation temperature.value Hf1-xSixO2 Figure 2.temperature is dependent on the annealing ambient and other processing conditions).0 0.[47. high-κ dielectric or interfacial layer can diffuse down to the channel 47 .13 Static and high frequency dielectric constant of Hf1-xSixO2 as a function of x.13. 25 20 15 Static 10 High frequency 5 0 0. in that it’s band-gap increases.[53] The crystallisation problem can be overcome by alloying hafnium oxide with SiO2.0 x . to form hafnium silicate (HfSiO2) which retains the stability against crystallisation close to 1000°c. By doing this the material becomes more SiO2 like. In addition. 55] The static and high frequency dielectric constant of hafnium Clausius Mossotti dielectric constant silicate as a function of silicon composition is shown in Figure 2. Poly-crystalline dielectrics are undesirable as they are composed of grains whose boundaries serve as high leakage current paths.2 0. 56] However nitrogen incorporated into the gate.4 0.8 1.

detailed below. the static dielectric constant of high-κ dielectrics results 48 . which provide excellent channel interface quality. Various studies. remote Coulomb scattering and remote roughness scattering. degrading device characteristics (e. These sources of scattering are termed remote as they are separated from the channel by the interfacial layer. i. However.14) and (2. Remote phonon scattering (RPS) Fischetti et al. are presently lower than those with just a SiO2 dielectric. The basic concepts are briefly reviewed here. particularly at low to mid Eeff. electron mobility in devices with hafnium based dielectrics and interfacial layer thicknesses of less than 2 nm. mobility.e.g. The relative contribution of each is currently under debate.5 High-κ mobility degradation From equations (2. Thus device engineers are faced with a trade-off between high on current and scalability.[57] A major objective of current research is to understand how this can be rectified.[57-61] 2. an increase in Cox due to a high-κ dielectric should result in an increase in on current.15). thus a more conductive channel is achieved. for a given supply voltage a greater inversion charge. generating a large number of interface states.[49] studied the role of phonon scattering from high-κ dielectrics on electron mobility in detail. As mentioned previously. have shown each mechanism to be significant 2 nm from the channel.interface during dopant activation. remote phonon scattering. Three scattering mechanisms are thought to play a role. 1/f noise).6. This is the case even with intentional thermal SiO2 interfacial layers.

this also results in a small difference between ε ox0 and ε ox∞ and so in a small electron/phonon coupling strength. Secondly the hard bonds results in large LO and SO phonon energies.58) It is important to note in equation (2.57). the large difference between ε ox0 and ε ox∞ in high-κ dielectrics. 1 ω SO  ε 0 + ε Si∞  2  = ωTO  ox∞ ∞   ε ox + ε Si  (2. The coupling strength is proportional to  1 1 hω SO  ∞ − ∞ ∞ 0  ε Si + ε ox ε Si + ε ox    (2.57) where ε si∞ is the optical permittivity of silicon and ω SO is the angular frequency of the interface longitudinal-optical phonon. This triggers frequent emissions and absorption processes by thermal electrons. Although the hard bonds of SiO2 result in an undesired small static dielectric constant.primarily from ionic polarization. Associated with these bonds are low-energy lattice oscillations (and associated phonons). ω SO is calculated from the dominant transverse-optical (TO) phonon modes in the dielectric and can be approximated by. Thermal electrons cannot emit excitations of such large energy 49 . due to highly polarisable (soft) metal-oxygen bonds. Electrons in the inversion layer can couple with surface optical (SO) modes arising at the dielectric/silicon interface from the longitudinal-optical (LO) modes of the dielectric. which are “optical” in nature due to the ionic character of the atomic bonds. results in a large coupling strength therefore large degradation of mobility.

Thus in MOSFETs with a SiO2 gate dielectric.[51.[57.[53. The reduction in coupling strength is accompanied by increasing phonon energies which together serve to reduce the mobility degradation. Watling et al.13.[49. 69] Electrostatic interaction with these charges 50 .[68]. For HfSiO2 the difference between ε ox0 and ε ox∞ decreases with decreasing Hf composition as shown in Figure 2. 62-63] Remote phonon scattering is reduced further with increasing SiO2 interfacial layer thickness for two reasons 1)The scattering potential decreases with increasing distance from the high-κ dielectric by a factor e − qtSiO 2 2)The turning on of SiO2 SO modes thereby decoupling the phonons in the high-κ and electrons in the channel. dipoles at the HfO2/SiO2 interface are formed by diffusion of oxygen atoms from HfO2 to SiO2. 53] Remote Coulomb scattering (RCS) Charge densities ranging from 6x1012 cm-2[64] to 7x1013 cm-2[51] at the high-κ/interfacial SiO2 layer have been reported in hafnium based gate stacks.[53] observe less than a 5% reduction in drive current when including this in the simulation of such devices. this type of phonon scattering is negligible. These have been attributed to induced dipoles (remote dipole scattering).and at room temperature there are too few thermally excited phonons to be absorbed. 65-67] In the model proposed by Kita et al. Diffusion of any nitrogen in the gate stack also creates fixed charge. This leaves oxygen vacancies in the HfO2 (positive charge) and excess oxygen in the SiO2 (negative charge). driven by the areal density difference in oxygen atoms.

a gate electrode of large work function. some groups have developed models of roughness from the highκ/interfacial oxide interface[72] and the gate/high-κ interface[73] suggesting it may degrade mobility. screening by inversion charges reduces the scattering potential. The work function of the gate electrode is largely responsible in setting Vt. is desired.modifies the electrostatic potential seen by carriers in the channel. a gate electrode of low work function. thus only a small Vgs is needed for inversion. bending the conduction band at the surface towards the Fermi level. However currently there is no publication that has convincingly shown that this is important by means of analysis of experimental data. equal to the valence band edge of 51 . Akasaka et al.[71] devlop a model for remote roughness scattering in poly-Si/SiO2/Si n-MOSFETs. Gamiz et al. Since the advent of high-κ gate stacks.[69] also report significant charges at the gate/high-κ interface. For a pMOSFET. Vt should be scaled down accordingly to ensure the on current is not reduced. For an n-MOSFET. equal to the conduction band edge of Si (~4. This depletes the substrate. Remote roughness scattering (RRS) Li et al. The resulting scattering has been shown to degrade electron mobility particularly at low to mid Eeff. With increasing Eeff. 2.[70] first developed an analytical model of remote roughness scattering from the metal/oxide in Al/SiO2/Si n-MOSFETs.7 Gate electrode As device dimensions and supply voltages continue are scaled down.05 eV).

poly-Si has limited carrier concentration (1019 – 1020 cm-3). The net result is an increase in EOT reducing MOSFET scalability. TaN. to set the work functions as required. is desired. Such “band edge” gates are necessary for a low Vt and S. TiN. poly-Si gates become depleted. easily deposited. A metal gate has a much higher carrier concentration (~1022 cm-3) and so gate depletion is reduced. A metal’s work function depends on its alloy composition. 74] In the past.[48.and p-MOSFETs respectively.S.17 eV). gate electrodes were made from polycrystalline Si (poly-Si).Si (~5. carbides and silicides of transition metals. in bulk MOSFETs. Work function stability after the RTA has been a major issue leading to intensive research into compounds with high thermal stabilities such as nitrides. effectively adding another capacitance in series with the oxide. There are many metal candidates but no world wide consensus as to which metal should be used as the parameters that influence the work function are complex. However. for n. metal gates are also effective for screening the soft optical phonons in high-κ dielectrics.[78-81].[75-77] showed that poly-Si gates are incompatible with high-κ dielectrics. and compatible with SiO2 and the process flow. HfN are all stable enough but have mid-gap work functions. thereby reducing remote phonon scattering. although degenerately doped. Hobbs et al. This is Si degenerately doped n-type or p-type. Most metals react with the 52 . In inversion. Furthermore. Poly-Si has the advantage that it is refractory. how it’s deposited and the underlying high-κ composition.

During the RTA.[68. 82-83] Another approach (now being used by Intel) is to employ a “gate last” process where a “dummy gate” is deposited on the high-κ dielectric. However in a real MOSFET.[7. the depletion regions at the source and drain extend into the channel region.8 The short channel effect The short channel effect is the decrease of the MOSFET Vt as the channel length is reduced. the RTA then applied.underlying oxide causing the effective work function of the gate stack to migrate towards the mid-gap of silicon during the RTA. the source and drain 53 . A final solution is to use a mid-gap metal gate for both nand p-MOSFETs. When deriving Vt for an ideal MOSFET in section 2. the metal does not experience the high temperature anneal but the process is more complicated and costly.[2] This is important as it is hard to control channel lengths precisely due to process tolerances.10). thereby relaxing the band edge constraint. Al2O3 or La2O3 for p-MOSFETs and nMOSFETs respectively).1 it was assumed that the depletion charge was balanced by equal but opposite charges in the gate.9 and 2. 2. Statistical variations in channel lengths then lead to problems with Vt control. and control Vt using silicon on insulator (SOI) and/or multiple gate technology (sections 2. these caps are doped into the high-κ dielectrics forming dipoles at the interface which modulate the effective work function of the gate stack.g. Providing the channel is sufficiently long. 84-85] Obviously with this approach. onto the high-κ dielectric.[54] One approach to tune the work function is to deposit capping layers (e. the dummy gate removed and then the band edge metal gate deposited.

54 . With increasing Vds. If the source and drain junction depths were equal to the inversion layer thickness. Thus the source-channel potential barrier is lowered below the built in potential resulting in significant drain leakage current with the gate unable to shut it off. Thus the MOSFET can be abruptly switched off. the reverse-biased depletion region at the drain extends further into the channel area and the gate controls even less depletion charge. the gate would retain complete control of the channel.depletion regions only occupy a small fraction of the entire channel and Vgs controls essentially all of the depletion charge. When Vds is sufficiently high or channel length sufficiently short. Control of the channel by the gate can be retained by not only increasing Cox but by proper scaling down of the source and drain junction depths and scaling up of the substrate doping concentration. In addition. further lowering Vt. however carrier mobility is degraded due to increased number of ionised impurities and increased vertical electric field. As the channel length decreases. Increasing the doping concentration reduces the depletion region widths. Less gate charge is now required to invert the channel. the fraction of charge controlled by the gate decreases. Vt is increased. the drain depletion region merges with the source depletion region. resulting in a lower Vt. However achieving such ultra-shallow junctions is limited by diffusion of the source and drain dopants.

9 Silicon on insulator (SOI) technology The short channel effect can be reduced by fabricating MOSFETs on a silicon film atop a ~100 nm to 400 nm thick buried insulating substrate. the most suitable techniques to manufacture SOI substrates are oxygen-ion implantation (SIMOX) into a Si wafer and wafer bonding techniques (e. The BOX restricts the depth of the source and drain depletion regions thus reducing their influence on the channel. but also relaxes the need to scale Cox so aggressively. If the neutral region in a PDSOI MOSFET is connected to ground by a substrate contact. known as a buried oxide or BOX (typically SiO2).g. If the neutral region is left floating. This not only allows a low substrate doping concentration. it can become charged causing the properties of the device.2. tSi > Wdepm (a partially depleted SOI MOSFET (PDSOI)) and MOSFETs where the silicon can be completely depleted tSi <Wdepm (fully depleted SOI MOSFET (FDSOI)). NanoCleave®. such as Vt. ELTRAN®). tSi and the doping concentration of the silicon film above the BOX. to be dependent on the history of its 55 . The silicon film forms the substrate of the MOSFETs. promoting a high carrier mobility. smart cut®. The BOX also has the benefit of reducing the source to substrate and drain to substrate junction capacitances which translates to faster MOSFET switching. The characteristics of an SOI MOSFET is dependent on the thickness. For VLSI applications. Two types of MOSFET can be distinguished: MOSFETs in which the silicon is never completely depleted i. the characteristics of the device will be exactly the same as a bulk MOSFET.e. AcuThin®.

the expression for Vt is very similar to the bulk MOSFET. and neglecting interface charge at the Si/BOX interface. i. [90] The increased control of the channel by the gate can be understood by comparing the distribution of depletion charges in long channel and short channel bulk and FDSOI MOSFETs as shown in Figure 2.[89] Vt = V fb + 2ψ b + eN a t Si C ox (2.[88] The physics of FDSOI MOSFETs is considered from now on.operation. The use of a mid-gap gate sets Vfb to 0 V assuming no charges in the dielectric. theoretically a very low Vt can be achieved using FDSOI technology.[87] These effects complicate design and require greater design margins. Reducing tSi reduces Qdep.e.4)).14. Providing Cox>> CBOX.[86] In addition the device will present a host of “floating body effects” such as the kink effect and the presence of a parasitic open-base bipolar transistor between the source and drain. FDSOI minimises floating body effects therefore is considered more viable. Qdep = eN a t Si (2.60) Typically the substrate receives no intentional doping which minimises ψ b (equation (2. The areal depletion charge in a FDSOI MOSFET is given by.59) Thus either a low substrate doping and/or a thin Si film is necessary to ensure the MOSFET is fully depleted. 56 .

[93. where the lengths of the upper and lower base are almost equal to the channel length. However in a short channel FDSOI MOSFET. carriers in ultrathin SOI are prone to self heating due to the low thermal conductivity of the 57 . ensures the gate will control a greater fraction of the channel. gate depletion charge retains its trapezoid shape due to the restriction of the source and drain depletion regions by the BOX. In addition. 95-97] However fabricating uniform ultrathin films is a challenge. It is obvious that reducing tSi. In a short channel bulk MOSFET the area is now a triangle.[91-93] A simple scaling rule for FDSOI MOSFETs demands t Si 4 < L to achieve good turn-off characteristics.[94] This has led to extensive research into ultrathin SOI MOSFETs. the depletion region controlled by the gate can be represented by the area of a trapezoid. In the long channel bulk MOSFET.14 Charge distribution in long and short channel bulk and FDSOI MOSFETs.Figure 2.

Eventually ultra-thin films will no longer adequately suppress short channel effects as channel lengths decrease. the drain electric field component through the BOX will cause appreciable barrier lowering near the source. Cristoloveanu and Li[105] and Marshall and Natarajan[106]. Simulations by Koh et al. Furthermore there is a limit on the scalability of FDSOI MOSFETs. the reader is referred to the books by Colinge[104]. The basic principle is shown in Figure 2. 58 . 2.1 Channel control By using additional gates.[97] show that using a thick BOX with a very low dielectric constant. 103] However reducing the thickness of the BOX increases the source and drain junction capacitance therefore the capacitive load of the device.10.15 which shows how the addition of a second gate further suppresses the source and drain depletion regions.[98-99] This degrades carrier mobility and the reliability of the device. allowing further scaling.[100-102] This field can be reduced by decreasing the thickness of the BOX and using a highly doped substrate or an underlying ground plane to terminate the field lines. increasing the subthreshold slope and off current. the electrostatics of the channel can be controlled much more effectively than in the FDSOI MOSFET allowing for further scaling.[101] and Wong et al.[92.BOX. reduces the drain electric field through it.10 Multiple gate technology 2. Under high Vds. For further information on nearly every aspect of SOI technology and its applications.

Adequate suppression of the short channel effect and off state leakage current requires that W fin ~ L 2 .Figure 2.10. This notion has given birth to a host of three-dimensional multi-gate MOSFETs which include a range of double-gate.15 Cross section of a fully depleted double-gate MOSFET. the finFET has emerged as the most promising candidate to replace the planar MOSFET due to processing simplicity.2 The finFET From the range of multi-gate MOSFETs. The basic fabrication process is described in section 6. triple-gate and surrounding-gate MOSFETs. It is desirable for Hfin to be as large as possible to maximise 59 . It follows conventional MOSFET processing and can be fabricated in any Si pilot line. Hfin and Wfin is the fin height and width respectively.61) where n is the number of fins.2. all straddled by a single gate line. The electric fields (arrows) and corresponding depletion charges from both gates and the source and drain are shown. with the latter theoretically providing the best possible control of the channel region. thus its effective width is given by. Weff = n(2 H fin + W fin ) (2. A finFET can have multiple fins in parallel.[103] 2.

60 .Weff. 2. making it an unlikely option in VLSI circuits. a finFET’s sidewalls and top surface lie in the (110) and (100) planes respectively when the device is oriented parallel or perpendicular to the wafer flat of a standard (100) wafer. Thus for the 22 nm node and beyond. Id therefore flows along the <110> direction.16.10. The electron mobility could be maximised by rotating the fins 45° as then the sidewalls would be in a (100) plane. Due to their vertical nature. the hole mobility is maximised but the electron mobility is minimised.3 FinFETs in inversion The proximity of a second gate can modify the electrostatics significantly and therefore the inversion charge distribution compared to a bulk MOSFET. In this orientation. The basic principles are most easily illustrated by considering a double gate finFET. therefore Id. The corresponding change in the energy band diagram is shown in Figure 2. the finFET can essentially be treated as a fully depleted double gate device where Id flows predominantly along its sidewall surfaces. However this incurs an area penalty on the wafer and increases complexity in circuit design. Consider the effect of decreasing Wfin whilst keeping Vgs constant.

When W fin < 2Wdepm . The voltage drop inside the silicon. Providing W fin > 2Wdepm a neutral region exists between both the depletion regions separating the channels.16 Energy-band diagram of two double-gate n-finFETs of different Wfin in inversion (Vgs > 0 V applied to both gates). increases with decreasing Wfin. Qg is fixed. increasing the electron concentration throughout the fin. the potential at the middle of the fin. The band diagram of a bulk n-MOSFET is shown for comparison.) As Vgs is fixed. Vox and therefore ψs remain constant. the fin becomes fully depleted and Qdep decreases linearly with Wfin. electrostatics requires that Qinv increases by the same amount to restore the total charge. ψc .Figure 2. As the charge on the gate. (The electric field lines from Qg now uncompensated by Qdep are paired with extra inversion charges. ψs-ψc which is mainly across Qdep will reduce with 61 .

the band bending ψs. the potential in the centre of the fin. ψc will increase. For small Vgs.i  W  fin     2 (2.62) 8ε 0 ε Si Therefore. The onset of volume inversion in a finFET depends not only on Na and Wfin. E conf h2 = 2mconf  π . The position of these energy levels above the conduction band edge is given by. as shown in Figure 2. Consider a finFET such that the electron wave functions are confined by the dielectric band offsets of the two sidewall interfaces.17.ψc . Qinv is no longer confined at the interfaces. The relationship of this voltage drop with Wfin and Na is given by. but also Vgs.decreasing Wfin.63) 62 . [107] ψ s −ψ c = 2 eN aW fin 8ε 0 ε Si = QdepW fin (2. As the Fermi level is constant for all Wfin.e. A quantum mechanical description is necessary in this case. increased ψc means increased electron concentration (Qinv) throughout the fin i. is small enough that the two sidewall interfaces and conduction band edge create a square quantum well whose eigenenergies are well separated from one another (in contrast to the triangular well of a bulk MOSFET). This is known as volume inversion.

whose wave function peaks at the middle of the well. As Vgs (therefore ψs-ψc) increases. The electron concentration is proportional to ψ(z)2. Further increase of Vgs (ψs.ψc) causes the conduction band edge to become strongly parabolic and the energy levels to become degenerate through pairing.[104] Volume inversion is maintained for higher Vgs 63 . weak parabolic and strong parabolic potential wells formed by the two dielectric interfaces and conduction band edge in a double gate finFET. etc). ψ(z) in square. (adapted from [104]) In this instance. and thus volume inversion occurs. surface inversion now occurs.17 Four first energy levels and two first wave functions. The wave functions now peak close to the interfaces. This change in shape of the well causes the energy levels to superimpose and shift up and pair (E1 with E2. the lowest sub-band is predominantly occupied.17). i. E3 with E4.e. resulting in the wave functions peaking closer to the interfaces. Note sub-wells are created at both interfaces in the strong parabolic case.Figure 2. confining the lowest energy states. the conduction band edge becomes more parabolic (shown in Figure 2.

Simulations by Gamiz et al. the wider the separation between eigenenergies and the higher the value of the lowest sub-band energy.[114] show the reduction in confinement due to volume inversion reduces bulk phonon scattering.10. typically 10 nm. As the sub-band energies. carrier scattering is reduced. Since the interface roughness 64 . Coulomb scattering from the BOX interface may also be significant when tSi < 10 nm. a higher Vgs is necessary for inversion. is further from the Fermi level. Vt starts to increase instead of decreasing.[113] For a finFET or double gate MOSFET operating in the volume inversion regime. 2. In an SOI n-MOSFET. The smaller Wfin. Thus the classical analysis of Vt is no longer valid.by decreasing Wfin.10.ψc is reduced with decreasing Wfin (equation 2. importantly the lowest sub-band energy.) 2. Depending on the interface charge density.62) the well retains its square shape.4 Confinement effects on Vt When Wfin or (tSi in a SOI MOSFET) is thinner than a critical value. (As ψs.5 Carrier mobility in finFETs Volume inversion Carrier mobility in SOI MOSFETs and double gate MOSFETs/finFETs has been intensively investigated.[108] This is due to the strong energy quantisation between the two dielectric interfaces which effectively increases the Si band-gap. bulk phonon[109-110] and interface roughness[111-112] scattering rates increase for tSi less than 20 nm and 10 nm respectively.

This increases the energy split between the LH and HH sub-bands reducing scattering between them. 65 . increasing the already high mobility as compared to the (100) orientation. uniaxial compressive strain along the <110> direction on the (110) orientation is the best configuration. interface roughness and Coulomb scattering are also reduced.[24] Thus the worst current flow direction can be converted into the best direction. This not only lowers the ∆2 sub-bands which exhibit mtran = 0. 119] Implementing these strains into the finFETs sidewalls to boost the poor (110)/<110> electron mobility and provide further enhancement to the hole mobility have been hot topics in recent years. For hole mobility.perturbation potential and Coulomb potential are larger near the interfaces and decrease towards the center of the channel. The most effective strain configuration for electrons is uniaxial tensile along the <110> direction on the (110) orientation. but warps the ∆2 sub-band energies reducing mtran and increasing mconf.[115-118] Strain technologies Straining silicon is an effective way to engineer its band structure and enhance the carrier mobility. This results in comparable mobility to that on the (100) unstrained orientation. Current methods utilize strained substrates (global strain).190m0.[35.

Lateral strain relaxation is performed during patterning resulting in uniaxial compressive strain[121.[125-126] For p-finFETs. • a biaxial (2D) tensile strained SOI substrate is used as the starting wafer. 131] and SiGe source and drains[127. these techniques differ. SiN.[141] 66 . 132-133]. has the advantage of applying stress. understanding the stress transfer is non-trivial. Since the required stress directions are opposite for n.g. recently employed by Intel[7]. due to the 3D nature of a fin. deposition method and temperature.or individual stressors for each finFET (local strain). without requiring any additional processing steps.[135-140]. The strain perpendicular to the fins is relaxed during fin patterning resulting in uniaxial tensile strain (the lateral strain relaxation technique)[120-124] • local strain techniques consist of tensile stress liners. It is known that a thin metal layer intrinsically induces a certain amount of stress depending on its thickness. 128-129. the effect of different stress distributions on electron mobility has only recently been understood. Furthermore. For n-finFETs. However. 130] • local strain techniques consist of compressive stress liners[120. Thus its implementation into finFET technology is of great interest. • a biaxial compressive strained SiGe OI substrate is used as the starting wafer. e.[134] A stressed metal gate electrode. 125-129] and SiC source drains. deposited over the gate[120.and p-finFETs.

[132. source drain engineering is being researched vigorously. 142-146] 67 . As a result.10.2. This reduces the effective Vgs therefore Id and has long been recognized as a performance limiting bottleneck in finFETs.6 Fin access resistance With decreasing Wfin access resistance increases due to the reduction in cross sectional area.

For additional information.1 Measurement apparatus All measurements were performed using a Desert Cryogenics probe station capable of being cooled to 4. The probe needles are operated with three micrometers each. Electrical connections to a wafer are made via a substrate chuck on which the wafer sits and four tungsten probe needles (of radius 10 µm).Chapter 3 : Electrical Characterisation Techniques This chapter describes the experimental apparatus and interpretation of the electrical measurements that were employed to characterise the FETs in this work.2 K. The range of motion in each direction is large enough to allow any point on the substrate chuck (3 cm x 4 cm) to be reached by any of the four probe needles. From measurements of current and capacitance as a function voltage. A good electrical contact between wafer and chuck is achieved by sticking the back of the wafer to a thin piece of copper using silver conductive paint. a vast amount of information regarding the device operation can be extracted. The description of the measurement apparatus is a condensed version of that written by Beer.[147] The extraction techniques are abridged versions from Schroder[148] and Nicollian and Brews[14]. 3. allowing movement on all axes. and then taping the 68 . Further information can be obtained by measuring over a range of temperatures. the reader should consult these texts.

Temperature sensors are present both at the shield and substrate chuck. Probe needles are thermally connected to both the shield and the substrate chuck with thick copper braids to ensure that the probes cool somewhat before having contact with the wafer. automatically using a negative feedback algorithm to achieve the user-specified temperature. A glass window is present above the wafer. to allow the probe needles to be aligned with a microscope situated above. The shield window is lead plated so not to compromise the electrical shielding. The internal pressure of the dewar (0. The region around the wafer is kept free of electrical noise by a shield. The shield in turn is housed in a completely closed chamber as it needs to be under vacuum when cooling for thermal insulation and removal of moisture from the chamber environment. in the shield and the vacuum chamber. Probe arms are able to move while maintaining vacuum with bellows. This also controls two heaters. which expand and contract thus keeping the chamber sealed. A vacuum of ~10-6 mbar is achieved with a two-stage pumping system consisting of a rotary roughing pump and a small turbo pump. where it evaporates and flows through into the low temperature probe station.edge of the copper piece onto the substrate chuck.5 bar) pushes liquid up a transfer tube. It travels under the substrate chuck 69 . High quality connections and coaxial cable throughout the measurement system ensure that the signal is protected from interference right to the probe needles. Cryogenic liquid (nitrogen or helium) is contained in a closed dewar. which are monitored electronically by a Lakeshore 330 temperature controller. one under the substrate chuck and one under the shield. which the probe arms enter through metalbraided holes that maintain a closed conducting surface around the wafer area.

The currents in the source. a high flow rate is required and achieved using an Edwards 9 CFM rotary pump. Connections to a device are made by manipulating the micrometers. Once contact to a device is made. a constant bias to the drain is applied and the resulting drain current is measured. All Id-Vgs measurements were made using an Agilent 4156C parameter analyser.2 Current-voltage measurements “The most common measurement to perform on a MOSFET is an Id-Vgs sweep: a gate voltage is applied to achieve the off-state and incremented to the on state (negative to positive bias for n-MOSFETs). 3. To ensure the temperature remains stable at 4.”[147] 70 . electrically shielded environment.2 K. piece of equipment which has a programmable interface enabling measurements to be performed and saved efficiently. gate and substrate are measured in addition to the drain to check that the MOSFET is operating normally without excessive leakage.and back out to vent. The substrate and source are biased at 0 V. whilst monitoring the probe tips through a microscope. the viewport of the measurement chamber is covered to provide a dark. It also contains in-built integration options to minimise electrical noise. This is an extremely sensitive (minimum detectable current of the order of a fA).

G or a capacitor in series with a resistor. which is applied to the gate. the DC voltage is applied to achieve the off-state and incremented to the on-state. This operates by superimposing a small oscillating AC voltage on a DC voltage. Using a four terminal pair configuration. The conductance is thus measured together with the capacitance.1 is a block diagram showing the internal working of the LCR meter when using the parallel configuration. The capacitance i. The parallel configuration is usually chosen as it most closely resembles a MOSFET. 71 . drain or substrate is measured from which the capacitance and conductance are calculated (the conductance is discussed below). Figure 3.3. C in parallel with a resistor/conductance. The resulting AC current through the source. the change in charge in response to the AC voltage is thus calculated for each DC voltage. As for the Id-Vgs sweep. the LCR meter models the MOSFET as either a capacitor.3 Capacitance-voltage measurements Capacitance-voltage (CV) and small signal conductance-voltage (GV) measurements were made using an Agilent E4980A precision LCR meter.e.

The 90° phase separator then splits the current I into Ic’ and Ip’. (discussed in section 3. The microcontroller calculates C and G from Ic’ and Ip’ respectively. calculates the capacitance and conductance from Ic’. A microcontroller. Ip’. measured by the “low terminal”. which it passes through a phase separator where I is split into Ic’ and Ip’ which are 90° out of phase and in phase with the AC voltage respectively. 72 .1: Operation of the LCR meter modelling the MOSFET as a capacitor in parallel with a resistor. Ic is the displacement current through the capacitor also commonly referred to as the quadrature current component as it is 90° out of phase with AC voltage. I. The LCR meter measures the total current I.Figure 3. f of the AC voltage.4. AC and DC voltages applied by the “high terminal” and resulting current. Ip is in phase with the AC voltage and represents small signal energy losses due to changes in occupancy of bulk and interface traps.1) and also DC leakage current through the gate dielectric. Calculation of C and G requires accurate measurements of the individual currents Ic and Ip. the magnitude and frequency. running a feedback algorithm.

MOSFETs with ultrathin oxides suffering from very high gate leakage currents may require measurements at radio frequencies (RF CV). i. Measuring large area MOSFETs also minimises the influence of parasitic capacitances inherent in the device. the phase separator must be able to accurately separate Ic and Ip. 73 . Ic and Ip in general may not be clean sinusoidal signals but contain various harmonics and noise. substrate or contact resistance. source/drain. typically ≥1 GHz[149]. However a trade off is required as large devices exhibit higher gate leakage current which may reduce Rp to an unacceptable level. The LCR meter enables measurements with frequencies of 20 Hz – 2 MHz.Obviously for an accurate calculation of capacitance and conductance we require Ic = Ic’ and Ip = Ip’ respectively. Consequently. the amplitude of Ic must be sufficiently large as not to be masked by Ip to prevent noisy or distorted CV profiles. Rs may originate from a high gate.e.2. Thus large area MOSFETs and/or high measurement frequencies are needed. further necessitating high measurement frequencies. For an accurate measurement of capacitance. Furthermore. we require Rp>>Xc where X c = 1 jωC and ω = 2πf . Until now we have not considered the effect of series resistance Rs shown in Figure 3. In this work such measurements were not necessary.

If the device exhibits a high series resistance and gate leakage current. no easy solution is forthcoming.3. In the case where R p = ∞ (or G = 0) and Rs is non negligible.Figure 3. 74 .2 Parasitic resistance in series with the parallel equivalent circuit The LCR meter does not account for Rs in the parallel equivalent circuit so we must ensure Rs<<Xc//Rp so that Rs does not significantly reduce Ic and Ip leading to large errors in the calculations of C and G. A phasor diagram of the admittance of the parallel equivalent circuit is shown in Figure 3. If the parallel circuit is selected. then a low measurement frequency is necessary to ensure Xc is sufficiently high. the series equivalent circuit is best suited.

1) G For an ideal capacitor. Prior to measurements. G = 0 for an ideal capacitor and θ = 90°. A TestPoint program provides a user-friendly interface to the E4980A to specify measurement parameters such as measurement frequency of the AC voltage. only the displacement current exists) therefore θ = 90° . The phase angle (or loss tangent) is given by. which themselves exhibit a capacitance and resistance. G = 0 (i.e.3: Phasor diagram of the admittance of the parallel equivalent circuit. In research. tan θ = ωC (3. There is a built in function which determines correction parameters automatically. reducing θ. DC voltage range.Figure 3. devices are not optimised and high series resistances. interface trap densities and gate leakage currents are not uncommon. various corrections must be performed to take into account the position and length of the cables. time delays and signal averaging parameters. The 75 .

The C-V profile of an n-MOSFET is shown in Figure 3. Figure 3. Cit.5. interface trap and inversion capacitances respectively. This is measured by connecting the gate to the high terminal and the source. 3.4. Cacc. Cdep.1 Capacitance-voltage profile The equivalent circuit of a MOSFET is shown in Figure 3.4: Equivalent circuit of a MOSFET Cox.program graphs the capacitance and conductance measured as a function of DC voltage allowing the user to determine whether the measurement was successful.3. In a real MOSFET there will also be parasitic capacitances between the gate and source/drain and between the substrate and source/drain but for a large area MOSFET. 76 . accumulation. drain and substrate to the low terminal (2 terminal measurement). Cinv are the dielectric (oxide). these are usually negligible. depletion.

Figure 3.5: CV profile of a n-MOSFET. A: accumulation, B: depletion and C: inversion.

The total capacitance C is given by:
1
1
1
=
+
C C ox C acc + C inv + C dep + C it

(3.2)

Cinv and Cacc are the areal inversion and accumulation layer capacitances
respectively, Cdep is the areal depletion layer capacitance and Cit is the areal
capacitance of the interface traps. The effect of Cit on the measured capacitance is
considered in section 3.4.1. It should be noted that not all of these capacitances are
present at any one time. At point A in the figure, Vgs is negative and the MOSFET is
in the accumulation region, i.e. majority carriers (holes) in the p-type substrate
strongly attracted to the dielectric-semiconductor interface. The differential change
in voltage caused by the AC voltage, causes a differential change in charge on the
gate and also the accumulation charge. The large number of majority carriers screens
the dielectric interface from the substrate and the measured capacitance is Cox. (In the
equivalent circuit, Cacc >> Cox). As Vgs becomes more positive, the majority carriers
are repelled from the surface and a depletion region begins to form (B). The AC
77

voltage causes a differential change in the depletion charge i.e. depletion region
width. The measured capacitance is now the result of two capacitors in series; that
due to the dielectric and that due to the forming depletion region. Hence:
1
1
1
=
+
C C ox C dep
C dep =

(3.3)

ε 0ε Si

(3.4)

Wdep

where interface traps have been neglected. The measured capacitance now begins to
decrease. The width of the depletion region increases as Vgs is made more positive
until the band bending reaches the threshold inversion point, where minority carriers
(electrons) readily supplied from the source and drain, form an inversion layer (C).
The inversion layer screens the depletion region. The AC voltage causes a
differential change in charge on the gate and the inversion charge, thus the measured
capacitance is Cox. (In the equivalent circuit, Cinv >> Cox).

3.3.2 Split C-V
Since the inversion charge is supplied by the source and drain, and the depletion
charge by the substrate, individual measurements of the source and drain, and
substrate currents allow the inversion and depletion capacitances to be obtained
separately. This is known as the split CV technique and was proposed by
Koomen[150] and later used by Sodini et al.[151] in the extraction of carrier
mobility (chapter 4). Figure 3.6 and Figure 3.7 show the experimental setup and both
halves or branches of a split CV measurement.

78

Figure 3.6 Electrical connections to measure the split CV of a MOSFET.

Figure 3.7:Gate-channel and gate-body split CV profiles for an n-MOSFET.

The gate-channel branch of the capacitance, Cgc, is obtained by measuring, the
current through the source and drain, (I1 in the figure) with the substrate grounded.
In accumulation and depletion, the source and drains are electrically disconnected
from the channel and only the gate overlap capacitances are measured. In inversion,
the potential barriers between the channel and source and drain regions are reduced.
Minority carriers from the heavily doped source and drain regions now flow to the
channel to form the inversion layer and I1 registers a current. Although the minority
carriers are in abundance in the source/drain regions, they encounter a resistance on
79

their way to the channel. The channel resistance and the various capacitances limit
the frequency response of the minority carriers. Either the frequency of the AC
voltage must be sufficiently low or the channel length sufficiently short to ensure the
minority carriers have enough time to form the inversion charge. To avoid distortion
of the CV curve (seen by a shift of the capacitance particularly in weak inversion
where the channel resistance is high), the measurement frequency must satisfy the
criterion;[152]
f <<

1

(3.5)

2πτ ch

where τch is the channel time constant. From Haddara et al.’s analysis based on a
transmission line model [152], we can derive an equation based on measurable
quantities;
f <<

4I d
2πC gc 0Vds

(3.6)

where Cgc0 is the quasistatic or low frequency gate-channel capacitance (in Farads).
As a guide, for SiO2 dielectrics thinner than 2 nm, L should be 10 µm or less when
using a measurement frequency of 1 MHz.[153]
The gate-body branch of the capacitance, Cgb, is obtained by measuring the current
through the substrate, (I2 in the figure) with the source and drain grounded. In
accumulation, majority carriers from the substrate flow to the surface and in
depletion, majority carriers are repelled from the interface. Therefore a current I2 is
measured. In inversion, the depletion charge stops increasing as it rapidly becomes
screened by the inversion charge. Thus the depletion charge no longer responds to
the AC voltage (the inversion charge responds but is not measured in this
80

Rsub (or well resistance) hence the measurement frequency must satisfy the criterion. f << 1 2πτ sub = 1 (3. Traps change occupancy in depletion and weak inversion. The change in trap occupancy in response to the AC voltage.) In depletion. This results in a higher measured capacitance than if no traps were 81 . gives rise to an extra capacitance.7) 2πRsub C gb where τsub is the substrate time constant. Cit in parallel with Cdep as shown in Figure 3. 3. In weak inversion the minority carrier band edge (conduction band for an n-MOSFET) is closer to the Fermi level and communicates with traps. no current I2 is measured and the capacitance is zero. Accumulation and depletion carrier response is limited by the substrate resistance.configuration).4 Extraction techniques 3.1 Interface trap density We now consider the effects of interface traps/states on C-V and G-V measurements. (Band bending essentially fixed in strong inversion.4.4. Majority carriers have very short response times so this is only becomes an issue for RF CV measurements[149] or when measuring at very low temperatures where substrate dopants are starting to be frozen out. the majority carrier band edge (valence band for an n-MOSFET) is close to the Fermi level and exchanges carriers with traps. as the band bending changes in these regimes and the Fermi level is swept through the band gap.

10) C ox − C hf Cit is related to Dit by. therefore if the measurement frequency is high enough. Dit = C it e (3. which allow the density of interface traps.9) where Clf and Chf are the capacitances measured under low frequency (typically 100 Hz) and high frequency (typically 1-2 MHz) conditions respectively. Rearranging these equations and eliminating Cdep yields an expression for Cit: C it = C ox C lf C ox − C lf − C ox C lf (3. In depletion we have that Cacc = Cinv = 0 therefore: 1 1 1 = + C lf C ox C dep + C it (3. Dit (expressed in units cm-2eV-1) to be extracted. Cit only contributes if the time period of the AC voltage is greater than the trap response times (see below). Several techniques are now described. High-Low Frequency C-V Technique This technique exploits the fact that it takes some finite time for interface traps to change occupancy.present.11) 82 .8) 1 1 1 = + C hf C ox C dep (3. there will be insufficient time for the interface traps to respond and the measured capacitance will exclude Cit.

caused by the AC voltage. Dit is obtained as such.8a). It is often more useful to plot Dit as a function of energy within the semiconductor band-gap using: Vgs  C   ox lf dV gs ψ s = ∫ 1 − C  V fb (3. A loss occurs when an interface trap cannot capture or emit carriers in phase with the AC voltage. No losses are observed at very low frequencies. the response of the trap lags behind the AC voltage. it is more convenient to represent a trap by a Git and Cit pair as shown in Figure 3.As Clf and Chf are measured as a function of Vgs. as traps do not respond at all. ψs then corresponds to the valence band edge in accumulation and the conduction band edge in inversion (in eV). 83 . as traps respond immediately. As the LCR meter measures a conductance. Conductance technique In depletion. the conductance represents the energy loss resulting from changes in interface trap occupancy. The loss associated with a single trap can be represented by a resistance Rit in series with its capacitance with time constant τ it = C it Rit as shown in Figure 3.8b). or at very high frequencies.12)  To obtain ψs over the whole device operating range. the integral should be split into two parts: integration from flat-band to inversion and integration from flat-band to accumulation.e. i.

G and capacitance.5  G p  e  ω    max (3. giving rise to a dispersion of time constants.14) 84 . The distribution of interface traps can be modelled by adding corresponding Git and Cit elements in parallel for each trap level. ωGC ox2 = ω G 2 + ω 2 (C ox − C )2 Gp (3. Integrating the trap admittances and accounting for the time constant dispersion. Gp can be calculated from the measured conductance. Dit = 2. C using. Nicollian and Brews[14] show that the resulting equivalent parallel conductance of the traps. Dit is calculated in depletion from the maximum of a G p ω versus ω plot using.13) is derived based on interface trap interactions with the majority carrier band.13) Equation (3.8a) Equivalent circuit of a MOSFET in depletion including an interface trap of time constant τit = RitCit b) parallel equivalent circuit Capture and emission occurs primarily by traps located within a few kT/e above and below the Fermi level. Each interface trap level within this interval contributes a different energy loss depending on its energy from the Fermi level. By measuring the capacitance and conductance as a function of Vgs and ω.Figure 3.

specifically the change in Vgs required to reduce Id by one decade. the frequency range needs to be large (~100 Hz to ~1 MHz) as does the number of frequencies used.12). The conductance technique is one of the most sensitive methods to determine Dit as the conductance is measured directly.To ensure that the maximum G p ω is observed.  C dep + C it n = 1 + C ox     (3. This can be converted to Dit as a function of band-gap energy using equation (3. is a measure of how quickly a MOSFET switches off. For a bulk MOSFET. occupation of interface traps by minority carriers and also occupation of bulk traps contribute to the conductance introducing error in the above technique. Sub-threshold Slope Technique The sub-threshold slope (or sub-threshold swing).15) which is measured in mV/decade. However it does require a large number of measurements and their analysis is very time consuming.  d (log10 I d )   S . The extraction is repeated at each applied DC voltage thus obtaining Dit as a function of Vgs. n is the capacitor divider ratio which is an indication of the fraction of Vgs appearing at the channel interface as ψs.16) 85 . It follows directly from a plot of log10 (Id) against Vgs. In weak inversion.S =   dV  gs   −1 = ln (10 ) nkT e (3. A value of n close to 1 is highly desirable as ultimately ψs is responsible for modulating the barrier between the source and drain and therefore Id.

9 leading to.3kT e  (3. 86 .Note the sub-threshold slope is strongly dependant on the interface trap capacitance which increases its value.9 Comparison of the equivalent circuits of a a) bulk and b) FDSOI MOSFET. Cit2 is the interface trap capacitance at the Si/BOX interface and CBOX is the buried oxide capacitance. the equivalent circuit in depletion is more complicated as shown in Figure 3. Dit can be extracted in weak inversion from the sub-threshold slope of a MOSFET using Dit = C it / e .S  C dep − 1 −  e  2. Dit = C ox  eS .17) Figure 3. In the case of a FDSOI MOSFET. A thick box (small CBOX) ensures a near ideal sub-threshold slope. It is not possible to achieve a value below approximately 60 mV/decade at room temperature.

Excluding Cit and Cit2 from the equivalent circuit we obtain.20) C ox (C dep + C BOX ) For a thick BOX. For 87 . CBOX << Cox and CBOX << Cdep.18) where C dep = C Si = ε Si ε 0 (3. In accumulation.4. The presence of CBOX and Cit2 reduces the sensitivity of the sub-threshold slope technique making it unsuitable for extracting Dit. As a result n is usually close to unity and a sub-threshold slope close to the ideal 60 mV/decade is obtained. a plot of 1 C hf2 against Vgs in depletion has a linear slope. therefore the slope is zero. Vfb is an important parameter when analysing capacitance profiles as it marks the boundary between accumulation and depletion. For a uniform substrate doping concentration. 3. Thus the knee at the boundary between accumulation and depletion corresponds to Vfb.2 Flat-band voltage The flat-band voltage.C dep C dep C dep  C n = 1 + it +  C ox C ox  C BOX C ox  −  1 + C it 2 + C dep C BOX C BOX (3. n = 1+ C dep C BOX (3. Chf is constant.19) t Si Cit2 is the areal interface trap capacitance at the Si/BOX interface and CSi is the areal capacitance of the Si film.

greater accuracy, evaluating

(

d 2 1 C hf2
dV

2
gs

)

produces a peak, the maximum of which

coincides with Vfb.

3.4.3 Inversion charge, depletion charge and vertical field
The sum of the parasitic gate-drain and gate-source overlap capacitances (measured
in accumulation) cause a vertical shift (parasitic offset) in the measured Cgc profile.
This becomes increasingly significant the smaller the area of the device. The
intrinsic Cgc profile can be recovered by subtracting the offset from the measured Cgc
profile. This is not always as straightforward as it sounds and is examined in detail
in chapter 4. The inversion charge density can then be obtained by integrating Cgc
with respect to Vgs:
Vgs

Qinv (Vgs ) = ∫ Cgc (Vgs )dVgs

(3.21)

−∞

Similarly, the depletion charge density is obtained by integrating Cgb from the flatband voltage:
V gs

Qdep (V gs ) = ∫ C gb (V gs )dV gs

(3.22)

V fb

Equations (3.21) and (3.22) assume that interface traps do not contribute to the
measurements of Cgc and Cgb. As discussed in section 3.4.1, interface traps can affect
CV measurements in depletion and weak inversion. Their contribution is most
noticeable in a Cgc profile; manifested as a (frequency dependent) shoulder in weak
inversion. Thus to accurately calculate Qinv in weak inversion and Qdep, a high
88

enough measurement frequency should be selected to prevent most of the traps from
responding.

The effective vertical field, Eeff, usually expressed in MVcm-1, is an approximation
to the average normal electric field a carrier in the channel experiences, as a result of
the applied gate bias. It is given by
E eff =

Qdep + ηQinv

(3.23)

ε 0ε Si

where η is an empirically determined factor referring to the averaging of the electric
field over the carrier distribution in the inversion layer. This factor was given as
11/32 in the scattering theory in section 2.5.1 according to equation (2.31). The
effective carrier mobility, µeff, extraction detailed in chapter 4, has historically been
expressed as a function of Eeff. On a (100) orientation, Takagi et al.[154] show that a
universal relationship exists for µeff over a wide range of Eeff and substrate doping
concentrations when η = ½ for electron and ⅓ for hole inversion layers.

On a (110) orientation, Takagi et al.[155] and Lee et al.[23] show using η = ⅓ is
necessary to maintain the universality for electron µeff. However recent detailed
studies have shown that the universality of hole µeff breaks down on the (110)
orientation and the conventional definition of η = ⅓ is incorrect.[35, 119, 156] Irie et
al.[156] show that the value of η is strongly related to the occupation of the lowest

sub-band, where the larger the occupation, the larger the value of η. Irie et al.[119]
demonstrate that η also depends on channel direction, therefore on the scattering
mechanisms in the inversion layer. They show that η = ⅓ for holes is particularly
89

unsuitable for the <110> channel direction. Furthermore, the modified carrier
distribution brought about by strain, SOI and multiple gates means the concept of
universality fails.[157]

In chapter 5, where (100) and (110) bulk MOSFETs are analysed, hole µeff is plotted
as a function of Ninv and Eeff. Following convention [34, 158-160], Takagi et al.’s
values for η are used and their µeff data included as a reference.

3.4.4 Doping profile
The doping concentration of the substrate can be extracted from the Cgb profile in
depletion. This technique is based on the width of the depletion region changing in
response to the AC voltage. Assuming an abrupt depletion layer edge and complete
dopant ionisation, the doping concentration is extracted using:

(

)



d 1 C hf2

N (V gs ) = ±2 eε 0ε Si
dV gs 

−1

(3.24)

where the positive sign is for an n-type substrate and the negative sign for a p-type
substrate.
To obtain the doping concentration as a function of depth, equation (3.24) is
calculated for each value of Vgs from flat-band throughout depletion. From equations
(3.4) and (3.9) the corresponding value of Wdep can be calculated from;
 1
1 
Wdep = ε 0 ε Si 

C

 hf C ox 

(3.25)

90

The onset of inversion limits the maximum depth which can be probed since this is
when the depletion depth reaches its maximum value. Since the charges that respond
to the AC voltage are mobile majority carriers, equation (3.24) actually measures the
majority carrier concentration at the edge of the depletion region, rather than the
dopant ion concentration itself. As a result, the resolution of this technique is limited
by the Debye length, LD, which is “a measure of the distance over which a charge
imbalance is neutralised by majority carriers.”[148] The Debye length is constant for
a uniform doping concentration and is given by:
 ε ε kT 
LD =  0 2 Si 
 q Na 

1

2

(3.26)

The resolution of this technique for a doping concentration of 1017 – 1018 cm-3 is
therefore around 10 nm. If the doping profile changes abruptly in a distance
comparable to the Debye length or less, the extracted profile will represent an
average of the true profile.

3.4.5 Drain current correction in the presence of significant gate
leakage current
If the gate dielectric is sufficiently thin and/or the MOSFET area sufficiently large,
gate leakage current, Ig reduces the measured drain current, Idm. For low Vds,
approximately half the gate current flows from the source and half from the drain as
shown in Figure 3.10. Using Kirchoff’s current law, the intrinsic drain current Id can
be recovered;[161]

91

When looking at experimental data however. gate current Ig and the measured drain current Idm. approximately half the gate current flows from the source and half from the drain. defined in section 2.6 Threshold voltage The threshold voltage.27) Figure 3.[162] A common technique is the linear extrapolation method.4. A review of 11 different extraction techniques is provided in the paper by OrtizConde et al. For small Vds.10 MOSFET cross section showing the true drain current Id.1 is often loosely quoted as the value of Vgs at which the MOSFET begins to turn on.I d = I dm + I g 2 (3. 3. Id is expected be linearly 92 . In an ideal MOSFET. Vt. The Id-Vgs curve of the MOSFET is measured with low Vds to ensure that the MOSFET is operating in the linear regime. the threshold voltage is not obvious and thus many different methods for extracting it have been proposed and in general they do not agree on a single value.

dependent on Vgs, as shown by equation (2.13), which is repeated here:
I d = µ eff

W

V2 
C ox (V gs − Vt )Vds − ds 
2
L

(3.28)

However, a real MOSFET exhibits sub-threshold leakage currents causing Id to be
non-linear in the threshold region. At high Vgs the slope of the Id-Vgs curve will
decrease due to resistances of the source and drain regions, degraded carrier mobility
and possibly high gate leakage current. Between these two regimes there is a point
of maximum slope on the Id-Vgs curve which by this method is extrapolated back to
the point of zero drain current, with this being defined as Vt. This method can suffer
if either the sub-threshold leakage is high extending the non-linearity of Id to higher
Vgs.

A more preferred technique is the transconductance method proposed by Tsuno et
al.[163] The transconductance gm is given by;
gm =

dI d
dV gs

(3.29)

This is essentially the same as the linear extrapolation method except that the
transconductance is extrapolated to zero from the point of its maximum slope. This
technique assumes that the mobility in the threshold region is dominated by
Coulomb scattering and is therefore proportional to Ninv:

µ eff ≈ αN inv ≈

αC ox
(V gs − Vt )
e

(3.30)

Substituting equation (3.30) into (3.28) and differentiating with respect to Vgs yields
an expression for the transconductance:

93

gm =

dI d
W 2α 2
=
C ox (V gs − Vt )Vds .
dV gs
L e

(3.31)

As expected, gm exhibits a linear dependence on Vgs at threshold and extrapolation to
zero gives Vgs = Vt. The maximum slope of gm usually lies in the non-linear tail of
the Id-Vgs curve. Thus this method tends to obtain a value of Vt closer to the point
where Id becomes negligibly small.

Vt can alternatively be defined as the Vgs that induces a given Ninv. Thus Vt can be

extracted based on the electrostatics rather than current or carrier mobility. Esseni et
al.[110] apply this technique to ultrathin SOI MOSFETs, where mobility is a

complicated function of tSi, defining Vt = Vgs corresponding to Ninv = 2x1011 cm-2.
Obviously this technique relies on accurate extraction of Ninv.

3.4.7 Source-drain resistance
The source and drain are not perfect conductors and have a resistance. The total
resistance of the source and drain is called the source-drain resistance Rsd or access
resistance. If this is comparable to the resistance of the channel, Id is degraded. The
most severe Id degradation occurs in the linear region (low Vds) of MOSFET
operation when Vgs is high because the channel resistance is low. The various
contributions to Rsd are described in detail in Taur and Ning[2]. The most common
method to extract Rsd is to treat the MOSFET as an equivalent circuit comprising the
source (Rs), drain (Rd) and channel (Rch) resistances in series, where Rsd = Rs + Rd .
Assuming that Rsd is a constant and that Rch for a given gate overdrive (Vgt =Vg − Vt)
94

is proportional to channel length (i.e. it’s resistivity is constant per unit length), then
Rsd can be extracted from a range of MOSFETs with different channel lengths. The

total MOSFET resistance, R = Vds/Id is plotted against channel length for several
values of Vgt. Note that Vt must be known for each MOSFET and that the extraction
technique used, must not be systematically affected by channel length. Linear
regressions are then performed through each series of points associated with each
Vgt. These regressions should intersect at a single point. Note the channel lengths

used should be small as not to exert excessive leverage on the slope of the
regressions (see figure 5.9a) for an example). The point of intersection corresponds
to the co-ordinates (∆L, Rsd). ∆L accounts for any discrepancy between the written
channel length L (as defined by the mask during fabrication) and the real channel
length L’. Thus we can define L’ as:
L' = L − ∆L

(3.32)

As with Rsd, this is most significant on MOSFETs with a short channel lengths
where Rch and L are comparable to Rsd and ∆L respectively. ∆L and Rsd may be
obtained with greater accuracy by plotting the intercept against the gradient of each
regression. This should yield a straight line with gradient -∆L and intercept Rsd found
by

a

second

linear

regression

(see

95

figure

5.9b)

for

an

example).

Chapter 4 : Improved Mobility
Extraction in MOSFETs
4.1 Introduction
This chapter describes the theory and extraction of the low field effective channel
mobility, µeff for the devices in this thesis. The methodology is demonstrated on a
long channel SOI quasi-planar finFET at 300 K and 4 K. We begin with briefly
describing the conventional extraction for a bulk MOSFET.

4.2 Conventional extraction
From sections 2.2.1 and 2.2.2 the total drain current, Id in a MOSFET is due to
carrier drift and diffusion. We shall express that here as;
I d = I Drift + I Diffusion

(4.1)

Id
dQ
= Qinv µE x − D inv
W
dx

(4.2)

where D = ε d µ e is the diffusion coefficient and εd the diffusion energy (defined
later by equation. (4.11)).
The effective mobility µeff, is extracted using equation (4.2) where typically Id is
measured by applying a voltage of 50 mV to the drain (for n-MOSFETs), and by
making a number of approximations. Firstly, Id is due to drift current only i.e. the
96

gd µ eff = gd L WQinv (4.4. drift-limited regime.2) can be simplified and µeff calculated using: µ eff = Id L VdsWQinv (4.3b) dI d dVds (4. 97 . Thereby (4.3a) This can also be expressed by replacing Id/Vds with the drain conductance. determining µeff requires the measurement of Qinv and Id as a function of Vgs. applicable when the MOSFET is operating in the above-threshold. Qinv can be approximated by Qinv = C ox (V gs − Vt ) .4) where gd = Hence. but it relies on Cox and Vt which are not necessarily well known.MOSFET operates well above threshold. providing that interface traps do not affect the measurement. When Vgs>>Vt and Vds is low.3 a more accurate approach based on a direct measure of Qinv as a function of Vgs is from the split C-V technique. As detailed in section 3.2) to be dropped (dQinv dx = 0) and Ex to be given by Vds/L. Qinv can be approximated as being uniform from the source to drain allowing the diffusion term in (4. This leads to error in the calculated mobility as not only is it an approximation.

the diffusion current in equation (4. Provided the drain bias is low and ignoring interface traps. With a finite applied Vds near threshold.[151] show that the values of dQinv dV gs (Cgc).3.2) should be considered.2. In this section we address the approximations made in section 4. F (V gs ) = dQinv dψ s C ox + dQs dψ s (4.5) where 0 ≤ F (V gs ) ≤ 1 and F (V gs ) explicitly given by.8) 98 .1) It is also shown that.4.3a) is most commonly used to obtain effective mobility due to its simplicity. Sodini et al. E x = F (V gs ) Vds L (4. hence is a function of position along the channel x and applied gate voltage Vgs. dQinv dx and Ex follow the same functional dependence with Vgs.3 Improved extraction. The lateral field Ex will also be dependent on this charge distribution. Sodini et al. derive.7) dQinv C V = F (V gs ) ox ds dx L (4.bulk MOSFET Equation (4.1 Diffusion and Ex-field correction To extract the mobility near threshold.Qinv decreases towards the drain. the Qinv is not uniformly distributed over the channel length . C gc = C ox F (V gs ) (4. 4.6) Qs is the total semiconductor charge (defined in section 2.

Id V ε   = µ eff ds F (V gs )Qinv + d C ox  W L e   µ eff = (I d (4. Note that no extra measurements are required than when the mobility is calculated with (4. Although (4.2). 4. they provide no explicit theoretical proof of this statement. Zebrev and Gurbonov[164] show. use ε d = kT which is only valid in weak inversion when the inversion layer is non degenerate. Sodini et al.10) is simple enough. Sodini et al. However.7) and (4. Ideally Id would be measured at very low bias (Sodini et 99 . is that inversion layers are often degenerate at large Vgs.11) This reduces to ε d = kT in weak inversion and ε d = E F − E0 in strong inversion. One point not considered by Sodini et al.3.3a) is required even near threshold.9) Vds )L (4. it was not explicitly stated in the original paper by Sodini et al.10) ε   F (V gs )W Qinv + d C ox  e   which is a more complete expression for mobility over the whole Vgs range.3a) or (4. since the finite drain bias during the measurement of Id reduces Qinv particularly near threshold.8) into (4. can lead to significant error in the extraction of µeff. state that the diffusion and Ex-field corrections have a “cancelling effect” effectively implying only the drift expression (4.Substituting (4.2 Finite drain bias correction Qinv measured by split CV.3b). ε d = kT (1 + e − ( E F − E0 ) / kT )ln(1 + e ( E F − E0 ) / kT ) (4. where Vds = 0 V.

we propose a new and simple technique to extract either Id/Vds or gd at Vds = 0 V.17) we can write the drain current in sub-threshold as.al.[170] In each case. Alternative CV techniques have been devised that measure the gate-to-drain and gate-to-source capacitances separately whilst biasing the substrate and the source to create the same bias conditions as the Id measurement. we measure sets of Id for different Vds and perform linear regressions to obtain the limiting values of either Id/Vds or gd at Vds = 0 V. eV  − ds  I d = I 0 1 − e kT      (4. 154. the measurement configurations are cumbersome. complicating an already difficult measurement. to obtain the correct Qinv.12b) . 165-166] and in some cases 100 mV[167] which creates a nonuniform channel.12a) where 2 W  kT  e (V −V ) nkT I 0 = µ eff C ox (n − 1)  e g t L  e  100 (4. suggest Vds < kT e ). Rather than trying to modify the CV measurement (possibly introducing additional errors). severely limiting their use in current and future technologies. they cannot be used for SOI devices without substrate contacts (above the BOX). but then noise is an issue so many Id measurements use Vds = 50 mV[65. In addition.[168-169] Modelling the channel as a transmission line network has also been employed with high frequency AC admittance measurements. The approach is somewhat different in the regions of sub- threshold and strong inversion: From equation (2. To address this problem.

13) or ln ( g d ) = − e  e  Vds + ln I0  kT  kT  (4. This may lead to error in the mobility when using (4. 4. Note that in the limit of small Vds (4.14) Hence a plot of ln(gd) against Vds.eV dI e − kTds gd = d = I0 e dVds kT (4.3a) gives the drift only expression. The predicted slope of -e/kT can be used to check the extraction is valid. 101 . Vds = 0 ) = I 0 e kT . The preferred equation which is widely used in the literature[171-173] removes the W dependence by factoring out the area (WL) in Cgc: Vgs Qinv 1 C gcmeas dV gs = ∫ WL −∞ (4. In the strong inversion region. the masked Wfin value may differ appreciably from the physical value in very narrow finFETs. at a particular gate voltage. is a straight line with the intercept yielding g d (V gs . so Id/Vds is numerically equal to gd in the limit of Vds = 0.15) into (4. Mobility in narrow finFETs is considered in chapter 6. plots of Id/Vds against Vds for given Vgs yield straight lines with the obvious intercepts of Id/Vds at Vds = 0 V.15) Inserting (4.12a) reduces to I d = I 0 eVds kT .4 Mobility extraction in SOI MOSFETs and finFETs When extracting the mobility of finFETs. Beyond threshold the slope of the semi-log plot will be seen to deviate from -e/kT.10).

Id = e W 1+ κ DN inv (0 ) L κ   κ eVds   1 − exp − 1 + κ ε d    (4. we use the theory by Zebrev and Gorbunov[164] who derive the drain current for a FDSOI MOSFET based on the sum of the drift and diffusion currents.17) which is based only on quantities near the source (x = 0) In their analysis they introduce the control parameter κ.1 Ex-field and diffusion correction To investigate the effect of the Ex-field and diffusion corrections analytically. which is the ratio of diffusion to drift current and is dependent on the various capacitances of an SOI device.16b) gs ∫C meas gc dV gs −∞ Of course equations (4. 4. Any error in L is likely to be insignificant in the present work as only long channel devices (≥10 µm) are considered.L2 I d µ eff = (4. κ= I Diffusion I Drift = C ox dξ = n dψ s dN inv dξ (4.16b) can be applied to an ordinary bulk MOSFET.4.18) 102 .16a) and (4.16a) Vgs Vds ∫ C meas gc dV gs −∞ or µ eff = V L2 g d (4.

α <<1 and Ex simplifies to Ex = ε d e 1−1+ α κL 1 − x (1 − 1 + α ) L = εd e α κL 103 (4.  κ eVds   1 − exp − 1 + κ ε εd e d   Ex = κL  x κ eVds 1 − 1 − exp − L  1+ κ εd      If we let α =− κ eVds 1+ κ εd If Vds → 0 .19) Providing Cox >> CBOX. repeated below. Zebrev and Gurbonov give.20). dN inv eN inv = dξ εd (4. as is the case for this work.20) therefore C ox ε d e 2 N inv κ= (4.   C Si C BOX  n = 1 +  C ox (C Si + C BOX )  (4.22) .21) The electric field along the channel is given by.where ξ is the chemical potential and n has been defined by equation (3. n = 1 corresponding to the bulk non-SOI case.

  κ eVds    x  N inv ( x ) = N inv (0)1 − 1 − exp −   L 1 + κ ε d     (4.26) As for (4.  x κ eVds   N inv ( x ) = N inv (0)1 −  L 1+ κ εd  (4.23) Vds L (4. dQinv ( x ) V κ N inv e 2 = − ds dx L 1+ κ εd (4. we have derived a new F function.30) 104 .25) Zebrev and Gurbonov derive the inversion charge density along the channel as.29) As Vds → 0 Ninv is uniform across channel and Ninv(0) = Ninv. when the exponent << 1.28) dQinv ( x ) Vds κ N inv (0)e 2 =− dx L 1+ κ εd (4.27) To evaluate the diffusion term we need an expression for dQinv/dx dN inv ( x ) N (0) κ eVds = − inv dx L 1+ κ εd (4.= Vds 1 L 1+ κ (4. Fz(Vgs). Fz (V gs ) = 1 = 1+ κ 1 C ε 1 + 2ox d e N inv (4.24) Ex = 1 C ε 1 + 2ox d e N inv Thus using the model by Zebrev and Gurbonov.23).

In this work it was possible to measure Id-Vgs from Vds of 100 mV down to 5 mV and Cgc at frequencies of 100 kHz-1 MHz. dQinv ( x ) V C 1 = − ds ox dx L 1+ κ (4. It is interesting to note that whereas the weak inversion current is diffusion-like at high Vds.31) dQinv ( x ) C V = − Fz (V gs ) ox ds dx L (4.21) into (4.Substituting (4.32) By substituting Fz into µeff.5 Experimental application to an SOI MOSFET To test the suggested methodology the various corrections are applied to a quasiplanar (Wfin = 1.2. The device specification is given in section 6. it is drift-like at low Vds. the particular capacitance values must first be assessed to check n = 1 for this to be the case. Thus we have shown theoretically that the Ex-field and diffusion corrections cancel out over the entire Vgs range supporting the claim of Sodini et al.16a).872 µm and L = 10 µm) FDSOI n-finFET at 300 K and 4 K. any variation in the lateral field Ex is exactly compensated for by the diffusion term. leaving the original “uncorrected” (4. No substrate contact is present therefore Cgb measurements were not possible. 105 .30). Vgs of 0 to 2 V was applied in 25 mV steps. 4. This can be seen from (4.17) which reduces to the drift only current when Vds → 0 . However.

Vgs Using equation (3.6).872 µm Hfin = 65 nm T = 300 K Vds = 50 mV Id = Idm + Ig/2 Vd = 50mV Vd = 100mV Vd = 60mV 1e-4 1e-5 Idm 3e-5 2e-5 Vd = 10mV Vd = 35mV 1e-6 Id (A) 6e-5 1e-7 1e-8 1e-9 L = 10 µm Wfin = 1.5 2. No frequency dependent shoulder in weak inversion or suppression of capacitance is present.1b) for a range of Vds.1).1 Id . This is shown in Figure 4.0 0. Figure 4.Vgs characteristics and phase angles.5 2.0 1. implying that interface traps and access resistance are not corrupting the measurement. f < 5 MHz is necessary for complete formation of the inversion charge.5 1.1 a) Gate leakage correction Idm and Ig are the measured drain current and gate leakage currents b) Corrected drain current data for a range of drain biases at 300 K 4.Vgs At large Vgs the measured drain current.5. The leakage corrected Id is shown in Figure 4.2 Cgc .0 Vgs (V) 1e-12 0. 5e-5 Current (A) 4e-5 1e-3 L = 10 µm Wfin = 1.0 Vgs (V) Figure 4.2a) shows the 300 K Cgc. Ig.872 µm Hfin = 65 nm T = 300 K 1e-10 1e-5 Ig 1e-11 0 0. Note despite the difference in θ with 106 .0 1.5. increasing Ic yielding higher values of θ. The decrease in θ with increasing Vgs is due to Ig. Higher measurement frequencies reduce the reactance of C in the equivalent circuit (figure 3.0 0.4. This has been corrected by adding the gate leakage current using equation (3.5 1.27). Idm is reduced due to gate leakage current.1a) for Vds = 50 mV.

5 V.6 0.2 1. (i.8 1.6 Cgc (µFcm-2) 1.0 0.0 1. b) Corresponding phase angles Figure 4.as seen by the drop in capacitance. 100 L = 10 µm Wfin = 1. the gate-drain and gatesource overlap parasitic capacitances are included in the measurement.frequency.0 0. However above 1.2 Phase Angle. This shows that a drop in θ due to Ig does not necessarily mean the measured capacitance is inaccurate.0 Vgs (V) 0.2 1.872 µm Hfin = 65 nm T = 300 K 1. the LCR meter is still able to measure the quadrature current in the equivalent circuit).2 1.4 1.4 1.2 a) Gate-channel capacitance for measurement frequencies in the range 10 kHz – 1 MHz.4 1.0 1. These are directly measured when the device is off during a Cgc measurement producing an offset.4 0.6 10 kHz 100 kHz 500 kHz 1 MHz 0.872 µm Hfin = 65 nm T = 300 K 20 0 0. Ig exceeds a critical value and a frequency of 10 kHz is no longer sufficient to measure Cgc accurately. the measured capacitances are the same over most of the Vgs range.2 0.4 0.e. Below 10 kHz measurement noise was unacceptably high.6 0.8 1. C0. which must be subtracted for accurate calculation of Ninv and µeff in weak 107 .6 Vgs (V) Figure 4.6 0.0 0. θ (Degrees) 2.2 0.8 1.0 80 1 MHz 10 kHz 100 kHz 500 kHz 60 40 L = 10 µm Wfin = 1.4 0. Although parasitic capacitances due to the equipment are accounted for prior to measurement. It must be pointed out that although θ = 90° in weak inversion this does not necessarily mean Ninv can be calculated accurately in this region.8 0.3 shows the calculated Ninv from the 100 kHz measurement.

Due to the sensitivity of C0 on µeff and Ninv in weak inversion. In Figure 4. the measurement accuracy of the LCR meter ( ± 1% when C ~ 0.4 V (Figure 4.075 V. also yields a value of ~0. with Vt ~0.inversion. (corresponding to a Vgs difference of 50 mV) causes µeff to vary by a factor of 2.3 pF and f = 100 kHz – 1 MHz) may be an issue when measuring such small capacitances. In addition.6 at Ninv = 1x109 cm-2.. In Figure 4. Neglect leads to an overestimation of Ninv which can lead to profound underestimation in the peak mobility.S. In this example.380 pF. µeff can only be reliably extracted from Ninv of approximately 1x1011 cm-2 to within an error of less than 5 %.6) and the measured S. a 2% variation in C0. = 65 mV/Dec. Terada et al. In any case using their equation.[174] state that Vgs0 should be defined as Vt -5S. 108 .075 V (Vgs0) corresponding to the minimum capacitance of 0. However the parasitics are not always constant and the signal to noise ratio may be poor making the subtraction difficult.S. However they assume C0 is solely due to parasitics.4 we demonstrate the effect of subtracting C0 at different Vgs on µeff.3 the offset was subtracted at Vgs = 0.

1.4 Effect of subtracting the offset capacitance on effective mobility extraction 109 .384 pF (Vgs = 0.6 1e+13 1.0 Ninv (cm ) Cgc (µFcm-2) 1e+12 1.1 V) C0 = 0.380 pF (Vgs = 0.2 1e+9 1e+8 1e+7 0.8 1e+14 1.4 0.2 0.0 -2 1e+11 1.0 1.2 1.8 1.125 V) 500 400 300 C0 = 0.2 0.3 Gate-channel capacitance measured at 100 kHz and calculated inversion charge density 900 700 2 -1 -1 Effective Mobility (cm V s ) 800 600 L = 10 µm Wfin = 1.872 µm Hfin = 65 nm T = 300 K Vds = 50 mV C0 = 0.0 0.075 V) 200 100 1e+8 1e+9 1e+10 1e+11 1e+12 1e+13 -2 Ninv (cm ) Figure 4.4 1.872 µm Hfin = 65 nm T = 300 K 0.6 L = 10 µm Wfin = 1.8 1e+10 0.6 Vgs (V) Figure 4.388 pF (Vgs = 0.4 100 kHz 0.4 0.6 0.

Qinv decreases for a given Vgs due to the channel pinch off effect -which becomes increasingly prevalent the smaller Vgs – Vds. µeff has been calculated down to Ninv =1x1010 cm-2. The large suppression of inferred mobility at higher Vds can clearly be seen. Figure 4. This manifests itself as an increase in Vt – seen by the shift in Id in Figure 4. based on a C0 = 0. L = 10 µm Wfin = 1. especially at low Ninv.872 µm Hfin = 65 nm Vds = 10 mV to 100 mV 800 2 -1 -1 Electron µeff (cm V s ) 1000 T = 300 K 600 400 200 0 1e+10 Increasing Vds 1e+11 1e+12 1e+13 -2 Ninv (cm ) Figure 4. for a range of drain biases.4. confirming the necessity of extrapolating to Vds = 0 V.5.5 Extracted mobility at 300 K showing the effect of increasing drain bias from 10 mV to 100 mV As Vds is increased.5 shows the “uncorrected” 300 K mobility as a function of Ninv.6.3 µeff extraction To demonstrate the possible application of the Vds correction in weak inversion.380 pF. is larger than during an Id measurement. 110 .1b) and the extracted Vt in Figure 4. The extracted mobility decreases as the measured Qinv.

7 has the correct slope of -38 V-1 and typical regression coefficients are better than 0.39 0.45 Vt (V) 0.70 V. 111 . at Vgs = 0.225 V.7 and Figure 4. In each case we see the predicted straight line behavior and are able to extract a conductance value for Vds = 0 V.00 0.6 Threshold voltage extracted from the max slope of transconductance measured as a function of drain bias The conductivity (gd and Id/Vds) at Vds = 0 V was extracted over the entire Vgs range. Figure 4.43 0.0.98. Figure 4.40 0.44 L = 10 µm Wfin = 1.10 Vds (V) Figure 4.02 0.41 0.872 µm Hfin = 65 nm T = 300 K 0. Note that the conductance in strong inversion (where carrier mobility is often reported) is already 8% lower at the standard measuring bias of Vds = 50 mV than at Vds = 0 V.46 0. respectively.8 show examples of the regression used in sub-threshold.08 0.42 0. and in strong inversion at Vgs = 0.04 0.06 0. indicating high accuracy.

05 0.03 0.07 0.5x10 cm -2 ln(gd) -13.7e-4 2.00 0.5 -14.08 Vds (V) Figure 4.9.-12.5 T = 300 K Vg = 0.7 Semi-log variation of drain conductance with drain bias in the sub-threshold region enabling the zero bias conductance to be extracted as the intercept 2.3e-4 0.5 -16.05 0.4e-4 2.8e-4 T = 300 K Vg = 0.02 0.5 -15.01 0.0 -15.01 0.5e-4 2.08 Vds (V) Figure 4.70 V Ninv = 1.04 0.7x1012 cm-2 Ids/Vds (S) 2. 112 .06 0.03 0.6e-4 2.02 0.8 Variation of drain current with drain bias in strong inversion from which the zero bias conductance can be extrapolated Having extracted the zero bias conductance values corresponding to each inversion charge density. and considering that the diffusion and Ex-field corrections cancel.0 -14.0 0.0 10 Ninv = 1.07 0.04 0.00 0.225 V -13. µeff can be calculated accurately as shown in Figure 4.06 0.

trapping effects may be further suppressed by inversion charge pumping[177] or by RF CV measurements. which is sensible in that it is consistent with the theory of interface charge scattering of nondegenerate carriers[17] and measurements of geometric magnetoresistance[175- 176] on SiO2 gated SOI transistors.[149] Other useful approaches combine CV techniques with modelling[150.872 µm Hfin = 65 nm T = 300 K 600 Drift only Vds = 50mV 400 200 0 1e+10 1e+11 1e+12 1e+13 Ninv (cm-2) Figure 4.9 may be partially due to fast trapping processes that affect the CV measurement. there maybe MOSFETs for which fast trapping is not an issue. Although a measurement frequency is used at which it is expected that most of the traps will be unable to respond. 178]. 151] Nevertheless. Furthermore. it may still be possible to obtain meaningful µeff data from improved measurements of Ninv.9 300 K mobility showing the effect of the various corrections Although µeff may not be accurate for Ninv ~1010 cm-2 some intuitive understanding can still be gained. for example. The fall in µeff to the left of the peak in Figure 4. which are not subject to trapping effects. in state of the art CMOS 113 .[148. Where geometric magnetoresistance methods are not available. µeff at 300 K shows a tendency to be independent of Ninv.1000 Vds correction 800 2 -1 -1 Electron µeff (cm V s ) Vds + Diffusion +E-field correction L = 10 µm Wfin = 1.

Therefore. for a range of Vds. it is important to assess the significance of Vds on the extraction of µeff. At 4 K.10 4 K extracted mobility showing the effect of increasing drain bias from 10 mV to 100 mV 114 .[179] Nevertheless µeff still strongly depends on Vds. Chapters 5 and 6 include modelling of µeff at 4 K. With these provisos. Figure 4.12. Effective Mobility (cm2V-1s-1) 1200 1000 800 L = 10 µm Wfin = 1. we also obtain good linear fits from which to extract zero bias conductivity values as shown in Figure 4.technologies.872 µm Hfin = 65 nm Vd:10 mV to 100 mV T=4K 600 Increasing Vds 400 200 0 1e+12 1e+13 Ninv (cm-2) Figure 4. the principles established in this work could have wider applicability.10 shows the “uncorrected” 4 K µeff as a function of Ninv. Possible corner inversion in the device at low temperature prevented accurate µeff extraction below Ninv = 7x1011 cm-2. as this may lead to incorrect fitting parameters in the modelling. The corrected mobility is shown in Figure 4.11.

05 0.11 Id/Vds in strong inversion at 4 K 1200 Vds + Diffusion + E-field correction 800 Vds correction 2 -1 -1 Electron µeff (cm V s ) 1000 600 Drift only Vds = 50 mV 400 L = 10 µm Wfin = 1.5x1012 cm-2 6.2e-4 6.875 V 7.8e-4 Id/Vd (S) 6.07 0.04 0.01 0.6e-4 0.0e-4 Ninv = 2.7.e.2e-4 T=4K Vgs = 0.8e-4 5.) the extraction may be sufficiently accurate.00 0. However this should be checked by applying the Vds correction on at least one device for the batch under examination.872 µm Hfin = 65 nm T=4K 200 0 1e+12 Ninv (cm-2) 1e+13 Figure 4.0e-4 5.08 Vd (V) Figure 4.03 0.12 4 K effective mobility showing the effect of the various corrections It must be pointed out that it may be possible to extract the mobility without needing to apply the Vds correction.02 0. device contacts etc.06 0. 115 .6e-4 6. noise is not an issue due to measuring equipment. Providing Id can be measured using a very low Vds ~5 – 10 mV (i.4e-4 6.

116 . to correct for the difference in drain bias between the Id-Vgs and Cgc-Vgs measurements.6 Summary In this chapter. A novel regression technique was proposed to extrapolate the drain conductance to Vds → 0 . accurate mobility is obtained using the drift only expression with the drain conductance correction. Corrections for the variation in the field along the channel and carrier diffusion. carrier diffusion and the absence of drain bias during Cgc-Vgs measurements. Typical mobility calculations ignore the variation in the field along the channel. The effective mobility was subsequently extracted on a FDSOI MOSFET at room temperature and at 4 K. Thus. providing the inversion charge is known accurately. included in the analysis.4. are shown to cancel in the limit Vds → 0 . without relying on any elaborate measurement technique. the theory and extraction of the low field effective channel mobility has been analysed. Not correcting for the difference in drain bias leads to significant error.

However. there is growing interest in fabricating MOSFETs on (110) orientated substrates. as the band structure in this orientation maximises hole mobility – over double that of (100) substrates. Secondly the interface trap density at the SiO2/Si interface is generally lowest on this orientation. in this case. despite the extensive number of publications on carrier transport in p-MOSFETs.[29. The conventional channel direction for MOSFETs is along the <110> direction.and p-MOSFETs respectively. However. 185] To get the best of both worlds. due to the complicated nature of the valence band.1 Introduction CMOS technology has conventionally been fabricated on (100) orientated substrates/wafers. as the bandstructure in this orientation maximises the electron mobility.[26-31] The results on the electrical characterisation of n.[155.and p-MOSFETs fabricated on bulk (100) and (110) wafers over the full range of channel directions are presented in 117 . IBM’s hybrid orientation technology (HOT)[181-182] utilises both the (100) and (110) orientations for n. understanding of hole mobility currently lags behind electron mobility.Chapter 5 : Si MOSFETs on (100) and (110) orientated substrates 5. 180-184] Unfortunately. electron mobility is reduced by half.

The implant doses were 1x1013 cm-2 of phosphorus at 300 keV and 1x1013 cm-2 of boron at 100 keV. Royal Institute of Technology. 5. channel direction and Eeff/Ninv. Emphasis is placed on understanding the dependence of mobility on orientation. Dry thermal oxidation for 35 min at T = 700°C was then used to grow the SiO2 gate dielectric. The doping concentration of the n+ poly gate was ~1020 cm-3. The main process steps are as follows.this chapter. A 950°C rapid thermal anneal for 30 seconds followed to activate the dopants.and p-MOSFETs respectively. Source and drain regions were formed by implanting with 2x1015 cm-2 of arsenic at 50 keV and 1x1015 cm-2 of boron at 4. Connections to the gate. source. Phosphorus and boron implants formed N and P-wells for the substrates of the pand n-MOSFETs respectively. Sweden on 100 mm diameter wafers. The MOSFETs were fabricated at KTH. 118 .2 Device overview. In both cases the intentional doping concentration was ~1017 cm-3. drain and substrate and their contact pads were formed by depositing 12 nm of Ni followed by sputtering TiW and then Al. N+ polysilicon was deposited on the SiO2 to form the gate itself with a projected thickness of 150 nm.5 keV for the n. measured by the author from the resistivity of a van der Pauw structure.

In the variable size array channel lengths.5 µm to 200 µm.5 V for the p. Firstly. Beer[147] shows that correlation between Vt and peak gm across a wafer can be caused by a systematic variation in Dit.1a) This single plot is a very useful way to quickly identify overall device performance as it not only shows any variation in Vt and peak gm. The test structures consist mainly of diodes. Figure 5.. The majority of the Id-Vgs measurements were performed with Vgs swept from 0 to -4 V and -0. MOSFETs have a fixed size (W = 4. Most of this chapter focuses on the OA MOSFETs. the variable size (VS) array and the orientated angle (OA) array.and n-MOSFETs respectively with Vds = ±10mV .7 µm and L = 25 µm) with channel directions varying by 178°. The MOSFETs are divided into two arrays. corresponding to the <110> and <112> directions for the (100) and (110) wafers respectively. each containing a host of process control/test structures and MOSFETs. and widths. and 10 µm to 100 µm. the latter essentially a measure of mobility. A plot of peak gm vs Vt is shown in Figure 5. 119 . 0° is parallel to the wafer flat.2.5 V to 3. respectively.Regions with high values of Dit caused large shifts in Vt and degraded the mobility. van der Pauw and Kelvin structures. Id-Vgs measurements on 10-20 10 µm x 10 µm p-MOSFETs were measured on different chips across each wafer to check device uniformity and locate the region of the best performing devices. In the OA array.1 Device layout Each wafer is divided up into chips 5 mm square. vary from 0.5.1b) lends some support to this theory as higher values of Dit also increase the sub-threshold slope which we observe. but identifies any correlation between the two.

12 -1. A more negative Vt is correlated to a smaller peak gm and higher S. 100 kHz. high gate leakage current.10 -1.7 µm n.48 0.S.08 Vt (V) -1.60 Sub-threshold slope (mV/Dec. This was necessary to check the capacitance scaled with area between the devices.02 -1. Measurements were performed using frequencies of 100 Hz.3 Capacitance – voltage measurements 5.52 (100) <110> 0.08 -1. and also to identify any size related measurement problems (e.06 -1.04 -1.06 -1.12 -1. Chips containing the best performing MOSFETs (highest peak gm) were subject to detailed investigation upon which the rest of this chapter is based. most probably due to a variation in Dit. 500 kHz and 1 MHz.) Peak gm (µS/µm) 0.0. 5. 10 kHz.1 Split CV Split CV measurements were performed on 50 µm x 50 µm.00 90 80 L = W = 10 µm Vds = -50 mV T = 300 K (110) <112> Vt vs Peak gm Vth vs Peak gm (uS/um) (100) <110> 70 60 -1.00 Vt (V) Figure 5. 100 µm x 100 µm.50 0.3.10 -1. frequency dispersion due to slow minority carrier response).02 -1.g.1 a) Peak gm vs Vt b) S.46 -1.S.56 (110) <112> 0. The variation in peak gm is 5% and 10% for the (100) and (110) wafers indicating good uniformity.and p-MOSFETs on both wafers.04 -1.54 0. vs Vt measured on 10 µm x 10 µm p-MOSFETs across the (100) and (110) wafers. The 120 . 200 µm x 100 µm and 25 µm x 4.58 100 L = W = 10 µm Vds = -50 mV T = 300 K 0.

2 compares Cgc between 100 µm x 100 µm and 25 µm x 4.9 nm 100 Hz 0.6)) in weak inversion (Vgs = . Providing a suitable frequency was chosen. the measurement frequency should be no greater than 100 kHz.9 nm CET = 3.0 0.0 -4 -3 -2 -1 0 -4 -3 -2 -1 0 Vgs (V) Vgs (V) Figure 5.7 µm (100) pMOSFETs In the case of the 25 µm x 4.7 µm T = 300 K L = W = 100 µm T = 300 K 0. clear dispersion is present in inversion for the 100 µm x 100 µm and 200 µm x 100 µm p-MOSFETs due to the large channel time constants associated with the long channel lengths.and n-MOSFETs.7 µm (100) p-MOSFETs. the 121 . Figure 5.6 1 MHz 10 kHz frequency 0.2 L = 25 µm W = 4.8 -2 Cgc (µFcm ) 0.0 1.6 Cgc (µFcm-2) 100 kHz 500 kHz 10 kHz 1 MHz frequency 0.7 µm MOSFET. (100) p-MOSFETs For frequencies exceeding 10 kHz.8 0.4 0.2 Cgc as a function of frequency for 100 µm x100 µm and 25 µm x 4. measurement noise was unacceptably high and is not shown.0 CET = 3.4 0.1 V) to ensure the minority carriers have sufficient time to respond. However below 10 kHz.size and frequency dependences on capacitance are now shown for the (100) p.2 0. the measurement frequency should be less than 12 kHz (calculated using equation (3. 1. For the large MOSFET.

The phase angles also shown are close to 90° over most of the data range. This is unusual considering the relatively large area of the device.8 Cgb (10 kHz) Phase Angle (degrees) 100 µm x 100 µm Cgc (10 kHz) 25 µm x 4.7 µm (100 kHz) 0. perhaps coupling of thermal noise from the wafer/substrate chuck to the substrate well is responsible.1 nm was measured in strong inversion.capacitance scaled with area between MOSFETs indicating uniform oxide growth.2 80 60 40 20 T = 300 K T = 300 K 0 0.3 shows the split CV of a 100 µm x 100 µm p-MOSFET and the Cgc branch of a 25 µm x 4.7 µm (100) nMOSFETs.1 ± 0. with a CET of 3. Cgc branch from 25 µm x 4.[186-187] Thus Cgb was measured on the 100 µm x 100 µm MOSFETs. 100 1.3 Split CV and phase angles for a (100) 100 µm x 100 µm p-MOSFET.0 -4 -2 0 -4 2 -2 0 2 Vgs (V) Vgs (V) Figure 5. Since the devices are not isolated from the wafer bulk. A CET of 4.4 compares Cgc between 100 µm x 100 µm and 25 µm x 4. Frequency 122 .9 ± 0.0 -2 C (µFcm ) 0.7 µm p-MOSFET included for comparison (100) n-MOSFETs Figure 5.1 nm. Measurement noise prevented reliable Cgb measurements on devices smaller than 50 µm x 50 µm even for frequencies of 1 MHz. Figure 5.7 µm p-MOSFET for comparison.4 0.6 0.

0 1.1 nm 500 kHz 0.7 µm n-MOSFET. visible by the noise at high Vgs for a frequency of 10 kHz. This is manifested clearly for the 25 µm x 4. The corresponding phase angles are also shown. However.4 0. In this case. due to their higher mobility. a frequency of ~500 kHz was necessary to reduce the capacitive reactance for the LCR meter to accurately measure the quadrature current and calculate the correct capacitance.8 100 kHz 100 kHz 10 kHz 500 kHz Cgc (µFcm-2) -2 Cgc (µFcm ) 0.6 0. the n-MOSFETs have a higher gate leakage current.7 µm T = 300 K L = W = 100 µm T = 300 K 0. 123 .7 µm (100) n-MOSFETs.4 10 kHz 0. Measurement noise was unacceptably high for frequencies below 10 kHz.2 0. The Cgb and Cgc branches of the 100 µm x 100 µm n-MOSFET are shown together in Figure 5.0 0 1 2 3 0 1 2 3 Vgs (V) Vgs (V) Figure 5.5. No frequency dispersion was observed in the 25 µm x 4.0 CET = 4.7 µm n-MOSFET. No dispersion was observed for the 25 µm x 4. 1.2 L = 25 µm W = 4.dispersion was considerably lower than for the p-MOSFETs as electrons respond more quickly than holes.1 nm CET = 4.7 µm MOSFET.6 1 MHz 0.4 Cgc measured as a function of frequency for 100 µm x 100 µm and 25 µm x 4.8 1 MHz frequency 0.0 0.

and p-MOSFETs are within error of each other with no obvious difference due to quantum confinement.0 0 -3 -2 -1 0 1 2 3 -3 Vgs (V) -2 -1 0 1 2 3 Vgs (V) Figure 5. we can compare the split CV between the (100) and (110) n.5 a) Split CV for the (100) 100 µm x 100 µm n-MOSFET and the Cgc branch for the 25 µm x 4. a higher CET for the n-MOSFET might be anticipated as electrons in the ∆4 valleys (mconf = 0.29m0). CET is higher on the (110) wafer due to the faster oxidation rate of (110) Si. The drop at high Vgs is due to gate leakage current Now the intricacies of the capacitance measurement have been discussed.4 0. 124 .and p-MOSFETs.2 80 60 40 20 T = 300 K T = 300 K 0.0 100 Cgb (10 kHz) 100 µm x 100 µm Cgc (10 kHz) 25 µm x 4. CET between the n. On the (100) wafer. 188] On each wafer.25). quantum confinement would result in a larger CET for the p-MOSFET compared with the n-MOSFET. On the (110) wafer.1.7 µm (500 kHz) Phase Angle (degrees) -2 C (µFcm ) 0. are confined further from the interface than holes (HH mconf > 1m0 see Figure 5.7 µm n-MOSFET.[180.6. which is probably insignificant to the relatively thick oxides. This can be understood by considering the occupation of the dominant sub-bands.4 V)[189] thus are confined closer to the interface than holes (HH mconf ~ 0. At 300 K ~60% of electrons occupy the ∆2 valleys (mconf = 0.8 0. These are shown in Figure 5.6 0.315m0).916m0) when Ninv ~ 1012 cm-2 (Vgs = 0. b) Corresponding phase angles.

1 nm 0.1 Flat-band voltages for n.0 1. Vfb compensates for this field.1 V ± 0.05V -0.05V -0.3.05V -0. The values are shown in Table 5. This is usually identified by a steep decrease in the capacitance in inversion and in accumulation for the n.0 -4 -2 0 2 -3 -2 -1 0 Vgs (V) 1 2 3 Vgs (V) Figure 5.and p-MOSFETs on (100) and (110) orientations.6 CET = 4.No significant depletion of the n+poly Si gate was evident.4 0. Vfb is accurate to within 50 mV.[2] 1. nMOS pMOS (100) Vfb (110) Vfb -0.and p-MOSFETs respectively.4 0.2 L = W = 100 µm f = 10 kHz T = 300 K 0.3 nm -2 C (µFcm-2) (100) 0.5 nm (110) 0.2 Flat-band voltage and interface trap density The work function difference between the n+poly Si gate and substrate.8 (110) 0.6 Split CV characteristics for the p.05V Table 5.and n-MOSFETs on the (100) and (110) orientations 5.8 (100) C (µFcm ) CET = 6. and oxide charge near the SiO2/Si interface create a built in field across the oxide and SiO2/Si interface (band bending).1 V ± 0.9 V ± 0.2 L = W = 100 µm f = 10 kHz T = 300 K 0.0 0.0 CET = 3.1.9 V ± 0. Since Vgs was incremented in 50 mV steps. due to its high doping.6 Col 2 vs 10kHz uF/cm2 Col 6 vs 10kHz uF/cm2 Col 10 vs Col 11 Col 14 vs Col 15 CET = 6. 125 .9 nm p-MOS n-MOS 0.

may be masking the in-phase current over most of the energy range. The resolution limit of the high-low frequency technique depends on Cit/Cdep i.1). The large quadrature current. A further error occurs close to flat-band. Figure 5. could only be applied over a narrow range of the band-gap on these MOSFETs. conductance and sub-threshold slope techniques (techniques described in section 3.Following the approach by Witczak et al. Previous studies have measured such values on (100) SiO2/Si interfaces using the conductance technique. usually applicable from flat-band to weak inversion. marked by the shaded regions. (from which the conductance is calculated). The conductance technique. Nicollian and Brews[14] calculate the minimum Dit. is 9x1010 cm-2eV-1.e.7 shows the Dit as a function of energy in the silicon band gap. are likely to be in error.[190]. from the quadrature current. As expected for a (100) SiO2/Si interface. on band bending and doping concentration. For a doping concentration of 1017 cm-3. This might be due to the limitation of the LCR meter in separating the in-phase current. for both the n.[14] However it should be pointed out that the mid-gap values extracted using the high-low frequency technique here.and p-MOSFETs. 126 . that can be measured to within an accuracy of 10% at mid-gap. Dit exhibits a “U” shaped distribution with energy. with mid-gap values within the range low 109 to low 1010 cm-2eV-1. Dit was extracted using the high-low frequency. where significant round off error due to the subtraction of the low and high frequency capacitances occurs.4. due to the large MOSFET area.

Oxidation of a (110) surface results in a higher Dit than on a (100) surface due to a higher density of surface atoms and available bonds.8 1.0 Energy in Si band-gap (eV) Energy in Si band-gap (eV) Figure 5. Conductance Dit (cm eV ) (110) High-Low CV Conductance 1. The doping is fairly uniform with an average concentration of 8x1016 cm-3 for both n.0 0.0e+9 0.4 0.6 0.5 Col 8 vs Col 7 (100) ColHigh-Low 11 vs Col 10 CV Col 13 vs Col 14 1e+10 Valence band edge 0.4 0.2 Conduction band edge nMOS L = W = 100 µm T = 300 K 1e+9 0. S.6 (100) High-Low CV 1.2 0.and n-MOSFETs respectively.S. 127 .8 shows the extracted doping profiles for the n-well and p-well substrates.3 Substrate doping profiles Figure 5.0e+11 -2 -1 1e+11 -2 -1 Dit (cm eV ) (110) High-Low CV .0e+12 1e+12 S.[181. Shaded areas indicate regions close to flat-band where large round-off errors can occur due to the subtraction of high and low frequency capacitances.and p-wells on both wafers.0 0. 1.0e+10 Conduction band edge pMOS L = W = 100 µm T = 300 K Valence band edge 1.S.7 Dit extracted on 100 µm x 100 µm n. 5. corresponding to the p.8 0.Note the good agreement between techniques towards the minority band edges where the high-low frequency technique is most accurate and where the conductance and sub-threshold slope techniques could be applied.and p-MOSFETs as a function of silicon band gap energy.0 1.3.5 vs . may be due to the low resolution of the high-low frequency technique as already discussed. 191] The apparent lower Dit near mid-gap.

Excellent linear regressions (coefficients of determination close to 1) enabled Rsd and ∆L to be extracted with high accuracy for the n. MOSFETs with channel lengths of 0.1e+18 1e+18 T = 300 K L = W = 100 µm -3 Boron p-well.and p-MOSFETs on (100) and (110) orientations 5.8 Extracted doping profiles for 100 µm x 100 µm n. Nevertheless. Na (cm ) -3 Phosphorus n-well.4 Extraction of Rsd and ∆L It was expected that Rsd and ∆L would be negligible fraction of the total resistances and channel lengths.5 µm. The complete set of results is summarised in Table 5.2.and p-MOSFETs on both wafers. 128 . 1 µm and 3 µm and width 10 µm were used in the extractions. Nd (cm ) T = 300 K L = W = 100 µm (100) 1e+17 (100) 1e+17 (110) (110) 1e+16 1e+16 20 40 60 80 100 120 140 20 40 60 80 100 120 140 Wdepl (nm) Wdepl (nm) Figure 5. As an example.8 µm. 0. Rsd and ∆L extractions were performed to check this was the case. Figure 5.9 shows the Rsd and ∆L extraction for the (100) p-MOSFETs.

0 0. The results show that Rsd and ∆L make up negligible fraction of R and L and therefore do not need to be accounted for in any further analysis. (100) nMOS pMOS Rsd (Ωµm) 830 1690 ∆L (µm) 0.0 2. This can be explained by considering that boron diffuses more easily than arsenic.04 0. The greater diffusion reduces the abruptness of the junction resulting in a higher Rsd[193-194] and ∆L.9a) Linear regressions (Vgt = Vgs . the latter due to diffusion under the gate.7 µm MOSFETs in strong inversion Total resistance.14 R=Vds/Id (Ωµm) ~105 ~105 Table 5.0 3.[192] (due to its smaller mass) during the 30 second 950° RTA. R is for the OA 25 µm x 4.2 Summary of Rsd and ∆L for the n.15 (110) R=Vds/Id (Ωµm) ~105 ~106 Rsd (Ωµm) 150 1080 ∆L (µm) 0.2 V Intercept of regression 3500 2500 Increasing Vgt 2000 1500 Vgt = -3 V 1000 500 50 40 30 20 10 0 0 0.Vt) and b) second regression to extract Rsd and ∆L for (100) p-MOSFETs.0 1.4000 70 pMOS (100) T = 300 K W = 10 µm R = Vds/Id (Ω) 3000 Rsd = 169 Ω 60 ∆L = 0. The p-MOSFETs exhibit higher values of Rsd and ∆L than the n-MOSFETs.5 -10 600 700 Gate length (µm) 800 900 1000 1100 1200 Slope of regression Figure 5.5 3.5 2. Total resistance.5 1.05 0. R has been calculated for 25 µm long devices in strong inversion with Vds = ±10mV .and p-MOSFETs on (100) and (110) wafers. In addition boron diffusion is faster for (100) compared to 129 .15 µm Vgt = -1.

Vt = -2. 130 . S. Id is highest along the <100> and <110> directions on the (100) and (110) orientations respectively. A large number of Id-Vgs measurements with Vds = -10 mV over the whole range of channel directions were performed to extract gm. we now focus on the orientated angle (OA) MOSFETs.5 p-MOSFET current – voltage measurements For the remainder of the chapter. and µeff. Typically. Vt.(110) Si[195] which might explain the higher Rsd and ∆L for the (100) p-MOSFETs. indicating good switching behaviour which comes as no surprise considering the long channel lengths. Id-Vgt for these directions and orientations are shown in Figure 5. (Ion corresponding to Id at Vgt = Vgs .10. Ion/Ioff ratios of 108 were measured. Gate leakage current was always at least 4 orders of magnitude lower than Id on the (100) wafer and 7 orders of magnitude lower on the (110) wafer. The same mechanism may also explain the same trend in the n-MOSFET data.S. 5.5 V).

131 .1 Transconductance Figure 5.3 to 5. For the (110) wafer. a 50% variation in peak gm between the <110> and <100> directions is observed. The variation on each wafer is due to the anisotropic mtran.3 V. a 3% variation between the <100> and <110> directions is observed. which can be seen by differentiating equation (2. (Hole mobility is analysed in section 5.11 b) shows the full gm characteristics for a select range of channel directions as a function of Vgt.5.7.7 µm Vds = -10 mV (110) <110> 1e-1 (100) <100> 1e-2 Id (µA/µm) 1e-3 1e-4 1e-5 1e-6 1e-7 1e-8 1e-9 -3 -2 -1 0 1 Vgt (V) Figure 5. The (110)/<110> MOSFET shows a 54% enhancement over the (100)/<110> MOSFET despite its thicker gate oxide.7 µm (100)/<100> and (110)/<110> pMOSFETs 5.5). therefore hole mobility. normalised by channel width.1e+0 L = 25 µm W = 4. Whereas for the (100) wafer.11 a) shows peak gm.13) with respect to Vgs. Peak gm is a measure of mobility. A striking feature is the difference in degradation of gm between the two wafers above a Vgt of -0.7.10 Linear Id vs Vgt characteristic for 25 µm x 4. as a function of channel direction and Figure 5.

90 µFcm-2 for the (100) wafer and Cox = 0. Vt is independent of channel direction with Vt = -1.06 0.02 (100) (100) 0.7 µm (100) and (110) p-MOSFETs 5. which accounts for the small difference in Fermi-levels between the n+ poly gate and n-type substrate.12 shows Vt.7 µm Vds = -10 mV 0.00 0. For both wafers.01 0.6).7 µm Vds = -10 mV <110> L = 25 µm W = 4.<112> <100> <100> <110> <112> <111> <110> <100> <110> <112> <110> 0.1 V. as a function of channel direction.06 V extracted for the (100) and (110) wafers respectively.54 µFcm-2 for the (110) wafer.050 L = 25 µm W = 4. which accounts for difference in oxide thickness and confinement.035 0. calculated from the maximum slope of gm. into equations (2.4) and (2.055 0.02 V and -1.11 a) Peak gm vs channel direction/angle b) gm vs Vgt for 25 µm x 4. Nd = 8x1016 cm-3 and Cox = 0.13 V which are very close to the extracted values. 132 .03 0.2 Threshold voltage Figure 5.03 V and -1. Inserting Vfb = 0.04 (110) 0.05 <111> (110) 0.030 0 20 40 60 80 100 120 140 160 180 -3 -2 -1 0 1 Vgt (V) Angle (Degrees) Figure 5.045 gm (µS/µm) Peak gm (µS/µm) 0.040 <112> <100> 0.5. gives Vt = -1.

7 µm Vds = -10 mV -0.<112> <111> <110> <100> <110> <112> <100> <100> <110> <112> <110> 0.12 Vt vs channel direction/angle for 25 µm x 4.2 Vt (V) -0.S.2 0 20 40 60 80 100 120 140 160 180 Angle (Degrees) Figure 5.S. S.5. is independent of channel direction with S.3 Sub-threshold slope Figure 5.0 (110) -1.S. The slight scatter in the data is due to some of the devices anomalously exhibiting higher off current. = 70 mV/Dec. which degrades the ability for the device to switch from the off state to the on state and vice versa.7 µm (100) and (110) p-MOSFETs 5.13 shows the sub-threshold slope as a function of channel direction. slightly higher for the (110) wafer.0 L = 25 µm W = 4.4 -0. For both wafers.8 (100) -1. The increase above the ideal S. 133 . of ~ 60 mV/Dec is due to Dit. the origin of which is unknown and unimportant in this work. and 78 mV/Dec extracted for the (100) and (110) wafers respectively.6 -0.

On the (110) orientation. Id varies with channel 134 .4 eV for p-MOSFETs). At Vgt = 2 V.S.7 µm Vds = -10 mV 90 (110) 80 (100) 70 60 0 20 40 60 80 100 120 140 160 180 Angle (Degrees) Figure 5. The higher Ig in this case as compared to the p-MOSFETs is most likely due to the smaller SiO2 barrier at the minority carrier band edge (3. Ig was typically the same order of magnitude as Id for the (100) wafer and 4 orders of magnitude lower for the (110) wafer. Ig was higher in the n-MOSFETs than the p-MOSFETs requiring the gate leakage current correction to be applied to Id. a large number of Id-Vgs measurements over the whole range of channel directions were performed to extract gm. Vt.7 µm (100) and (110) p-MOSFETs 5. S. Id is highest on the (100) orientation where it is independent of channel direction.<112> <111> <110> <100> <110> <112> <100> <100> <110> <112> <110> Sub-Threshold Slope (mV/Dec) 100 L = 25 µm W = 4.13 Sub-threshold slope vs channel direction/angle for 25 µm x 4.6 n-MOSFET current-voltage measurements Following the same procedure on the p-MOSFETs. and µeff. In all measurements Vds = 10 mV.5 eV for n-MOSFETs compared to 4.

135 . The (110)/<100> n-MOSFET shows a 48% decrease compared to the (100) n-MOSFETs. For the (110) wafer.15a) shows the peak gm normalized by channel width as a function of channel direction and Figure 5.direction with its maximum along the <100> direction.7 µm (100)/<100> and (110)/<100> nMOSFETs 5.14 shows Id-Vgt characteristics for the (100)/<100> and (110)/<100> n-MOSFETs.15b) shows the full gm characteristics for a select range of directions as a function of Vgt. a 24% variation in peak gm between the <100> and <110> directions is observed.0 Vgt (V) Figure 5. peak gm is independent of channel direction. 1e+0 (100) <100> 1e-1 1e-2 (110) <100> Id (µA/µm) 1e-3 1e-4 1e-5 1e-6 1e-7 L = 25 µm W = 4.1 Transconductance Figure 5.0 0.5 0. Figure 5.5 1.5 2. Whereas for the (100) wafer.0 1.7 µm Vds = 10 mV 1e-8 1e-9 1e-10 -0. not accounting for the thicker oxide on the (110) orientation.14 Linear Id vs Vgt characteristic for 25 µm x 4.6.

2 Threshold voltage Figure 5. Vt = 0.6.10 0.10 gm (µS/µm) -1 Peak gm (µSµm ) 0.04 (110) 0.02 V for the (110) and (100) wafers respectively.5 2.<112> <111> <110> <100> <110> <112> <100> <100> <110> <112> <110> 0.11 V and 0.6) we obtain Vt = 0.14 0.08 (100) 0.12 (100) 0. 136 .04 0 20 40 60 80 100 120 140 160 180 0.16 shows Vt for both wafers is independent of channel direction.12 L = 25 µm W = 4. resulting in very small values of Vt.03 V for the (100) wafer which are very close to the extracted values.7 µm Vds = 10 mV 0.0 1. the n+ poly gate serves to deplete the substrate.14 0.08 <100> <112> <111> <110> 0.7 µm Vds = 10 mV L = 25 µm W = 4.0 Vgt (V) Angle (Degrees) Figure 5.5 1.06 0.15 a) Peak gm vs channel direction/angle b) gm vs Vgt for 25 µm x 4.5 0.13 V for the (110) wafer and 0. Unlike the p-MOSFETs. From equations (2.02 0.7 µm (100) and (110) n-MOSFETs 5.00 -0.4) and (2.0 0.06 (110) 0.

3 Sub-threshold slope S.16 Vt vs channel direction/angle for 25 µm x 4.04 (100) 0. is independent of channel direction with values of ~71 mV/Dec and ~78 mV/Dec for the (100) and (110) wafers.06 0.08 0. Again.S.S.7 µm Vds = 10 mV 0.12 (110) Vt (V) 0.6.10 L = 25 µm W = 4.7 µm (100) and (110) n-MOSFETs 5.<112> <111> <110> <100> <110> <112> <100> <100> <110> <112> <110> 0. 137 .00 0 20 40 60 80 100 120 140 160 180 Angle (Degrees) Figure 5.14 0. is shown in Figure 5. As for the p-MOSFETs.17. the scatter in the data is due to some devices exhibiting anomalously high off currents.02 0. S.

interface charge and roughness from the SiO2/Si interface. Thus the mobility limiting scattering mechanisms are due to bulk phonons.7 Effective mobility The variation in Id and gm with channel direction and orientation is due to the variation in mobility. At 4 K. 196198] interface should be negligible for the oxide thicknesses in this work.<112> <111> <110> <100> <110> <112> <100> <100> <110> <112> <110> Sub-Threshold Slope (mV/Dec) 100 L = 25 µm W = 4. Remote charge and remote roughness scattering from the poly-Si/SiO2[37. the 138 . We now examine the dependence of effective mobility on surface orientation and channel direction. ionised impurities in the substrate.17 Sub-threshold slope vs channel direction/angle for 25 µm x 4.7 µm Vds = 10 mV 95 90 85 (110) 80 75 70 (100) 65 0 20 40 60 80 100 120 140 160 180 Angle (Degrees) Figure 5. Id-Vgs measured with Vds = ±10mV was sufficiently low that error in peak µeff due to the finite Vds did not exceed 2%.7 µm (100) and (110) n-MOSFETs 5. 71. phonons are frozen out allowing a more detailed study of interface roughness.

This can be explained by considering that quantum confinement between the oxide and conduction band splits the degeneracy of the ∆2 and ∆4 conduction band minima.190 0. is presented in section 5. 5.190 0.3 for convenience.19m0 for ∆4) the majority of electrons populate the lower energy ∆2 valleys which have circular constant energy contours in the xy plane (confinement in the z direction).190 0.19m0 independent of channel direction and.190 (Modulated by confinement) 0. for both (100) and (110) orientations.916 0.7. Modelling of the 4 K mobility to extract the SiO2/Si roughness parameters.1 n-MOSFETS .190 mconf/m0 mscat/m0 gv 0.916 0. The mobility on the (100) wafer is independent of channel direction with peak µeff ~ 455 cm2V-1s-1.8. (mconf = 0. Electrons thereby have mtran = 0.3 Electron effective masses for the (100) and (110) orientations Figure 5.315/0.18a) shows the peak mobility as a function of channel direction and Figure 5.553 0. Due to the large difference in mconf.Variation of µeff with channel direction and surface orientation The electron effective masses are reproduced in Table 5.315 0. ∆ and Λ.6 MVcm-1.190/0. for a 139 .417 0.18b) shows the mobility at Eeff = 0.553 0.324 0.190 0.190 0.916m0 for ∆2 and mconf = 0.417 ∆2 ∆4 ∆4 ∆2 Table 5.dominant cause of mobility degradation at high Eeff. Surface Orientation (100) (110) <100> <110> mtran/m0 mtran/m0 0.916 0.

µeff is independent of channel direction. ∆4 valleys. the splitting is a lot smaller due to the small difference in confinement masses (mconf = 0. At Eeff = 0. Compared to the (100) orientation. Thus if the population of the ∆2 valleys increases at the expense of the ∆4 valleys. the µeff variation can be explained considering the more heavily populated.[24] From figure 2.190m0) directions). 140 . reducing µeff to 350 cm2V-1s-1. the µeff variation is reduced. mtran is largest (0.5.190m0 for ∆2) and at room temperature. µeff = 336 cm2V-1s-1 along the <100> direction and 267 cm2V-1s-1 along the <110> direction.19m0) along the <100> direction. corresponding to the lowest µeff and lowest (0. Under confinement.given Eeff.553m0) along the <110> direction. The variation can be explained by an anisotropic mtran. In the ∆2 valleys. corresponding to the highest µeff.6 MVcm-1.315m0 for ∆4 and mconf = 0. However.916m0) and smallest along the <110> (0. The peak mobility on the (110) wafer varies by 26% depending on orientation. the ∆4 valleys are lower in energy than the ∆2 valleys. interface roughness scattering dominates. a large percentage of electrons have sufficient energy to occupy the ∆2 valleys. mtran varies in the opposite direction (largest along the <100> (0.

7.[199-200] The small roll off at low Eeff is due to LCS and IIS. making it difficult to analyse these effects. The smaller energy split results in increased inter-band optical phonon scattering and population of ∆2 valleys.[201].<112> <111> <110> <100> <110> <112> <100> <100> <110> <112> <111> <110> <100> <110> <112> <110> <112> <100> <100> <110> <112> <110> 400 Electron µeff (cm V s ) 350 -1 -1 450 (100) (100) 300 2 2 -1 -1 Peak electron µeff (cm V s ) 500 L = 25 µm W = 4.7 µm Vds = 10 mV 400 350 300 (110) Angle vs Peak Mobility Angle Si(110) vs Peak mobility 250 L = 25 µm W = 4. In the work by Nakabayashi et al.7 µm Vds = 10 mV 200 Eeff = 0. An understanding of the processes affecting the lower limit of µeff in this regime is restricted by accurate calculation of Qinv.6 MVcm-1 150 (110) 100 250 50 0 20 40 60 80 100 120 140 160 180 0 20 40 Angle (Degrees) 60 80 100 120 140 160 180 Angle (Degrees) Figure 5. The higher density of states results in a higher scattering frequency. the mobility limited by LCS is largely 141 .18a) Peak electron µeff and b) electron µeff at Eeff = 0. the individual mobilities limited by LCS and IIS have been extracted and analysed.19 and may be qualitatively interpreted on the basis of models used by previous authors. For a given Dit.6 MVcm-1 vs channel direction/angle for 25 µm x 4.2 n-MOSFETs – Variation of µeff with Eeff µeff vs Eeff for a select range of devices on the (100) and (110) orientations are shown in Figure 5.7 µm (100) and (110) n-MOSFETs 5. The lower µeff on the (110) orientation is largely attributable to the smaller energy split between the ∆4 and ∆2 valleys and the larger density of states of the lower energy valleys.

9) might be expected. At Eeff = 0.[159] show that LRS begins to limit µeff at lower Eeff on the (110) orientation.independent of orientation due to a trade-off between mconf and mtran. differences in confinement between orientations are irrelevant to the mobility limited by IIS.19b) shows µeff measured at 4 K and Figure 5. Once Eeff increases beyond ~0.4 MVcm-1 142 . This results in an increase in µeff along the <110> and a decrease along the <100> directions.1 eV. thereby increasing the occupancy of the ∆2 valleys at the expense of the ∆4 valleys. shown more clearly in Figure 5. This can be understood considering the higher density of states and therefore LRS rate.4 MVcm-1.[199] In addition. .18b) This reduction between (110)/<100> and (110)/<110> with increasing Eeff is attributable to the non-parabolicity of the E-k relationship along the <110> direction at the energy minima. Figure 5. the non-parabolicity reduces the energy difference between the ∆2 and ∆4 valleys. Since ionised impurities are distributed uniformly in the substrate. increasing scattering.6 MVcm-1 the variation in µeff with channel direction is reduced to 20%. However the decrease above Eeff ~0. which then decreases the rate of splitting with increasing Eeff. which serves to reduce the mobility.[24-25] This also accounts for the steeper decrease in µeff with increasing Eeff on the (110) orientation compared to that on the (100).20 shows the ratio µeff <100>/µeff <110> at 300 K and 4 K. This effectively increases mconf of the ∆2 valleys when their minima exceed 0. At 4 K the majority of carriers reside in the ∆4 valleys[24] and therefore a constant ratio equal to mtran <100>/ mtran <110> (~2. Gaubert et al.A larger mconf results in confinement of carriers nearer to the interface charge.

4 2. These ratios show the same trend as Uchida et al.[24] 143 .19 Electron µeff vs Eeff extracted at 300 K and 4 K.1 -1 1 Eeff (MVcm ) 0. Takagi et al.’s data (Na = 1x1017 cm-3 for (110)[155] and 7.[24] 10000 1000 (100) -1 -1 Electron µeff (cm V s ) eff (110) Takagi et al.7 µm Vds = 10 mV T=4K 10 0.7 µm Vds = 10 mV T = 300 K 10 1000 <100> (110) <112> <111> <110> 100 L = 25 µm W = 4.2x1016 cm-3 for (100)[154]) is included for comparison.6 1.20 Electron µeff <100>/µeff <110> vs Eeff at 300 K and 4 K on the (110) orientation.2 1.2 4K L = 25 µm W = 4. (110) electron µ<100>/µ<110> 2.4 300 K 1.1 -1 EEff (MVcm ) 1 Figure 5. 2 2 -1 -1 Electron µ (cm V s ) (100) <100> <112> <111> <110> 100 L = 25 µm W = 4. one plot is shown as µeff is independent of channel direction.7 µm Vds = 10 mV 2. For the (100) orientation.demonstrates that the increase in mconf of the ∆2 valleys due to the non-parabolicity is sufficient that electron repopulation still plays a role.0 1.0 0.8 1.1 -1 1 EEff (MVcm ) Figure 5.

34.) 0. for very low Ninv) are reproduced below for convenience.15 (Saito et al.) 0.. University of Glasgow.e. mscat and mtran for the HH band were calculated using 4 band k•p at k = 0 by Dr.43 (Takagi et al. there are no reports of how mtran.7.) 0.) (Saito et al.2 (Takagi et al. channel direction and Ninv has been investigated by many authors.15 (Saitoh et al.4 Literature values of hole effective masses calculated at k = 0. The masses are shown in Table 5.29 (Takagi et al. Saitoh et al. Jeremy Watling at the Device Modelling Group.20 0.5.) HH 0.[29-30. 202-204] However the role of the effective masses and LH-HH sub-band splitting is under debate.58 (Saito et al.28 0.) (Saito et al. mscat and mconf vary with Ninv.50.59 (Mizuno et al. mconf.) (110) mscat/m0 mconf/m0 Subband 0.3 p-MOSFETs – Variation of hole µeff with orientation Hole mobility as a function of surface orientation.) 0. making a comprehensive understanding of the mobility and scattering mechanisms difficult. The reported hole effective masses (at k = 0 i. 0.17 (Takagi et al. 184.5 144 .) HH LH Table 5. Whilst the variation of mobility with channel direction is explained by an anisotropic mtran.) LH 0. Surface Orientatio n (100) mtran/m0 <100> mtran/m0 <110> 0.

56 <111> 0.[199-200] shows for a doping concentration of ~1017 cm-3 the LH-HH energy split on the (110) 145 . 199.5 Effective masses calculated by 4 band k•p for the HH sub-band (calculated by Dr Jeremy Watling) Note the good agreement with the literature values.28 mscat/m0 0. In the case of the (110) wafer.21b) shows µeff at Eeff = 0.6 MVcm-1/Ninv = 1x1013 cm-2 these enhancements increase to 300% and 80%.21a) shows the peak µeff as a function of channel direction and Figure 5. Comparing the two orientations.(100) mconf/m0 0. peak µeff varies by ~46% between the <110> (peak µeff = 242 cm2V-1s-1) and <100> (peak µeff = 165 cm2V-1s-1) channel directions. 35] Uchida et al. It is reminded that hole mobility is plotted as a function of Ninv as well as Eeff due to the ambiguity of η in the calculation of Eeff (equation 3. Recent work [34-35. 204] attributes the higher mobility on the (110) orientation to the suppression of inter-band optical phonon scattering using the following argument.56 mscat/m0 0. The LH-HH energy split is larger on the (110) orientation than on the (100) due to the larger difference in mconf.54 mtran/m0 <100> 0. Peak µeff on the (100) wafer varies by ~7% between the <100> (peak µeff = 139 cm2V-1s-1) and <110> (peak µeff = 130 cm2V-1s-1) channel directions. At Eeff = 0.28 <110> 0.42 (110) mtran/m0 <100> 0.56 <112> 0.6 MVcm-1/Ninv = 1x1013 cm-2.56 mconf/m0 0.[29.28 <110> 0. peak µeff on the (110) orientation is enhanced by 86% along the <110> direction and 19% along the <100> direction. The values obtained for (110) mtran and mscat are discussed in relation to µeff further on.23). Figure 5.69 Table 5.

’s[119] (110) hole µeff is included in Figure 5.7 µm Vds = -10 mV T = 300 K 240 2 -1 -1 Peak hole µeff (cm V s ) 260 60 0 20 40 60 80 100 120 140 160 180 0 Angle (Degrees) 20 40 60 80 100 120 140 160 180 Angle (Degrees) Figure 5. which is significant at low Ninv. the LH-HH energy splitting is much smaller than the optical phonon energy. Note η = ⅓ is used in the calculation of Eeff. shown more clearly in Figure 5. 146 .6 MVcm-1 vs channel direction/angle for 25 µm x 4.7 µm (100) and (110) p-MOSFETs.orientation is larger than the optical phonon energy. It is expected that their larger µeff.6 MVcm-1 180 160 T = 300 K 140 120 100 (100) 80 120 Ninv ~ 1x1013 cm-2 (110) Si (100) Angle vs Peak mobility Si (110) Angle vs Peak Mobility 2 (110) -1 -1 220 <112> <110> L = 25 µm W = 4. Although this partly explains the weak dependence of µeff with Eeff/Ninv on the (110) orientation and the strong degradation of µeff on the (100) orientation. For comparison. On the (100) orientation.22b).22a) and Figure 5.22. might be explained by a lower doping concentration. <112> <111> <110> <100> <110> <112> <100> <100> <110> <112> <111> <110> <100> <110> <112> <110> <112> <100> <100> <110> 240 200 180 160 (100) 140 200 EEff = 0. The variation with Eeff and Ninv for a few select channel directions are shown in Figure 5.22b). Thus inter-band optical phonon scattering is suppressed.7 µm Vds = -10 mV 220 Hole µeff (cm V s ) L = 25 µm W = 4. therefore lower IIS and LCS. this argument does not account for the difference in mtran and mscat between the two orientations or the impact of the other scattering mechanisms. thus optical phonon scattering is not suppressed regardless of Eeff. particularly with increasing Eeff. Irie et al.21a) Peak hole µeff and b) µeff at Ninv = 1x1013 cm-2/Eeff = 0.

1x1016 cm-3) is included for comparison b) Hole µeff vs Ninv.[29] show that µeff should be higher in the <110> direction than the <100> direction.7. Irie et al. (100) <110> <100> 100 Irie et al. the peak µeff on the (100)/<100> orientation is 7% higher than on the (100)/<110> orientation. they state this “might result in a µeff enhancement of a factor ~2”. We now discuss the behaviour of hole µeff on the (100) orientation.[159] measure a 10% enhancement in the <100> direction but provides no physical explanation. As already stated.7 µm Vds = -10 mV T = 300 K -2 1e+13 Ninv (cm ) Figure 5. Sayama et al. Note η = ⅓ is used in the calculation of Eeff. As mtran differs by a factor of 2 between the two directions.’s[119] (110)/<110> and <100> data (Nd ~ 1015 cm-3?) is included for comparison. Saito et al. Simulations by Fischetti et al. serving to increase µeff.4. Takagi et al.[32] observe a 5% enhancement in the <100> direction. The small difference of mconf between the LH and HH sub-bands results in a small HH and LH splitting and subsequently a large occupation of the LH.4 p-MOSFETs – Variation of hole µeff with Eeff/Ninv <110> (100) 10 0.’s[154] (100)/<110> data (Nd = 5. (110) <110> (110) <100> -1 -1 (110) 1000 L = 25 µm W = 4. On the other hand Gaubert et al. specifying the masses in Table 5.[205] measure an ~8% enhancement in the <100> direction at low Eeff and attribute it to the lighter HH mass in the <100> direction.22a) Hole µeff vs Eeff.5.7 µm Vds = -10 mV T = 300 K Hole µeff (cm V s ) <112> <100> <110> <111> -1 -1 Hole µeff (cm V s ) 1000 1 (110) <100> 100 <110> (100) Eeff (MV/cm) vs Si (100) OA0 Eeff (MV/cm) vs Si (100) OA44 Col 13 vs Si (110) OA0 Col 13 vs Si (110) OA24 Col 13 vs Si (110) OA54 Col 13 vs Si (110) OA146 10 1e+11 1e+12 L = 25 µm W = 4. particularly along the <110> 147 . However this can only be based on occupation of the HH band.1 EEff (MVcm-1) <110> <100> 2 2 Takagi et al.

T )d 2 k || (5. Francisco 148 . the effective masses in the HH sub-band at 300 K and 4 K as a function of Ninv/Eeff were calculated by Dr. HH 1 ∂2E = 2 h ∂k x2 HH 1 = 2 h ∫ ∂ 2 E HH (k|| ) ∂k x2 f (E HH (k || ).26. What is actually observed is a small decrease in enhancement.4.1) Upon the author’s request.5 Improved effective mass calculation and 300 K hole µeff analysis A more appropriate method to calculate the hole masses is to average equation (2. where population of the HH sub-band is higher. ~4% at Eeff = 0. µeff can not be explained in terms of the effective masses in Table 5. Takagi et al.direction.18) over k in the transport plane.6 MVcm-1. At 4 K. the calculated values of mtran on the (110) orientation also do not predict the correct trend in mobility . Luca Donetti and Prof. Furthermore. calculated at k = 0 have very limited application in explaining µeff. more holes occupy the HH band. 1 mtran .forecasting the highest mobility along the <100> channel direction. Despite the small difference in mconf.7. k||.[31] Thus to calculate mtran in the HH sub-band. possibly explaining the small enhancement. a much greater enhancement is expected. Thus more detailed calculations of the hole masses are required to correctly interpret the mobility. points out that with increasing confinement. 5. Therefore we might expect to see the enhancement increase with increasing Eeff/Ninv. It is therefore fair to say that effective masses. weighted by the Fermi distribution. only a 9% enhancement in peak µeff is observed as shown in Figure 5. However. From the above discussion.

The variation on the (110) orientation is comparable to the variation in the experimental µeff.23 shows mtran. E HH (k || ) was calculated with their 6-band k•p-Poisson solver. The simulator calculates mtran as a function of Ninv. mconf was evaluated based on known energy levels in triangular wells with different Eeff. To gain a simplistic understanding of µeff. Figure 5. This is obviously more accurate for the (110) orientation due the large LH-HH sub-band splitting. Francisco Gamiz. we follow the approach of Donetti et al.7 mtran/m0 0. calculated by this technique at Ninv = 1x1013 cm-2.5 0. as a function of channel direction on both the (100) and (110) orientations.3 Ninv ~ 1x10 13 -2 cm 0. (Calculations performed by Luca Donetti and Prof.2 0 20 40 60 80 100 120 140 160 180 Angle (Degrees) Figure 5.4 (110) 0.7 0. mtran was calculated from an average over the k-plane for Ninv = 1x1013 cm-2. Universidad de Granada. Spain.[31] and analyse µeff in terms of the dominantly occupied HH sub-band.8 (100) 0. details of which are given in [30-31].Gamiz at the Departamento Electronica. <112> <111> <110> <100> <110> <112> <100> <100> <110> <112> <110> 0.6 x1.8 x2.23 mtran in the HH sub-band as a function of channel direction on (100) and (110) orientations.) 149 .

This implies that reduced inter-band optical phonon scattering at high Ninv is of secondary importance.25 shows mconf vs Eeff. It is interesting to observe that mtran and mscat on the (110) orientation decrease with increasing Ninv whereas they increase with increasing Ninv on the (100) orientation. However the difference may be small enough to have been averaged out during the calculations.58m0 at Ninv = 3x1010 cm-2 agreeing with Saito et al.24a) and b) shows mtran and mscat vs Ninv and Figure 5. For the (100) orientation and <110> direction. this value is not relevant for the full range of device operation. We now propose a hypothesis as to why the scattering mechanisms appear to play a secondary role. observed in Figure 5.22b). the scattering mechanisms are 150 . i. mtran = 0. At low Ninv. mtran is larger on the (110) orientation. On the (100) orientation. Firstly. This explains the crossover in µeff between the (100) and (110) orientations at low Ninv. mtran is independent of channel direction.[32] However. the variation in mtran is comparable to the variation in µeff with enhancements of 270% and 80% over the (100) orientation. A slightly lower mtran in the <100> direction than in the <110> direction was expected to explain the small enhancement of µeff. Figure 5. largely explaining not only the variation of µeff with channel direction but also the enhancement of µeff over the (100) orientation. Thus it can be inferred that mtran largely explains the difference between µeff on the (100) orientation and on the (110) orientation as a function of Ninv as well as channel direction.On the (110) orientation.e. mtran has been calculated for just the <100> and <110> directions on the (110) orientation as these directions show the greatest variation in µeff.

increasing scattering. On the (100) orientation. the weaker confinement. Then again.4 and Table 5.5.3. As discussed in section 5.7. However the weaker confinement has the benefit of weaker LCS and LRS. is approached as Eeff tends to zero. In the case of the (110) orientation.3.7. 0.5.4 and Table 5. 151 . reducing scattering.convoluted functions of mscat and mconf.) It is possible that the increase in mconf and the decrease in mscat with increasing Ninv compensate each other. the increase in mconf increases the LH-HH sub-band splitting reducing inter-band optical phonon scattering. the decrease in mscat means a reduction in the density of states. mconf increases with Eeff. results in smaller LH-HH subband splitting and large inter-band optical phonon scattering. results in stronger LCS and LRS as the respective scattering potentials are higher closer to the interface. On the other hand. close to the values in Table 5. However the increasing confinement. (Note the value. mconf = 0. the increase in mscat means an increase in the density of states. as compared to the (110) orientation.27m0 independent of Ninv which is in agreement with the values in Table 5.56m0. As discussed in section 5.

8 (110) <100> 0. any difference in interface roughness between the two orientations is currently unknown.2 1.0 0.0 1e+10 1e+11 1e+12 0.4 0. (calculations performed by Luca Donetti and Francisco Gamiz) 2.8 4 K effective mobility modelling So far we have qualitatively been able to explain the variation in µeff in terms of the effective masses. Whilst slightly higher Dit on the (110) wafer than the (100) wafer has been measured. it is very difficult to ascertain the role of the various material parameters.6 mscat/m0 mtran/m0 (100) 0.5 2. 152 .0 1. However.0 1e+10 1e+13 1e+11 1e+12 1e+13 -2 -2 Ninv (cm ) Ninv (cm ) Figure 5.25 mconf vs Eeff (calculations performed by Luca Donetti and Francisco Gamiz) 5.0 0.0 -1 EEff (MVcm ) Figure 5.4 <110> 0.6 (110) mconf/m0 1.24a) mtran in the HH sub-band as a function of Ninv The variation explains the difference in µeff between the (100) and (110) orientations b) mscat as a function of Ninv.6 (100) 0.2 0.8 (100) 1.4 0.6 0.2 (110) 0.2 0.0 0.5 1. due to the different contributions of mconf. mscat and mtran.0 0.4 1.1.2 T = 300 K T = 300 K 0.8 0.0 1.8 1.

shows roughness at a SiO2/Si interface on a (110) orientation is isotropic.[202] assumes a smoother (110) interface in their modelling. 10000 <100> <100> Ninv (cm-2) vs 4K Si (100) 0 deg (100) Ninv (cm-2) vs 4K Si (100) 140 deg 5mV Ninv (cm-2) vs 4K Si (110)<110> OA54 <110> Ninv (cm-2) vs 4K Si (110) OA150 <100> 100 0.[180] show using transmission electron microscopy and from mobility measurements that the roughness is the same in their devices. By measuring µeff at 4 K. phonons are frozen out and the effects of Coulomb and roughness scattering can be more easily determined. the rougher the interface. Figure 5. On the contrary Sun et al.26a) 4 K hole µeff vs Eeff.[182-183] and Momose et al.7 µm Vds = -10 mV T=4K -1 -1 (110) 2 2 <110> 1000 Hole µeff (cm V s ) L = 25 µm W = 4.1 -1 Eeff (MVcm ) L = 25 µm W = 4. Although this has been observed to affect µeff at a GaAs/AlAs interface[207]. b) 4 K hole µeff vs Ninv 153 (110) 1000 . Yang et al. Another consideration is that roughness may be anisotropic.[188] show oxidation of a (110) Si substrate results in a higher interface roughness whereas Yang et al.and requires a quantitative analysis.[181] and Nakamura et al. The study by Chen et al.[206] shows the thicker the oxide.26 shows the hole µeff measured at 4 K and Figure 5. the study by Sun and Plummer[208].7 µm Vds = -10 mV T=4K -1 -1 Hole µeff (cm V s ) 10000 1 <110> <100> <100> <110> (100) 100 1e+11 1e+12 1e+13 -2 Ninv (cm ) Figure 5.27 shows mtran and mscat calculated at 4 K.

0.55 Table 5.1 1e+11 1e+12 -2 1e+13 1e+14 -2 Ninv (cm ) Ninv (cm ) Figure 5. µeff is modelled up to Ninv ~6x1012 cm-2 using constant values of mscat and mtran.6.3 <110> 0.27a) mtran as a function of Ninv b) mscat as a function of Ninv at 4 K Using the scattering theory in section 2.2 0.91 0.5 mscat/m0 0. These are shown in Table 5.27 0.7 0.23 <100> 0.19 <110> 0.25 0.6 0.32 <100> 0.19 gv mconf/m0 mscat/m0 mtran/m0 4 0.22 n-MOS (100) gv 2 mconf/m0 mscat/m0 0. within 15% of those calculated in Figure 5. µeff measured at 4 K is modelled in terms of IIS.7 (110) <100> 0.56 mtran/m0 <110> 0.8 0. 154 .4 0.6 mtran/m0 T=4K 0.40 <110> 0.5. ∆ and Λ as fitting parameters.6 4 K effective masses used in the modelling of 4 K hole µeff. LCS and LRS using nimp.2 0.3 0.8 (100) 0.5 0.27.32 0.9 T=4K (100) 0.4 (110) 0.56 gv mconf/m0 mscat/m0 mtran/m0 1 See Figure 5.1 1e+11 1e+12 1e+13 1e+14 0.19 (110) mtran/m0 <110> 0. 4 K effective masses used in modelling p-MOS HH band (100) (110) gv mconf/m0 mscat/m0 1 0.

6 nm[29]. [38] and Pirovano et al.55 nm[38] and Λ varies between 1 nm[36] and 2.28 Doping profile extracted from CV at 4 K. For a (100) SiO2/Si interface. 300 K average doping concentration shown for comparison Intuitively we would expect ∆ and Λ for n.24 nm[209] to 0. Indeed. measurement noise prevented reliable extraction beyond approximately 80 nm. Although Wdep = 120 nm was measured.28 shows an extraction of the doping profile at 4 K.To model IIS. -3 4 K effective Na/Nd (cm ) 1e+17 300 K average 8e+16 (100) n-MOS 6e+16 (110) 4e+16 p-MOS 2e+16 T=4K L = W = 100 µm 0 20 30 40 50 60 70 80 Wdep (nm) Figure 5.30 show examples of µLCS and µLRS calculated for different values of nimp.and p-MOSFETs to be the same on a given wafer. Figure 5.29 and Figure 5.[36] stress that the validity of ∆ and Λ must be judged on whether the values can explain both electron and hole surface roughness mobility consistently. Figure 5. we have to bear in mind that the ionised doping concentration decreases when cooling. ∆ and Λ. reports of ∆ range from 0. Ishihara et al. 155 .

31 and Figure 5. µTot has been calculated using Matthiessen's rule: 1 µ Tot = 1 µ IIS + 1 µ LCS + 1 (5.2 nm 1e+4 ∆= 0.7 and the respective fits to the 4 K µeff data are shown in Figure 5. The total mobility.30 Calculated µLRS as a function of Ninv for different values of ∆ and Λ for a (100) nMOSFET As expected. 156 .6 nm 1e+3 1e+5 1e+4 Λ= 1.29 Calculated µLCS as a function of Ninv for different values of nimp for a (100) nMOSFET 1e+7 1e+7 ∆= 0.5 nm 1e+3 1e+2 1e+2 0 1e+12 2e+12 3e+12 4e+12 5e+12 6e+12 -2 0 1e+12 2e+12 3e+12 4e+12 5e+12 6e+12 -2 Ninv (cm ) Ninv (cm ) Figure 5.1e+5 nimp = 3x1011 cm-2 1e+4 nimp = 5x1011 cm-2 2 -1 -1 µLCS (cm V s ) nimp = 1x1011 cm-2 1e+3 1e+2 0 1e+12 2e+12 3e+12 4e+12 5e+12 6e+12 -2 Ninv (cm ) Figure 5.4 nm ∆= 0.and p-MOSFETs are shown in Table 5.4 nm Λ= 2 nm 1e+6 -1 -1 LRS µ (cm V s ) 1e+5 2 2 -1 -1 LRS µ (cm V s ) 1e+6 ∆= 0.2) µ LRS The modelling parameters for the (100) n.5 nm 2 nm Λ= 2. decreasing the mobility. increasing either one of these parameters increases the relevant scattering rate.32.

33 and Figure 5. One might expect nimp at 4 K to be greater than the Dit measured at 300 K. An interesting result is that ∆ and Λ agree with the (100) wafer within error suggesting the oxide interfaces are very similar for the two orientations. were necessary to fit the data at higher Ninv.34 nm and Λ = 2 nm. Values of ∆ = 0. calculated by equation (2. using the effective masses in Table 5.and p-MOSFETs at low Ninv.34.7). caused by the decrease in intrinsic carrier concentration. Using similar parameters (Table 5. nimp ~5x1012 cm-2.56 eV due to the shift in Fermi-level towards the majority carrier band edge. Thus more interface traps are charged over the wider energy range.6 was unsuccessful necessitating very large fitting parameters. At 300 K this energy difference is ~0. However we must be mindful of the assumptions used in these models and that the various fitting parameters can mask their shortcomings. However at 4 K. This is most likely due to occupation of the higher ∆2 sub-bands.4). e.g. good fits to µeff on the (110)/<100> and <110> p-MOSFETs were obtained as shown in Figure 5. Modelling of the (110) n-MOSFETs.10). lowered by their non- 157 .4 eV.A value of nimp ~ 3x1011 cm-2 which is comparable to the extracted Dit near weak inversion (Figure 5.8). this could be closer to 0. and constant doping of 6x1016 cm-3 enabled good fits to µeff of both n. Consider that in strong inversion the charged interface states exist between mid-gap and the Fermi-level (figure 2. which lie within the range reported in the literature.

Luca Donetti to verify the fitting parameters. Detailed simulations of the 300 K and 4 K data are currently in progress by Dr.parabolicity. 158 .

3 2 .0 x 1011 ± 0.7 µm Vds = -10 mV T=4K 1e+5 2 -1 -1 Hole µeff (cm V s ) 1e+6 (100) pMOS IIS 1e+4 LCS LRS 1e+3 LCS+IIS+LRS 1e+2 0 1e+12 2e+12 3e+12 4e+12 5e+12 6e+12 -2 Ninv (cm ) Figure 5.7 Fitting parameters used in the modelling of (100) electron and hole 4 K µeff 1e+6 L = 25 µm W = 4.05 Λ (nm) 2 .05 0.5 x1011 n-MOS p-MOS Na/Nd (cm-3) 6.0 ± 0 . LCS and LRS 159 .34 ± 0. LCS and LRS L = 25 µm W = 4.34 ± 0.5 x1011 3.0 ± 0 .3 Table 5.0x1016 6.0 x 1011 ± 0.32 Modelling of the 4 K (100) hole µeff in terms of IIS.31 Modelling of the 4 K (100) electron µeff in terms of IIS.0x1016 ∆ (nm) 0.(100) 4 K modelling parameters LCS IIS LRS nimp (cm-2) 3.7 µm Vds = 10 mV T=4K 2 -1 -1 Electron µeff (cm V s ) (100) nMOS 1e+5 LRS Col 4 vs Col 2 Col 4 vs IIS Col 4 vs LCS IIS Col 4 vs SR Col 4 vs Col 8 1e+4 LCS LCS +IIS+ LRS 1e+3 0 1e+12 2e+12 3e+12 4e+12 5e+12 6e+12 -2 Ninv (cm ) Figure 5.

3 ± 0 .3 Table 5.32 ± 0.38 ± 0.34 Modelling of the 4 K (110)/<110> hole µeff in terms of IIS.4x1016 ∆ (nm) 0.3 2 .33 Modelling of the 4 K (110)/<100> hole µeff in terms of IIS.7 µm Vds = -10 mV T=4K 1e+5 2 -1 -1 Hole µeff (cm V s ) 1e+6 (110)/<100> pMOS IIS 1e+4 LRS LCS 1e+3 LCS+IIS+LRS 1e+2 0 1e+12 2e+12 3e+12 4e+12 5e+12 6e+12 -2 Ninv (cm ) Figure 5.4x1016 5.0 x 1011 ± 0.3 ± 0 .05 Λ (nm) 2 . LCS and LRS L = 25 µm W = 4.2 x 1011 ± 0. LCS and LRS 160 .7 µm Vds = -10 mV T=4K 1e+5 (110)/<110> pMOS IIS 2 -1 -1 Hole µeff (cm V s ) 1e+6 1e+4 LRS LCS 1e+3 LCS+IIS+LRS 1e+2 0 1e+12 2e+12 3e+12 4e+12 5e+12 6e+12 -2 Ninv (cm ) Figure 5.5 x1011 3.05 0.8 Fitting parameters used in the modelling of (110)/<100> and <110> 4 K hole µeff L = 25 µm W = 4.p-MOS (110) 4 K modelling parameters LCS IIS LRS nimp (cm-2) 3.5 x1011 <100> <110> Na/Nd (cm-3) 5.

9 Summary n.5. gm.and p-MOSFETs with n+polySi/SiO2 gate stacks. local charge and roughness scattering mechanisms (phonons frozen out) revealed comparable Si/SiO2 interface quality between the (100) and (110) orientations. Dit.S. substrate orientation and channel direction could largely be explained by the variation in transport mass. to interpret the hole µeff.. µeff was also extracted at 4 K. The hole band structure is much more complicated and required novel sophisticated calculations of the effective masses of the dominantly occupied HH sub-band. Subsequently. The behaviour of the electron mobility can be explained relatively easily in terms of constant effective masses and sub-band splitting thanks to the simple conduction band-structure. the dependence of hole µeff on Ninv. µeff and the doping profile were extracted at room temperature. The main focus is on the analysis of µeff as a function of Ninv. substrate orientation and channel direction. fabricated on (100) and (110) orientated wafers have been electrically characterised in detail. S. 161 . Vt. Analytical modelling of the 4 K electron and hole mobility in terms of ionised impurity. Rsd. ∆L.

The 162 . 6. However. the electrical characteristics of planar MOSFETs on (100) and (110) surface orientations were analysed in detail.1 Introduction In chapter 5. whose physical properties may differ. The thickness of the BOX was ~145 nm and the thickness of the SOI was ~ 88 nm. 300 mm boron doped SOI (100) wafers (provided by SOITEC) of resistivity 10-15 Ωcm (corresponding Na ~ 1015 cm-3) were used as the starting platform. Belgium using a VLSI-compatible process. Much of the analysis is used in this chapter to interpret the mobility in state of the art finFETs. we now have the added complexity of both surfaces.Chapter 6 : Si finFETs with high-κ dielectrics and metal gates 6. being present on a single device and also the inclusion of high-κ dielectrics and metal gates.2 Device overview N-channel and p-channel finFETs were fabricated on separate wafers at NXP Semiconductors. The basic process flow is summarised as follows.

Fins were defined along the <110> and <100> directions (parallel and 45° to the wafer flat respectively) to produce finFETs with (110) and (100) sidewalls. roughened during the dry etch.6O and 5 nm TiN deposited by plasma enhanced atomic layer deposition and a poly-Si cap. The gate stack. fabricated on a BOX. with the BOX acting as an etch stop layer. A dry etch (reactive ion etch) of the hard mask and Si was then performed. Figure 6. followed by metal organic chemical vapour deposition (MOCVD) of 2.3 nm Hf0. which straddles the fin. was formed by a 1 nm SiO2 interfacial oxide. Wfin were varied from 1872 nm below 5 nm. Figure 6.[210-211] (Occasionally this reduces Hfin by 2 nm). The final patterning step was an anneal in H2 to round the fin corners and smoothen the sidewalls.SOI was thinned to 65 nm using a wet etch to define the prospective fin heights. Hfin.1 illustrates the patterned fins of a prospective finFET. Fins were then patterned by depositing a hard mask followed by immersion lithography.4Si0. Fin widths.1 Illustration of the patterned Si fins (10 in parallel) of a prospective finFET. Any native oxides were subsequently removed using HF based wet chemistry. After gate 163 .

BF2 for pchannel) and spacers were formed. A cross sectional TEM image of a 20 nm wide finFET is shown in Figure 6.2. There were no electrical contacts to the device channels which meant only the Cgc branch of the split CV could be measured. A big problem 164 .1. Finally a 1050 °c RTA was used to activate the dopants.5x109 cm-2. Figure 6. Access resistance was reduced with 40 nm Si selective epitaxial growth. Implantation of As+P for the n-channel and B for pchannel followed by 10 nm NiSi formed the source/drain contacts.patterning. particularly for CV measurements. source and drain extensions were implanted (As for n-channel. Further information on the device processing are given in [212-213]. In any case the light doping of the fins and the BOX meant the finFETs were fully depleted with Ndep no greater than 6. All devices exhibited large gate leakage currents necessitating corrections for Id. a typical example of which has already been shown in figure 4. Measuring long channel and multi-fin devices was necessary for a high signal-noise ratio.2 Cross sectional TEM image of a 20 nm wide finFET Electrical measurements in this work were performed on finFETs of length 10 µm with 10 fins in parallel.

1 nm. For channel lengths of 10 µm.3a) a small decrease in Cox with decreasing Wfin is observed.3a) shows Cgc for Wfin ranging from 1872 nm to 16 nm and Figure 6. This was a real nuisance as working finFETs with Wfin < 16 nm were not only scarce but also displayed large variations in Id.during measurements was the breakdown of the gate dielectrics.5 obtained from the Clausius-Mossotti relation (figure 2. making analysis difficult. suggesting confinement is weaker on the (110) sidewalls compared to the (100) top surface.1 n-finFETs Figure 6. (CET is constant within extraction error. Measurement frequencies of 100 kHz – 1 MHz were used.4 shows Vt extracted from the maximum slope of gm.) An unexpected feature is the increase in Vt with decreasing Wfin.6O was calculated as approximately 8 using equation (2.3. Note this is not too different from the value of 6.1 ± 0. Figure 6.3 Gate – channel capacitance and threshold voltage 6. Vt was expected to be constant due to the light fin doping and correspondingly small Ndep.12).56) corresponding to the measured CET of 2. From Figure 6. which confirms the 165 . manifested by excessive gate leakage. It was worse with decreasing Wfin and during low temperature measurements. The large variation was attributed to the devices having “broken fins”.4Si0. The dielectric constant of the Hf0. observed by the shift in Cgc to higher Vgs. 6.3b) shows the associated CET as a function of Wfin.

5 L = 10 µm 300 K Wfin = 1872 nm 2. for n-finFETs with Wfin ranging from 1872 nm to 16 nm and L = 10 µm.5 1.5 nm 866 nm 1872 nm 0.3a) Cgc characteristics. are large enough not to be affected by structural quantum confinement effects.0 Wfin = 16 nm CET (nm) -2 Cgc (µFcm ) 1.0 2.1 0.5 1.5nm 367.trend.0 10 1.5 Vt (V) 0.3 0.0 0. Note the Wfin presented here. b) Corresponding CETs.5 100 1000 10000 Wfin (nm) Vgs (V) Figure 6. 2.4 Vt for n-finFETs with Wfin in the range 16 nm – 1872 nm.5 1.0 0.6 L = 10µm T = 300 K Vds = 10 mV 0. Vt is extracted from the maximum slope of gm. 0.4 0.5 1.0 10 100 1000 10000 Wfin (nm) Figure 6.0 0. 166 .2 0.0 0.5 L = 10 µm 300 K 0.0 16 nm 27.

0 0. Figure 6. Vt is fairly independent of Wfin. the former indicating uniform dielectric thickness on the top surface and sidewalls of the fins.1 nm was obtained for all Wfin.0 2.5 0.3. 167 . Cox and Vt is constant with Wfin. As expected.0 12nm 22nm 32nm 42nm 72nm 364nm 864nm 1864nm 1.6 shows Vt for the range of Wfin.5a) Cgc characteristics.2 p-finFETs Figure 6. A CET of 2.5 -1.1 ± 0. i.0 0.5 1. b) Corresponding CETs. for p-finFETs with Wfin ranging from 1864 nm to 12 nm and L = 10 µm.0 -2.e. same as the n-finFETs.5a) shows Cgc for Wfin ranging from 1864 nm to 12 nm and Figure 6. Although some random variation is observed. A value of approximately 0.36 V was obtained which corroborates with the Cgc measurements.5 0.0 CET (nm) -2 Cgc (µFcm ) 1.5 1. extracted from the maximum slope of gm.0 10 100 1000 10000 Wfin (nm) Vgs (V) Figure 6.0 -0.0 -1.5 300 K L = 10 µm 0.5 L = 10 µm 300 K 2.6. 2.5b) shows the associated CET as a function of Wfin.

0 10 100 1000 10000 Wfin (nm) Figure 6.6 L = 10µm T = 300 K Vds = -10 mV Threshold Voltage (V) -0. If volume inversion was present. that volume inversion is not observed for thicknesses of 5 nm in double gate (110) p- 168 .5 -0. Vt is extracted from the maximum slope of gm.4 Volume or surface inversion The Cgc characteristics for both n.[217] surmise from mobility measurements. 214-216]. Simulations of the inversion charge distribution in the ∆4 sub-bands in double gate (110) n-MOSFETs have been performed in [115.3 -0.6 Vt for p-finFETs with Wfin in the range 12 nm – 1872 nm.2 nm or less are required for volume inversion to be maintained up to Ninv = 5x1012 cm-2. Silicon thicknesses of 5. suggesting volume inversion is not present for the Wfin shown here. Tsutsui et al. (Volume inversion is observed for thicknesses of 9 nm but only up to 1x1012 cm-2) On the contrary.1 0.-0. 6.and p-finFETs are analogous to bulk MOSFETs.4 -0. a drop in the capacitance might be observed as carriers travel down the centre of the fin rather than at the interfaces.2 -0.

5 300 K effective mobility 6.1 n-finFETs Electron and hole µeff were extracted using equation (4. Figure 6. on (100) and (110) SiO2/Si bulk MOSFETs has been included as a reference.[31] show volume inversion is not observed for thicknesses as small as 4 nm. 6.16a) with Id-Vgs measured with Vds = ±10mV . calculations of the inversion charge distribution by Donetti et al.5. Data from Takagi et al. 169 .MOSFETs. Furthermore.7 shows electron µeff for Wfin ranging from 16 nm to 1872 nm as a function of Ninv.

bulk (100)/<110> 2 -1 -1 Electron µeff (cm V s ) 367.5 nm. ionised impurity scattering (IIS) is not responsible.5nm Takagi et al.5nm 27. Such finFETs can be treated as essentially (100) SOI MOSFETs and are termed quasi-planar. bulk (110)/<110> 16nm Hfin = 65 nm L = 10 µm Vds = 10 mV T = 300 K 100 1e+11 1e+12 1e+13 -2 Ninv (cm ) Figure 6. For Wfin ≥ 367.1000 Takagi et al.9x1015 cm-3) [154] and (110) (Na =2.5 nm 26 nm 22 nm 17.’s (100) data over most of the Ninv range and so now will discuss why this might be. We can see that µeff in this set of finFETs is ~20% lower than Takagi et al. Since the doping concentrations are comparable. (100) (Na = 3. Takagi et al. The SiO2 interlayer should ensure local roughness scattering (LRS) and local Coulomb scattering (LCS) are 170 .1872 nm 37. µeff can be analysed in terms of transport along the (100) top surface and <110> channel direction.8x1015 cm-3)[155] bulk MOSFET data included for comparison.5 nm .7 Electron µeff for Wfin ranging from 16 nm to 1872 nm. the (110) sidewalls make up less than 35% of the effective width.

In line with these studies Shah et al.3 respectively from figure 2.3 nm from the channel) can also be neglected. This measurement is in agreement with charge pumping measurements performed by Garros et al. Coulomb and roughness scattering from the Si/BOX interface is not likely to be the cause of mobility reduction.Dit of ~1011 cm-2 in weak inversion was measured by charge pumping measurements at NXP Semiconductors on bulk MOSFETs with the same gate stack.. These mechanisms have been shown to be important 10 nm from the channel in SOI MOSFETs. O’Regan et al. This leaves high-κ related remote scattering mechanisms i.[51] show SO phonon plays a minor role in the electron mobility degradation of TiN/HfO2 MOSFETs and that RCS is the primary cause.4Si0. Thirdly.e.[111. Chau et al.12) results in a weak coupling strength between SO phonons and the inversion charge. 218] The influence of the remote TiN/HfSiO interface (3.[220] and Casse et al. the small difference in static and high frequency permittivity (6.comparable to those of the bulk MOSFET.[81] show that screening of the dielectric by carriers in the inversion layer reduces the strength of RPS at large electron densities (HfO2).[219] and Datta et al. the SiO2 interfacial layer decouples the phonons from the channel and reduces their effective scattering potential.[57] on a similar gate stack. Firstly. In the present case.5 and 3. Since the fin top surface is 65 nm from the BOX. Secondly.6O dielectric is likely to be of secondary importance for 3 reasons. remote charges from the HfSiO/SiO2 interface. RPS from the Hf0. remote phonon (RPS) and/or remote Coulomb scattering (RCS).[79] shows that a TiN gate is effective in screening phonon in a HfO2 dielectric from coupling to the channel. ~1 nm from the 171 . 114.

The electron mobility in (110)/<110> inversion layers is the lowest among the various silicon crystal orientations. the quasi-planar finFET and (100) reference are in close agreement which implies RCS and RPS are negligible in this case.3 nm from the channel.’s (110)/<110> data. the top (100) surface only makes up less than ~28% of the effective width thus µeff can be analysed in terms of transport along the (110)/<110> sidewalls.channel are likely to be responsible.8 shows hole µeff for Wfin ranging from 12 nm to 1866 nm as a function of Ninv. a ~60% enhancement from Ninv= 5x1012 cm-2 is observed and is maintained with increasing Ninv. 6. Since the devices did not intentionally receive any stress liners. Comparing µeff with Takagi et al. since quantization effects mean the valleys. are only scarcely populated. most likely due to RCS as discussed above. whilst the low mtran.[119] on (100)/<110> and (110)/<110> planar bulk SiO2/Si MOSFETs has been included for reference with the quasi-planar and (110) dominated finFETs respectively. the ∆4 valleys.in this case. In contrast to the n-finFETs. The negligible RPS can be explained using the arguments 172 . Any charges at the TiN/HfSiO interface are ~ 3. The enhancement of electron µeff at high Ninv suggests the presence of strain in the sidewalls of the fins. therefore unlikely to play a significant role. For Wfin ≤ 36 nm. Data from Irie et al. µeff is lower than the bulk data. At low Ninv.5.2 p-finFETs Figure 6. with the heaviest mtran are the most populated . ∆2 valleys. stress induced by the metal gate must be responsible.

For Wfin ≤ 26 nm. hole µeff is in agreement with the (110) reference up to 2x1012 cm-2. However it is akin to the experimental findings by Casse et al. it decreases. (100)/<110> bulk p-MOSFET 0 1e+12 Ninv (cm-2) Figure 6. This hypothesis is examined in more detail in section 6.’s[119] planar bulk (100)/<110> and (110)/<110> p-MOSFET data is included for reference. (110)/<110> bulk p-MOSFET 2 22 nm 26 nm 200 366 nm 866 nm 100 1866 nm Hfin = 65 nm L = 10 µm Vds = -10 mV T = 300K Irie et al. Weber et al.[51].8 Hole µeff for Wfin ranging from 12 to 1866 nm. 173 . after which.above.[222] who show holes are far less affected by RCS than electrons.7. This is most likely due to the sidewalls having a larger roughness. 400 300 16 nm -1 -1 Hole µeff (cm V s ) Decreasing Wfin 12 nm Irie et al. The discrepancy with the n-finFETs on the role of RCS is unclear. Irie et al.[221] and Lime et al.

6 Strain characterisation The results in this section were carried out by the device modelling group at DIEGM.6. Via delle Scienze. In section 6. Nano-materials group CEMES-CNRS. Figure 6. Udine. a non-trivial dependence of the mobility on the device stress components is predicted.e. thereby explaining the experimental mobility.10 show the simulated FinFET mobility change induced by each one of the three stress components. Belgium. Italy.5. fin width (TfW) and along the channel (TfL) on the sidewall mobility were performed by DIEGM. Tensile and compressive stress along the channel enhances electron and hole mobility respectively. However compressive stress in the fin height increases the electron mobility while hardly effecting the hole mobility. fin height (TfH).9 and Figure 6.1 it was proposed that strain in the fin sidewalls induced by the metal gate was the likely cause of the enhanced electron mobility. France and NXP Semiconductors. Simulations of the impact of stress in the main device directions i. 174 . As seen. The stress impact was analysed by means of double gate electron and hole mobility simulations where stress was systematically applied along each of the directions.

Figure 6.9 Simulated electron mobility change induced by stress components in the fin height. Figure sourced from [223]) Figure 6.11 summarises the effect on mobility of the stress components. width and length directions. 175 .10 Simulated hole mobility change induced by stress components in the fin height. Simulation is for the (110) sidewalls of a n-finFET at Ninv = 8x1012 cm-2. (Simulations performed at DIEGM. width and length directions. Simulation is for the (110) sidewalls of a p-finFET at Ninv = 8x1012 cm-2 (Simulations performed at DIEGM. Figure sourced from [223]) Figure 6.

Note a tensile TfL for electrons and compressive TfL for holes stress may be exploited to further enhance FinFET mobility.1 GPa. (Sourced from [223]) To gain a definitive understanding. There are stress configurations that can simultaneously improve both electrons and hole mobility. The holographic measurement shows a large compressive strain component in the fin height direction and also a weaker tensile strain component in the fin width direction. Strain along the channel was negligible for the long channel finFETs in this work. strain values of -0.11 The impact on the electron and hole FinFET mobility of the three device stress components. Figure 6. direct measurements of the finFET strain were made with a novel holographic interferometry technique[224] at CEMES-CNRS.3% in fin width direction were measured corresponding to a dominant fin height stress component of -1. From Figure 6.9 we see this is approximately the stress needed to explain the electron mobility enhancement. For a Wfin = 10 nm finFET.8% in fin height direction and 0. 176 . according to mobility simulations at DIEGM.Figure 6.12 shows the measured strain pattern in the fin cross section.

Figure 6. This causes a lowering of the ∆2 valleys with respect to the ∆4 valleys leading to a repopulation of the ∆2 valleys. reverting the unstrained population situation.13 shows the occupancy of the ∆2 and ∆4 valleys as a function of compressive TfH stress when Ninv = 8x1012 cm-2. Note the strain is antagonistic with respect to the sub-band splitting produced by confinement which lowers the ∆4 valleys. and also a weaker tensile strain component in the fin width direction (shown in red). mobility enhancements follows from this repopulation effect. Since the ∆2 valleys feature a low mtran. 90% of electrons occupy the ∆2 valleys. For TfH = -1. induced by the metal gate in a 10 nm fin cross section. There is a large compressive strain component in the fin height direction (shown in green). (Adapted from [223]) Calculations at DIEGM showed that the mechanism responsible for the electron mobility enhancement is strain-induced re-population of the ∆2 valleys produced by the compressive TfH stress.12 Holographic measurement of the strain pattern. France. Hence the stress-induced re-population is more effective at small than at large Ninv. Strain in the channel direction is negligible in long channels.1 GPa. Measurement was performed at CEMES-CNRS.[141] Figure 6. 177 .

The formula on the top axis expresses the relative energy shift of the ∆2 valleys with respect to the ∆4 valleys as a function of the fin height stress component. (Simulation performed at DIEGM.12.[223] 178 . are not included in this thesis and the reader is referred to Serra et al.and p-finFETs with Wfin ≤ 36 nm. Figure sourced from [223]) Process simulations performed at NXP revealed that the large vertical compressive strain and weaker tensile strain in the fin width direction is induced by the large difference in the thermal expansion coefficients of the silicon channel and the TiN metal gate (2. good agreement was obtained with the measured mobilities for n.Figure 6. The strain is formed by plastic relaxation of TiN gate during the cooling phase of the high temperature anneal. Simulations of the sidewall mobilities at 300 K and 77 K were performed at DIEGM using a multi sub-band Monte Carlo simulator. By comparison.13 Occupancy of the ∆2 and ∆4 in (110) silicon at Ninv = 8x1012 cm-2 as a function of finheight stress.5 and 9.4 respectively). Data measured by the author at 77 K data. the as-deposited strain due to intrinsic stress in TiN was found to be negligible. Using the strain values in Figure 6.

7 4 K effective mobility 6. 6.No simulations were performed on the effect of the stress on the top surface mobility. as phonons are frozen out. As the stress is predominantly applied perpendicular to this surface.2 have been included. it is reasonable to assume the mobility is unaffected.5.1 n-finFETs By cooling to 4 K the effects of interface related charge and roughness can be analyzed.7.14 shows the 4 K electron mobility for n-finFETs with Wfin in the range of 16 nm to 1872 nm. Figure 6. 179 . For reference (100)/<110> and (110)/<110> bulk n+poly-Si/SiO2/Si n-MOSFETs from section 5.

Therefore the scattering rate is higher for a 180 . at low Ninv. However. µeff is lower in the quasi-planar finFETs signifying a higher Coulomb scattering rate on the (100) top surface.190m0 although this latter value increases slightly due to energy band non-parabolicity. On the (100) interface. Thus electrons are confined closer to the (100) interface.Hfin = 65 nm L = 10 µm Vds = 10 mV T=4K Wfin = 16 nm 1000 2 -1 -1 Electron µeff (cm V s ) (100)/<110> bulk n-MOSFET Decreasing Wfin Wfin = 1872 nm 100 (110)/<110> bulk n-MOSFET 2e+12 4e+12 6e+12 8e+12 1e+13 Ninv (cm-2) Figure 6. Bulk (100)/<110> and (110)/<110> n-MOSFET data (dashed lines) included for comparison. with mtran = 0. Since there is no reason to expect that the magnitude of interface or remote charges should be higher on the top interface.14 Electron µeff measured at 4 K for Wfin ranging from 1872 nm to 16 nm.190m0. this increase in scattering suggests the difference in confinement between the two interfaces maybe responsible. As the majority of electrons occupy the ∆2 valleys on both the (100) top surface and (110) sidewall interfaces.916m0. we might expect µeff to be relatively independent of Wfin. whereas on the (110) interface. mconf = 0. mconf = 0.

The large degradation of mobility in the quasi-planar finFET below the bulk (100)/<110> n-MOSFET particularly at low Ninv can be explained by high remote charge density. The large difference in band structure between the (110) dominated finFETs and the bulk (110)/<110> n-MOSFET makes a qualitative comparison of physical parameters such as roughness difficult.7. Interestingly. Since electrons are confined further from the (110) interface. a reduction in interface roughness due to strain has been reported for biaxial tensile strained MOSFETs[225]. 6. µeff is independent of Wfin demonstrating a comparable LRS rate between the top and sidewall interfaces. however there is no evidence of a reduction due to strain here.given interface or remote charge density. At high Ninv.2 p-finFETs Figure 6. not exposed to this etch. the sidewalls must be physically rougher than the top surface for LRS to be the same. particularly as the bulk MOSFET has a higher doping concentration.15 shows the 4 K hole mobility for n-finFETs with Wfin in the range of 22 nm to 1872 nm. 181 . The H2 anneal may not have fully restored the sidewall surfaces to match that of the top surface. The origin of this could be due to the damage incurred by the dry etch.

To assist understanding. with exception of the source and drain implants. the bulk n+polySi/SiO2/Si (100)/<110> and (110)/<110> p-MOSFET data from section 5.1600 L = 10 µm Vds = -10 mV T=4K 1200 1000 2 -1 -1 Hole µeff (cm V s ) 1400 Hfin = 65 nm (110)/<110> bulk p-MOSFET 800 Wfin = 22 nm 34 nm 600 400 200 64 nm 364 nm 864 nm 1872 nm (100)/<110> bulk p-MOSFET 0 2e+12 4e+12 6e+12 8e+12 1e+13 -2 Ninv (cm ) Figure 6. due to the large difference in valence band structure between the (100)/<110> and (110)/<110> orientations. However.22) Although these bulk p-MOSFETs have a higher substrate doping 182 . From the discussion on 4 K electron mobility a higher sidewall roughness should be observed for the p-finFETs since they underwent the same processing. it is difficult to ascertain if roughness is larger on the sidewalls just by comparing µeff between the (110) dominated and quasiplanar finFETs.15 Hole µeff measured at 4 K for p-finFETs with Wfin ranging from 1872 nm to 22 nm. (Corresponding room temperature µeff agrees with literature data at high Ninv. (110)/<110> and (100)/<110> bulk p-MOSFET data (dashed lines) included for comparison.6 have been included for comparison. which is left unchanged by the strain. See figure 5.

We will adapt the model by Yang and Henson[37] who formulated a model for Coulomb scattering from ionised dopant impurities in a polysilicon gate in a n+polySi/SiO2/Si MOSFET. In their analysis they model 300 K electron µeff. At high Ninv the quasi-planar finFETs exhibit a slightly higher µeff (as was the case at room temperature).8 4 K modelling of quasi-planar finFETs Following the procedure outlined in section 5. Their analysis is based on ground sub-band occupation. As we suspect remote charges from the high-κ/SiO2 interface are significant.1) . They derive the following momentum relaxation time. 6. confirming the hypothesis to explain the electron µeff.6. the same models can be applied to the 4 K electron and hole µeff in the quasi-planar finFETs (Wfin = 1872 nm). by treating them as (100)/<110> planar MOSFETs. an analytical model for RCS is required. For Wfin ≤ 64 nm. µeff remains significantly lower than the (110)/<110> bulk p-MOSFETs suggesting higher sidewall roughness. ∆2 minima for electrons and HH band for holes. 1 τk = mscat e 4 N poly 8πh (ε 0 ε r ) 3 2 2 ( ) P 0 e −2 qz1 − e −2 qz 2 (1 − cos(θ )) ∫0 2q q + s P + δP 2 2 dθ av 0 2π ( ( )) 183 (6.therefore IIS rates. their µeff is higher than that of the finFETs at low Ninv suggesting RCS is important at low temperature. This might be explained by the lower Eeff due to the lower doping therefore lower LRS.

Npoly is the doping concentration of the gate. 1 τk = 8πh (ε 0 ε r ) 3 2 ( [ ) P02 2qe −2 qz1 (1 − cos θ ) ∫0 2q q + s P + δP 2 2 dθ av 0 2π mscat e 4 nr ( )] 184 (6.1). s= e 2 N inv 2ε 0ε r E F (6. a sheet density of charge and using Taylor expansion.5) By modelling the charge distribution as a delta function. we can write.In their notation.2) 8(b + q ) 3 (ε εr = δ= 8b 3 + 2b 2 q + 3bq 2 Si + ε SiO2 ) (6.16.4) 2ε r The screening function due to Ninv is given by. replacing Npoly with nr. z 2 = z1 + δ z (6. δz at a high-κ/SiO2 interfacial oxide interface as shown in Figure 6. Pav = (6.6) Substituting equation (6.6) into equation (6. z1 is the physical thickness of the gate oxide and z2-z1 the width of the depletion region in the polysilicon gate when a gate voltage is applied.7) .3) 2 (ε Si − ε SiO2 ) (6. we can write.

nr is modelled as a sheet of charge at the high-κ/SiO2 interface. We can thus extract the roughness parameters of the (100) surface and quantify any remote charge. Keeping with. nr. Using Matthiessen’s rule.Figure 6. Intuitively we expect these to be similar for the n.1. z1 is the interfacial oxide thickness.16 Schematic of a high-κ gate stack. The modelled 4 K electron and hole effective mobilities are shown in Figure 6.18. ∆.8) µ LRS The Dit value of 1x1011 cm-2 measured in weak inversion was used in the LCS model and the room temperature doping concentration of 1x1015 cm-3 used in the IIS model. 1 µ Tot = 1 µ RCS + 1 µ IIS + 1 µ LCS + 1 (6. 185 . The modelling parameters are shown in Table 6. Yang and Henson’s notation.17 and Figure 6. Remote charge density. Λ were used as fitting parameters to the experimental data.and p-finFETs.

05 Λ (nm) 2 .3 8.0 x1012 ± 0. local Coulomb.3 Table 6.5 x1012 -2 nimp (cm ) 1.0x1011 -3 Na (cm ) 1.3 ± 0 .38 ± 0.05 2 .0x1015 0.1 Parameters used in the mobility modelling of quasi planar n.0 x1012 ± 0.3 ± 0 .5 x1012 1. remote Coulomb and local roughness scattering mechanisms.0x1015 ∆ (nm) 0.RCS -2 nfinFET pfinFET 4 K modelling parameters LCS IIS LRS nr (cm ) 8.0x1011 1.41 ± 0.17 4 K electron µeff of a quasi-planar n-finFET (Wfin = 1872 nm) modelled in terms of ionised impurity.and p. 186 .finFETs 1e+7 Wfin = 1872 nm Hfin = 65 nm 1e+6 2 -1 -1 Electron µeff (cm V s ) IIS L = 10 µm Vds = 10 mV 1e+5 LCS 1e+4 LRS RCS 1e+3 Total 1e+2 0 2e+12 4e+12 6e+12 8e+12 1e+13 Ninv (cm-2) Figure 6.

In the RCS model. local Coulomb. showing that RCS is the dominant Coulomb scattering mechanism.1e+7 IIS Wfin = 1872 nm L = 10 µm Vds = -10 mV 2 -1 -1 Hole µeff (cm V s ) 1e+6 1e+5 LCS 1e+4 LRS 1e+3 RCS Total 1e+2 0 1e+12 2e+12 3e+12 4e+12 5e+12 6e+12 Ninv (cm-2) Figure 6. The extracted values of nr are not too different from that obtained by Kaushik et al. It is unclear why RCS is dominant at 300 K down to 4 K for electrons but only at 4 K for holes. they estimate nr ~ 6x1012 cm-2 in devices with a Hf0. Note the small impact of LCS and IIS on electron and hole µeff. remote Coulomb and local roughness scattering mechanisms.[64] Using an etching technique.18 4 K hole µeff of a quasi-planar p-finFET (Wfin = 1872 nm) modelled in terms of ionised impurity.5Si0. a value of nr = 8x1012 cm-2 was required to fit both sets of data at low Ninv. (Dit in their case < 3x1011 cm-2.1 it was speculated that the weaker confinement on the 187 . This is also observed by Lime et al.[222] who state Coulomb scattering “contributes more efficiently at low temperature”. It still has an impact on mobility.) In section 6.5O dielectric deposited by MOCVD and a 10 nm TaN/TiN gate electrode.7. exposed to a 1000°c RTA. particularly so for electrons at Ninv = 1x1013 cm-2.

This is process dependent.[51. a multi sub-band Monte Carlo simulation of the 300 K electron mobility of a quasi-planar n-finFET (Wfin = 1872 nm) was performed.190m0 as opposed to 0. It should be pointed out that a TiN gate can modify the interface roughness.916m0 results in a 50% higher RCS calculated mobility and a 70% higher LCS calculated mobility at Ninv = 1x1012 cm-2. mconf = 0.7. Upon the author’s request. 226] The extracted values of ∆ and Λ in the present work are in rough agreement with those obtained for the bulk poly-Si/SiO2/Si MOSFETs in table 5. Using.strained (110) surface compared to the (100) surface was the reason for the higher electron mobility at low Ninv. using the remote charge density extracted at 4 K. 188 . The simulation and comparison to the measured data is shown in Figure 6. At Ninv = 8x1012 cm-2 the LRS calculated mobility is higher by 22%.19. Thus it can be deduced this is insignificant for the gate stack in the present work. The models show that the mobility is indeed a strong function of mconf.

The effects of phonon scattering (bulk and remote) PS.1000 2 -1 -1 Electron µeff (cm V s ) Takagi et al.19 Multi sub-band Monte Carlo simulations of the 300 K electron mobility of a quasiplanar n-finFET (performed at DIEGM). confirming the argument in section 6. This indicates the simple analytical approach developed here to extract remote charge density. It was found that accounting for all the scattering mechanisms (detailed in the figure).5. The remote charge density extracted at 4 K. bulk (100)/<110> Wfin = 1872 nm Takagi et al.’s bulk Si/SiO2 (100)/<110> data is shown for reference. is a reasonable approximation at room temperature. is used in the modelling of RCS with the resulting mobility within 12% of the measured mobility. 189 . Note also RCS accounts for the mobility degradation below the bulk SiO2/Si reference. bulk (100)/<110> No PS No LCS No RCS PS 11 -2 PS + LCS (nimp = 1x10 cm ) + RCS (nr = 8x1012 cm-2) Hfin = 65 nm L = 10 µm Vds = 10 mV T = 300 K 100 1e+12 1e+13 -2 Ninv (cm ) Figure 6.1. LRS is included in all simulations. LCS and RCS are independently shown. Takagi et al. the simulated mobility agrees with the measured mobility to within 12%.

A model for remote Coulomb scattering from the Hf0. On the other hand. This was attributed to remote Coulomb scattering.6.4Si0.9 Summary This chapter presents detailed mobility analysis of n. which suggests that the H2 anneal.6O/SiO2 interface was developed. with fin widths of 1872 nm (quasi-planar) down to 12 nm and TiN/Hf0.6O/SiO2 gate stacks. This strain leaves the hole mobility unaffected. This was due to vertical compressive strain in the fin sidewalls induced by the difference in thermal expansion coefficients between the TiN gate and Si fin. used to repair the damage is insufficient. Analytical modelling of the 4 K electron and hole mobilities of quasi190 . The electron mobility of a quasi-planar ((100) dominant) n-finFET was found to be approximately 20% lower than the (100) bulk MOSFET literature reference. the hole mobility was not degraded by remote charge and was in agreement with the literature (100) reference.and p-finFETs.4Si0. This is probably due to the damage caused by the dry (reactive ion) etch used to pattern the sidewalls. Electron and hole mobilities were extracted at 300 K and 4 K. The finFETs have a (100) top surface and (110) sidewalls. Analysis of the 4 K electron and hole mobility suggests the sidewall roughness is higher than on the top surface. The 300 K (110) sidewall electron mobility showed a 60% enhancement over the (110) bulk MOSFET literature reference data.

ionised impurity. Remote charge densities of 8x1012 cm-2 were subsequently extracted. indicating good top surface interface quality. Roughness parameters at the SiO2/Si interface were found to be comparable to literature values. local charge and roughness scattering mechanisms.planar finFETs was then performed in terms of remote charge scattering. 191 .

7. providing the inversion charge is known accurately. The findings are highly relevant for the continuation of Si based technology. accurate extraction in weak inversion is now limited by errors in deducing the inversion charge. Blindly extracting the mobility at a drain bias of 50 mV. The focus is on the accurate extraction and modelling of carrier mobility to assess the performance limiting mechanisms. Thus.1 Chapter 4 In chapter 4. as is usually done. underestimates the mobility. The analysis shows that the variation in the field along the channel is exactly compensated by the diffusion current in the limit Vds → 0 . 192 . accurate mobility is obtained using the drift only expression with the drain conductance correction. The main results are summarised below. the extraction of the effective channel mobility and possible errors have been analysed in detail. which industry is currently researching. However. A novel regression technique was proposed to extrapolate the drain conductance to zero drain bias in order to correct for the difference in drain bias between Id-Vgs and Cgc-Vgs measurements.Chapter 7 : Conclusion This thesis has provided greater understanding of the carrier transport in novel Si MOSFETs and finFETs.

The behaviour of electron mobility is well known and was explained using the constant effective masses corresponding to the conduction sub-band minima. substrate orientation and channel direction. by averaging the mass calculations over the Brillouin zone. weighted by the Fermi distribution to obtain the effective masses as a function of inversion charge density. The MOSFETs had channel lengths of 25 µm and n+polySi/SiO2 gate stacks which enabled detailed analysis of the mobility dependence on substrate orientation and channel direction without being concerned with high-κ dielectric related scattering mechanisms. On the contrary. the latter for freezing out phonons and allowing qualitative and quantitative analysis of just Coulomb and interface roughness scattering mechanisms. Mobility measurements were performed at 300 K and 4 K. a qualitative description of the mobility was performed. due to the complex nature of the valence band. were unable to explain the observed mobility dependence on inversion charge density.2 Chapter 5 In chapter 5.7. local charge and roughness scattering mechanisms revealed comparable Si/SiO2 interface quality between the (100) and 193 . which are usually reported. Using these masses. n. Simulations of the relevant masses were performed. hole mobility is less well understood.and p-MOSFETs fabricated on (100) and (110) substrate orientations were electrically characterised in detail. at 300 K and 4 K by Luca Donetti at Universidad de Granada. Analytical modelling of the 4 K electron and hole mobility in terms of ionised impurity. Zone centre effective masses.

with fin widths of 1872 nm (quasi-planar) down to 12 nm and TiN/Hf0.4Si0. a 60% enhancement of the 300 K sidewall electron mobility was found over (110) bulk MOSFET literature reference data. the hole mobility was not degraded by remote charge and was in agreement with the literature (100) reference. For inversion charge densities above 5x1012 cm-2.4Si0. which implied that the sidewalls were strained. the sidewall electron mobility was degraded below the reference due to remote charge scattering from the Hf0. For inversion charge densities below 5x1012 cm-2. The electron mobility of a quasi-planar n-finFET was found to be approximately 20% lower than the literature (100) reference. This was attributed to the remote charge scattering. Monte Carlo simulations of the 300 K mobility are currently in progress at Universidad de Granada for comparison. Electron and hole mobilities were measured at 300 K and 4 K (additional work at 77 K is not shown in this thesis). 194 . This strain serves to enhance the electron mobility and leaves the hole mobility unaffected.and p-finFETs.6O/SiO2 interface. On the other hand.3 Chapter 6 Chapter 6 is based on detailed mobility analysis of n. 7.6O/SiO2 gate stacks. The finFETs in this study have a (100) top surface and (110) sidewalls.(110) orientations. The corresponding stress is due to a difference in thermal expansion coefficients between the TiN gate and Si fin which induced vertical compressive strain into the fin sidewalls.

6O/SiO2 interface was developed by adapting an existing model for remote charge scattering from ionised impurities in a polySi gate. thus showing good fin top surface interface quality. A model for remote charge scattering from the Hf0. Analytical modelling of the 4 K electron and hole mobilities of quasi-planar finFETs was then performed in terms of remote charge scattering. used to repair the damage is insufficient. ionised impurity. 195 . which suggests that the H2 anneal. a Monte Carlo simulation of the 300 K electron mobility of a quasiplanar n-finFET was performed at University of Udine. Remote charge densities of 8x1012 cm-2 were necessary to fit both the electron and hole mobility at low inversion charge densities. showing that the parameters deduced at low temperature are in reasonable agreement with those at 300 K. using the extracted remote charge density. Extracted roughness parameters were comparable with values extracted in chapter 5 and literature values for the SiO2/Si interface. Upon the author’s request. This is probably due to the damage caused by the dry (reactive ion) etch used to pattern the sidewalls. Thus even higher mobilities may be realised if this is addressed.4Si0. local charge and roughness scattering mechanisms. The simulated and measured mobility were within 12% of each other.Analysis of 4 K electron and hole mobility suggests the sidewall roughness is higher than on the top surface.

Ti-based) and metal gate combinations. and there would be scope to further improve the model for remote charge scattering proposed here. In addition. For instance. Little has been published in these areas. with sidewalls in the (100) plane) would enable analysis of the mobility on these strained (100) surfaces.7.2 and 0.g. there is still considerably more to learn. a full analysis of this batch following the analysis used for the Si MOSFETs in this thesis may provide more detailed understanding of the carrier transport and mobility limiting scattering mechanisms.4) n. The Si MOSFETs on (100) and (110) wafers analysed in chapter 5 are part of a batch which contain buried channel pseudomorphic strained Si1-xGex (x = 0. Although SiGe has been intensively researched in the past for MOSFET applications. especially with regard to analysing “higher-κ” dielectrics (e.and p-MOSFETs which are also fabricated on these orientations and have channels in the full range of directions.4 Further work While this work has contributed to our understanding of the mobility limiting mechanisms associated with Si MOSFETs. low frequency (1/f) noise measurements and their modelling on the finFETs may provide further insight into the role of oxide charge trapping for corroboration with the mobility data.e. finFETs and high-κ/metal gates. The impact of the high-κ/metal gate is still a hot topic amongst researchers. measurements on the 45° rotated finFETs (i. No study yet has been undertaken to 196 .

197 . Such devices could have significantly higher mobilities and be of relevance for future technology nodes. There is also considerable scope for further research on strained SiGe or pure Ge based finFETs.compare different metal gate materials and thicknesses for the purpose of inducing stress in finFETs and the subsequent impact on mobility.

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