IEEE Asian Solid-State Circuits Conference



November 10 - 12, 2014/Kaohsiung, Taiwan

A Nonvolatile Look-Up Table Using ReRAM for
Reconfigurable Logic
Wen-Pin Lin1, Shyh-Shyuan Sheu2, Chia-Chen Kuo1, Pei-Ling Tseng1, Meng-Fan Chang3, Keng-Li Su1, Chih-Sheng
Lin1,3 , Kan-Hsueh Tsai1, Sih-Han Lee1, Szu-Chieh Liu1,Yu-Sheng Chen1, Heng-Yuan Lee1, Ching-Chih Hsu1,
Frederick T. Chen1, Tzu-Kun Ku1, Ming-Jinn Tsai1, Ming-Jer Kao1
1

Electronics and Optoelectronics Research Laboratories (EOL), ITRI, Hsinchu, Taiwan
2
National Taipei University, Taipei, Taiwan
3
National Tsing Hua University, Hsinchu, Taiwan
3
Ming Shin University of Science & Technology, Hsinchu, Taiwan
E-mail : sssheu@gmail.com
compatibility and a higher resistance ratio compared with other
emerging memories such as phase-change random access
memories (PCRAM), magnetoresistive random-access memory
(MRAM), and ferroelectric random-access memory (FeRAM).
In addition, ReRAM is a high-performance, nonvolatile
memory with a write speed as fast as 5 ns [5], [9], [10]. The
proposed nonvolatile LUT reduces the area and active-power
consumption compare with SRAM-based LUT and published
nvLUTs .

Abstract—This study demonstrated a nonvolatile look-up
table (nvLUT) that involves using resistive random access
memory (ReRAM) cells with normally-off and instant-on
functions for suppressing standby current. Compared with the
conventional static random access memory (SRAM)magnetoresistive random-access memory (MRAM)-hybrid LUTs
the proposed ReRAM-based two-input nvLUT circuit decreases
the number of transistors and the area of nvLUT by 79% and
90.4%, respectively. The areas of the two- and three-input
ReRAM nvLUTs are 11.5% and 74.2% smaller than the other
MRAM-based two-input and PCM-based three-input LUTs,
respectively. Because of the low current switching and high Rratio characteristics of ReRAM, the proposed ReRAM-based
nvLUT achieves 24% less power consumption than that of
SRAM-MRAM-hybrid LUTs. The functionality of the fabricated
adder of the three-input ReRAM nvLUT was confirmed using an
HfOx-based ReRAM and a 0.18-ȝm complementary metal-oxide
semiconductor with a delay time of 900 ps.

II.

A. Technological Background
Fig. 1 (a) shows the ReRAM devices comprising a
TiN/TiOx/HfOx/TiN structure. The typical bipolar switching
IV characteristics are displayed in Fig. 1 (b). The lowresistance state (LRS) in the SET operation is achieved by
applying a positive voltage (1.5V) across the top electrode (TE)
and the bottom electrode (BE). By contrast, the RESET
operation requires a negative voltage (-1.1V) to achieve the
high-resistance state (HRS). The write time of the HfOx-based
ReRAM can be as fast as 5 ns [10].

Keywords—LUT; Look-Up Table; FPGA; nonvolatile logic;
resistive memory; ReRAM; RRAM

I.

INTRODUCTION

Miniaturizing electronic products and integrated circuit (IC)
chips is crucial in the developing of advanced semiconductor
technology. Current configurable ICs have various internal
connection structures and designs of an internal configurable
logic block (CLB), which is equipped with an embedded
memory that serves as a look-up table (LUT) [1]г[8]. A
conventional reconfigurable logic circuit uses the SRAM to
store the configuration information. However, the SRAM may
cost approximately 40% of the total area [8], resulting in higher
cost and longer routing delay. To maintain the configuration
data during the power-off mode, a nonvolatile memory is also
required. Traditionally, the data is serially transferred from the
SRAM to the nonvolatile memory unit, which consumes both
time and energy. Because of recent developments in the
emerging memory technology, these obstacles can be resolved
by replacing the SRAM with a more compact nonvolatile
memory unit.

(a)

This paper proposes a novel ReRAM-based LUT for
reconfigurable logic. An nonvolatile look-up table (nvLUT)
can be implemented with various kind of emerging memory
devices, however, ReRAM provides better CMOS process

978-1-4799-4089-9/14/$31.00 © 2014 IEEE

RERAM-BASED, NONVOLATILE, LOOK-UP TABLE

(b)
(c)
Fig. 1 1T2R memory unit (a) Cell Structure and Layout (b) IV
characteristic of HfOx RRAM (c) Schematic 

H) by applying reset voltage VR. Operation of the Proposed Memory Unit As shown in Table 2. this implies that the operating current can be reduced by increasing the HRS resistance. when the logic value “1” is written into the memory unit. and read/write control circuit. Moreover. W. compared with the 1T1R structure. 5 shows another application of nvLUT. Moreover. 2 Read principle of proposed memory unit  . 6. Vread should not be greater than the minimum disturb voltage of 0. When the logic value “0” is written into the memory unit. The CRS architecture guarantees that the combined resistance of RA and RB is higher than HRS. W. the operator may write any desired truth table into the memory units. which comprises two three-input LUTs. A. Table 2 Operation table of proposed 1T2R memory unit RESET SET READ ReRAM A B W S RA RB RA RB - 0V F VS F 0V F 0V F Vs VREAD VDD VDD VG SET VG SET 0V VR VR 0V 0V 0V D. the CRS structure further increases the speed of the read operation because the output is always driven by the LRS ReRAM device. Fig. Fig. The SET operation can be performed by applying 0V to S. applying VDD. Table 1 Truth table of proposed 1T2R memory unit RA HRS HRS LRS LRS RB HRS LRS HRS LRS State Forbidden “1” “0” Forbidden C. The “0” state is defined with RA = HRS and RB = LRS. A. which thus minimizes the DC leakage in the read operation. the selecting circuit selects a particular memory unit based on the input logic value. and applying SET voltage Vs on Nodes S. and RB is reset to HRS. Because the configured data are stored in the ReRAM device. The RB is then set to a low-resistance state (LRS. RA is set to LRS. The RESET operation can be performed similarly. Using this approach. and B.5 V [12]. respectively. Nodes A and B are adopted to Vread and 0 V. 4 displays the simulation results of a two-input nvLUT for the NAND gate. 3 depicts a two-input LUT with a two-input NAND configuration. For standby operations. 1 (c) displays the architecture of the proposed 1T2R memory unit. The W terminal of each memory unit can be shared. grounding. which consists of an NMOS switch transistor (MSEL) and two HfOx-based ReRAMs (RA and RB). As observed in Fig. floating. A. and B provide the path for applying read and write bias conditions. the nvLUT can be shut down to prevent extra power consumption. L) by grounding. the full adder. as listed in Table 1. Vs to Ax or Bx (based on which ReRAM device requires the SET operation) and by applying a pulse with the amplitude of VG_SET on W. Architechture of the Proposed 1T2R Memory Unit Fig. The ReRAM devices RA and RB work jointly as a complementary resistive switching (CRS) device [11]. Terminals S. 2 displays the read operation conditions of the proposed memory unit. applying clamping voltage VG_SET. and B. The “1” state is defined with RA = LRS and RB = HRS. the RA is reset to a high-resistance state (HRS. the memory unit can operate correctly and instantly after power restoration. 3 2 input LUT based on memory unit Fig. Moreover. Fig. because the targeted HRS of the device is > 1M ohm. Table 3 shows a common function with its corresponding memory unit resistance state configuration. and floating on nodes S. The output is “1” if the C terminal of the memory unit is larger than Vref. Proposed Nonvolatile Look-Up Table The proposed nvLUT consists of plurality of the proposed memory units. power consumption of the two-input LUT can be reduced by 24%. Fig. Outputs of the memory units 0í3 correspond to XY = 00г11. During the read operation.B. respectively. The detailed operation would be descripted in the next section. The BEs of RA and RB are connected to the output of the memory unit terminal C. respectively. Fig. For the read operation. one for the sum S and another for the carry out (Cout). to prevent the ReRAM device from read disturbance. The sensing amplifiers then determine the output logic values according to the reference voltage (Vref). selecting circuit. The select transistor MSEL provides stable write conditions by directly controlling the terminal C. respectively. the RESET and SET operations are required to store and configure data into the memory unit.

and 2. respectively. Table 4 shows the performance comparison of the LUTs.0. the delay time can be as fast as 900 ps. and 2. Cout and Sum. the proposed nvLUT can be expexted to realize a normally-off and instant-on reconfigurable logic Fig.4% and 11.5%. Moreover. Hence.18-ȝm CMOS. the area of the proposed two-input LUT can reduce the area by 90. The proposed LUT can achieve a delay time of 900 ps at a power supply of 1. and nvLUTs [3]. The output bits. exhibit the operation of the full adder. MRAM-based nvSRAMs [2]. 4 R/W operation of the 2-input LUT for NAND gate Fig. as expected. Moreover. 8 Micro photograph of proposed LUT Fig.8 V. As the result. the proposed nvLUT consisting of ReRAM as the memory unit can be successfully used to achieve lower cost. compared with the PCM-based nvLUTs. [4]. 7 depicts the analysis of the fulladder delay time against VDD. high operation speed. Fig. this indicates that the proposed nvLUT has the ability to perform normally-off and instant-on functions. 7 Delay time vs. 11 displays the measured propagation delay of the full adder. 10 shows the measured output waveforms of the full adder. Power consumption of the two-input LUT can be reduced by 24%. The pull-up and pull-down delay time values are 900 and 730 ps. RESULTS.8% compared with the conventional SRAM-MRAM-hybrid LUTs [3]. the area of the three-input LUTs can be reduced by 74. zero standby power.2% [4]. Fig. 10 Measured waveforms of the full adder  . 5 Two 3-input LUT based full adder Fig. AND CONCLUSION Fig.8% compared with the conventional SRAMMRAM-hybrid LUTs [3]. Therefore. In addition. 9 shows the measured waveforms of the NAND and NOR gates in the two-input LUT. 9 Measured waveforms of the 2-input LUT Fig. 36%. respectively. respectively [3]. VDD III. These waveforms demonstrate a normal adder operation. Fig. followed by a power off and then a power on. 36%. MEASUREMENT. 8 displays a photomicrograph of the fabricated chip with the proposed LUTs using the HfOx-based ReRAM with a Fig. respectively. Fig. The output indicates the correct result with an input sweep from 00 to 11. 6 Power consumption vs. [3]. MRAM-based nvSRAMs [2] and nvLUTs [3]. R-ratio Fig. Table 3 Operating ReRAM states of 2-input LUT Function ReRAM State RA1 RB1 RA2 RB2 RA3 RB3 RA4 RB4 NOR H L L H L H L H OR L H H L H L H L NAND H L H L H L L H AND L H L H L H H L XOR L H H L H L L H XNOR H L L H L H H L Compared with the conventional SRAM-MRAM-hybrid LUTs and the MRAM-based nvLUTs.

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